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e Verication Components (eVCs)

e Verication Components (eVCs) are reusable, pre-veried, congurable, plug-and-play verication components written in the e language. Each eVC is a ready-to-use verication environment, typically focusing on a specic protocol or architecture. Since they are designed for reuse, eVCs drastically shorten the time required to create a verication environment. By incorporating eVCs into your design, you shorten the time required to begin testing, you get a higher quality verication result, and you avoid the need for in-house protocol expertise. In other words, you can start verifying your design sooner and can do so with fewer resources. Each eVC includes three integrated components:

A stimuli generator for injecting and generating trafc Monitors and checkers for viewing outputs and checking protocol rules Coverage reports showing the functional coverage of scenarios on the bus
You can use eVCs in a variety of design applications. eVCs are compatible with both Verilog and VHDL devices and with all HDL simulators that Specman Elite supports. eVCs encompass a major portion of your verication environment: you can create test environments faster and you are less dependent on having expertise in the particular protocol the eVC supports, so you can do less work creating your environment and simplify the work of writing tests. Using eVCs leads to improvements in both test and overall product quality. eVCs are congurable and extensible. You can use an eVC as a full verication environment or add it to an existing environment. eVCs are easy for you to extend because you can view the eVC interface, and your extensions are reusable. (Keeping extensions in a separate le will simplify adopting any future upgrades to the eVC.) All eVCs should be eRM-compliant. For more information on eRM, see the e Reuse Methodology (eRM) Developer Manual.
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e Verication Components (eVCs)

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Verication Advisor