Esd Manual

Electronics System Design Lab
VII Sem ECE
EC 2404 ELECTRONICS SYSTEM DESIGN LAB 1. Design of a 4-20mA transmitter for a bridge type transducer. Design the Instrumentation amplifier with the bridge type transducer (Thermistor or any resistance variation transducers) and convert the amplified voltage from the instrumentation amplifier to 4 20 mA current using op-amp. Plot the variation of the temperature Vs output current. 2. Design of AC/DC voltage regulator using SCR Design a phase controlled voltage regulator using full wave rectifier and SCR, vary the conduction angle and plot the output voltage. 3. Design of process control timer Design a sequential timer to switch on & off at least 3 relays in a particular sequence using timer IC. 4. Design of AM / FM modulator / demodulator i. Design AM signal using multiplier IC for the given carrier frequency and modulation index and demodulate the AM signal using envelope detector. ii. Design FM signal using VCO IC NE566 for the given carrier frequency and demodulate the same using PLL NE 565. 5. Design of Wireless data modem. Design a FSK modulator using 555/XR 2206 and convert it to sine wave using filter and transmit the same using IR LED and demodulate the same PLL NE 565/XR 2212. 6. PCB layout design using CAD Drawing the schematic of simple electronic circuit and design of PCB layout using CAD 7. Microcontroller based systems design Design of microcontroller based system for simple applications like security systems combination lock. 8. DSP based system design Design a DSP based system for echo cancellation, using TMS/ADSP DSP kit. 9. Psuedo-random Sequence Generator 10. Arithmetic Logic Unit Design Note: Kits should not be used. Instead each experiment may be given as mini project. TOTAL= 45 PERIODS
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VII Sem ECE
INDEX
S.No. 1 2 3 4 Experiment Name Design of a 4-20mA transmitter for a bridge type transducer AC/DC voltage regulator using SCR Design of process control timer a) Design of AM modulator / demodulator b) Design of FM modulator 5 6 7 8 9 10 Design a FSK modulator using XR 2206 PCB layout design using CAD Psuedo-random Sequence Generator Arithmetic Logic Unit Design Microcontroller based systems design DSP based system design
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1.
DESIGN OF A 4-20mA TRANSMITTER FOR A BRIDGE TYPE TRANSDUCER.
AIM: To design the instrumentation amplifier with the bridge type transducer and convert the amplified voltage from the instrumentation amplifier to 4-20mA current using op-amp. SOFTWARE REQUIRED: Orcad THEORY: In a number of industrial and consumer applications physical quantities such as temperature, pressure and light intensity are to be measured and controlled. These physical quantities measured with the help of transducers have to be amplified so that it can drive the display system. This function is performed by an instrumentation amplifier. The circuit uses a resistive transducer whose resistance changes as a function of the physical quantity to be measured. The bridge is initially balanced by a dc supply so that V1=V2. As the physical quantity changes, the resistance RT of the transducer also changes, causing an unbalance in the bridge (V1V2). This differential voltage gets amplified by the three op-amp differential instrumentation amplifier. The amplified voltage is converted to current using V-I converter. The important features of instrumentation amplifier are: 1. 2. 3. 4. 5. High Gain Accuracy High CMRR High Gain Stability With Low Temperature Coefficient Low Dc Output High Output Impedance
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VII Sem ECE
DESIGN: A sensistor is a type of resistor whose resistance changes with temperature. Instrumentation Amplifier:
Let V1 = 2.3v V2 = 2.5v V0 = 4v Assume R' = 45k R = 10k V0 = R2/R1(1+90k/10k)(0.2v) 4v = R2/R1(1+90k/10k)(0.2v) 4 = 2R2/R1 R2/R1 = 2. Let R1 = 50k R2 = 100k V - I Converter: Let V0 = 4v I0 = 8mA R = V0/ I0 R = 500
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VII Sem ECE
CIRCUIT DIAGRAM:
0 V
3 U + 3 7 O V O 1 5 1 S 4 5 5 2 1 1 R 2 2 2 1 1 3 2 k 11 2
V
c R 5 0 6 21 R k 1 0 1 0 2 0 k V 1 O 5 S U S V k 7 1 R 5 0 7 2 k 1 R 1 0 8 2 5 9 V d c 4 V2 8 U 1 6 5 Vu 1 T 2 1 2 Ad c7 4 R 1 1 1 2 5 0 0 1 R 5 0 2 0 2 0
I
V+ V-
O 2 u R 5
V
6 U T 5 1 S 1 V d0 c
0
3 4 R 5 4 1 R 4 0 5 5 k 3 + k V2 4 O O V+
1 2 R 5 1 1 5 V d V c 1
1 2 2 k 4
0
R 5 1 k U 5 4 5 1 2 1 V 5 S U S 7 5 V d c 1 V 1 T 2 1 2 d c 1
1 k R
0
1 O
0 0
0 1 O
V 5 S U S V
1 U VL 1 6 5 3 5 V 1
1 1 Md T 2 0 d
1 0 c7 4 1
1 5 5 . 5
V-
1 6 5
O V+ 3 u A + 7 O 1 V 1
0k
O V+ 7 1 3 + O
4 7
PINDIAGRAM of IC741:
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. Use PSPICE simulator and run.
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VII Sem ECE
3. Note down the input voltages applied to the IA, output voltage of IA and output current. 4. Vary the resistance value and note down the readings.
5. Plot the variation of resistance Vs output current.
TABULATION: Sl.No Resistance Input (k) Voltage (V1) volts Input Voltage (V2) volts Output Voltage (V0 )volts Output Current (I0 )mA
RESULT: Thus the instrumentation amplifier with the bridge type transducer was designed and the amplified voltage was converted to current.
VIVA QUESTIONS: 1. 2. 3. 4. 5. What is Instrumentation Amplifier? Explain the working of the circuit. When will wheat stone bridge be balanced? Give the important features of IA. What is a transducer?
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VII Sem ECE
2. AC/DC VOLTAGE REGULATOR USING SCR

AIM: To construct a phase controlled voltage regulator using full wave rectifier and SCR. SOFTWARE: OrCad THEORY: In phase control the Thyristors are used as switches to connect the load circuit to the input ac supply, for a part of every input cycle. That is the ac supply voltage is chopped using Thyristors during a part of each input cycle. The thyristor switch is turned on for a part of every half cycle, so that input supply voltage appears across the load and then turned off during the remaining part of input half cycle to disconnect the ac supply from the load. By controlling the phase angle or the trigger angle (delay angle), the output RMS voltage across the load can be controlled. The trigger delay angle is defined as the phase angle (the value of t) at which the thyristor turns on and the load current begins to flow. CIRCUIT DIAGRAM:
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VII Sem ECE
R D 52
0 1 F M 7E F P Q = L = V = 1 0 0 5 1 k
D V O F F = 0 2 N 1 5 9 5 X 2 V A M P L = V = 5 8
V
V O 1 k V A N 4 F 0 R0
0
1 1 5 2 R 1 9 1 k R 1 k 7 2
X 3 2 N
9 VI5
1 k
V 5 V d c
1 2
GRAPH:
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. Use PSPICE simulator and run. 3. Note down the input voltages applied to the SCR, output voltage and current of SCR.
VII Sem ECE
4. Plot the Graph.
RESULT: Thus the phase controlled voltage regulator using full wave rectifier and SCR was constructed and output was verified. VIVA QUESTIONS: 1. 2. 3. 4. 5. What is meant by phase controlled voltage regulator? Explain the operation of the circuit. List the applications of SCR. What is firing angle? Give the methods to trigger the SCR?
3. DESIGN OF PROCESS CONTROL TIMER

AIM: Design a sequential timer to switch on & off 3 relays in a particular sequence using timer IC. SOFTWARE REQUIRED: OrCad THEORY: The process control is the activities involved in ensuring a process is predictable, stable and consistently operating at a level(target) of performance with only normal variation. The IC 555 is highly stable device for generating accurate time delay oscillations. The process control timer designed using timer IC555 is operated in either astable or monostable mode. There are three timers used to trigger the other timers through a switch control. The output of the next timer is obtained after a delay with respect to the delay in the triggering of the circuit. DESIGN: vc= Vcc (1 e-t/RC)
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VII Sem ECE
At t = T, vc= (2/3) Vcc Therefore, T=1.1RC Here, T=1.1 ms Assume C= 0.1uF R= R= 10K
CIRCUIT DIAGRAM:
d c 5 V 2 d c
0
4 R 2 V 1 V 2 T D T R T F P W P E = = = R = = = 5 0 0 0 0 = V 6
V
0
1 0 k 4 R 2 E 8 U 7 R O 1 2 1 0 k G E 2 L D . 1 1 u 2 4 R 2 . 1 u 3 2 E 8 1 1 2 0 k 5 V d c
8 S
3 R O 1 2 G
EV TC C 7 D I S C H A T R I G G E R6 T H R E S H O
E L D
3 1
0m
2
m 1
V
52 C O N T R O 1 L . 1 u 0 U T GP N D U T C 4 5 5 5 a .l t 1 u 1 1 2 2 1 k 1
S EV T C C 7 D I S C H A T R I G G E R6 T H R E S H O U C O T GP 1 5 N N U
2 . 1 u 1 22 R
52 T R O L D T . 1 u 5 5 a lt 1 1
9 R G
0
V
5 k
S EV TC C 7 D I S C H A T R I G G E R6 T H R E S H O
0
0 1 1 k 1 22
O L. 1 D u 52 C O N T R O 1 L U T GP N D U T 0 5 5 5 a .l t 1 u 1 1
0
V
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VII Sem ECE
TABULATION:
Timer 1 Timer 2 Timer 3
Time, t = Time, t = Time, t =
ms ms ms
Frequency= Frequency= Frequency=
Hz Hz Hz
GRAPH:
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. Use PSPICE simulator and run. 3. Note down the input voltages applied and the output at each stage. 4. Plot the Graph.
VII Sem ECE
RESULT: Thus a sequential timer was designed to switch on & off 3 relays in a particular sequence using timer IC. VIVA QUESTIONS: 1. 2. 3. 4. 5. List the application of the Timer. Explain the circuit operation What is a relay and give its uses? What do you mean by a process control timer? Why is monostable multivibrator used in the circuit?
4a)
AM MODULATOR / DEMODULATOR
AIM: To construct Amplitude Modulator circuit using multiplier IC and Demodulator circuit using envelop detector.
SOFTWARE REQUIRED: OrCad
THEORY:
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VII Sem ECE
Modulation is achieved by varying one of the three parameters, amplitude, frequency and phase in accordance with the message signal while keeping the other two parameters as constant. Hence the amplitude is varied in accordance with the instantaneous values of the low frequency signals. The frequency of the carrier is much greater than the amplitude of the modulating signal to avoid over modulation.
CIRCUIT DIAGRAM:
0 V 4
C 1 1 2 8 1 5 V d c D W 7 1 N 4 0 0 1 D 2 R 12
0
V 1 1 2 3 4 6
. 1 1 u X 1 X 2 Y 1 Y 2 Z V + 2 2
V V F
O A R
F M E
F P Q
= L = =
5 1 k
5 0 k D C 6 3 3 / A 3 2 D 1
V -
V V F
O A R
F M E
F P Q
= L = =
5 1 0 k
A 1
. 0 0 9 u C 4
. 1 u V 3 d c
0 0
1 5 V
Modulation Index =
GRAPH:
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VII Sem ECE
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. Use PSPICE simulator and run. 3. Note down the input voltages applied and output voltage 4. Also note down the demodulated output. 5. Plot the Graph and calculate the modulation index.
RESULT: Thus the message signal was modulated and demodulated. The modulation index was also calculated. VIVA QUESTIONS:
1. What is modulation and the need for it? Give its types.
2. 3. 4. 5.
What is an envelope detector? Explain the working of the circuit. What is demodulation? What is modulation index?
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VII Sem ECE
4.b FREQUENCY MODULATION AIM: To perform the Frequency modulation using IC 566 and to calculate the modulation index for various modulating voltages. HARDWARE REQUIRED: Frequency generator, IC NE566, Resistors, Capacitor, CRO, Bread board and connecting wires, RPS.
THEORY: Frequency modulation is a process of changing the frequency of a carrier wave in accordance with the slowly varying base band signal. The main advantage of this modulation is that it can provide better discrimination against noise. Frequency Modulation using IC 566: A VCO is a circuit that provides an oscillating signal whose frequency can be adjusted over a control by Dc voltage. VCO can generate both square and triangular wave signal whose frequency is set by an external capacitor and resistor and then varied by an applied DC voltage. IC 566 contains a current source to charge and discharge an external capacitor C 1 at a rate set by an external resistor. R1 and a modulating DC output voltage. The Schmitt trigger circuit present in the IC is used to switch the current source between charge and discharge capacitor and triangular voltage developed across the capacitor and the square wave from the Schmitt trigger are provide as the output of the buffer amplifier. The R2 and R3 combination is a voltage divider, the voltage VC must be in the range 3/4 VCC < VC < VCC. The modulating voltage must be less than 3/4VCC the frequency fc can be calculated using the formula fo = 2 (VCC-Vc) R1 C1 VCC. For a fixed value of VC and a constant C1 the frequency can be varied at 10:1 similarly for a constant R1 C1 product value the frequency modulation can be done at 10:1 ratio.
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VII Sem ECE
CIRCUIT DIAGRAM
pin diagram of NE566
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VII Sem ECE
GRAPH:
PROCEDURE: 1. The circuit connection is made as shown in the circuit diagram. 2. The modulating signal FM is given from a FG (1KHZ) 3. For various values of modulating voltage Vm the values of Fmax and Fmin are noted. 4. The values of the modulation index are calculated. RESULT: Thus the FM circuit using IC566 was performed and the modulation index was found. VIVA VOCE: 1. What will be the changes in the wave under FM when the amplitude or frequency of the modulating signal is increased ? 2. The FM station have less noise while receiving the signal. Justify your answer. 3. What happens when a stronger signal and a weaker signal both overlap at the same frequency in FM? 4. Name two applications of two way mobile radio? 5. Which mathematical expression is used to decide the side band amplitudes in a FM signal?
VII Sem ECE
5. DESIGN OF FSK MODULATOR USING XR 2206 AIM: To design a FSK Modulator using XR 2206.
COMPONENTS REQUIRED: IC XR 2206, Resistors, Capacitors.
THEORY: In digital data communication, binary code is transmitted by shifting the carrier frequency between two preset frequencies. This type of the transmission is called Frequency Shift Keying. The standard digital data input frequency is 150Hz. Modem takes the digital electrical pulses from the terminal and converts it into the analog signal that can be transmitted. The FSK technique is employed for the modulation of digital Signal.
CIRCUIT DIAGRAM:
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VII Sem ECE
GRAPH:
PROCEDURE:
VII Sem ECE
1. Connections are given as per the circuit diagram. 2. Give the message signal. 3. Check the output and verify. 4. Switch off the input to find the carrier frequency. 5. Plot the graph for input and output. RESULT: Thus a FSK was implemented using XR2206 and verified the results. VIVA QUESTIONS: 1. 2. 3. 4. 5. What is FSK? How is timer used to modulate the signal? Give the pin details of XR2206. List the applications of FSK. Explain the working of the circuit
6. PCB LAYOUT DESIGN USING CAD

AIM: To draw the schematic of simple electronic circuit and design a PCB layout using CAD
SOFTWARE REQUIRED: OrCad
THEORY:
The Computer Aided analysis is essential and can provide information about the circuit performances. It permits.
VII Sem ECE
Evaluation of effects of variation in elements such as resistors, transistors etc. The assessment of performance improvements or degradations.
Evaluation of the effects of noise and signal distortion without the need of
expensive measuring instruments.

Sensitivity analysis to determine the permissible bounds due to the tolerances
on
each and every element value or parameter of active elements. Evaluation of the effects of non-linear elements of the circuit performance. Optimization of the design of electronic circuits in terms of circuit parameters.
CIRCUIT DIAGRAM: Cascode Amplifier:

0
9 V 2 5 1 k 1 1 2 1 0 u 2 5 k 1 5 u 1 = 0 V 3 = Q = 2 0 0 1 k m 2 2 1 4 k 1 1 B 2 . 7 k 1 C 1 1 0 7 A 2 1 Q 2 5 u 2 B C 2 1 0 7 A 2 9 0 k 1 2 3 . 3 k d c
V V A F M
O P R
F L E
2 0 u
OUTPUT LAYERS:
Global Layer
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Top Layer
Bottom Layer
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PROCEDURE:
1. Draw the circuit diagram using Pspice and get the simulated output.
2. Create .mnl file Select the required file

Go to tools and select create netlist Click Layout from the dialog box appearing and give OK.
Note the path in which the .mnl file is created. 3. To create PCB Design Open OrCad Layout Plus
Make the data of OrCad Layout Plus to default
Take the .mnl file and save it.

Select the obstacle from tools and select all the components. Auto Auto
Place Auto route
Board Board
View the Global Layer. View the individual layers by selecting tools, layer. Give backspace and select the
layers.
RESULT: Thus a schematic of cascode amplifier circuit was designed and a PCB layout using CAD was obtained VIVA QUESTIONS: 1. What is netlist? 2. Define placement and routing.
VII Sem ECE
3. What is Layout? What is global layer 4. What are the advantages of PCB? 5. Explain the procedure to bring out the Layout of any electronic circuit using CAD
7.
PSUEDO-RANDOM SEQUENCE GENERATOR
AIM: To stimulate and implement a PRBS Generator.
SOFTWARES REQUIRED: PC with Xilinx ISE Software 9.1i
PROGRAM:
Simulation module prbs(rand,clk,reset); input clk,reset; output rand;

VII Sem ECE
wire rand; reg [3:0]temp; always @ (posedge reset) begin temp<=4hf; end always @ (posedge clk) begin if(~reset) begin temp<={temp[0]^temp[1],temp[3],temp[2],temp[1]}; end end assign rand =temp[0]; endmodule
Test Bench module prbstest(); reg clk,reset;

VII Sem ECE
wire rand; prbs p1(rand,clk,reset); initial begin forever begin clk<=0; #5 clk<=1; #5 clk<=0; end end initial begin reset=1; #12 reset=0; #90 reset=1; #12 reset=0; end endmodule
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PROCEDURE:
1. Write the coding. 2. Use Xilinx ISE simulator and run.
3. Note the output and verify.
RESULT: Thus a PRBS Generator is simulated in Verilog and implemented using Spartan3 FPGA kit.
VIVA QUESTIONS:
VII Sem ECE
1. 2.
What is PRBS Generator? Explain the program. 3. What is HDL and give its types? 4. What is shift register? 5. Give the specifications of Spartan3
8. SIMULATION OF ALU USING XILINX
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VII Sem ECE
AIM: To stimulate and implement an ALU using Xilinx.
SOFTWARES REQUIRED: PC with Xilinx ISE Software 9.1i ,
PROGRAM: module ALU(out,flag,sel,clear,a,b); output reg [3:0]out,flag; input [3:0]a,b,sel; input clear; reg [4:0]t; reg c,s,p,z; always @ (a or b or sel or clear) begin if(~clear) begin t=0; c=0;
VII Sem ECE
s=0; p=0; z=0; flag=0; end else begin if(sel[3]==1'b0) begin case(sel[2:0]) 3'b000: begin t=a+b; if(t[4]==1) c=1; else c=0; end 3'b001: begin t=a-b; if(t[4]==1) c=1; else c=0; end 3'b010: t=a[1:0]*b[1:0]; default t=9'b0; endcase if(a[3]^b[3]) s=1; else s=0; end else begin case(sel[2:0]) 3'b000:t=a|b;
VII Sem ECE
3'b001:t=a&b; 3'b010:t=a^b; 3'b011:t=(~a)|(~b); 3'b100:t=(~a)&(~b); 3'b101:t=a~^b; 3'b110:t=~a; 3'b111:t=~b; endcase end end end always @ (a or b or sel or clear) begin out=t[3:0]; p=out[0]+out[1]+out[2]+out[3]; if (t==0) z=1; else z=0; assign flag[0]=p; assign flag[1]=s; assign flag[2]=c;
VII Sem ECE
assign flag[3]=z; end endmodule
PROCEDURE:
1. Write the coding. 2. Use Xilinx ISE simulator and run.
3. Note the output and verify.
RESULT:
Thus a ALU is simulated in Verilog and implemented using Spartan3 FPGA kit VIVA QUESTIONS: 1. 2. 3. 4. 5. Explain the logic of the program. What is ALU? What is Xilinx ISE Simulator? What is the use of a simulator? Write a program to implement Y= AB + C.
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Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

DESIGN OF A 4-20mA TRANSMITTER FOR A BRIDGE TYPE TRANSDUCER.

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Electronics System Design Lab

VII Sem ECE

5. Plot the variation of resistance Vs output current.

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

2. AC/DC VOLTAGE REGULATOR USING SCR

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Electronics System Design Lab

VII Sem ECE

4. Plot the Graph.

3. DESIGN OF PROCESS CONTROL TIMER

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Timer 1 Timer 2 Timer 3

Time, t = Time, t = Time, t =

Frequency= Frequency= Frequency=

Electronics System Design Lab

VII Sem ECE

SOFTWARE REQUIRED: OrCad

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

pin diagram of NE566

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE

Electronics System Design Lab

VII Sem ECE

COMPONENTS REQUIRED: IC XR 2206, Resistors, Capacitors.

Jerusalem College of Engineering

Electronics System Design Lab

VII Sem ECE