VLSI

Prof. Vojin G. Oklobdzija

References (used for creation of the presentation material):

[1] Mead, Conway, Introduction to VLSI Systems, Addison Wesley Publishing. [2] Glasser, Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison Wesley Publishing. [3] Weste, Eshraghian, Principles of CMOS VLSI Design, Addison Wesley Publishing. [4] Shoji, CMOS Digital Circuits Technology, Prentice Hall.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Historical Overview
nMOS era: 1970-85 Pass-transistor design Domino CMOS, 1982
NORA DCVSL

CPL, DPL
DCVS-PG SRPL LEAP

SOI-CMOS
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 2

n-MOS Design Era

LSI started with nMOS: pass-transistor design experience:
- Flourished at the beginning of the nMOS era (popularized by Mead-Conway book) - Allows high density layout and compact design style - Fast: outperforming gate based design - Low in power

Drawbacks:
Not compatible with existing design tools Exhibiting testability and reliability problems

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Pass-Transistor Design
Another way of looking at Karnaugh Map: AND function

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Pass-Transistor Design

A
B
AB AB AB AB AB
A B

B
Two-variable function

B
B
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits

B A B A B
5

Pass-Transistor Design
Threshold Voltage Drop problem:

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Pass-Transistor Design
Solving the Threshold Voltage Drop problem in CMOS:

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Pass-Transistor Design

Function Generator
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Pass-Transistor Design
Full 1-bit Adder

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Pass-Transistor Design
Compact ALU Example (IBM PC/RT) Circ. 1984

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Control Lines A - inputs Odd Operation Arithmetic A+B A+B+1 A-B B-A B+1 +1 A+1 +1 Logical 1 B 1 1 1 1 1 1 1 0 1 1 A 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Subtract Subtract Increment 2s compl Increment 2s compl Add 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 K1 K2 Qn A A Even B Odd B B - inputs Even Odd

Output Control

Even

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1

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Advanced Digital Integrated Circuits

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Pass-Transistor Design
Compact ALU Example (IBM PC/RT)

H

CI

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Using Pass-Transistor Design to Speed-up Addition

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Review of CMOS
Prof. Vojin G. Oklobdzija

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Advanced Digital Integrated Circuits

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CMOS Basics

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CMOS Basics

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CMOS Basics

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CMOS Basics
A complex path example:

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CMOS Basics
Primitive gates: More complex blocks are realizable in CMOS

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CMOS Deficiencies:
Various remedies:

Muli-Input NOR function in CMOS is slow

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CMOS Deficiencies and Remedies

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CMOS Deficiencies and Remedies

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CMOS Basic
Inverter Transfer function:
Logic voltage levels are VOH and VOL and VIL and VIH The inverter transfer function lie within the shaded region

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CMOS Basic: Inverter Characteristic

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CMOS Basic: Inverter Characteristic

T2

td tf
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CL

tr
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CMOS Basic: Inverter Characteristic

Transistors during the transition

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CMOS Basic: Inverter Switching

VO } VDD  Vin

0 VO } VDD  Vin

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CMOS Basic: Power

During the static state there is no current Current is only present during transistion: Short circuit current (crow-bar current) Charging and discharging of the output capacitor Leakage Current

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CMOS Basic: Power

PCMOS=kCLV2DDfo
This is an E=mc2 of low-power design
There are three ways to control power:
- Reducing Power-Supply Voltage (most effective !!) - Reducing the switching activity k (various ways) - Reducing CL (technology scaling etc.) - Reducing the required frequency of operation (?)

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

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CMOS Basic: Delay

Which one of the three designs is the fastest ? How can we find this out without simulation ?
a7

a0

a7 a6 a5 a4 a3 a a1
a
a7 a4 a3

Learn about Logical Effort !

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CMOS Basic: Delay

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CMOS Basic: Delay

Delay can be approximated with:

RND7Cin1+RNORCin2+RND2Cout
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CMOS Basic: Delay

Delay of a signal path in CMOS logic is dependent on: Fan-in of a gate
Represented as a resistance of the pull-up/down transistor path of the gate

Fan-out of a gate
Represented as a capacitive load at the output

Number of CMOS blocks in the path. Wire delay connecting various blocks.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

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CMOS Basic: Delay

Delay of a signal path in CMOS logic can be reduced by: Making the transistors larger in order to minimize resistance of a pull-up/down path in the gate Making the transistors smaller in order to minimize the capacitive load of each gate Reducing the number of CMOS blocks in the path. Bringing the blocks closer and/or choosing the less wire intensive topology.
Note that these requirements are often contradictory

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CMOS Basic: Delay

How to estimate delay and critical timing in CMOS circuits ? How to determine the proper transistor sizing in order to make a compromise with contradicting requirements ? How to choose the right circuit topology ? The Answer: Logical Effort
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