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Set
S 0 0 1 1
R 0 1 0 1
Q Q 0 1 0
Q Q 1 0 0
Cross-NAND SR flip-flop
Reset Q
Set
6.071 Digital Logic
S 0 0 1 1
R 0 1 0 1
Q 1 0 1 Q
Q 1 1 0 Q
Slide 2
Clocked Level-Triggered NAND SR Flip-Flop
R CLK NAND enable gates Q SR flip-flop Q
CLK 0 0 0 0 1 1 1 1
6.071 Digital Logic
S 0 0 1 1 0 0 1 1
R 0 1 0 1 0 1 0 1
Q Q Q Q Q 0 0 1 Q
Q Q Q Q Q 0 1 0 Q
hold hold SR inputs hold disabled hold hold reset SR inputs set enabled indeterminate
2
Slide 3
Edge-Triggered SR Flip-Flops We can make the level triggered flip-flop more flexible (in terms of timing control) by turning it into an edge-triggered flip-flop. An edge-triggered flip-flop only samples the inputs during either a positive or negative clock edge. This conversion can be done by taking the clock signal and running it through a level-triggered, pulse generator network and taking the corresponding output as the clock signal.
Positive edge-triggered CLK delay gate X Y Z Negative edge-triggered CLK CLK delay gate X Y Z
CLK X Y Z
6.071 Digital Logic
CLK CLK X Y Z
Slide 4
Level and Edge Triggered Flip-Flop Symbols
no triangle means level-triggered triangle means edge-triggered
S CLK R
S CLK R
Q Q
Q Q
inverted output (complement)
S CLK R
Q CLK Q R S
no bubble next to triangle means positive edge-triggered input
Q Q
edge-triggered
S CLK R
bubble next to triangle means negative edge-triggered input
6.071 Digital Logic
Q CLK Q R S
Q Q
Slide 5
D-Type Flip-Flops D 0 1 Q 0 1 Q 1 Reset 0 Set
logic symbol
D R NAND made into an inverter SR flip-flop Q
Q Q Q
Slide 6
Divide by Two Circuit
D CLK Note: Edge Detector CLK Q Q D Q At clock pulse edge, Q goes to D Q
So every time there is a clock pulse, Q is set to the old value of D. Therefore, Q changes (as does D) but by the time D changes, the edge is past.
6.071 Digital Logic 6
Slide 7
Stop-Go Indicator
D Q Q red green
300
Slide 8
Divide-by-Two Counter
Slide 9
Synchronizer
A
stop start D CLK Q Q Q
A D Q B
Slide 10
Synchronizer 2 We see timing is important, so we want to synchronize signals.
On/Off D CLK Q out Q
off
on
off
10
Slide 11
JK Flip-Flops
J Clock (C) K
pulse generator
Q Q
Slide 12
JK Flip-Flops 2
0 R
Rin is (0,X) output is high; Sin is (0,1) output is high. all outputs are high.
The problem is that you can not hold this condition. The input 1,1 can only hold outputs of (0,1) or (1,0).
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Slide 13
JK Flip-Flops 3 C 0 1 Positive edge-trigger J K Q Q Q Q hold X X X X Q Q hold X X Q Q hold Q Q hold 0 0 0 1 0 1 Reset 1 0 1 0 Set Q Q Toggle 1 1
C 0 1
Slide 14
JK Flip-Flop with Preset and Clear
Q PRE K CLK
Q CLR J
14
Slide 15
JK Flip-Flop with Preset and Clear (Negative Edge-Triggered) PRE CLR CLK X 1 0 X 0 1 X 0 0 1 1 1 1 1 1 1 1 1 1 0,1 J X X X 0 0 1 1 1 K X X X 0 1 0 1 1 Q Q 1 0 0 1 1 1 Q0 Q0 0 0 0 0 Q0 Q0 Q0 Q0
PRE
J C K CLR
Q Q
Slide 16
JK Flip-Flop with Preset and Clear (Positive Edge-Triggered) PRE CLR CLK X 1 0 X 0 1 X 0 0 1 1 1 1 1 1 1 1 1 1 0,1 J X X X 0 0 1 1 1 K X X X 0 1 0 1 1 Q Q 1 0 0 1 1 1 Q0 Q0 0 0 0 0 Q0 Q0 Q0 Q0
PRE
J C K CLR
Q Q
Slide 17
MOD-16 Ripple Counter/divide-by-2,4,8,16 Counter +5V
J PRE Q J PRE Q J PRE Q J PRE Q
CLK CLR
Q K CLR
Q K CLR
K Q CLR
K Q CLR
divide-by-2
divide-by-4 Q1
divide-by-8 Q2
divide-by-16 Q3 (MSB)
0000 0
17
Slide 18
MOD-16 Ripple Counter 2 +5V
J PRE Q J PRE Q J PRE Q J PRE Q
Q K CLR
Q K CLR
K Q CLR
K Q CLR
CLR
Q0 Q1 Q2 Q3
CLK This circuit will count to up to 15 and then will disable (all bits = 0). Note: If one uses the Qs as the counting bits instead of the Qs, the Counter will count down from 15 and disable when 0 is reached.
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Slide 19
MOD-16 Synchronous Counter +5V
J PRE Q J PRE Q J PRE Q J PRE Q
CLK CLR
K Q CLR
K Q CLR
Q K CLR
Q K CLR
divide-by-2 (LSB) Q0
divide-by-4 Q1
divide-by-8 Q2
divide-by-16 (MSB) Q3
CLR CLK Q0 Q1 Q2 Q3
0000 0
19
Slide 20
4-Bit Counter IC The 7493s internal structure consists of four JK flip-flops connected to provide separate MOD-2 and MOD-8 sections. Both of these are clocked by separate clock inputs. The MOD-2 uses Cp0 as its clock input while MOD-8 uses Cp1. Cp0 Cp1 MR 12 2 3 MR1 MR2 Q0 L Q1 Q2 Q3 L L count count count L
14 1
7493
Q0 Q1 Q2 Q3 12 9 8 11
H L H L
H H L L
20
Slide 21
74193 Presettable 4-bit Binary Up/Down Counter
11 PL 5 4 CPU CPD MR 14 Inputs MR1 PL CpU CpD Reset Parallel load H H L L L H H L X X L L L L H H X X X L H H H L H L X X H H D0 D1 D2 D3 X X L H H L X X X X L H H L X X X X L H H L X X X X L H H L X X 15 D0 Q0 3 1 10 D1 D2 TC U 9 D3 12 13
Q1 Q2 TCD Q3 2 6 7
H = HIGH voltage level; L = LOW voltage level; X = dont care; = LOW-to-HIGH voltage transition 6.071 Digital Logic 21
Slide 22
Block Diagrams of Various Shift Registers Serial in / Serial out:
Serial in 010 1 0 1 1 0 1 0 0 Serial out 0 0 1
Parallel out 1 1 0 1 0 0 1 1 0 1 0 0
22
1 0
Slide 23
Creating Devices toff
ton
ton
Some device creating power There are two modes for destruction 1.) Short term ton is too long. Instantaneous heat load too high. Assume no heat dissipation during ton. 2.) long term - duty cycle ton/toff too high. Test for 2 conditions n-bits ton < tmax ton/toff < duty cycle MSB LSB
overflow up counter down zero? reset
If overflow trigger relay tc 2n = tmax If zero disable, clock until next edge of ON
23
ON
ON
Slide 24
Problem Explain why mon-stable is not so useful. Solve problem using: 1x 555 - clock flip/flops, simple logic 1x up/down counter borrow carry clear
24
Slide 25
4-bit Serial in/Serial out Shift Registers
Serial in 010 Serial Input D3 Q3 CLK f-f 0 Shift Right 1 0 1 1 D2 Q2 CLK f-f 0 D1 Q1 CLK f-f 0 Serial out 001 D0 Q0 CLK f-f 0 Serial Output
clock Serial out 100 Serial Output Shift Left 1 1 0 1 Serial in 010 Serial Input
D0 Q0 CLK f-f 0
D1 Q1 CLK f-f 1
D2 Q2 CLK f-f 2
D3 Q3 CLK f-f 3
clock
6.071 Digital Logic 25
Slide 26
Parallel-to-Serial Shift Register
SHIFT/LOAD
SHIFT LOAD
D0
D1
D2
D3
D0 Q0 CLK f-f 0
D1 Q1 CLK f-f 1
D2 Q2 CLK f-f 2
D3 Q3 CLK f-f 3
Serial output
Serial Shift 26
Slide 27
JK Parallel-to-Serial Shift Register
Serial output
27
Slide 28
8-Bit Serial-to-Parallel Data Converter
+5V 9 2 Serial data input clock 14 VCC MR DSb
Sa
1 Q0 3 Q1 4 Q 5 Q3 6 Q4 10 Q 11 Q6 12 Q7 13
5 2
1D 8
3D 0 4D 1 7D 8D 3 13 D 4 14 D 17 D 6 18 D 7 CLK
5 2
CLK
28
Slide 29
8-Bit Parallel-to-Serial Interface
+5V 0 0 1 0 0 1 1 0 11 12 13 14 3 4 5 6 1 15 2 D0 D1 D2 D3 D4 D5 D6 D7 PL CE CLK GND DS 10 8 16 VCC
Q7 Q7
9 7
Serial Device
29