Tutorial Example 5-1

A B C P4

P3

P2

P1

P0

Multiplier logic circuit

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Tutorial Example 5-2

SEL D0 Y D1

1-out-of-2 data selector circuit

S1 S0 D0 D1 SEL D0 data_sel2 D1 Y SEL D0 data_sel2 D1 D2 D3 SEL D0 data_sel2 D1 Y Y Y

Block diagram for 1-out-of-4 data selector circuit

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Tutorial Example 6-1

SUBDESIGN 2bit_compare ( a[1..0], b[1..0] :INPUT; % a[1..0] and b[1..0] are the two, 2-bit inputs % gt, lt, eq :OUTPUT; ) % solution 1 % BEGIN -- functions defined with Boolean expressions gt = a1 & !b1 # a0 & !b1 & !b0 # a1 & a0 & !b0; lt = !a1 & b1 # !a0 & b1 & b0 # !a1 & !a0 & b0; eq = !gt & !lt; % Boolean symbols & AND # OR ! NOT % END;

SUBDESIGN 2bit_compare ( a[1..0], b[1..0] gt, lt, eq ) % solution 2 % BEGIN gt = a[] > b[]; lt = a[] < b[]; eq = a[] == b[]; END;

:INPUT; :OUTPUT;

-- gt is high if a > b -- lt is high if a < b -- eq is high if a = b

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SUBDESIGN 2bit_compare ( a[1..0], b[1..0] :INPUT; gt, lt, eq :OUTPUT; ) % solution 3 % BEGIN IF a[] > b[] -- 1st expression tested THEN gt = VCC; lt = GND; eq = GND; ELSIF a[] < b[] -- 2nd expression tested THEN gt = GND; lt = VCC; eq = GND; ELSE gt = GND; lt = GND; eq = VCC; END IF; END;

SUBDESIGN 2bit_compare ( a[1..0], b[1..0] :INPUT; gt, lt, eq :OUTPUT; ) % solution 4 % BEGIN TABLE -- truth table format a[], b[] => gt, lt, B"00", B"00" => 0, 0, B"00", B"01" => 0, 1, B"00", B"10" => 0, 1, B"00", B"11" => 0, 1, B"01", B"00" => 1, 0, B"01", B"01" => 0, 0, B"01", B"10" => 0, 1, B"01", B"11" => 0, 1, B"10", B"00" => 1, 0, B"10", B"01" => 1, 0, B"10", B"10" => 0, 0, B"10", B"11" => 0, 1, B"11", B"00" => 1, 0, B"11", B"01" => 1, 0, B"11", B"10" => 1, 0, B"11", B"11" => 0, 0, END TABLE; END;

eq; 1; 0; 0; 0; 0; 1; 0; 0; 0; 0; 1; 0; 0; 0; 0; 1;

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ENTITY two_bit_compare IS PORT ( a : IN BIT_VECTOR (1 DOWNTO 0); b : IN BIT_VECTOR (1 DOWNTO 0); -- a & b inputs are each 2-bit arrays gt : OUT BIT; lt : OUT BIT; eq : OUT BIT -- each output is a single bit ); END two_bit_compare; ARCHITECTURE soln1 OF two_bit_compare IS BEGIN -- Boolean expressions for each output gt <= (a(1) AND NOT b(1)) OR (a(0) AND NOT b(1) AND NOT b(0)) OR (a(1) AND a(0) AND NOT b(0)); lt <= (NOT a(1) AND b(1)) OR (NOT a(0) AND b(1) AND b(0)) OR (NOT a(1) AND NOT a(0) AND b(0)); eq <= NOT (a(1) XOR b(1)) AND NOT (a(0) XOR b(0)); END soln1;

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ENTITY two_bit_compare IS PORT ( a : IN INTEGER RANGE 0 TO 3; b : IN INTEGER RANGE 0 TO 3; -- integer inputs will have numerical values gt : OUT BIT; lt : OUT BIT; eq : OUT BIT ); END two_bit_compare; ARCHITECTURE soln2 OF two_bit_compare IS BEGIN PROCESS (a, b) -- a & b are in sensitivity list BEGIN -- 1st IF that tests true makes signal assignments IF (a > b) THEN gt <= '1'; lt <= '0'; eq <= '0'; ELSIF (a < b) THEN gt <= '0'; lt <= '1'; eq <= '0'; ELSE gt <= '0'; lt <= '0'; eq <= '1'; END IF; END PROCESS; END soln2;

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ENTITY two_bit_compare IS PORT ( a : IN INTEGER RANGE 0 TO 3; b : IN INTEGER RANGE 0 TO 3; -- a & b will have numerical values as integers gt : OUT BIT; lt : OUT BIT; eq : OUT BIT ); END two_bit_compare; ARCHITECTURE soln3 OF two_bit_compare IS BEGIN PROCESS (a, b) -- change on a or b invokes process BEGIN CASE a IS WHEN 0 => CASE b IS WHEN 0 gt <= WHEN 1 gt <= WHEN 2 gt <= WHEN 3 gt <= END CASE; WHEN 1 => CASE b IS WHEN 0 gt <= WHEN 1 gt <= WHEN 2 gt <= WHEN 3 gt <= END CASE; -- 1st case evaluates a value

-=> '0'; => '0'; => '0'; => '0';

2nd case evaluates b value lt <= '0'; lt <= '1'; lt <= '1'; lt <= '1'; eq <= '1'; eq <= '0'; eq <= '0'; eq <= '0';

=> '1'; => '0'; => '0'; => '0';

lt <= '0'; lt <= '0'; lt <= '1'; lt <= '1';

eq <= '0'; eq <= '1'; eq <= '0'; eq <= '0';

(continued)

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WHEN 2 => CASE b IS WHEN 0 gt <= WHEN 1 gt <= WHEN 2 gt <= WHEN 3 gt <= END CASE; WHEN 3 => CASE b IS WHEN 0 gt <= WHEN 1 gt <= WHEN 2 gt <= WHEN 3 gt <= END CASE; END CASE; END PROCESS; END soln3;

=> '1'; => '1'; => '0'; => '0';

lt <= '0'; lt <= '0'; lt <= '0'; lt <= '1';

eq <= '0'; eq <= '0'; eq <= '1'; eq <= '0';

=> '1'; => '1'; => '1'; => '0';

lt <= '0'; lt <= '0'; lt <= '0'; lt <= '0';

eq <= '0'; eq <= '0'; eq <= '0'; eq <= '1';

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ENTITY two_bit_compare IS PORT ( a : IN BIT_VECTOR (1 DOWNTO 0); b : IN BIT_VECTOR (1 DOWNTO 0); -- bit vectors do not have a value gt : OUT BIT; lt : OUT BIT; eq : OUT BIT ); END two_bit_compare; ARCHITECTURE soln4 OF two_bit_compare IS SIGNAL input : BIT_VECTOR (3 DOWNTO 0); SIGNAL output : BIT_VECTOR (2 DOWNTO 0); -- these signals are created for our convenience BEGIN input <= a & b; WITH input SELECT output <= -- concatenates input bits -- input selects output "001" WHEN "0000", "010" WHEN "0001", "010" WHEN "0010", "010" WHEN "0011", "100" WHEN "0100", "001" WHEN "0101", "010" WHEN "0110", "010" WHEN "0111", "100" WHEN "1000", "100" WHEN "1001", "001" WHEN "1010", "010" WHEN "1011", "100" WHEN "1100", "100" WHEN "1101", "100" WHEN "1110", "001" WHEN "1111"; -- connect array bits to ports

gt <= output(2); lt <= output(1); eq <= output(0); END soln4;

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Tutorial Example 6-2

SUBDESIGN codes ( in[3..0] :INPUT; out[3..0] :OUTPUT; ) % solution 1 % BEGIN DEFAULTS out[] = B"1111"; -- default outputs END DEFAULTS; TABLE -- truth table defines valid BCD inputs in[] => out[]; % 2421 BCD 5421 BCD % B"0000" => B"0000"; B"0001" => B"0001"; B"0010" => B"0010"; B"0011" => B"0011"; B"0100" => B"0100"; B"1011" => B"1000"; B"1100" => B"1001"; B"1101" => B"1010"; B"1110" => B"1011"; B"1111" => B"1100"; END TABLE; END;

SUBDESIGN codes ( in[3..0] :INPUT; out[3..0] :OUTPUT; ) % solution 2 % BEGIN -- select appropriate output with IFs IF in[] == B"0000" THEN out[] = B"0000"; ELSIF in[] == B"0001" THEN out[] = B"0001"; ELSIF in[] == B"0010" THEN out[] = B"0010"; ELSIF in[] == B"0011" THEN out[] = B"0011"; ELSIF in[] == B"0100" THEN out[] = B"0100"; ELSIF in[] == B"1011" THEN out[] = B"1000"; ELSIF in[] == B"1100" THEN out[] = B"1001"; ELSIF in[] == B"1101" THEN out[] = B"1010"; ELSIF in[] == B"1110" THEN out[] = B"1011"; ELSIF in[] == B"1111" THEN out[] = B"1100"; ELSE out[] = B"1111"; END IF; END;

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SUBDESIGN codes ( in[3..0] :INPUT; out[3..0] :OUTPUT; ) % solution 3 % BEGIN -- selects appropriate output with CASE CASE in[] IS WHEN B"0000" => out[] = B"0000"; WHEN B"0001" => out[] = B"0001"; WHEN B"0010" => out[] = B"0010"; WHEN B"0011" => out[] = B"0011"; WHEN B"0100" => out[] = B"0100"; WHEN B"1011" => out[] = B"1000"; WHEN B"1100" => out[] = B"1001"; WHEN B"1101" => out[] = B"1010"; WHEN B"1110" => out[] = B"1011"; WHEN B"1111" => out[] = B"1100"; WHEN OTHERS => out[] = B"1111"; END CASE; END;

SUBDESIGN codes ( in[3..0] :INPUT; out[3..0] :OUTPUT; ) % solution 4 % BEGIN -- define outputs with Boolean expressions out3 = in3 # in2 & in0 # in2 & in1; out2 = !in3 & in2 # in3 & !in2 & !in1 # in3 & !in2 & !in0 # in2 & in1 & in0; out1 = in1 & !in0 # !in3 & in1 # in2 & !in1 & in0 # in3 & !in2 & !in1; out0 = !in3 & in0 # in3 & !in0 # in3 & !in2 & !in1 # !in3 & in2 & in1; END;

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ENTITY code IS PORT ( d, c, b, a p, q, r, s ); END code;

: IN BIT; : OUT BIT

ARCHITECTURE solution1 OF code IS SIGNAL input : BIT_VECTOR (3 DOWNTO 0); SIGNAL output : BIT_VECTOR (3 DOWNTO 0); BEGIN input <= d & c & b & a; p q r s <= <= <= <= output(3); output(2); output(1); output(0);

-- concatenation of input bits -- connect array bit to output

WITH input SELECT output <=

"0000" "0001" "0010" "0011" "0100" "1000" "1001" "1010" "1011" "1100" "1111"

-- input selects output pattern WHEN "0000", WHEN "0001", WHEN "0010", WHEN "0011", WHEN "0100", WHEN "1011", WHEN "1100", WHEN "1101", WHEN "1110", WHEN "1111", WHEN OTHERS;

END solution1;

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ENTITY code IS PORT ( d, c, b, a p, q, r, s ); END code;

: IN BIT; : OUT BIT

ARCHITECTURE solution2 OF code IS SIGNAL input : BIT_VECTOR (3 DOWNTO 0); SIGNAL output : BIT_VECTOR (3 DOWNTO 0); BEGIN input <= d & c & b & a; -- concatenates inputs p <= output(3); -- output array to ports q <= output(2); r <= output(1); s <= output(0); PROCESS (input) BEGIN IF input ELSIF input ELSIF input ELSIF input ELSIF input ELSIF input ELSIF input ELSIF input ELSIF input ELSIF input ELSE END IF; END PROCESS; END solution2; -- change on input invokes process = = = = = = = = = = "0000" "0001" "0010" "0011" "0100" "1011" "1100" "1101" "1110" "1111" THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN output output output output output output output output output output output <= <= <= <= <= <= <= <= <= <= <= "0000"; "0001"; "0010"; "0011"; "0100"; "1000"; "1001"; "1010"; "1011"; "1100"; "1111";

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ENTITY code IS PORT ( d, c, b, a p, q, r, s ); END code;

: IN BIT; : OUT BIT

ARCHITECTURE solution3 OF code IS SIGNAL input : BIT_VECTOR (3 DOWNTO 0); SIGNAL output : BIT_VECTOR (3 DOWNTO 0); BEGIN input <= d & c & b & a; -- concatenates inputs p <= output(3); -- connects output ports q <= output(2); r <= output(1); s <= output(0); PROCESS (input) BEGIN CASE input WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN END CASE; END PROCESS; END solution3; -- change on input invokes process IS "0000" "0001" "0010" "0011" "0100" "1011" "1100" "1101" "1110" "1111" OTHERS

=> => => => => => => => => => =>

output output output output output output output output output output output

<= <= <= <= <= <= <= <= <= <= <=

"0000"; "0001"; "0010"; "0011"; "0100"; "1000"; "1001"; "1010"; "1011"; "1100"; "1111";

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ENTITY code IS PORT ( d, c, b, a p, q, r, s ); END code;

: IN BIT; : OUT BIT

ARCHITECTURE solution4 OF code IS SIGNAL nd, nc, nb, na : BIT; BEGIN nd nc nb na <= <= <= <= NOT NOT NOT NOT d; c; b; a;

-- buried nodes

p <= d OR (c AND a) OR (c AND b); q <= (nd AND c) OR (d AND nc AND nb) OR (d AND nc AND na) OR (c AND b AND a); r <= (b AND na) OR (nd AND b) OR (c AND nb AND a) OR (d AND nc AND nb); s <= (nd AND a) OR (d AND na) OR (d AND nc AND nb) OR (nd AND c AND b); END solution4;

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Tutorial Example 6-3

SUBDESIGN multiplexer ( en, d[3..0], s[1..0] y ) % solution 1 % VARIABLE sel[3..0] BEGIN sel0 sel1 sel2 sel3 = !s1 & !s0; = !s1 & s0; = s1 & !s0; = s1 & s0; -- define 4 select combinations

:INPUT; :OUTPUT;

:NODE;

-- buried nodes

-- Boolean expression to route selected input to y y = (d0 & sel0 # d1 & sel1 # d2 & sel2 # d3 & sel3) & en; END;

SUBDESIGN multiplexer ( en, d[3..0], s[1..0] :INPUT; y :OUTPUT; ) % solution 2 % BEGIN -- IFs 1st determine desired output when enabled IF s[] == 0 & en THEN y = d0; ELSIF s[] == 1 & en THEN y = d1; ELSIF s[] == 2 & en THEN y = d2; ELSIF s[] == 3 & en THEN y = d3; ELSE y = GND; -- output if disabled END IF; END;

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SUBDESIGN multiplexer ( en, d[3..0], s[1..0] :INPUT; y :OUTPUT; ) % solution 3 % BEGIN -- uses nested IFs IF en THEN -- evaluate 2nd IF when 1st one true IF s[] == 0 THEN y = d0; ELSIF s[] == 1 THEN y = d1; ELSIF s[] == 2 THEN y = d2; ELSE y = d3; END IF; ELSE y = GND; -- disabled output END IF; END;

SUBDESIGN multiplexer ( en, d[3..0], s[1..0] :INPUT; y :OUTPUT; ) % solution 4 % BEGIN -- CASE nested inside IF statement IF en THEN -- evaluate CASE when enable is true CASE s[] IS WHEN 0 => y = d0; WHEN 1 => y = d1; WHEN 2 => y = d2; WHEN 3 => y = d3; END CASE; ELSE y = GND; -- output when disabled END IF; END;

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ENTITY multiplexer IS PORT ( en : IN BIT; d : IN BIT_VECTOR (3 DOWNTO 0); s : IN BIT_VECTOR (1 DOWNTO 0); y : OUT BIT ); END multiplexer; ARCHITECTURE boolean OF multiplexer IS SIGNAL sel : BIT_VECTOR (0 TO 3); BEGIN sel(0) <= '1' WHEN (s = "00") ELSE '0'; sel(1) <= '1' WHEN (s = "01") ELSE '0'; sel(2) <= '1' WHEN (s = "10") ELSE '0'; sel(3) <= '1' WHEN (s = "11") ELSE '0'; y <= ((d(0) AND OR (d(1) AND OR (d(2) AND OR (d(3) AND END boolean;

-----

conditional signal assignment statements

sel(0)) -- Boolean expression sel(1)) sel(2)) sel(3))) AND en;

ENTITY multiplexer IS PORT ( en : IN BIT; d : IN BIT_VECTOR (3 DOWNTO 0); s : IN BIT_VECTOR (1 DOWNTO 0); y : OUT BIT ); END multiplexer; ARCHITECTURE ifand OF multiplexer IS BEGIN PROCESS (en, d, s) -- process with sensitivity list BEGIN IF (s = "00" AND en = '1') THEN y <= d(0); ELSIF (s = "01" AND en = '1') THEN y <= d(1); ELSIF (s = "10" AND en = '1') THEN y <= d(2); ELSIF (s = "11" AND en = '1') THEN y <= d(3); ELSE y <= '0'; -- disabled output END IF; END PROCESS; END ifand;

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ENTITY multiplexer IS PORT ( en : IN BIT; d : IN BIT_VECTOR (3 DOWNTO 0); s : IN BIT_VECTOR (1 DOWNTO 0); y : OUT BIT ); END multiplexer; ARCHITECTURE nestif OF multiplexer IS BEGIN PROCESS (en, d, s) -- process with sensitivity list BEGIN IF (en = '1') THEN -- nested IFs IF (s = "00") THEN y <= d(0); ELSIF (s = "01") THEN y <= d(1); ELSIF (s = "10") THEN y <= d(2); ELSE y <= d(3); END IF; ELSE y <= '0'; -- disabled output END IF; END PROCESS; END nestif;

ENTITY multiplexer IS PORT ( en : IN BIT; d : IN BIT_VECTOR (3 DOWNTO 0); s : IN BIT_VECTOR (1 DOWNTO 0); y : OUT BIT ); END multiplexer; ARCHITECTURE ifcase OF multiplexer IS BEGIN PROCESS (en, d, s) -- process with sensitivity list BEGIN IF (en = '1') THEN -- IF with nested CASE CASE s IS WHEN "00" => y <= d(0); WHEN "01" => y <= d(1); WHEN "10" => y <= d(2); WHEN "11" => y <= d(3); END CASE; ELSE y <= '0'; -- disabled output END IF; END PROCESS; END ifcase;

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ENTITY multiplexer IS PORT ( en : IN BIT; d : IN BIT_VECTOR (3 DOWNTO 0); s : IN BIT_VECTOR (1 DOWNTO 0); y : OUT BIT ); END multiplexer; ARCHITECTURE assign OF multiplexer IS BEGIN -- conditional signal assignment statement y <= d(0) WHEN s = "00" AND en = '1' ELSE d(1) WHEN s = "01" AND en = '1' ELSE d(2) WHEN s = "10" AND en = '1' ELSE d(3) WHEN s = "11" AND en = '1' ELSE '0'; -- disabled END assign;

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