Section: TE-C Roll #

Computer Organization and Architecture TE-C

Wednesday, May 16, 2007
QUIZ # 6: RISC PIPELINE
Max Marks = 15; Max Time: 15 minutes
A RISC processor has the following pipeline stages (Not all the stages are used for all the instructions,
therefore please do not use a stage if not used by the instruction):
• IFD : Instruction fetch & decode
• RR: Register(s) Read
• EAL: Execute ALU Operation
• RW: Register Write
• TSF: Test Status Flag i.e. a carry flag for a conditional branch
• MR: Memory to Register Transfer
• RM: Register to Memory Transfer

For the following Instructions in Table A (location A100 contains value 100).
No. Address Instruction Operation
1 FF00 MOV #200 AC  200
2 FF01 MOV R1, (A100) R1  (A100)
3 FF02 SUB R1 AC  AC – R1
4 FF03 BRZ FF00 If Zero flag is set jump to
the address FF00 i.e. PC 
FF00
5 FF04 STORE (A100) AC  (A100)

Please complete the pipeline in Table B. Please watch out for data dependencies and insert NOOP (No
Operation) Instruction where needed.

TABLE B – TIME 
PIPELINE T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
Stgaes
Instruction
No.
1 (1) IFD RW
2 (2) IFD MR
3 (3) IFD RR EAL RW
4(NOOP) IFD
5 (NOOP) IFD
6 (4) IFD RR TSF
7 (NOOP) IFD
8 (NOOP) IFD
9 (5) IFD RR RM
The values in brackets show the original instruction number from Table A