Compal Confidential: Schematics Document DT Transport or Prescott Ufcpga With ATI-RC300M+SB200 Core Logic

A
LA-2411
1
Compal confidential
Schematics Document
DT TRANSPORT or Prescott uFCPGA
with
ATI-RC300M+SB200 core logic
2004-06-28
REV:0.3
Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Cover Sheet
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
of
65
Compal confidential
File Name :LA2411
Fan Control
page 7
Intel Northwood/Prescott Processor

uFCBGA-479/uFCPGA-478 CPU
page 4,5,6
page 7
CRT & TV-OUT Conn.

page 25
H_A#(3..31)
LCD Conn
Memory BUS(DDR)
DDR-SO-DIMM X2
BANK 0, 1, 2, 3page 14,15,16
W/O EXT VGA CHIP
W/EXT VGA CHIP

W/EXT VGA CHIP
page 24
H_D#(0..63)
ATI-RC300M
W/O EXT VGA CHIP
page 25
PSB
800MHz
CLOCK GENERATOR
ICS951402AGT
Thermal Sensor
ADM1032AR
VGA M9 Embeded
868 pin u-BGA
AGP BUS
ATI-M9+X/M10C
page 8,9,10,11,12,13
2.5V DDR- 200/266

USB1.1
page 42
BT
page 17,18,19,20,21
USB2.0
USB conn x4
page 35
VGA DDR x2 CHB
VGA DDR x2 CHA
page 23
Audio Codec
ALC 250
A-Link
page 22
AMP & Audio Jack
page 36
MDC & BT Conn

3.3V 33 MHz
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)
CardBus Controller
IEEE 1394
Mini PCI
LAN
ENE 714/1410
RTL 81000CL
TI-TSB43AB22
socket
page 33
page 34
page 41
page 31
ATI-SB200
AC-LINK
page 26,27,28,29
IDSEL:AD16
IDSEL:AD18
(PIRQA#,GNT#0,REQ#0)(PIRQC#,GNT#3,REQ#3)
Slot 0
RJ45 CONN
page 33
page 32
page 41
HDD
Connector
Primary IDE
page 30
CDROM
Connector
page
Secondary IDE
Card slot
page 32
page 42
Mini-PCI solt
BGA 457 pin
ATA-100
RJ11 CONN
page 42
PCI BUS
page 37
ATA-100
30
LPC BUS
RTC CKT.
page 26
CABLE CONN.
ENE910
Power OK CKT.
page 46
Power On/Off CKT.

page 46
page 44
page 40
*RJ45 CONN
*LINE IN JACK
*DC JACK
*COM PORT
*USB CONN x1
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT
+TV-OUT PORT
page 38
Int.KBD
Touch Pad
page 41
SUPER I/O SMC 207
page 43
FIR
page 43
EC I/O Buffer
DC/DC Interface CKT.
4
BIOS
page 45
KEY
page 45
4
page 47
Power Circuit DC/DC

Title
page 50,51,52,53,54,55,56,57
Block Diagram
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
of
65
Voltage Rails
Power Plane
Description
S0-S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+VCC_CORE
Core voltage for CPU
ON
OFF
OFF
+VCCVID
The voltage for Processor VID select
ON
OFF
OFF
+1.25VS
1.25V switched power rail for DDR Vtt
ON
OFF
OFF
+1.2VS_VGA
1.2V I/O power rail for ATI-VGA M9+X/M10P.
ON
OFF
OFF
OFF
+1.5VS
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
ON
OFF
+1.8VS
1.8V switched power rail for ATI-RS300M/RC300M NB.
ON
OFF
OFF
+2.5VALW
2.5V always on power rail
ON
ON
ON*
+2.5V
2.5V system power rail for DDR
ON
ON
OFF
+2.5VS
2.5V switched power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V
3.3V system power rail for SB,LAN,CardReader and HUB.
ON
ON
OFF
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5V
5V system power rail .
ON
ON
OFF
+5VS
5V switched power rail
ON
OFF
OFF
+12VALW
12V always on power rail
ON
ON
ON*
RTCVCC
RTC power
ON
ON
ON
Symbol Note :
: means Digital Ground
: means Analog Ground

@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means build ATI SB USB2.0 related to turn on the function .
NEC@ : means build NEC USB2.0 related to turn on the function .
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID Table for AD channel

External PCI Devices
1
Vcc
Ra
DEVICE
IDSEL #
REQ/GNT #
PIRQ
NB Internal VGA
N /A
N /A
AGP BUS
AGP_DEVSEL
N /A
SOUTHBRIDGE
AD31 (INT.)
N /A
N /A
Board ID
0
1
2
3
4
5
6
7
USB
AD30 (INT.)
N /A
AC97
AD31 (INT.)
N /A
ATA 100
AD31 (INT.)
N /A
ETH ERNET
AD24(INT.)
N /A
1394
AD16
L AN
AD19
CARD BUS
AD20
A .B
Wireless LAN(MINI PCI) AD18
Board ID
0
1
2
3
4
5
6
7
I2C / SMBUS ADDRESSING

DEVICE
HEX
ADDRESS
DDR SO-DIMM 0
A0
1010000X
DDR SO-DIMM 1
A2
1010001X
CLOCK GENERATOR (EXT.)
D2
1101001X
3.3V +/- 5%
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
PCB Revision
0.1

Title
Notes List
A
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
of
65
+VCC_CORE
<8> H_REQ#[0..4]
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
<8> H_ADS#
R230
51_0402_5%
1
2
AP#0
AP#1
BINIT#
IERR#
H6
D2
G2
G4
BR0#
BPRI#
BNR#
LOCK#
AF22
AF23
BCLK0
BCLK1
51_0402_5%
<24> CK_BCLK
<24> CK_BCLK#
CK_BCLK
CK_BCLK#
F3
E3
E2
HIT#
HITM#
DEFER#
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
<8> H_HIT#
<8> H_HITM#
<8> H_DEFER#
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
H_D#[0..63] <8>
H _D#0
H _D#1
H _D#2
H _D#3
H _D#4
H _D#5
H _D#6
H _D#7
H _D#8
H _D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
+5VS
+5VS
R1099
R1100
47K_0402_5%
47K_0402_5%
AMP_3-1565030-1_Prescott
2
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
1
2
<8> H_BR0#
<8> H_BPRI#
<8> H_BNR#
<8> H_LOCK#
AC1
V5
AA3
AC3
BOOTSELECT
R231
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
+VCC_CORE
H_ IERR#
J1
K5
J4
J3
H3
G1
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
Prescott
AD1
+VCC_CORE
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
<8> H_A#[3..31]
A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10
JP8A
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
H_BOOTSELECT <54>
+VCC_CORE
TESTHI11
B6
FERR#
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
Pull-up 200ohm
to +VCC_CORE
TESTHI11
Pull-up 62ohm
to +VCC_CORE
FERR#/PBE# Pull-up 62ohm

to +VCC_CORE
Northwood MT
Pin name
Commend
Connect to PLD
CPUPREF through
0ohm
GHI
Northwood
Prescott
Pull-up 62ohm
to +VCC_CORE
Pop
Pop
Pop
Pop
Pop
Pop
Pop
Pull-up 62ohm
to +VCC_CORE
ITPCLKOUT0
Pull-up56ohm
to +VCC_CORE
Pop
Pop
AB22
ITPCLKOUT1 Pull-up 56ohm

to +VCC_CORE
TESTHI7
Pull-up 62ohm
to +VCC_CORE
ITPCLKOUT1
Pull-up 56ohm
to +VCC_CORE
Pop
Pop
Pop
NC
VIDPWRGD
Pull-up 2.43K ohm

to +VCCVID
NC
Depop
Pop
Depop
Depop
Pop
Depop
Depop
Pop
Depop
Pop
Depop
Pop
Pop
Depop
Pop
Pop
Pop
Pop
NC
float
VID5
Pull-up1Kohm to
+3VRUN & connect
to PWRIC
NC
float
AF3
NC
float
VCCVIDLB
Connect to +VCCVID
NC
float
VCCA
Connect to CPU
Filter
VCCIOPLL
Connect to CPU
Filter
VCCA
Connect to CPU
Filter
Connect to CPU
Filter
VCCA
Connect to CPU
Filter
VCCIOPLL
Connect to CPU
Filter
AD1
VSS
Connect to GND
BOOTSELECT CPU determine
VSS
Connect to GND
AE26
VSS
Connect to GND
OPTIMIZED/ float
COMPAT#
VSS
Connect to GND
AD25
TESTHI12
Pull-up 200ohm
to +VCC_CORE
5
TESTHI12
Pull-up 62ohm
to +VCC_CORE
E
3
VCCIOPLL
AD20
float
AD3
AE23
100K_0402_5%
FERR#
TESTHI6
MMBT3904_SOT23
R900
Northwood
MT
ITPCLKOUT0 Pull-up56ohm
to +VCC_CORE
float
Q106
2SC2411K_SC59
Commend
AA20
AD2
2
Q107
A6
Commend
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood
Pin name
2 22K_0402_5%
R899 1
Reference Intel document

Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Connect to PLD
through 0ohm
DPSLP
4

Title
Prescott Processor in uFCPGA478

3
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
of
65
+VCC_CORE
Place near SB200 (U6)

R514
R513
1
56_0402_5%
2 H_F ERR#
R515
1
56_0402_5%
2 H_THERMTRIP#
130_0402_5%
2 H_PROCHOT#
R518
1
300_0402_5%
2 H _PWRGOOD
R519
1
Place near CPU
<8> H_RS#[0..2]
H_RS#0
H_RS#1
H_RS#2
F1
G5
F4
AB2
J6
<8> H_TRDY#
56_0402_5%
2 H_RESET#
<26> H_A20M#
<26> H_FERR#
<26> H_IGNNE#
<26> H_SMI#
<26> H_PWRGOOD
<26> H_STPCLK#
C6
B6
B2
B5
AB23
Y4
H_F ERR#
H _PWRGOOD
<26> H_INTR
<26> H_NMI
<26> H_INIT#
<8,26> H_RESET#
D1
E5
W5
AB25
H_RESET#
H5
H2
AD6
AD5
<8> H_DBSY#
<8> H_DRDY#
<13,24> BSEL0
<13,24> BSEL1
<7> H_THERMDA
<7> H_THERMDC
+VCC_CORE
<7> H_THERMTRIP#
R529
R530
1
1
1
2
3
4
2 56_0402_5%
2 56_0402_5%
8
7
6
5
H_THERMDA
H_THERMDC
B3
C4
H_THERMTRIP#
A2
RS#0
RS#1
RS#2
RSP#
TRDY#
AF26
@0_0402_5%
SKTOCC#
R517
1
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
JP8B
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
DP#0
DP#1
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3
A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
D4
C1
D5
F7
E6
TCK
TDI
TDO
TMS
TRST#
@0_0402_5%
AE26
DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3
E22
K22
R22
W22
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<8>
<8>
<8>
<8>
DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
F21
J23
P23
W23
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<8>
<8>
<8>
<8>
ADSTB#0
ADSTB#1
L5
R5
H_ADSTB#0 <8>
H_ADSTB#1 <8>
E21
G25
P26
V21
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
+VCC_CORE
H_TESTHI0_1
R521
2 56_0402_5%
H_TESTHI2_7
R522
2 56_0402_5%
1
2
3
4
1
1
56_0804_8P4R_5%
8
7
6
5
2 300_0402_5%
2 56_0402_5%
RP136
H_TESTHI8
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
R990
R527
CPU_GHI# <27>
CPU_STP#
Prescott
THERMTRIP#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
Pop: Northwood
Depop: Prescott
R520
1
AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25
THERMDA
THERMDC
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
AA21
AA6
F20
F6
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12
DBSY#
DRDY#
BSEL0
BSEL1
AC6
AB5
AC4
Y6
AA5
AB4
+CPU_GTLREF
OPTIMIZED/COMPAT#
LINT0
LINT1
INIT#
RESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
J26
K25
K26
L25
for mobile CPU
RP137 56_0804_8P4R_5%
Note: Please change to 10uH, DC current

of 100mA parts and close to cap
+VCC_CORE
LQG21F4R7N00_0805
2
33U_D2_8M_R35
1
C544
+
1
+
C854
<54> VCCSENSE
<54> VSSSENSE
+VCCVID
2
33U_D2_8M_R35
R1017
A5
A4
AF3
1
2
0_0402_5%
H_VSSA
AD22
DBI#0
DBI#1
DBI#2
DBI#3
VCCIOPLL
VCCA
VSSA
LQG21F4R7N00_0805
ITP_DBRESET#
PROCHOT#
MCERR#
SLP#
H_PROCHOT#
NC1
NC2
NC3
NC4
NC5
A22
A7
AF25
AF24
AE21
51.1 Ohm for Northwood,

61.9 Ohm for Prescott
+VCC_CORE
+3VS
R546
@54.9_0603_1%
ITP_TDO
1
2
V ID0
V ID1
V ID2
V ID3
V ID4
V ID5
<8>
<8>
<8>
<8>
W/O ITP
H_PROCHOT# <49>
H_CPUSLP# <26>
VCCVID
R540
61.9_0603_1%
2
R539
61.9_0603_1%
COMP0
COMP1
AMP_3-1565030-1_Prescott
AF4
2.H_VCCIOPLL,HVCCA,HVSSA trace wide

12 mil s(min)
L24
P1
width= 10mil
VIDPWRGD
COMP0
COMP1
1.Place cap within 600 mils of

the VCCA and VSSA pins.
AE25
C3
V6
AB26
ITP_CLK0
ITP_CLK1
AD2
<24> CK_ITP
<24> CK_ITP#
AC26
AD26
VID0
VID1
VID2
VID3
VID4
VID5
PLL Layout note :
CK_ITP
CK_ITP#
AE5
AE4
AE3
AE2
AE1
AD3
R1017->
Pop: Prescott
Depop: Northwood
DBR#
VCCSENSE
VSSSENSE
VCCVIDLB
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
L37
AD20
AE23
H _VCCA
F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
L36
1
+VCCVID
C932
0.1U_0402_10V6K
R_E
R541
680_0603_5%
1
2
RE
Pop: Prescott
Depop: Northwood
+VCCVID
+3VALW
R545
H_ VID_PWRGD
H_ VID_PWRGD
1
14
4.7K_0402_5%
If CPU is P4 , Change the resistor

R 546 va lue to 75_0603_1%
SN74LVC14APWLE_TSSOP14
O
G
1
U32A
2
G
Q45
<53,54> VID_PWRGD
R547
@54.9_0603_1%
ITP_DBRESET#
1
2
2N7002 1N_SOT23
+3VS
Close to the ITP
GTL Reference Voltage
R993
4.7K_0402_5%
Layout note :
CPU_STP#
ITP_TMS
1
1K_0402_5%
ITP_TDI
2
<11,26,54> CPUCLK_STP#
Q96
MMBT3904_SOT23
+3VS
<54> VID5
<54> VID4
2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.
R553
100_0402_1%
R_A
<54>
<54>
<54>
<54>
+CPU_GTLREF
VID3
VID2
VID1
VID0
12K_0402_5%
R1125
2
+VCC_CORE
Q95
MMBT3904_SOT23
R552
1
1. +CPU_GTLREF Trace wide

12mils(min),Space 15mils
R550
1K_0402_5%
2
1
V ID5
R542
1K_0402_5%
V ID4
R543
1K_0402_5%
5
6
7
8
4
3
2
1
V ID3
V ID2
V ID1
V ID0
RP94
1K_1206_8P4R_5%
ITP_TCK
1
1K_0402_5%
2
R556
R558
R_B
169_0402_1%
2
Close to the CPU

R559
1K_0402_5%
1
2
C546
1U_0603_10V4Z
C547
220P_0402_25V8K
ITP_TRST#
Title
Between the CPU and ITP
Prescott Processor in uFCPGA478

Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
of
65
Place 11 North of Socket(Stuff 6)

+VCC_CORE
1
C131
22U_1206_16V4Z
1
C132
22U_1206_16V4Z
1
C133
22U_1206_16V4Z
1
C134
22U_1206_16V4Z
1
C135
22U_1206_16V4Z
1
C136
22U_1206_16V4Z
1
C137
22U_1206_16V4Z
1
C138
22U_1206_16V4Z
1
C139
22U_1206_16V4Z
1
C140
22U_1206_16V4Z
C141
22U_1206_16V4Z
Place 12 Inside Socket(Stuff all)

+VCC_CORE
1
C142
22U_1206_16V4Z
1
C143
22U_1206_16V4Z
1
C144
22U_1206_16V4Z
1
C145
22U_1206_16V4Z
1
C146
22U_1206_16V4Z
1
C147
22U_1206_16V4Z
1
C148
22U_1206_16V4Z
1
C149
22U_1206_16V4Z
1
C150
22U_1206_16V4Z
C151
22U_1206_16V4Z
+VCC_CORE
1
C152
22U_1206_16V4Z
C153
22U_1206_16V4Z
Place 9 South of Socket(Unstuff all)

+VCC_CORE
1
C154
22U_1206_16V4Z
1
C155
22U_1206_16V4Z
1
C156
22U_1206_16V4Z
1
C157
22U_1206_16V4Z
1
C158
22U_1206_16V4Z
1
C159
22U_1206_16V4Z
1
C160
22U_1206_16V4Z
1
C161
22U_1206_16V4Z
C162
22U_1206_16V4Z
SANYO OS-CON 820uF H:13*3 (C163,C164,C165)

SANYO OS-CON 820uF H:9*2 (C166,C167)
+VCC_CORE
+ C163
2
+ C164
820U_E9_2_5V_M_R7
820U_E9_2_5V_M_R7
+ C165
2
Place Inside Socket around the edge
820U_E9_2_5V_M_R7
+VCC_CORE
+ C166
+ C167
820U_E9_2_5V_M_R7
820U_E9_2_5V_M_R7
C168
0.22U_0603_10V7K
C169
0.22U_0603_10V7K
C170
0.22U_0603_10V7K
C171
0.22U_0603_10V7K
C172
0.22U_0603_10V7K
C173
0.22U_0603_10V7K
+VCC_CORE
C174
+
2
C175
+
470U_D2_2.5VM
C176
+
470U_D2_2.5VM
C177
+
@470U_D2_2.5VM
C178
+
@470U_D2_2.5VM
@470U_D2_2.5VM
+VCC_CORE
C179
+
2
C180
+
470U_D2_2.5VM
C181
+
470U_D2_2.5VM
C182
+
470U_D2_2.5VM
C183
+
470U_D2_2.5VM
@470U_D2_2.5VM

Title
CPU Decoupling
5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
of
65
Thermal Sensor ADM1032AR

+3VALW
H_THERMDA
H_THERMDA <5>
H_THERMDC
W= 15mil
H_THERMDC <5>
C251
1 0.1U_0402_10V6K
R283
U8
@10K_0402_5%
C253
2200P_0402_25V7K
VDD
SCLK
EC_SMC_2 <44>
H_THERMDA
D+
SDATA
EC_SMD_2 <44>
H_THERMDC
D-
ALERT#
THERM#
GND
ADM1032AR_SOP8
Address:1001_100X
R286 2
+VCC_CORE
1 300_0402_5%
C256 2
1 @1U_0603_10V6K
C
H_THERMTRIP#
<5> H_THERMTRIP#
MAINPWON <48,49,51>
Q17
2SC2411K_SC59
FAN CONN.1
FAN CONN. 2
+5VS
+5VS
+12VALW
2
FA N1
D25
2
8.2K_0402_5%
C265
1N4148_SOD80
10U_0805_10V4Z
5
6
OUT
-IN
R914 1
LM358A_SO8
C855
JP10
1
1
R918
1
2
3
2 100_0402_5%
2
C841
2
B
FMMT619_SOT23
+IN
R916
10K_0402_5%
1
R917
EN_FAN2
<44> EN_FAN2
0.1U_0402_10V6K
U10B
C838
10U_0805_16V4Z
R919 1
10U_0805_16V4Z
FA N2
0.1U_0402_10V6K
2
8.2K_0402_5%
1SS355_SOD323
D26
C266
1N4148_SOD80
10U_0805_10V4Z
ACES_85205-0300
JP11
C856
1
2
3
ACES_85205-0300
1000P_0402_16V7K
+3VS
C839
D68
Q91
2
D67
Q90
FMMT619_SOT23
LM358A_SO8
2
B
-IN
R915
10K_0402_5%
2 100_0402_5%
2
C840
R913 1
C
OUT
+IN
G
U10A
P
EN_FAN1
<44> EN_FAN1
1SS355_SOD323
1000P_0402_16V7K
2 10K_0402_5%
+3VS
<44> FANSPEED1
R920 1
2 10K_0402_5%
<44> FANSPEED2
1
C907
1000P_0402_16V7K
C908
1000P_0402_16V7K

Title
CPU Thermal Sensor&FAN CTRL

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
of
65
H_A#[3..31]
H_A#[3..31] <4>
H_REQ#[0..4]
H_REQ#[0..4] <4>
H_D#[ 0..63]
H_D#[0..63] <4>
U27A
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
U30
T30
R28
R25
U25
T28
V29
T26
U29
U26
V26
T25
V25
U27
U28
T29
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRD Y#
H_DBSY#
H_BR0#
H_LOCK#
L27
K25
H26
J27
L26
G27
F25
K26
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_BR0#
CPU_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
A17
G25
G26
J25
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
H_TRDY#
H_HIT#
H_HITM#
F26
J26
H25
CPU_TRDY#
CPU_HIT#
CPU_HITM#
A9
AH5
AG5
C7
CPU_RSET#
SUS_STAT#
SYSRESET#
POWERGOOD
2 24.9_0402_1% COMP_N
V28
CPU_COMP_N
R382 1
2 49.9_0402_1% COMP_P
L34
CPVDD
1
2
@1U_0603_10V6K
HB-1M2012-121JT03_0805
1
2CPVSS
C361
1
2
10U_0805_10V4Z
C996
W29
CPU_COMP_P
H23
CPVDD
J23
CPVSS
--> 412_0402_1%
R380 1
Note: PLACE CLOSE TO RC300M,

USE 10/10 WIDTH/SPACE
+VCC_CORE
PLACE CLOSE TO U27 Ball

W28, USE 20/20
WIDTH/SPACE
R383
+VCC_CORE
+1.8VS
<5,26> H_RESET#
<5> H_RS#2
<5> H_RS#1
<5> H_RS#0
<5> H_TRDY#
<4> H_HIT#
<4> H_HITM#
2 330_0402_5%
<27> NB_SUS_STAT#
<17,26> NB_RST#
<10,46> NB_PWRGD
R381 1
W28
CPU_VREF
100_0402_1%
DATA GROUP 1
ADDR. GROUP 1
Y29
Y28
THERMALDIODE_N
THERMALDIODE_P
B17
TESTMODE
NB_GTLREF
DATA GROUP 2
0.1U_0402_10V6K
C974
2
1
DATA GROUP 3
<4> H_ADS#
<4> H_BNR#
<4> H_BPRI#
<4> H_DEFER#
<5> H_DRDY#
<5> H_DBSY#
<4> H_BR0#
<4> H_LOCK#
R384
169_0402_1%
C362
1U_0603_10V6K
C363
220P_0402_25V8K
R385
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_DSTBN0#
CPU_DSTBP0#
L30
K29
J29
H28
K28
K30
H29
J28
F28
H30
E30
D29
G28
E29
D30
F29
E28
G30
G29
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_DSTBN1#
CPU_DSTBP1#
B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
A28
D27
E27
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_DSTBN2#
CPU_DSTBP2#
F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
D23
E22
F22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_DSTBN3#
CPU_DSTBP3#
B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
F19
E19
F18
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3
PENTIUMAGTL+ I/F
IV
<5> H_ADSTB#1
CONTROL
MISC.
<5> H_ADSTB#0
ADDR. GROUP 0
M28
P25
M25
N29
N30
M26
N28
P29
P26
R29
P30
P28
N26
N27
M29
N25
R26
L28
L29
R27
DATA GROUP 0
PART 1 OF 6
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>
H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>
H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>
4.7K_0402_5% 216RC300M_BGA_718
2
C363 CLOSE
TO Ball W28
+VCC_CORE
0.1U_0402_10V6K
C364
22U_1206_16V4Z_V1
2
A
C365
C366
2
2
0.1U_0402_10V6K
C367
0.1U_0402_10V6K
1
C368
C369
0.1U_0402_10V6K
1
C370
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K
C371
2
2
0.1U_0402_10V6K
C372
0.1U_0402_10V6K
A

Title
ATI RC300M-AGTL+
5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
of
65
RP27
DDRA_DQ36
DDRA_DQ32
1
2
0_0404_4P2R_5%
RP31
DDRA_SDQ9
4
DDRA_SDQ13
3
DDRA_DQ37
DDRA_DQ33
1
2
0_0404_4P2R_5%
RP30
DDRA_SDQ37
4
DDRA_SDQ33
3
DDRA_DQ10
DDRA_DQ14
0_0404_4P2R_5%
RP34
DDRA_SDQ10
1
4
DDRA_SDQ14
2
3
DDRA_DQ38
DDRA_DQ34
1
2
0_0404_4P2R_5%
RP33
DDRA_SDQ38
4
DDRA_SDQ34
3
DDRA_DQ11
DDRA_DQ15
0_0404_4P2R_5%
RP37
DDRA_SDQ11
1
4
DDRA_SDQ15
2
3
DDRA_DQ39
DDRA_DQ35
1
2
0_0404_4P2R_5%
RP36
DDRA_SDQ39
4
DDRA_SDQ35
3
DDRA_DQS4 2
R386
0_0404_4P2R_5%
DDRA_SDQS4
1
0_0402_5%
RP28
U27B
<14,15,16> DDRA_RAS#
<14,15,16> DDRA_CAS#
<14,15,16> DDRA_WE#
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7
AH7
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
DDRA_RAS#
DDRA_CAS#
AF24
AF25
MEM_RAS#
MEM_CAS#
DDRA_WE#
AE24
MEM_WE#
AJ8
AF9
AH13
AE21
AJ23
AJ27
AC28
AA25
MEM_DQS0
MEM_DQS1
MEM_DQS2
MEM_DQS3
MEM_DQS4
MEM_DQS5
MEM_DQS6
MEM_DQS7
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
<14> DDRA_CLK0
<14> DDRA_CLK0#
<14> DDRA_CLK1
<14> DDRA_CLK1#
<15> DDRA_CLK3
<15> DDRA_CLK3#
<15> DDRA_CLK4
<15> DDRA_CLK4#
<14,16>
<14,16>
<15,16>
<15,16>
<14,16>
<14,16>
<15,16>
<15,16>
B
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
+1.8VS
DDRA_CLK0
DDRA_CLK0#
AK10
AH10
MEM_CK0
MEM_CK0#
DDRA_CLK1
DDRA_CLK1#
AH18
AJ19
MEM_CK1
MEM_CK1#
AG30
AG29
MEM_CK2
MEM_CK2#
DDRA_CLK3
DDRA_CLK3#
AK11
AJ11
MEM_CK3
MEM_CK3#
DDRA_CLK4
DDRA_CLK4#
AH17
AJ18
MEM_CK4
MEM_CK4#
AF28
AG28
MEM_CK5
MEM_CK5#
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3
AF13
AE13
AG14
AF14
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
L35 1
2
HB-1M2012-121JT03_0805
MPVDD
C375
1
2MPVSS
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
AH26
AH27
AF26
AG27
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
AC18
MPVDD
AD18
MEM I/F
PART 2 OF 6
DDRA_ADD0
DDRA_ADD1
DDRA_ADD2
DDRA_ADD3
DDRA_ADD4
DDRA_ADD5
DDRA_ADD6
DDRA_ADD7
DDRA_ADD8
DDRA_ADD9
DDRA_ADD10
DDRA_ADD11
DDRA_ADD12
DDRA_ADD13
DDRA_ADD14
DDRA_ADD15
MPVSS
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
AG6
AJ7
AJ9
AJ10
AJ6
AH6
AH8
AH9
AE7
AE8
AE12
AF12
AF7
AF8
AE11
AF11
AJ12
AH12
AH14
AH15
AH11
AJ13
AJ15
AJ16
AF18
AG20
AG21
AF22
AF19
AF20
AE22
AF23
AJ21
AJ22
AJ24
AK25
AH21
AH22
AH24
AJ25
AK26
AK27
AJ28
AH29
AH25
AJ26
AJ29
AH30
AF29
AE29
AB28
AA28
AE28
AD28
AC29
AB29
AC26
AB25
Y26
W26
AE26
AD26
AA26
Y27
MEM_CAP1
AF6
C373 1
0.47U_0603_16V7K
MEM_CAP2
AA29
C374 1
0.47U_0603_16V7K
MEM_COMP
AK19
MEM_DDRVREF
DDRA_DQ8
DDRA_DQ12
1
2
DDRA_DQ9
DDRA_DQ13
1
2
DDRA_DQS1 2
R387
DDRA_DM1
2
R388
DDRA_DQ0
DDRA_DQ4
1
2
DDRA_DQ1
DDRA_DQ5
DDRA_DQ45
DDRA_DQ41
0_0404_4P2R_5%
RP44
DDRA_SDQ45
1
4
DDRA_SDQ41
2
3
DDRA_DQ3
DDRA_DQ7
0_0404_4P2R_5%
RP45
DDRA_SDQ3
1
4
DDRA_SDQ7
2
3
DDRA_DQ46
DDRA_DQ42
1
2
0_0404_4P2R_5%
RP46
DDRA_SDQ46
4
DDRA_SDQ42
3
DDRA_DQ2
DDRA_DQ6
1
2
0_0404_4P2R_5%
RP47
DDRA_SDQ2
4
DDRA_SDQ6
3
DDRA_DQ47
DDRA_DQ43
1
2
0_0404_4P2R_5%
RP48
DDRA_SDQ47
4
DDRA_SDQ43
3
0_0404_4P2R_5%
DDRA_SDQS0
1
0_0402_5%
DDRA_DQS5 2
R395
0_0404_4P2R_5%
DDRA_SDQS5
1
0_0402_5%
DDRA_DQ21
DDRA_DQ17
0_0404_4P2R_5%
RP51
DDRA_SDQ21
1
4
DDRA_SDQ17
2
3
+2.5V
L
@0.1U_0402_10V6K
DDRA_DQ19
DDRA_DQ23
MEN_COMP R405 1
C858
C859
C860
@0.1U_0402_10V6K
DDRA_SDM5
1
0_0402_5%
DDRA_DQ61
DDRA_DQ57
1
2
0_0404_4P2R_5%
RP52
DDRA_SDQ61
4
DDRA_SDQ57
3
DDRA_SDQ18
DDRA_SDQ22
DDRA_DQ62
DDRA_DQ58
1
2
0_0404_4P2R_5%
RP54
DDRA_SDQ62
4
DDRA_SDQ58
3
0_0404_4P2R_5%
RP55
DDRA_SDQ19
4
DDRA_SDQ23
3
DDRA_DQ63
DDRA_DQ59
1
2
0_0404_4P2R_5%
RP56
DDRA_SDQ63
4
DDRA_SDQ59
3
0_0404_4P2R_5%
DDRA_SDM2
1
0_0402_5%
DDRA_DQS7 2
R404
0_0404_4P2R_5%
DDRA_SDQS7
1
0_0402_5%
4
3
DDRA_SDQS2
1
0_0402_5%
4
3
DDRA_DM7
2
R407
DDRA_SDQ60
DDRA_SDQ56
1
2
DDRA_DQ52
DDRA_DQ48
1
2
DDRA_DQ25
DDRA_DQ29
0_0404_4P2R_5%
RP59
DDRA_SDQ25
1
4
DDRA_SDQ29
2
3
DDRA_DQ53
DDRA_DQ49
0_0404_4P2R_5%
RP60
DDRA_SDQ53
1
4
DDRA_SDQ49
2
3
DDRA_DQ26
DDRA_DQ30
0_0404_4P2R_5%
RP61
DDRA_SDQ26
1
4
DDRA_SDQ30
2
3
DDRA_DQ50
DDRA_DQ54
0_0404_4P2R_5%
RP62
DDRA_SDQ50
1
4
DDRA_SDQ54
2
3
DDRA_DQ27
DDRA_DQ31
1
2
0_0404_4P2R_5%
RP63
DDRA_SDQ27
4
DDRA_SDQ31
3
DDRA_DQ51
DDRA_DQ55
1
2
0_0404_4P2R_5%
RP64
DDRA_SDQ51
4
DDRA_SDQ55
3
DDRA_DQS3 2
R412
0_0404_4P2R_5%
DDRA_SDQS3
1
0_0402_5%
DDRA_DQS6 2
R413
0_0404_4P2R_5%
DDRA_SDQS6
1
0_0402_5%
4
3
DDRA_DM3
2
R415
DDRA_SDQ[0..63]
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDM3
1
0_0402_5%
4
3
DDRA_DM6
2
R416
DDRA_SDM[0..7] <14,15,16>
DDRA_SDQ[0..63] <14,15,16>
B
DDRA_SDQS[0..7]
RP58
DDRA_DQ24
DDRA_DQ28
1K_0603_1%
DDRA_SDM[0..7]
DDRA_SDM7
1
0_0402_5%
RP57
DDRA_ADD[0..15]
DDRA_SDQ52
DDRA_SDQ48
DDRA_SDQS[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
Layout note
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
DDRA_SDM6
1
0_0402_5%
+2.5V
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C861
C378
0.1U_0402_10V6K
RP50
1
2
DDRA_DQS2 2
R406
AK20
0.1U_0402_10V6K
1
1
2
DDRA_DM2
2
R403
2 49.9_0402_1%
C857
DDRA_SDQ44
DDRA_SDQ40
DDRA_DQ60
DDRA_DQ56
1
2
Group 6 sweep Group 7
R409
DDR_VREF trace width of

20mils and space
20mils(min)
DDRA_SDQ20
DDRA_SDQ16
RP53
DDRA_DQ18
DDRA_DQ22
1K_0603_1%
4
3
0_0404_4P2R_5%
0.1U_0402_10V6K
DDRA_DM5
2
R398
1
2
R408
DDRA_SDM0
1
0_0402_5%
4
3
RP49
1
C377
DDRA_SDQ0
DDRA_SDQ4
DDRA_DQ20
DDRA_DQ16
DDR_VREF
DDR_VREF
DDRA_SDM4
1
0_0402_5%
0_0404_4P2R_5%
RP43
DDRA_SDQ1
1
4
DDRA_SDQ5
2
3
+2.5V
RP41
4
3
DDRA_DM0
2
R397
0.1U_0402_10V6K
DDRA_DM4
2
R389
DDRA_SDQ36
DDRA_SDQ32
1
2
DDRA_DQS0 2
R394
1
C376
0_0404_4P2R_5%
DDRA_SDQS1
1
0_0402_5%
DDRA_SDM1
1
0_0402_5%
4
3
DDRA_DQ44
DDRA_DQ40
216RC300M_BGA_718
DDRA_SDQ8
DDRA_SDQ12
RP40
2.2U_0805_10V4Z
+2.5V
4
3
C379
C380
C381
C382
C383
C384
C385
C386
C387
C388
C389
C390
C391
@0.1U_0402_10V6K
150U_D2_6.3VM
@0.1U_0402_10V6K
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
0.1U_0402_10V6K

Title
ATI RC300M-DDR I/F

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
of
65
A_AD[0..31]
<13,26> A_AD[0..31]
A_CBE#[0..3]
<13,26> A_CBE#[0..3]
U27C
PCI_PAR/ALINK_NC
PCI_FRAME#/ALINK_STROBE#
PCI_IRDY#/ALINK_ACAT#
PCI_TRDY#/ALINK_END#
INTA#
ALINK_DEVSEL#
PCI_STOP#/ALINK_OFF#
A_SBREQ#
A_SBGNT#
W5
W6
1
2 R570
8.2K_0402_5%
+3VS
AGP_GNT#
AGP_REQ#
<17> AGP_GNT#
<17> AGP_REQ#
?
AGP8X_DET#
<17> AGP8X_DET#
AGPREF_8X
<17> VREF_8X_IN
ALINK_SBREQ#
ALINK_SBGNT#
V5
V6
PCI_REQ#0/ALINK_NC
PCI_GNT#0/ALINK_NC
K5
K6
AGP2_GNT#/AGP3_GNT
AGP2_REQ#/AGP3_REQ
M5
J6
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
<26> A_SBREQ#
<26> A_SBGNT#
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#2/AGP3_CBE2
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
R3
M1
L3
H1
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP_PAR
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
P5
R6
T6
T5
P6
R5
C1
D3
N6
N5
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI/PIPE#
AGP_DBI_LO
AGP_RBF#
AGP_WBF#
+1.5VS
+1.5VS
AGP8X_DET#
AGP_VREF/TMDS_VREF
0.1U_0402_10V6K
R575 1
Ra
AGP_COMP
J5
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
C3
C2
D4
E4
F6
F5
G6
G5
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
L6
M6
L5
AGP_ST0
AGP_ST1
AGP_ST2
AGP_COMP
169_0402_1%
R576
2 NAPG@0_0402_5%
2 NAPG@0_0402_5%
ENBKL#
ENAVDD <17,25>
AGP_SBA4
R562
2 NAPG@0_0402_5%
AGP_STP# <17,27>
AGP_SBA5
R563
2 NAPG@0_0402_5%
AGP_SBA1
R994
2 NAPG@0_0402_5%
DDC_DAT
AGP_SBA0
R995
2 NAPG@0_0402_5%
DDC_CLK
AGP_BUSY# <17,27>
DDC_DAT <17,25>
DDC_CLK <17,25>
Pop for internal AGP

Depop for M11P
AGP_AD[0..31]
AGP_AD[0..31] <17>
AGP_SBA[0..7]
AGP_SBA[0..7] <17>
AGP_CBE#[0..3]
AGP_CBE#[0..3] <17>
AGP_ST[0..2]
AGP_ST[0..2] <17>
AGP_SBSTB <17>
AGP_SBSTB# <17>
AGP_ADSTB0 <17>
AGP_ADSTB0# <17>
AGP_ADSTB1 <17>
AGP_ADSTB1# <17>
+3VS
AGP_IRDY# <17>
AGP_TRDY# <17>
AGP_STOP# <17>
AGP_PAR <17>
AGP_FRAME# <17>
AGP_DEVSEL# <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_RBF# <17>
AGP_WBF# <17>
R567
NAGP@10K_0402_5%
+3VS
R568
R569
1
NAPG@10K_0402_5%
D
ENBKL <17,44>
NAGP@0_0402_5%
2
G
NAGP@2N7002_SOT23
D Q1
Q2
NAGP@2N7002_SOT23
2
G
<8,46> NB_PWRGD
ENBKL#
B
Rb
324_0402_1%
1
216RC300M_BGA_718
+3VS
AGPREF_8X
8X(M9+M10@)
PLACE CLOSE TO
CONNECTOR
R577
Rc
R945
100_0402_1%
Depop
324_0402_1%
1K_0402_1%
100_0402_1%
1K_0402_1%
NAGP@47K_0402
Depop for M11P
4X(NAGP@)
169_0402_1%
Ra
Rb
Rc
R561
C550
1
R560
AGP_SBA3
AD5
AC6
AC5
AD2
W4
AD3
AD6
E5
E6
T3
U2
G3
H2
AGP_SBA2
A_PAR
A_STROBE#
A_ACAT#
A_END#
2 0_0402_5%
A_DEVSEL#
A_OFF#
PCI Bus 0 / A-Link I/F
<13,26> A_PAR
<26> A_STROBE#
<26> A_ACAT#
<26> A_END#
R1005 1
<17,26,31,34> PCI_PIRQA#
<26> A_DEVSEL#
<26> A_OFF#
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
AGPAND LVDS MUXED SIGNALS
ALINK_CBE#0
ALINK_CBE#1
ALINK_CBE#2
ALINK_CBE#3
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AG4
AE2
AC3
AA3
Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP_AD31
PART 3 OF 6
ALINK_AD0
ALINK_AD1
ALINK_AD2
ALINK_AD3
ALINK_AD4
ALINK_AD5
ALINK_AD6
ALINK_AD7
ALINK_AD8
ALINK_AD9
ALINK_AD10
ALINK_AD11
ALINK_AD12
ALINK_AD13
ALINK_AD14
ALINK_AD15
ALINK_AD16
ALINK_AD17
ALINK_AD18
ALINK_AD19
ALINK_AD20
ALINK_AD21
ALINK_AD22
ALINK_AD23
ALINK_AD24
ALINK_AD25
ALINK_AD26
ALINK_AD27
ALINK_AD28
ALINK_AD29
ALINK_AD30
ALINK_AD31
AK5
AJ5
AJ4
AH4
AJ3
AJ2
AH2
AH1
AG2
AG1
AG3
AF3
AF1
AF2
AF4
AE3
AE4
AE5
AE6
AC2
AC4
AB3
AB2
AB5
AB6
AA2
AA4
AA5
AA6
Y3
Y5
Y6
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
AGP8X_DET#
ATI request
+1.5VS
+3VS
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.5VS
10U_0805_10V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.01U_0402_16V7Z
0.01U_0402_16V7Z
0.01U_0402_16V7Z 0.01U_0402_16V7Z
0.01U_0402_16V7Z
1
C551
47U_B_6.3VM
+
2
C553
C554
2
0.1U_0402_10V6K
C555
C556
2
0.1U_0402_10V6K
C557
C558
2
0.1U_0402_10V6K
+1.5VS
C559
C560
2
0.1U_0402_10V6K
C561
C632
2
0.1U_0402_10V6K
C562
C563
C564
C565
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K
C566
C567
2
2
0.1U_0402_10V6K
C568
C569
C947
2
2
0.1U_0402_10V6K
C948
C864
C949
C950
C935
C936
C933
C934
C951
2
2
2
2
2
2
2
2
2
2
0.01U_0402_16V7Z
0.01U_0402_16V7Z
0.01U_0402_16V7Z
0.01U_0402_16V7Z
0.01U_0402_16V7Z
+1.5VS
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
A
C552
47U_B_6.3VM
+
2
C570
C571
2
0.1U_0402_10V6K
C572
2
2
0.1U_0402_10V6K
C573
C574
0.1U_0402_10V6K
C575
C576
2
2
0.1U_0402_10V6K
C577
C578
C937
C938
2
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
C939
C940
2
2
0.1U_0402_10V6K
C941
C942
2
2
0.1U_0402_10V6K
C943
C944
2
2
0.1U_0402_10V6K
C945
C946
2
2
0.1U_0402_10V6K
Note: PLACE CLOSE TO U27 (NB RC300M)

Title
ATI RC300M-AGP, ALINK BUS

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
10
of
65
+3VS
L58
+2.5VS
1
2
FBM-11-160808-121-T_0603
L59
C586
0.1U_0402_10V6K
KC FBM-L11-201209-221LMAT_0805
L61
1
2
KC FBM-L11-201209-221LMAT_08051
C589
+1.8VS
C
+1.8VS_AVDDQ
C590
0.1U_0402_10V6K
0.1U_0402_10V6K
2
2
L62
1
2
KC FBM-L11-201209-221LMAT_0805 1
1
1
C591
C592
C593
10U_0805_16V4Z
2
2
2
0.1U_0402_10V6K
R584 1
CLK_AGP_66M
R587
RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R
2 715 _0402_1% NB_RSET
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD_18
G11
PLLVSS
<24> CLK_NB_BCLK
<24> CLK_NB_BCLK#
F14
F15
E14
C8
D9
RED
GREEN
BLUE
DACHSYNC
DACVSYNC
C14
RSET
RC300M_X1
RC300M_X2
A4
B4
XTALIN
XTALOUT
CLK_NB_BCLK
CLK_NB_BCLK#
A5
B5
HCLKIN
HCLKIN#
B6
A6
SYS_FBCLKOUT
SYS_FBCLKOUT#
D8
ALINK_CLK
R588
56_0402_5%
TXB0-_NB <25>
TXB0+_NB <25>
TXB1-_NB <25>
TXB1+_NB <25>
TXB2-_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXBCLK+_NB <25>
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
E10
D10
B9
C9
D11
E11
B10
C10
TXA0-_NB <25>
TXA0+_NB <25>
TXA1-_NB <25>
TXA1+_NB <25>
TXA2-_NB <25>
TXA2+_NB <25>
TXACLK-_NB <25>
TXACLK+_NB <25>
LPVDD_18
A12
@15P_0402_50V8J
<24> CLK_AGP_66M
<24> CLK_MEM_66M
LPVSS
A11
B12
C12
LVSSR
LVSSR
B11
C11
C_R
E15
CRMA_R
Y_G
C15
LUMA_R
COMP_B
D15
COMPS_R
DACSCL
D6
DDCCLK_R
C6
CLK_MEM_66M
AGPCLKOUT
DDCDATA_R
B3
AGPCLKIN
CPUSTOP#
D5
A3
R591
EXT_MEM_CLK
D7
B7
+3VS
USBCLK
REF27
SYSCLK
A8
SYSCLK#
B8
R592
10K_0402_5%
@10_0402_5%
OSC
2
0.1U_0402_10V6K
2
10U_0805_16V4Z
2
10U_0805_16V4Z
Q97
@2N7002 1N_SOT23
3
CPUCLK_STP#
CPUCLK_STP# <5,26,54>
PCI_RST# <26,30,31,33,34,38,41,44>
B
R589
R590
C5
+1.8VS
KC FBM-L11-201209-221LMAT_0805
0.1U_0402_10V6K
1
2
L64
1
1
1
C598
C599
C600
CLK. GEN.
+1.8VS
KC FBM-L11-201209-221LMAT_0805
0.1U_0402_10V6K
1
2
L63
1
1
C595
C596
2
2
0.1U_0402_10V6K
+1.8VS_LVDDR
DACSDA
CLK_MEM_66M
B
CLK_AGP_66M
B2
C594
C601
+1.8VS_LPVDD
LVDDR_18
LVDDR_18
@10_0402_5%
AVDDDI_18
C13
0.1U_0402_10V6K
R585 0_0402_5%
1
2
<24> REFCLK1_NB
PLLVDD_18
AVSSN
B14
D12
E12
F11
F12
D13
D14
E13
F13
+1.8VS
B13
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXCLK_UN
TXCLK_UP
SVID
0.1U_0402_10V6K
+1.8VS_AVDDDI
PART 4 OF 6
AVDD_25
2
G
KC FBM-L11-201209-221LMAT_0805
L60
1
2
1
C588
VDDR3
VDDR3
A14
CRT
+1.8VS
C587
0.1U_0402_10V6K
LVDS
U27D
G9
H9
@0_0402_5%
1K_0402_5%
+3VS
216RC300M_BGA_718
C603
@15P_0402_50V8J
L
L
Note: PLACE CLOSE TO U27 (NB CHIP)
Note: PLACE CLOSE TO U27 (NB CHIP)
C604
R593
@1M_0402_1%
RC300M_X2
Note: PLACE CLOSE TO U6 (VGA CHIP)
<17,25> CRT_R
<17,25> CRT_G
<17,25> CRT_B
CRT_R R594 1
CRT_G R595 1
CRT_B R596 1
<17,25> CRT_HSYNC
<17,25> CRT_VSYNC
CRT_HSYNC 1
CRT_VSYNC 2
TV_CRMA <17,46>
TV_LUMA <17,46>
TV_COMPS <17,46>
2 NAPG@0_0402_5%TV_CRMA
2 NAPG@0_0402_5%TV_LUMA
2 NAPG@0_0402_5%TV_COMPS
R597 1
R598 1
R599 1
RC300M_X1
CRMA_R
LUMA_R
COMPS_R
@18P_0402_50V8K
Y4
@14.31818MHZ_20P_6X1430004201
C605
@18P_0402_50V8K
2 NAPG@0_0402_5%RED_R
2 NAPG@0_0402_5%GREEN_R
2 NAPG@0_0402_5%BLUE_R
RP103
4
3
HSYNC_R
VSYNC_R
NAGP@0_4P2R_0402_5%
RP104
DDCCLK_R
DDCDATA_R
4
3
1
2
3VDDCCL
3VDDCDA
3VDDCCL <17,25>
3VDDCDA <17,25>

Title
NAGP@0_4P2R_0402_5%
ATI RC300M-VIDEO I/F

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
11
of
65
+1.5VS
+2.5V
U27E
U27F
PART 5 OF 6
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
+VCC_CORE
C16
D16
D17
E16
E17
F16
F17
G17
G21
G23
G24
H16
H17
H19
H21
H24
K23
K24
M23
P23
P24
T23
T24
U23
U24
W30
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDR2_CPU
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
AA1
AA7
AA8
AC7
AC8
AD1
AD7
AD8
AK3
W8
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDL_ALINK
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
E7
F7
G8
MEM I/F PWR
A29
AB23
AB24
AB27
AB4
AB8
AC1
AC11
AC14
AC16
AC20
AC30
AD11
AD14
AD16
AD20
AD4
AE27
AF30
AF5
AG10
AG13
AG16
AG19
AG22
AG25
AG7
AH28
AH3
AJ1
AK13
AK2
AK22
AK29
AK4
AK7
B1
B16
B30
C19
C23
C27
C4
D21
D25
E3
E8
E9
F27
F4
F8
G14
G15
G18
G20
H14
H15
H18
H20
H27
H4
H8
J7
CPU I/F PWR
+1.5VS
AGP PWR
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
POWER
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
CORE PWR
F10
F9
G12
H12
H13
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
P18
P19
U12
U13
U14
U17
U18
U19
V12
V13
V14
V17
V18
V19
W12
W13
W14
W17
W18
W19
+3VS
ALINK PWR
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PART 6 OF 6
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R23
R7
R8
T12
T13
T14
T15
T16
T17
T18
T19
T27
T4
U15
U16
U7
U8
V15
V16
V27
V4
V7
V8
W15
W16
W27
Y1
Y23
Y24
Y30
Y4
Y7
Y8
R19
R18
R17
R16
R15
R14
R13
R12
R1
P4
P27
P16
P15
N8
N24
N23
N16
N15
M4
M27
M16
M15
L8
L7
L25
L24
L23
K4
K27
J8
216RC300M_BGA_718
M9-M10@0_0603_5%
R418
1
R419
1
+1.5VS
Pop for M11P
Depop for internal AGP
NAGP@0_0603_5%
2
+3VS
+1.8VS
VDD_18
VDD_18
VDD_18
VDD_18
AC22
AC9
H10
H22
Depop for M11P
216RC300M_BGA_718
+1.8VS
0.1U_0402_10V6K
C579
10U_0805_10V4Z
C580
C581
2
0.1U_0402_10V6K
C582
2
0.1U_0402_10V6K
C583
0.1U_0402_10V6K

Title
ATI RC300M-POWER
5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
12
of
65
R420 1
A_AD30
R422
R425
R427 1
A_AD29
R429
2 10K_0402_5%
+3VS
4.7K_0402_5% 2
1
D85
RB751V_SOD323
R424 1
10K_0402_5%
2
4.7K_0402_5% 2
1
D86
RB751V_SOD323
2 10K_0402_5%
BSEL1 <5,24>
A_CBE#[0..3]
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
+3VS
BSEL0 <5,24>
A_AD18
@4.7K_0402_5%
R421
@4.7K_0402_5%
R423
4.7K_0402_5%
+3VS
0: DISABLE
1:ENABLE
A_AD17
R426
@4.7K_0402_5%
R428
4.7K_0402_5%
+3VS
R430 1
R431
2 @10K_0402_5%
A_AD28: SPREAD SPECTRUM ENABLE
+3VS
4.7K_0402_5%
DEFAULT:0
<10,26> A_PAR
A_AD27
R435
2 10K_0402_5%
A_AD27: FrcShortReset#
+3VS
@4.7K_0402_5%
A_PAR
R463
@4.7K_0402_5%
R460
4.7K_0402_5%
R438 1
R440
2 10K_0402_5%
+3VS
PAR: EXTENDED DEBUG MODE

DEFAULT : 1
0: DEBUG MODE
1: NORMAL
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
0: DISABLE
1: ENABLE
R434 1
DEFAULT: 0
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28
A_AD18 : ENABLE PHASE CALIBRATION

DEFAULT: 0
00: 100 MHZ

01: 133 MHZ
10: 200MHZ
11:166 MHZ
A_AD29: STRAP CONFIGURATION
+3VS
A_AD[0..31]
<10,26> A_AD[0..31]
<10,26> A_CBE#[0..3]
A_AD31
A_AD26 : ENABLE IOQ
+3VS
@4.7K_0402_5%
DEFAULT: 1
0: IOQ=1
1: IOQ=12
R443 1
A_AD25
R444
2 10K_0402_5%
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
+3VS
@4.7K_0402_5%
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24
R448 1
2 10K_0402_5%
AD25=1 DESTOP CPU

AD25=0 MOBILE CPU
AD17--DON'T CARE
A_AD24 : MOBILE CPU SELECT
+3VS
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
R452 1
A_AD23
R454
2 10K_0402_5%
A_AD23 : CLOCK BYPASS DISABLE
+3VS
@4.7K_0402_5%
DEFAULT: 1
0: TEST MODE
1: NORMAL
R1309 1
A_AD22
R457
2 10K_0402_5%
+3VS
@4.7K_0402_5%
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
R461 1
A_AD21
R462
2 10K_0402_5%
A_AD21 : AUTO_CAL ENABLE
+3VS
@4.7K_0402_5%
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20
R464
@4.7K_0402_5%
R465
4.7K_0402_5%
A_AD20 : INTERNAL CLK GEN ENABLE
+3VS
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE#3
R466
@4.7K_0402_5%
R467
@4.7K_0402_5%
A_CBE#3: NOT USED
+3VS
A_CBE#0
R468
@4.7K_0402_5%
R469
@4.7K_0402_5%
A_CBE#0 :NO USED
+3VS

Title
ATI RC300M-SYSTEM STRAP

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
13
of
65
+2.5V
+2.5V
+2.5V
1
+2.5V
<9,15,16> DDRA_SDQS[0..7]
DDRA_SDQ8
DDRA_SDQ9
D DRA_ADD[0..15]
<9,15,16> DDRA_ADD[0..15]
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDM[0..7]
<9,15,16> DDRA_SDM[0..7]
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
<9> DDRA_CLK0
<9> DDRA_CLK0#
DDRA_SDQ16
DDRA_SDQ17
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
<9,16> DDRA_CKE_R1
DDRA_CKE_R1
D DRA_ADD12
DD RA_ADD9
DD RA_ADD7
DD RA_ADD5
DD RA_ADD3
DD RA_ADD1
D DRA_ADD10
D DRA_ADD13
DD RA_WE#
DDRA_CS#0
D DRA_ADD15
<9,15,16> DDRA_WE#
<9,16> DDRA_CS#0
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
<15,24,27> SMB_CK_DAT2
<15,24,27> SMB_CK_CLK2
+3VS
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
R472
C411
0.1U_0402_10V6K 1K_0603_1%
D DRA_VREF
DDRA_SDQS[0..7]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDRA_SDQ15
DDRA_SDQ4
R473
C412
0.1U_0402_10V6K 1K_0603_1%
2
<9,15,16> DDRA_SDQ[0..63]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
JP24
DDRA_SDQ[0..63]
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_VREF trace width of

20mils and space 20mils(min)

DDRA_SDQ20
DDRA_SDQ21
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE_R0
DDRA_CKE_R0 <9,16>
D DRA_ADD11
DD RA_ADD8
DD RA_ADD6
DD RA_ADD4
DD RA_ADD2
DD RA_ADD0
D DRA_ADD14
DDRA_RAS#
DDRA_CAS#
DDRA_CS#1
DDRA_RAS# <9,15,16>
DDRA_CAS# <9,15,16>
DDRA_CS#1 <9,16>
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_CLK1# <9>
DDRA_CLK1 <9>
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
AMP_1565918-1
DIMM0
REVERSE
+2.5V
System Memory Decoupling caps

C413
0.1U_0402_10V6K
C414
0.1U_0402_10V6K
C415
0.1U_0402_10V6K
C416
0.1U_0402_10V6K
C417
0.1U_0402_10V6K
C418
0.1U_0402_10V6K
C419
0.1U_0402_10V6K
C420
0.1U_0402_10V6K
C421
0.1U_0402_10V6K
C422
0.1U_0402_10V6K
C423
0.1U_0402_10V6K
C424
0.1U_0402_10V6K
C425
10U_0805_6.3V6M
+2.5V
A
C426
0.1U_0402_10V6K
C427
0.1U_0402_10V6K
C428
0.1U_0402_10V6K
C429
0.1U_0402_10V6K
C430
0.1U_0402_10V6K
C431
0.1U_0402_10V6K
C432
0.1U_0402_10V6K
C433
0.1U_0402_10V6K
C434
0.1U_0402_10V6K
C435
0.1U_0402_10V6K
C436
0.1U_0402_10V6K
C437
0.1U_0402_10V6K
C438
10U_0805_6.3V6M

Title
5
DDR-SODIMM SLOT1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
14
of
65
+2.5V
DDRA_SDQ[0..63]
+2.5V
+2.5V
+2.5V
1
DDRA_SDQS[0..7]
D DRA_ADD[0..15]
JP23
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDRA_SDM[0..7]
<9,14,16> DDRA_SDM[0..7]
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ0

D
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
<9> DDRA_CLK3
<9> DDRA_CLK3#
DDRA_SDQ16
DDRA_SDQ17
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE3
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SMA13
DDRA_SWE#
DDRA_SCS#2
DDRA_SMA15
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
B
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ48
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
<14,24,27> SMB_CK_DAT2
<14,24,27> SMB_CK_CLK2
+3VS
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ4
R470
C392
0.1U_0402_10V6K 1K_0603_1%
D DRB_VREF
<9,14,16> DDRA_ADD[0..15]
R471
C393
0.1U_0402_10V6K 1K_0603_1%
2
<9,14,16> DDRA_SDQS[0..7]
<9,14,16> DDRA_SDQ[0..63]
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRB_VREF trace width of

20mils and space
20mils(min)

DDRA_SDQ20
DDRA_SDQ21
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ30
DDRA_SDQ31
<9,16> DDRA_CKE_R3
DDRA_CKE_R3 2
R1122
1 DDRA_CKE3
10_0402_5%
<9,16> DDRA_CKE_R2
DDRA_CKE_R2 2
R1121
RP26
DDRA_SMA9 1
DDRA_SMA12 2
1 DDRA_CKE2
10_0402_5%
RP29
4
3
DD RA_ADD9
D DRA_ADD12
DDRA_SMA5
DDRA_SMA7
10_0404_4P2R_5%
RP32
1
4 DD RA_ADD5
2
3 DD RA_ADD7
DDRA_SMA11
DDRA_SMA8
DDRA_SMA1
DDRA_SMA3
1
2
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SMA13 1
DDRA_SMA10 2
DD RA_ADD8 1
D DRA_ADD11 2
4
3
DDRA_SMA8
DDRA_SMA11
10_0404_4P2R_5%
RP35
DD RA_ADD4 1
DDRA_SMA4
4
DD RA_ADD6 2
DDRA_SMA6
3
C
DDRA_CKE2
DDRA_SMA14
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#3
<9,14,16> DDRA_WE#
<9,16> DDRA_CS#2
DDRA_SDQ36
DDRA_SDQ37
10_0404_4P2R_5%
RP38
4 DD RA_ADD1
3 DD RA_ADD3
DD RA_ADD0 1
DD RA_ADD2 2
10_0404_4P2R_5%
RP42
4 D DRA_ADD13
3 D DRA_ADD10
D DRA_ADD14 2
R390
DDRA_SMA14
1
10_0402_5%
DDRA_RAS#
2
R396
1 DDRA_SRAS#
10_0402_5%
DDRA_CAS#
2
R393
1 DDRA_SCAS#
10_0402_5%
DDRA_CS#3
2
R402
1 DDRA_SCS#3
10_0402_5%
10_0404_4P2R_5%
DD RA_WE#
2
1 DDRA_SWE#
R392
10_0402_5%
DDRA_CS#2 2
1 DDRA_SCS#2
R401
10_0402_5%
DDRA_SMA15 2
1 D DRA_ADD15
R391
10_0402_5%
10_0404_4P2R_5%
RP39
DDRA_SMA0
4
DDRA_SMA2
3
10_0404_4P2R_5%
<9,14,16> DDRA_RAS#
<9,14,16> DDRA_CAS#
<9,16> DDRA_CS#3
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ46
DDRA_SDQ47
DDRA_CLK4# <9>
DDRA_CLK4 <9>
DDRA_SDQ60
DDRA_SDQ61
B
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
+3VS
AMP_1565917-1
DIMM1
STANDARD
System Memory Decoupling caps

+2.5V
1
A
C394
C395
C396
C397
C398
C399
C400
C401
C402
150U_D2_6.3VM
1
C1118 +
22U_1206_10V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
150U_D2_6.3VM
C1119 +
10U_0805_6.3V6M
2
10U_0805_6.3V6M
+2.5V
C403
0.1U_0402_10V6K
C404
0.1U_0402_10V6K
C405
0.1U_0402_10V6K
C406
0.1U_0402_10V6K
C407
0.1U_0402_10V6K
C408
0.1U_0402_10V6K
C409
0.1U_0402_10V6K
1
C410
0.1U_0402_10V6K
C1120 +
C1121 +
2
150U_D2_6.3VM

Title
150U_D2_6.3VM
3
DDR-SODIMM SLOT2
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
15
of
65
DDR Termination resistors & Decoupling caps

+1.25VS
+1.25VS
RP65
RP67
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ12
DDRA_SDQ13
1
2
3
4
8
7
6
5
8
7
6
5
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ14
1
2
3
4
56 _0804_8P4R_5%
RP68
8
7
6
5
4
3
56 _0804_8P4R_5%
RP69
DDRA_CKE_R0
1
DDRA_CKE_R1
2
1
2
3
4
56 _0804_8P4R_5%
RP71
8
7
6
5
8
7
6
5
33_0404_4P2R_5%
PIR
RP75
DD RA_ADD9
1
DD RA_ADD3
2
DD
RA_ADD7
3
DD RA_ADD5
4
1
2
3
4
56 _0804_8P4R_5%
RP74
8
7
6
5
1
2
3
4
56 _0804_8P4R_5%
RP77
8
7
6
5
8
7
6
5
33_0804_8P4R_5%
RP81
DD RA_ADD8
1
DD RA_ADD6
2
DD RA_ADD4
3
DD RA_ADD2
4
1
2
3
4
56 _0804_8P4R_5%
RP80
8
7
6
5
8
7
6
5
33_0804_8P4R_5%
RP84
DD RA_ADD0
1
D DRA_ADD14
2
DDRA_RAS#
3
DDRA_CAS#
4
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ22
4
3
33_0804_8P4R_5%
RP87
DD RA_WE#
1
D DRA_ADD11
2
1
2
3
4
56 _0804_8P4R_5%
RP83
8
7
6
5
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ28
1
2
3
4
56 _0804_8P4R_5%
RP86
8
7
6
5
DDRA_SDQ29 1
DDRA_SDM3 2
DDRA_SDQ25 3
DDRA_SDQS3 4
56 _0804_8P4R_5%
RP90
8
7
6
5
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ20
DDRA_SDQ21
RP66
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ26
DDRA_SDQ27
1
2
3
4
8
7
6
5
DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>
BOM & Layout 93.1.9

R1180
2
@100_0402_5%
33_0804_8P4R_5%
RP78
DD RA_ADD1
8
1
D DRA_ADD10
7
2
D DRA_ADD13
6
3
D DRA_ADD15
5
4
DDRA_RAS# <9,14,15>
DDRA_CAS# <9,14,15>
R474
DDRA_CS#0 <9,14>
DDRA_CS#3 <9,15>
33_0404_4P2R_5%
D DRA_ADD12
1
33_0402_5%
RP72
DDRA_CKE_R3
4
1
DDRA_CKE_R2
3
2
56 _0804_8P4R_5%
RP70
DDRA_SDQS4
1
DDRA_SDQ34
2
DDRA_SDM4
3
DDRA_SDQ38
4
8
7
6
5
56 _0804_8P4R_5%
RP73
DDRA_SDQ35
1
DDRA_SDQ39
2
DDRA_SDQ44
3
DDRA_SDQ40
4
8
7
6
5
56 _0804_8P4R_5%
RP76
DDRA_SDQ46
1
DDRA_SDQ47
2
DDRA_SDQ42
3
DDRA_SDQ43
4
8
7
6
5
56 _0804_8P4R_5%
RP79
DDRA_SDQ45
1
DDRA_SDM5
2
DDRA_SDQ41
3
DDRA_SDQS5
4
8
7
6
5
56 _0804_8P4R_5%
RP82
DDRA_SDQ60
1
DDRA_SDQ61
2
DDRA_SDQ56
3
DDRA_SDQ57
4
8
7
6
5
56 _0804_8P4R_5%
RP85
DDRA_SDM7
1
DDRA_SDQ62
2
DDRA_SDQS7
3
DDRA_SDQ58
4
8
7
6
5
56 _0804_8P4R_5%
RP88
DDRA_SDQ63
1
DDRA_SDQ52
2
DDRA_SDQ59
3
DDRA_SDQ48
4
8
7
6
5
56 _0804_8P4R_5%
RP91
DDRA_SDQ53
1
DDRA_SDM6
2
DDRA_SDQ49
3
DDRA_SDQS6
4
8
7
6
5
56 _0804_8P4R_5%
RP93
DDRA_SDQ54
1
DDRA_SDQ55
2
DDRA_SDQ51
3
DDRA_SDQ50
4
DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>
33_0404_4P2R_5%
RP92
DDRA_CS#1
4
1
DDRA_CS#2
3
2
DDRA_CS#1 <9,14>
DDRA_CS#2 <9,15>
33_0404_4P2R_5%
56 _0804_8P4R_5%
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ36
DDRA_SDQ37
8
7
6
5
DDRA_WE# <9,14,15>
33_0404_4P2R_5%
RP89
DDRA_CS#0
4
1
DDRA_CS#3
3
2
1
2
3
4
+2.5V
C475
0.1U_0402_10V6K
C476
0.1U_0402_10V6K
C477
0.1U_0402_10V6K
C478
0.1U_0402_10V6K
C479
0.1U_0402_10V6K
C480
0.1U_0402_10V6K
C481
0.1U_0402_10V6K
C482
0.1U_0402_10V6K
+1.25VS
+2.5V
C493
0.1U_0402_10V6K
C494
0.1U_0402_10V6K
C495
0.1U_0402_10V6K
C496
0.1U_0402_10V6K
C497
4.7U_0805_16V6K
+1.25VS
56 _0804_8P4R_5%
DDRA_SDQ[0..63]
<9,14,15> DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
<9,14,15> DDRA_SDQS[0..7]
D DRA_ADD[0..15]
<9,14,15> DDRA_ADD[0..15]
DDRA_SDM[0..7]
<9,14,15> DDRA_SDM[0..7]
+2.5V
C451
0.1U_0402_10V6K
C452
0.1U_0402_10V6K
C453
0.1U_0402_10V6K
C454
0.1U_0402_10V6K
C455
0.1U_0402_10V6K
C456
0.1U_0402_10V6K
C457
0.1U_0402_10V6K
C458
0.1U_0402_10V6K
+1.25VS
+1.25VS
C459
0.1U_0402_10V6K
C460
0.1U_0402_10V6K
C461
0.1U_0402_10V6K
C462
0.1U_0402_10V6K
C463
0.1U_0402_10V6K
C464
0.1U_0402_10V6K
C465
0.1U_0402_10V6K
C466
0.1U_0402_10V6K
+1.25VS
C467
0.1U_0402_10V6K
C468
0.1U_0402_10V6K
C469
0.1U_0402_10V6K
C470
0.1U_0402_10V6K
C471
0.1U_0402_10V6K
C472
0.1U_0402_10V6K
C473
0.1U_0402_10V6K
C474
0.1U_0402_10V6K
+1.25VS
C483
C484
C485
C486
C487
C488
C489
C490
+ C491
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
4.7U_0805_16V6K
+ C492
4.7U_0805_16V6K
2
@100U_D2_10M_R45 100U_D2_10M_R45
2

Title
5
DDR Termination Resistors

Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
16
of
65
If M10+P POP 47_0603_1%

If M9+P POP 137_0603_1%
2 (15mil) 47_0603_1%
@47_0603_1%
2
<10> AGP_DBI_HI/PIPE#
<10> AGP_DBI_LO
AF29
AD27
AE28
ST0
ST1
ST2
AGP_SBSTB
AGP_SBSTB#
AB29
AB28
SB_STBF
SB_STBS
M26
M27
AGPREF
AGPTEST
DIGON
BLON/(BLON#)
AE12
AG12
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
DDC2CLK
DDC2DATA
AE13
AE14
HPD1
AF12
R
G
B
HSYNC
VSYNC
AK27
AJ27
AJ26
AG25
AH25
AGP_DBI_HI/PIPE# AB25
AGP_DBI_LO AB26
715_0603_1%
TV_CRMA
TV_LUMA
TV_COMPS
DBI_HI
DBI_LO
AC25
AGP8X_DET#
AE11
AF11
DMINUS
DPLUS
AK21
R2SET
AJ23
AJ22
AK22
AJ24
AK24
C_R
Y_G
COMP_B
H2SYNC
V2SYNC
AG23
AG24
DDC3CLK
DDC3DATA
R936
10K_0402_5%
SSIN
AK25
SSIN
R574
10K_0402_5%
SSOUT
AJ25
SSOUT
XTALIN
R275 1
1
<27> AGP_SUS_STAT#
R253
2 1K_0603_5%
2
SUSSTAT#
AH28
XTALIN
AJ29
XTALOUT
AH27
TESTEN
AG26
SUS_STAT#
THRM
R238
1 @10K_0402_5%
STRAP_F
R240
1 @10K_0402_5%
STRAP_G
R241
R242
2
2
1 M10@10K_0402_5%
1 @10K_0402_5%
STRAP_H
R243
R244
2
2
1 M10@10K_0402_5%
1 @10K_0402_5%
STRAP_J
R245
R246
2
2
1 @10K_0402_5%
1 @10K_0402_5%
STRAP_K
R247
R248
2
2
1 @10K_0402_5%
1 @10K_0402_5%
STRAP_O
R250
1 @10K_0402_5%
STRAP_L
R252
1 @10K_0402_5%
STRAP_M
R254
1 @10K_0402_5%
STRAP_N
R255
1 @10K_0402_5%
STRAP_R
R256
R1255
2
2
1 @10K_0402_5%
1 10K_0402_5%
STRAP_S
R257
R1256
2
2
1 @10K_0402_5%
1 10K_0402_5%
STRAP_T
R259
R260
2
2
1 @10K_0402_5%
1 @10K_0402_5%
1
2
1
2
GPIO5
GPIO6
R239
STRAP_R
STRAP_S
M10@1K_0603_1%
2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO9
GPIO11
DDC_DAT <10,25>
DDC_CLK <10,25>
STRAP_T
GPIO12
GPIO13
DVOMODE 1
R258
2
0_0402_5%
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXACLKTXACLK+
TXB0TXB0+
TXB1TXB1+
TXB2TXB2+
<25>
<25>
<25>
<25>
<25>
<25>
Size
Vendor
4Mx32
Samsung
4Mx32
Hynix
8Mx32
Samsung
8Mx32
Hynix
M9+X
TXACLK- <25>
TXACLK+ <25>
TXB0- <25>
TXB0+ <25>
TXB1- <25>
TXB1+ <25>
TXB2- <25>
TXB2+ <25>
M10-P
Ra
180_0603_5% 261_0603_1%
Rb
150_0402_5% 150_0402_5%
+3VS
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
+3VS
R261
10K_0402_5%
M9@10K_0402_5%
R1297
TXBCLKTXBCLK+
ENAVDD
1
R829
1
R830
ENAVDD <10,25>
M9@0_0402_5%
ENBKL
2
M10@0_0402_5%
VDD
TXBCLK- <25>
TXBCLK+ <25>
ENBKL
D
2
G
ENBKL <10,44>
OE
OUT
GND
RSET
AH26
AF25
AF24
AUXWIN
AF26
TEST_MCLK/(NC)
B6
TEST_YCLK/(NC)
E8
PLLTEST/(NC)
AE25
RSTB_MSK/(NC)
AG29
FREQOUT 1
R262
27MHZ_15P
C186
0.1U_0402_10V6K
Rb
spread sprum
100K_0402_5%
2
10K_0402_5%
U7
SS%
0
1
Spread % Setting for

Freq. Range
Fin>Fout>Fin-1.25%
+3VS
FREQOUT
+3VS
X1/CLK
2
R269
2
R270
Fin>Fout>Fin-3.75%
7
1
10K_0402_5%
8
1
10K_0402_5%
C189
2
2
0.1U_0402_10V6K
CLKOUT
5 R268 1
FS1
X2
FS2
SS%
2
R16
+3VS
L13
1
0.1U_0402_10V6K
1
1
2.2U_0603_6.3V4Z
C191
FCM2012C-800_0805
C190
22_0402_5%
2
XTALIN_SS
@0_0402_5%
2
R271
SS%
2
2
0.1U_0402_10V6K
R1 1
L
1
R276
@15P_0402_50V8J
Q30
(15mil)
AGP_RSET 1
2
R272
499_0402_1%
3VDDCDA
3VDDCDA <11,25>
3VDDCCL
3VDDCCL <11,25>
1
R274
C187
M9@2N7002_SOT23
C188
CRT_R <11,25>
CRT_G <11,25>
CRT_B <11,25>
CRT_HSYNC <11,25>
CRT_VSYNC <11,25>
XTALIN
2
261_0603_1%
R263
150_0402_5%
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
Ra
For VGA DDR
R267
1.5V OSC out for M9+X

1.2V OSC out for
M10-P
3.3V OSC out for W180
X1
Selection Table For W180
DDC1DATA
DDC1CLK
Vedio Memory Config.
+3VS
2
1 @10K_0402_5%
R273
XTALIN_SS
2
R2 @22_0402_5%
W180-01GT_SO8
1
0_0402_5%
10K_0402_5%
A
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)
2
1K_0603_5%
Title
0_0402_5%
SA002160E00(0301021300)
STRAP_E
AGP_ST0
AGP_ST1
AGP_ST2
1 @10K_0402_5%
M10@1K_0603_1%
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
AGP8X_DET#
Low:
<10> AGP8X_DET#
AGP3.0
<11,46> TV_CRMA
<11,46> TV_LUMA
<11,46> TV_COMPS
AD28
AD29
AC28
AC29
AA28
AA29
Y28
Y29
R265 1
2
M9+M10@0_0402_5%
(15mil)
R266
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
1 @10K_0402_5%
1
1
R1316
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
(25mil)
R264
AE10
R236
DVOMODE
R233
STRAP_D
<10> AGP_SBSTB
<10> AGP_SBSTB#
AJ10
AK10
AJ11
AH11
STRAP_B
GPIO4
0.1U_0402_10V6K
STP_AGP#
AGP_BUSY#
RBF#
AD_STBF_0
AD_STBF_1
AD_STBS_0
AD_STBS_1
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
1 @10K_0402_5%
VDD
C185
(Closed to M26)
+1.5VS
WBF#
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
GND
<10> VREF_8X_IN
AC26
AGP_STP#
AH30
AGP_BUSY# AH29
AGP_RBF#
AE29
AGP_ADSTB0
M28
AGP_ADSTB1
V25
AGP_ADSTB0# M29
AGP_ADSTB1# V26
<10,27> AGP_STP#
<10,27> AGP_BUSY#
<10> AGP_RBF#
<10> AGP_ADSTB0
<10> AGP_ADSTB1
<10> AGP_ADSTB0#
<10> AGP_ADSTB1#
PCICLK
RST#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTA#
R234
AF5
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
R232
VGA_Disable
GPIO7
<10> AGP_WBF#
AG30
AG28
AF28
AD26
M25
N26
V29
V28
W29
W28
AE26
STRAP_A
+3VS
NB_RST# 1
2
R6
<10> AGP_REQ#
0_0603_5%
<10> AGP_GNT#
<10> AGP_PAR
<10> AGP_STOP#
<10> AGP_DEVSEL#
<10> AGP_TRDY#
<10> AGP_IRDY#
<10> AGP_FRAME#
<10,26,31,34> PCI_PIRQA#
CLK_AGP_EXT_66M
NB_RST_R#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
ID_Disable
GPIO8
D69
1
ROMCS#
+3VS
For 8Mx32 VGA DRAM only
<8,26> NB_RST#
C/BE#0
C/BE#1
C/BE#2
C/BE#3
AGP, DAC & LVDS INTERFACE
R1149
@10K_0402_5%
@RB751V_SOD323
N29
U28
P26
U26
VREFG/(NC)
STRAP_G
AJ5
STRAP_H
AH5
STRAP_J
AJ4
STRAP_K
AK4
STRAP_D
AH4
STRAP_E
AF4
STRAP_F
DRAM128M
AJ3
+3VS
STRAP_B
AK3
STRAP_A
AH3
STRAP_O
AJ2
DRAM128M
AH2
STRAP_L
R955
AH1
@10K_0402_5%
STRAP_M
AG3
STRAP_N
AG1
AG2
R235 1
AF3
2 @1K_0402_5%
AF2 MCLK_SPREADR237 1
2 XTALIN_SS
0_0402_5%
VREFG
(25 mil)
AG4
<24> CLK_AGP_EXT_66M
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
2
@10_0402_5%
LVDS
C184 @10P_0402_50V8K
1
2
1
R249
AGP8X
TMDS
<10> AGP_ST[0..2]
SSC DAC2
AGP_ST[0..2]
M10-P/(M9+X)
(1/6)
DAC1
AGP_CBE#[0..3]
<10> AGP_CBE#[0..3]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CLK
<10> AGP_SBA[0..7]
H29
H28
J29
J28
K29
K28
L29
L28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27
W26
W25
Y26
Y25
AA26
AA25
AA27
PCI/AGP
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SBA[0..7]
ZV PORT / EXT TMDS / GPIO / ROM
AGP_AD[0..31]
<10> AGP_AD[0..31]
+3VS
U6A
ATI M10-P & M9+X (AGP BUS)

3
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
17
of
65
<22> NMAA[0..13]
<22> NDQMA[0..7]
<22> NDQSA[0..7]
MEMORY
INTERFACE A
<22> NMDA[0..63]
NMDA[0..63]
NMAA[0..13]
NDQMA[0..7]
NDQSA[0..7]
U6B
M10-P/(M9+X)
AA0
(2/6)
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12/(AA13)
AA13/(AA12)
AA14/(NC)
E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
J25
F29
E25
A27
F15
C15
C11
E11
NDQMA0
NDQMA1
NDQMA2
NDQMA3
NDQMA4
NDQMA5
NDQMA6
NDQMA7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
J27
F30
F24
B27
E16
B16
B11
F10
NDQSA0
NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7
RASA#
A19
NMRASA#
CASA#
E18
NMCASA#
WEA#
E19
NMWEA#
CSA0#
E20
NMCSA0#
CSA1#
F20
NMCSA1#
CKEA
B19
NMCKEA
CLKA0
CLKA0#
B21
C20
NMCLKA0
NMCLKA0#
CLKA1
CLKA1#
C18
A18
NMCLKA1
NMCLKA1#
DIMA0
DIMA1
D30
B13
+2.5VS
R475
(25 mil)
1K_0402_1%
MVREFD
NMRASA# <22>
NMCASA# <22>
C498
NMWEA# <22>
0.1U_0402_10V6K
R478
1K_0402_1%
NMCSA0# <22>
NMCSA1# <22>
NMCKEA <22>
+2.5VS
1
NMCLKA0 <22>
NMCLKA0# <22>
NMCLKA1 <22>
NMCLKA1# <22>
R486
MVREFD
B7
MVREFD
MVREFS/(NC)
B8
MVREFS
(25 mil)
M10@1K_0402_1%
MVREFS
C503
M10@0.1U_0402_16V4Z
R487
M10@1K_0402_1%
2
2
DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
MEMORY INTERFACE
A
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
SA002160E00(0301021300)
Poped for M10-P

Depoped for
M9+X

Title
ATI M10-P/M9+X DDR-A

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
18
of
65
MEMORY
INTERFACE B
<23> NMDB[0..63]
<23> NMAB[0..13]
<23> NDQMB[0..7]
<23> NDQSB[0..7]
NMDB[0..63]
NMAB[0..13]
NDQMB[0..7]
NDQSB[0..7]
U6C
D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
M10-P/(M9+X)
(3/6)
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
E6
B2
J5
G3
W6
W2
AC6
AD2
NDQMB0
NDQMB1
NDQMB2
NDQMB3
NDQMB4
NDQMB5
NDQMB6
NDQMB7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
F6
B3
K6
G1
V5
W1
AC5
AD1
NDQSB0
NDQSB1
NDQSB2
NDQSB3
NDQSB4
NDQSB5
NDQSB6
NDQSB7
RASB#
R2
NMRASB#
CASB#
T5
NMCASB#
WEB#
T6
NMWEB#
CSB0#
R5
NMCSB0#
CSB1#
R6
NMCSB1#
CKEB
R3
NMCKEB
CLKB0
CLKB0#
N1
N2
NMCLKB0
NMCLKB0#
CLKB1
CLKB1#
T2
T3
NMCLKB1
NMCLKB1#
MEMVMODE0
MEMVMODE1
C6
C7
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12/(AB13)
AB13/(AB12)
AB14/(NC)
MEMORY INTERFACE B
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
NMRASB# <23>
NMCASB# <23>
B
NMWEB# <23>
NMCSB0# <23>
NMCSB1# <23>
NMCKEB <23>
NMCLKB0 <23>
NMCLKB0# <23>
NMCLKB1 <23>
NMCLKB1# <23>
+1.8VS
DIMB0
DIMB1
MEMTEST
R509 1
R510 1
2 4.7K_0402_5%
2 4.7K_0402_5%
R511 1
2 47_0603_1%
(15mil)
E3
AA3
C8
SA002160E00(0301021300)

Title
ATI M10-P/M9+X DDR-B

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
19
of
65
POWER
INTERFACE
U6D
+2.5VS
Poped for
M10-P
R277 1
R278 1
+1.5VS
2
2
R279 1
M10@0_0805_5%
Poped for M10-P

Poped for M9+X
B
+1.8VS
R282 1
2
M9@0_0805_5%
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_DAC1.8
M10@0_0402_5%
M10@0_0402_5%
B1
B30
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
D5
D8
D11
D13
D14
D17
D20
D23
D26
E27
F4
G7
G10
G13
G15
G19
G22
G27
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N4
N7
N8
R1
T4
T7
T8
V4
V7
V8
D19
R4
AC11
AC20
H11
H20
+VDDC1.5 L23
P8
Y23
Y8
AK12
AJ12
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1/(CLKAFB)
VDDR1/(CLKBFB)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
VDDC15/(VDDC18)
AVDD
A2VDD
A2VDD
A2VDDQ
AH22
AJ21
AF23
A2VSSN
A2VSSN
A2VSSQ
AH23
AD24
VDDRH0
VDDRH1
F18
N6
VSSRH0
VSSRH1
F19
M6
MPVDD
MPVSS
A7
A6
PVDD
PVSS
AK28
AJ28
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
AC10
AC9
AD10
AD9
AG7
0.1U_0402_10V6K
22U_1206_10V4Z
+VDD_MEMPLL1.8
C193
C194
AVSSN
AVSSQ
LVSSR
LVSSR
LVSSR
LVSSR
LPVSS
C197
22U_1206_10V4Z
C202
2.2U_0603_6.3V4Z
C198
C199
2
0.1U_0402_10V6K
C92
0.01U_0402_16V7K
1
C200
2
0.1U_0402_10V6K
C201
0.1U_0402_10V6K
1
C862
10U_0805_6.3V6M
C863
AF13
AF14
TXVSSR
TXVSSR
TXVSSR
AG13
AG14
AH12
C866
0.01U_0402_16V7K 0.1U_0402_10V6K
1
C867
C868
C869
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K
C207
L15
1
2
CHB1608U301_0603
(20 mil)
+2.5VS
C203
C204
0.1U_0402_10V6K
1U_0603_10V6K
0.1U_0402_10V6K
1
C870
C871
2
2
0.1U_0402_10V6K
+2.5VS
C205
0.1U_0402_10V6K
+VDD_PLL1.8
L16
1
2
CHB1608U301_0603
1
C208
C209
0.1U_0402_10V6K
L17
1
2
CHB1608U301_0603
(20 mil)
+1.8VS
10U_0805_6.3V6M
+1.8VS
C210
0.1U_0402_10V6K
0.1U_0402_10V6K
+VDD_DAC1.8
+VDD_MEMPLL1.8
L18
1
2
CHB1608U301_0603
Poped for M10-P

(20 mil)
R280
1
1
R281
M10@0_0603_5%
2
+VDD_PNLIO2.5
2
+VDD_PNLIO1.8
M9@0_0603_5%
+VDD_PNLIO1.8
+VDD_PNLPLL1.8
C211
10U_0805_6.3V6M
Poped for M9+X
L19
1
2
CHB1608U301_0603
(20 mil)
+1.8VS
C212
C213
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.8VS
2.2U_0603_6.3V4Z
C931
+VDD_PNLIO1.8
(20 mil)
+VDD_DAC1.8
10U_0805_6.3V6M
L20
1
2
CHB1608U301
0.1U_0402_10V6K
C215
C216
C217
0.1U_0402_10V6K
+VDDC1.5
0.1U_0402_10V6K
C967
0.1U_0402_10V6K
(20 mil)
C218
10U_0805_6.3V6M
SA002160E00(0301021300)
1
2
@CHB1608U301
C219
C220
C968
C969
0.1U_0402_10V6K
0.1U_0402_10V6K
C970
0.1U_0402_10V6K
+2.5VS
U59
VOUT
VIN
PG
EN
0.1U_0402_10V6K
L21
5
2
+LVDDR
0.1U_0402_10V6K
+VDD_PNLIO1.8
As close as possible to related pin
+1.8VS
+VDD_PNLIO2.5
TXVDDR
TXVDDR
C865
+2.5VDDRH
L14
1
2
CHB1608U301_0603
(20 mil)
C206
0.1U_0402_10V6K
1
2
2
2
0.01U_0402_16V7K
0.1U_0402_10V6K
+VDD_PNLPLL1.8
C214
AE23
AE21
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)
(20 mil)
AF20
AF15
AE19
AE16
AJ19
VSS1DI
VSS2DI
+VDD_DAC2.5
AE20 +LVDDR
AE17
AF21
AE15
AJ20
AE24
AE22
C196
0.01U_0402_16V7K
0.1U_0402_10V6K
+3VS
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27
VDD1DI
VDD2DI
0.01U_0402_16V7K
1
+VDD_PLL1.8
+1.5VS
LVDDR_25/(LVDDR_18_25)
LVDDR_25/(LVDDR_18_25)
LVDDR_18
LVDDR_18
LPVDD
C195
+1.5VS
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
+3VS
0.1U_0402_10V6K
TPVDD
TPVSS
AH24
AG21
AH21
AF22
+2.5VDDRH
C192
I/O POWER
+2.5VS
D
M10-P/(M9+X)
(4/6)
GND
+3VS
MIC5205-2.8BM5_SOT23-5~D
A
C549
@470P_0402_50V7K
SA052050010(MIC5205-2.8BM5), max:150mA

Title
ATI M10-P/M9+X POWER-A

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
20
of
65
U6E
+VGA_CORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CORE POWER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H4
H8
H9
H12
H14
H18
H21
H23
H27
K1
K23
K24
K27
K30
K7
K8
L4
M30
M7
M8
N23
N24
N27
P4
R23
R24
R30
R7
R8
T1
T27
U23
U4
U8
V30
W23
W24
W27
W7
W8
Y4
G9
G12
G16
G18
G21
G24
POWER
INTERFACE
SA002160E00(0301021300)
+VGA_CORE
22U_1206_10V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
0.01U_0402_16V7K
1
+
C221
1
C223
47U_D2_6.3VM
1
C224
1
C225
1
C226
22U_1206_10V4Z
1
C227
1
C228
0.1U_0402_10V6K
1
C229
0.1U_0402_10V6K
C230
2
+VGA_CORE
U6F
0.01U_0402_16V7K
1
C222
1
+
C231
150U_D2_6.3VM
2
2
0.01U_0402_16V7K
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
P18
P19
U12
U13
U14
U17
U18
U19
V12
V13
V14
V17
V18
V19
W12
W13
W14
W17
W18
W19
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AB22
AB9
J10
J12
J14
J15
J16
J17
J19
J21
K22
K9
M22
M9
P22
P9
R22
R9
T22
T9
U22
U9
V22
V9
Y22
Y9
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
M10-P/(M9+X)
(6/6)
VDDC
VDDC
AD15
AD13
AC17
AC15
AC13
VDDCI
VDDCI
VDDCI
VDDCI
T12
M15
W16
R19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R12
R13
T13
R14
T14
N15
P15
R15
T15
U15
V15
W15
H16
M16
N16
P16
R16
T16
U16
V16
R17
T17
R18
T18
T19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA22
AA9
J11
J13
J18
J20
J22
J9
L22
L9
N22
N9
W22
W9
M10-P&M9+X VDDC
VDDC
COMMON
VDDC
CORE POWER
M10-P/(M9+X)
(5/6)
A10
A16
A2
A22
A29
AA30
AB1
AB23
AB24
AB27
AB4
AB7
AB8
AC12
AC14
AC16
AC18
AC4
AD12
AD16
AD18
AD25
AD30
AE27
AG11
AG15
AG18
AG22
AG27
AG5
AG9
AJ1
AJ30
AK2
AK29
C1
C28
C3
C30
D10
D12
D15
D18
D21
D24
D25
D27
D4
D6
D9
E4
F27
M10-P
ONLY
M9+X
ONLY
+VGA_CORE_CI
SA002160E00(0301021300)
+2.5VS
22U_1206_10V4Z
1
0.1U_0402_10V6K
1
C232
1
C233
0.1U_0402_10V6K
1
C234
2
1
C235
0.01U_0402_16V7K
1
C236
2
1
C237
1
C238
C239
0.01U_0402_16V7K
+VGA_CORE_CI
(20 mil)
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C240
+2.5VS
22U_1206_10V4Z
1
0.1U_0402_10V6K
1
C243
1
C244
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C245
2
1
C246
L22
1
2
CHB1608U301
0.1U_0402_10V6K
0.1U_0402_10V6K
0.01U_0402_16V7K
1
C247
2
0.1U_0402_10V6K
1
C248
+VGA_CORE
C242
0.1U_0402_10V6K
JOPEN5
PAD-OPEN 4x4m
1
2
10U_0805_6.3V6M
1
C249
C241
2
480MIL
As close as ppossible to related pin
C250
0.01U_0402_16V7K
+1.2VS_VGA
(12A,480mils ,Via NO.=24)
0.1U_0402_10V6K

Title
ATI M10-P/M9+X POWER-B

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
21
of
65
VGA DDR FOR CHANNEL A

+2.5VS
+2.5VS
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0805_10V3M
C505
10U_0805_10V3M
C506
C507
C508
1
C509
C510
1
C1123
1
C511
C1126
10U_0805_10V3M
1
C512
22U_1206_10V4Z
C513
2
10U_0805_10V3M
0.1U_0402_10V6K
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
B3
H12
H3
B12
DM0
DM1
DM2
DM3
NDQSA2
NDQSA3
NDQSA0
NDQSA1
B2
H13
H2
B13
DQS0
DQS1
DQS2
DQS3
VREF_1
N13
M13
L9
M10
VREF
MCL
RFU1
RFU2
M2
L2
L3
N2
RAS#
CAS#
WE#
CS#
0.1U_0402_10V6K
1K_0402_1%
(25mil)
1
C516
0.1U_0402_10V6K
<18>
<18>
<18>
<18>
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
<18> NMCKEA
NMCLKA0
R625
56.2_0402_1%
C628
10P_0402_50V8K
R627
56.2_0402_1%
NMCLKA0#
CKE
CK
CK#
C4
C11
H4
H11
L12
L13
M3
M4
N3
NC
NC
NC
NC
NC
NC
NC
NC
NC
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
D8
E4
E11
L4
L7
L8
L11
+2.5VS
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
NDQMA6
NDQMA7
NDQMA4
NDQMA5
B3
H12
H3
B12
DM0
DM1
DM2
DM3
NDQSA6
NDQSA7
NDQSA4
NDQSA5
B2
H13
H2
B13
DQS0
DQS1
DQS2
DQS3
VREF_2
N13
M13
L9
M10
VREF
MCL
RFU1
RFU2
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
M2
L2
L3
N2
RAS#
CAS#
WE#
CS#
R489
1K_0402_1%
(25mil)
R491
1K_0402_1%
+2.5VS
C517
0.1U_0402_10V6K
NMCKEA
<18> NMCLKA1
NMCLKA1
R626
56.2_0402_1%
C629
10P_0402_50V8K
1
R628
56.2_0402_1%
<18> NMCLKA1#
NMCLKA1#
NMCSA1#
N12
CKE
M11
M12
CK
CK#
C4
C11
H4
H11
L12
L13
M3
M4
N3
NC
NC
NC
NC
NC
NC
NC
NC
NC
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
NMCSA1#
N12
M11
M12
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NMDA23
NMDA22
NMDA21
NMDA20
NMDA19
NMDA18
NMDA17
NMDA16
NMDA31
NMDA30
NMDA29
NMDA28
NMDA27
NMDA26
NMDA25
NMDA24
NMDA7
NMDA6
NMDA5
NMDA4
NMDA3
NMDA2
NMDA1
NMDA0
NMDA15
NMDA14
NMDA13
NMDA12
NMDA11
NMDA10
NMDA9
NMDA8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
D8
E4
E11
L4
L7
L8
L11
NMDA55
NMDA54
NMDA53
NMDA52
NMDA51
NMDA50
NMDA49
NMDA48
NMDA63
NMDA62
NMDA61
NMDA60
NMDA59
NMDA58
NMDA57
NMDA56
NMDA39
NMDA38
NMDA37
NMDA36
NMDA35
NMDA34
NMDA33
NMDA32
NMDA47
NMDA46
NMDA45
NMDA44
NMDA43
NMDA42
NMDA41
NMDA40
+2.5VS
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
R488
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
NDQMA2
NDQMA3
NDQMA0
NDQMA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
+2.5VS
C1125
0.1U_0402_10V6K
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
U29
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
U28
<18> NMCSA1#
NDQSA[0..7]
<18> NDQSA[0..7]
<18> NMCLKA0#
NDQMA[0..7]
<18> NDQMA[0..7]
<18> NMCLKA0
1
C1124
NMDA[0..63]
<18> NMDA[0..63]
1
C1122
NMAA[0..13]
<18> NMAA[0..13]
1K_0402_1%
1
C515
0.1U_0402_10V6K
R490
22U_1206_10V4Z
1
C514
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
C504
K4D263238A-GC
K4D263238A-GC

Title
VGA DDR FOR CHANNEL A

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
22
of
65
+2.5VS
22U_1206_10V4Z
1
C518
0.1U_0402_10V6K
0.01U_0402_16V7K
0.1U_0402_10V6K
0.01U_0402_16V7K
C519
2
1
C520
C521
1
C522
C523
C524
0.01U_0402_16V7K
C525
C526
22U_1206_10V4Z
22U_1206_10V4Z
1
C527
0.01U_0402_16V7K
0.1U_0402_10V6K
1
C528
1
C529
0.1U_0402_10V6K
1
C530
0.01U_0402_16V7K
0.1U_0402_10V6K
C531
1
C532
0.1U_0402_10V6K
VGA DDR FOR CHANNEL

B
+2.5VS
C533
C534
0.01U_0402_16V7K
0.01U_0402_16V7K
1
C535
22U_1206_10V4Z
1
C536
C537
0.01U_0402_16V7K
D
0.1U_0402_10V6K
0.1U_0402_10V6K
NMAB[0..13]
<19> NMAB[0..13]
DM0
DM1
DM2
DM3
NDQSB0
NDQSB2
NDQSB1
NDQSB3
B2
H13
H2
B13
DQS0
DQS1
DQS2
DQS3
VREF_3
N13
M13
L9
M10
VREF
MCL
RFU1
RFU2
M2
L2
L3
N2
RAS#
CAS#
WE#
CS#
1K_0603_1%
(25mil)
R496
C538
0.1U_0402_10V6K
<19>
<19>
<19>
<19>
1K_0603_1%
1
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
<19> NMCKEB
NMCLKB0
<19> NMCLKB0
R629
R6311
10P_0402_50V8K
56.2_0402_1%
C630
56.2_0402_1%
2
<19> NMCLKB0#
NMCSB1#
CKE
CK
CK#
C4
C11
H4
H11
L12
L13
M3
M4
N3
NC
NC
NC
NC
NC
NC
NC
NC
NC
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
D8
E4
E11
L4
L7
L8
L11
R494
1K_0603_1%
(25mil)
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
NDQMB5
NDQMB7
NDQMB4
NDQMB6
B3
H12
H3
B12
DM0
DM1
DM2
DM3
NDQSB5
NDQSB7
NDQSB4
NDQSB6
B2
H13
H2
B13
DQS0
DQS1
DQS2
DQS3
VREF_4
N13
M13
L9
M10
VREF
MCL
RFU1
RFU2
M2
L2
L3
N2
RAS#
CAS#
WE#
CS#
R497
1K_0603_1%
+2.5VS
C539
0.1U_0402_10V6K
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
<19> NMCLKB1
NMCLKB1
R630
R6321
56.2_0402_1%
C631
10P_0402_50V8K
56.2_0402_1%
2
<19> NMCLKB1#
NMCLKB1#
NMCSB1#
N12
CKE
M11
M12
CK
CK#
C4
C11
H4
H11
L12
L13
M3
M4
N3
NC
NC
NC
NC
NC
NC
NC
NC
NC
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
<19> NMCSB1#
NMCLKB0#
N12
M11
M12
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
+2.5VS
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
D8
E4
E11
L4
L7
L8
L11
NMDB47
NMDB46
NMDB45
NMDB44
NMDB43
NMDB42
NMDB41
NMDB40
NMDB63
NMDB62
NMDB61
NMDB60
NMDB59
NMDB58
NMDB57
NMDB56
NMDB39
NMDB38
NMDB37
NMDB36
NMDB35
NMDB34
NMDB33
NMDB32
NMDB55
NMDB54
NMDB53
NMDB52
NMDB51
NMDB50
NMDB49
NMDB48
+2.5VS
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
R495
NMDB7
NMDB6
NMDB5
NMDB4
NMDB3
NMDB2
NMDB1
NMDB0
NMDB23
NMDB22
NMDB21
NMDB20
NMDB19
NMDB18
NMDB17
NMDB16
NMDB15
NMDB14
NMDB13
NMDB12
NMDB11
NMDB10
NMDB9
NMDB8
NMDB31
NMDB30
NMDB29
NMDB28
NMDB27
NMDB26
NMDB25
NMDB24
B3
H12
H3
B12
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
NDQMB0
NDQMB2
NDQMB1
NDQMB3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
+2.5VS
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NDQSB[0..7]
<19> NDQSB[0..7]
U31
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
U30
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
NDQMB[0..7]
<19> NDQMB[0..7]
B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
NMDB[0..63]
<19> NMDB[0..63]
K4D263238A-GC
K4D263238A-GC

Title
VGA DDR FOR CHANNEL B

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
23
of
65
+3VS
+3V_CLK
CLK_BCLK
R193
@0_0402_5%
CLK_BCLK#
R194
@0_0402_5%
CK_ITP <5>
CK_ITP# <5>
L11
1
Width=40 mils
HB-1M2012-121JT03_0805
C118
0.1U_0402_10V6K
1
C119
2
10U_0805_6.3V6M
C120
0.1U_0402_10V6K
1
C121
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
2
0.1U_0402_10V6K
C122
C123
C124
0.1U_0402_10V6K
42
48
30
29
19
13
1
9
2.2P_0402_50V8C
XTALIN_CLK
2
Y2
R963
14.318MHZ
@1M_0402_5%
VDDCPU
VDDSD
VDDAGP
VDD48M
VDDPCI
VDDPCI
VDDREF
VDDXTAL
U5
C127
XIN
VDDA
+3V_VDD
36
C128
1
C130
XTALOUT_CLK
2
2.2P_0402_50V8C
0.1U_0402_10V6K
VSSA
37
VSSA
CPUT0
40
CLK_BCLK
XOUT
10U_0805_6.3V6M
1
C129
R195 1
0.1U_0402_10V6K
1
C126
SMB_CK_CLK2 35
SMB_CK_DAT2 34
0.1U_0402_10V6K
2 33_0402_1%
CK_BCLK
+3VS
R1056 1
R1111 1
R962 1
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
24/48#
PCI33/66#
10
45
12
26
11
CPUC0
39
CLK_BCLK#
R200 1
2 33_0402_1%
CPUT1
44
CLK_NB
R201 1
2 33_0402_1%
VTTPWRGD/PD#
CPU_STP#
PCI_STOP#
24/48#SEL
PCI33/66#SEL
<11> REFCLK1_NB
<38> CLK_14M_SIO
<27> CLK_SB_14M
2 @33_0402_1%
2 33_0402_1%
R996 1
R215 1
R997 1
2 68_0402_5%
2 33_0402_1%
2 33_0402_1%
R1068 1
2 33_0402_1%
CLK_48M
CLK_SD
FS2
FS1
FS0
27
28
4
3
2
CLK_IREF
38
2 49.9_0402_1%
R203 1
2 49.9_0402_1%
2 33_0402_1%
CLK_NB_BCLK# <11>
SDRAMOUT
47
MEM_66M
R205 1
2 33_0402_1%
CLK_MEM_66M <11>
AGPCLK0
AGPCLK1
32
31
AGP_66M
R208 1
AGP_EXT_66M R210 1
2 33_0402_1%
2 M9_M10@33_0402_1%
CLK_AGP_66M <11>
CLK_AGP_EXT_66M <17>
FS3/PCICLK_F0
FS4/PCICLK_F1
14
15
FS3
FS4
2 33_0402_1%
CLK_ALINK_SB <26>
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
16
17
20
21
22
23
IREF
R218
R213 1
8
5
18
24
25
33
46
41
GNDXTAL
GNDREF
GNDPCI
GNDPCI
GND48M
GNDAGP
GNDSD
GNDCPU
475_0402_1%
CLK_NB_BCLK <11>
R202 1
R204 1
48MHz_1
48MHz_0
FS2/REF2
FS1/REF1
FS0/REF0
CK_BCLK# <4>
CLK_NB#
<36> CLK_14M_CODEC
R206 1
R207 1
2 49.9_0402_1%
CK_BCLK#
43
CPUC1
<27> CLK_SB_48M
<31> CLK_SD_48M
CK_BCLK <4>
2 49.9_0402_1%
R197 1
SCLK
SDATA
+3VS
C125
R196 1
<14,15,27> SMB_CK_CLK2
<14,15,27> SMB_CK_DAT2
<27,46> VTT_PWRGD
L12
1
2
CHB2012U121_0805
ICS951402AGT_TSSOP48
CLOCK FREQUENCY SELECT TABLE
R220
Spreaf OFF OR
Center spread +/-0.3%
FS1
FS0
FS2
FS3
FS4
PCI33/66#
R219
Note: 0 = PULL LOW

1 = PULL HIGH
4
<5,13> BSEL1
D83
2 RB751V_SOD323
<5,13> BSEL0
D84
2 RB751V_SOD323
10K_0402_5%
+3V_CLK
R221
1
R222
@10K_0402_5% @10K_0402_5%
@10K_0402_5%
R223
10K_0402_5%
100
R998
R999
R224
R225
R226
R227
R228
10K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@10K_0402_5%
2
100
133
200
133
200
+3V_CLK
With Spread Enabled
MEM
CPU
FS4 FS3 FS2 FS1 FS0
A-LINK FREQ
PCI33/66# = HIGH
66MHZ
PCI33/66# = LOW
33MHZ

Title
Clock Generator
Size
Document Number
Rev
0.1
LA-2411
, 07, 2004
Date:
G
Sheet
24
H
of
65
LCD CONN
+3VS
TXB2+
TXB2-
<17> TXA0+
<17> TXA0-
TXA0+
TXA0-
<17> TXACLK+
<17> TXACLK<17> TXB1+
<17> TXB1-
TXACLK+
TXACLKTXB1+
TXB1+3VS
TXB0+
TXB0-
TXB0+ <17>
TXB0- <17>
TXBCLK+
TXBCLK-
C619
LCDVDD
R174
C620
0.01U_0402_50V7K
D16
<44> BKOFF#
2 RB751V_SOD323
DISPOFF#
220P_0402_50V7K
INVT_PWM <44>
DAC_BRIG <44>
+3VS
DDC_CLK <10,17>
DDC_DAT <10,17>
+3VS
+12VALW
1
INVPWR_B+
R1007
R175
R1008
LCDVDD
+12VALW
1
+12VALW
<11> TXA0+_NB
<11> TXA0-_NB
TXA0+_NB
TXA0-_NB
<11> TXB1+_NB
<11> TXB1-_NB
TXACLK+_NB
TXACLK-_NB
TXB1+_NB
TXB1-_NB
+3VS
For internal AGP
0.1U_0402_10V6K
27P_0402_50V8J
C88
R182
100K_0402_5%
27P_0402_50V8J
TXB0+_NB
TXB0-_NB
TXB0+_NB <11>
TXB0-_NB <11>
TXBCLK+_NB
TXBCLK-_NB
TXBCLK+_NB <11>
TXBCLK-_NB <11>
R181
1
1 2
0.1U_0402_10V6K
2
G
Q10
2N7002_SOT23 S
LCDVDD
D
C90
2
G
Q11
2N7002_SOT23
C91
150K_0402_5%
DISPOFF#
INVT_PWM
DAC_BRIG
ENAVDD
<10,17> ENAVDD
22K
Q12
22K
DDC_CLK
DDC_DAT
0.1U_0402_10V6K
4.7U_0805_10V4Z
DTC124EK_SOT23
R1115
SI2302DS: N CHANNEL
VGS: 4.5V, RDS: 85 mOHM
VGS: 2.5V, RDS: 115mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V
SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V
1.2K_0402_5%
INVPWR_B+
NAGP@JST BM40B-SRDS
D23
DAN217_SOT23
D22
DAN217_SOT23
D21
DAN217_SOT23
+3VS +5VS
CRT_VCC
D17
<11> TXACLK+_NB
<11> TXACLK-_NB
C87
C994
TXB2+_NB
TXB2-_NB
<11> TXB2+_NB
<11> TXB2-_NB
TXA1+_NB
TXA1-_NB
C993
<11> TXA1+_NB
<11> TXA1-_NB
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
AT LEAST 60 MIL
<11> TXA2+_NB
<11> TXA2-_NB
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
LCDVDD_A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
G
S Q9
SI2302DS 1N_SOT23
C89
0.047U_0402_16V4Z
R180
C86
4.7U_0805_10V4Z
+5VS
1K_0402_1%
JP28
100K_0402_5%
2.2K_0402_5%
DDC_CLK
DDC_DAT
TXA2+_NB
TXA2-_NB
2 L38
C997
KC FBM-L11-201209-221LMAT_0805
2.2K_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
INVPWR_B+
1
2 L2
KC FBM-L11-201209-221LMAT_0805
DISPOFF#
TXBCLK+ <17>
TXBCLK- <17> 10U_0805_10V3M
M9-M10@JST BM40B-SRDS
For M9/M110P/M11P
B+
4.7K_0402_5%
<17> TXB2+
<17> TXB2-
C618
TXA1+
TXA1-
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
<17> TXA1+
<17> TXA1-
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
TXA2+
TXA2-
1000P_0402_50V8J
<17> TXA2+
<17> TXA2-
AT LEAST 60 MIL
LCDVDD_A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
L41
1
2
KC FBM-L11-201209-221LMAT_0805
JP27
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
CRT CONNECTOR
2
1
RB411D_SOT23 FUSE_1A
C97
0.1U_0402_10V6K
3VDDCDA
<11,17> 3VDDCDA
R_CRT_VCC
F1
1
1
3VDDCCL
<11,17> 3VDDCCL
SUYIN_7849S-15G2T-HC
B
U57
R1153 20_0402_5%
2
74AHCT1G125GW
R187
CRTL_B
C102
10P_0402_50V8K
C103
C104
22P_0402_25V8K
2
C105
R1117
10P_0402_50V8K 75_0402_5%
L9
1
2
FBM-L10-160808-300LM-T
75_0402_5%
22P_0402_25V8K
22P_0402_25V8K
10P_0402_50V8K
2
DAN217_SOT23
DAN217_SOT23
C116
R191
R192
4.7K_0402_5%
10P_0402_50V8K
220P_0402_25V8K
220P_0402_25V8K
4
Q14
3VDDCCL
3
2N7002 1N_SOT23
4.7K_0402_5%
Title
+3VS
D43
C109
3
D42
74AHCT1G125GW
U58
C108
C117
1
3VDDCDA
3
2N7002 1N_SOT23
1
+5VS
CRT_VSYNC
CRT_VSYNCRFL
1
2
FBM-L10-160808-300LM-T
R1154 20_0402_5%
<11,17> CRT_VSYNC
Q13
CRT_HSYNCRFL
L10
1
R1118
4.7K_0402_5%
4.7K_0402_5%
C101
5
CRT_HSYNC
<11,17> CRT_HSYNC
C100 R186
2 FCM2012C-800_0805
75_0402_5%
CRTL_G
L6 1
R185
2
1K_0402
CRTL_R
2 FCM2012C-800_0805
R1150
CRT_VCC
2 FCM2012C-800_0805
L5 1
<11,17> CRT_B
CRT_B
L3 1
2
G
<11,17> CRT_G
10P_0402_50V8K
CRT_G
2
G
CRT_R
<11,17> CRT_R
JP6 6
11
1
7
12
2
8
13
3
CRT_VCC
9
14
4
10
15
5

LCD,CRT,TV-OUT & Inverter BD CONN.
Size
Custom
Date:
Document Number
Rev
0.1
LA-2411
, 07, 2004
Sheet
1
25
of
65
+3VS
PCI _IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
Trace length of PCI_CLK_R + PCI_CLK_FB should

be less than 200 mils.
A_CBE#[0..3]
U3A
H_CPUFERR#
R134
10_0402_5%
C77
@470_0402_5%
15P_0402_50V8J
2 2
R1000
Q98
@MMBT3904_SOT23
CPURSTIN#
1
+3VS
1
<5,8> H_RESET#
R946
+3VS
8.2K_0402_5%
A_SERR#
R40
SBCLK_STP#
<5,11,54> CPUCLK_STP#
H_PW RGOOD
**
C1068
1 220P_0402_50V7K
+3VS
<10> A_STROBE#
<10> A_DEVSEL#
<10> A_ACAT#
<10> A_END#
<10,13> A_PAR
<10> A_OFF#
C1067
1 220P_0402_50V7K
H_SMI#
C1066
1 220P_0402_50V7K
H_STPCLK#
C1065
1 220P_0402_50V7K
R921
H_IGNNE#
C1064
1 220P_0402_50V7K
4.7K_0402_5%
H_A20M#
C956
1 220P_0402_50V7K
H_INIT#
C617
1 220P_0402_50V7K
H_INTR
C78
1 220P_0402_50V7K
H_NMI
C79
1 220P_0402_50V7K
H_CPUSLP#
1K_0402_5%
<10> A_SBREQ#
<10> A_SBGNT#
<10,17,31,34> PCI_PIRQA#
<31> PCI_PIRQB#
<41> PCI_PIRQC#
<33,41> PCI_PIRQD#
+3VS
PLACE CLOSE TO CPU SOCKET
+VCC_CORE
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
H22
P23
L23
N23
N22
M23
M22
K22
M21
M20
L21
K21
L20
N21
K23
K20
F23
G21
F20
H21
F22
F21
G20
E21
E20
D23
D22
E22
D20
C23
D21
C22
L22
J23
G22
E23
H20
J21
G23
H23
J20
J22
P22
B21
B20
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#
SBCLK_STP#
PCICLK_STP#
N20
R23
CPU_STP#/DPSLP#
PCI_STP#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
C20
P20
B23
P21
A_INTA#
INTB#
INTC#
INTD#
RTCX1
AC12
X1
RTCX2
AC11
X2
R169
330_0402_5%
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
CPURSTIN#
<5> H_PWRGOOD
<5> H_INTR
<5> H_NMI
<5> H_INIT#
<5> H_SMI#
<5> H_CPUSLP#
<5> H_IGNNE#
<5> H_A20M#
R149
R150
R151
R152
R153
R154
R156
R158
R1001
47K_0402_5%
<5> H_STPCLK#
<54> DPRSLPVR
R1002
2 47K_0402_5%
R1064 1
R1065 1
R1067 1
B18
E4
B17
B16
C17
C16
F19
D17
D18
E19
E16
E17
E18
C19
C18
B19
H_A20M#
H_CPUFERR#
H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#
PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24/RTC_AD7
AD25/RTC_AD6
AD26/RTC_AD5
AD27/RTC_AD4
AD28/RTC_AD3
AD29/RTC_AD2
AD30/RTC_AD1
AD31/RTC_AD0
CBE#0/ROMA10
CBE#1/ROMA1
CBE#2/ROMWE#
CBE#3/RTC_RD#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR
STOP#
PERR#
SERR#
REQ#0
REQ#1
REQ#2
REQ#3/PDMAREQ0#
REQ#4/PLLBP33/PDMAREQ1#
GNT#0
GNT#1
GNT#2
GNT#3/PDMAGNT0#
GNT#4/PLLBP50/PDMAGNT1#
CLKRUN#
C15
B1
C1
A1
D2
B2
C2
A2
D3
C3
A3
D4
B4
C4
A4
D5
B5
C8
D8
B8
A8
C9
D9
B9
A9
C10
B10
D11
A10
C11
B11
D12
A11
B3
C5
A7
D10
B7
A6
C7
D7
A5
B6
C6
D6
B12
C12
D13
A12
C13
A13
B13
C14
D14
B14
A20
PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI _IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_CLKRUN#
PCI CLKS
MMBT3904_SOT23
1
+VCC_CORE
PCI_1394
PCI_LAN
PCI_PCM
PCI_MINI
PCI_EC
PCI_SIO
GPIO0
2 10K_0402_5% SB_APIC_D0
2 10K_0402_5% SB_APIC_D1
2 1K_0402_1%
PCI INTERFACE
2 2
Q5
<5> H_FERR#
CLK_ALINK_SB
PCICLKF
A_RST#
CPURSTIN#
CPU_PWRGD
INTR/LINT0
NMI/LINT1
INIT
SMI#
SLP#
IGNNE#
A20M#
FERR#
STPCLK#
SSMUXSEL/GPIO0
DPRSLPVR
APIC_D0
APIC_D1
APIC_CLK
R122
R123
R124
R126
R127
R128
1
1
1
1
1
1
2
2
2
2
2
2
PCI_CLK_R R130 1
PCI_CLK_FB
39_0402_5%
39_0402_5%
39_0402_5%
39_0402_5%
39_0402_5%
39_0402_5%
RP15
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_FRAME#
2 @22P_0402_50V8J
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
8.2K _8P4R_0804_5%
RP18
5
6
7
8
8.2K _8P4R_0804_5%
PCI_REQ#4
8.2K_0402_5%
R137
PCI_GNT#4
8.2K_0402_5%
R138
C
RP21
PCI_CBE#[0..3]
R1151 2
10K_0402_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PCI_CBE#[0..3] <31,33,34,41>
GPIO1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#0
LDRQ#1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
LPC_AD0 <38,44>
LPC_AD1 <38,44>
LPC_AD2 <38,44>
LPC_AD3 <38,44>
LPC_FRAME# <38,44>
SERIRQ
AC13
SIRQ
SIRQ <31,38,44>
USBOC5#/GPM1
RTC_ALE/USBOC4#/GPIO3
RTC_WR#/RTC_CLKOUT
RTC_CS#/USBOC3#/GPIO2
VBAT
RTC_GND
AA2
AB7
AB8
AC8
AC10
AB11
OVCUR#5
OVCUR#4
4
3
2
1
5
6
7
8
100K_1206_8P4R_5%
PCI_FRAME# <31,33,34,41>
PCI_DEVSEL# <31,33,34,41>
PCI_IRDY# <31,33,34,41>
PCI_TRDY# <31,33,34,41>
PCI_PAR <31,33,34,41>
PCI_STOP# <31,33,34,41>
PCI_PERR# <31,33,34,41>
PCI_SERR# <31,33,41>
PCI_REQ#0 <34>
PCI_REQ#1 <33>
PCI_REQ#2 <31>
PCI_REQ#3 <41>
PCI_REQ#4 <41>
PCI_GNT#0 <34>
PCI_GNT#1 <33>
PCI_GNT#2 <31>
PCI_GNT#3 <41>
PCI_GNT#4 <41>
PCI_CLKRUN# <33,38,41,44>
RP138
SIRQ
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
1
2
3
4
8
7
6
5
10K_0804_8P4R_5%
PCI_CLKRUN# R146 2
4.7K_0402_5%
GPIO0
R1155
1 10K_0402_5%
OVCUR#3
R1300
1 10K_0402_5%
OVCUR#4
R1157
1 10K_0402_5%
OVCUR#5
R1059
2 10K_0402_5%
+3V
+3V
LPC_DRQ#1 <38>
RTC Battery
BATT1
2
OVCUR#3 <35>
+RTCBATT
+RTCBATT
+SB_VBAT
D93
R168
1
PCI_RST#
PCI_RST# <11,30,31,33,34,38,41,44>
C80
1U_0603_10V4Z
W=20mils
R1298
1
2
220_0805_5%
JOPEN1
2
No short
2
CHGRTC
C1128
0.1U_0402_16V4Z
A
O
7
10 13
12
NB_RST#
NB_RST# <8,17>
I
G
11
32.768KHZ_12.5P_1TJS125DJ2A073
Place J1 close
to DDR-SODIMM
U45F
14
+3VALW
+3VALW
U45E
NBRST#
220_0805_5%
2
2
O
G
7
2
@20M_0603_5%
+RTCVCC
14
9
10K_0402_5%
12P_0402_50V8J
U45D
14
O
G
1
1
R966
R172
U45B
4
OUT
Y1
NC
4
3
2
1
BAS40-04_SOT23
PCIRST# 3
C82
5
6
7
8
South bridge SB200
14
1
IN
NC
2
C81
12P_0402_50V8J
5
6
7
8
4
3
2
1
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
+SB_VBAT
RTCX1
0.1U_0402_10V6K
4
3
2
1
RP17
C872
8.2K _8P4R_0804_5%
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
R171 20M_0603_5%
1
2
RTCX2
5
6
7
8
RP16
RTCBATT
+3VALW
4
3
2
1
8.2K _8P4R_0804_5%
PCI_AD[0..31] <29,31,33,34,41>
AB5
OVCUR#3
5
6
7
8
8.2K _8P4R_0804_5%
CLK_PCI_1394 <34>
CLK_PCI_LAN <33>
CLK_PCI_PCM <31>
CLK_PCI_MINI <41>
CLK_PCI_EC <44>
CLK_PCI_SIO <38>
2 39_0402_5%
C76 1
PCI_AD[0..31]
Y14
AA14
AB14
AA13
AB13
AC14
Y13
GPIO1/ROMCS#
L PC
R131
330_0402_5%
470_0402_5%
B15
D16
A14
A15
A16
A17
D15
A18
A19
Part 1 of 3
B22
R22
RTC
PULL DOWN FOR S3
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK_FB
SB200 SB
NBRST#
A-LINK INTERFACE
R132
8.2K_0402_5%
XTAL
R125
CPU
+3VS
CLK_ALINK_SB
<24> CLK_ALINK_SB
+VCC_CORE
4
3
2
1
<10,13> A_CBE#[0..3]
RP14
Layout note:
A_AD[0..31]
<10,13> A_AD[0..31]
Title

SB200M(1/4)- PCI/CPU/LPC
5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 15, 2004
Sheet
1
26
of
65
SB_EC_THERM#
D2
1 RB751V_SOD323
EC_THERM#
EC_THERM# <44>
SB_PM_BATLOW#
D3
1 RB751V_SOD323
PM_BATLOW#
PM_BATLOW# <44>
SB_EC_SWI#
D4
1 RB751V_SOD323
EC_SWI#
EC_SWI# <44>
SB_GA20
D5
1 RB751V_SOD323
GA20
GA20 <44>
U3B
USB20P3-
<35> USB20P2+
USB20P2+
<35> USB20P2-
USB20P2-
<35> USB20P1+
USB20P1+
<35> USB20P1-
USB20P1-
<35> USB20P0+
USB20P0+
<35> USB20P0-
USB20P0-
R92
@10_0402_5%
C75
@15P_0402_50V8J
RP1111
2
3
4
8
7
6
5
15K_1206_8P4R_5%
USB20P4+
USB20P4USB20P5USB20P5+
RP1121
2
3
4
8
7
6
5
15K_1206_8P4R_5%
USB20P3USB20P3+
USB20P2USB20P2+
RP1131
2
3
4
8
7
6
5
15K_1206_8P4R_5%
<29>
<29>
<29>
<29>
R1301
1 10K_0402_5%
R1302
1 10K_0402_5%
OVCUR#2
R1303
2 10K_0402_5%
R947 2
+3V
R948 2
+3V
USB_HSDP0+
USB_FLDP0+
USB_HSDM0USB_FLDM0-
R5
W1
V4
V2
MCOL
MCRS
MDCK
MDIO
AGP_STP# D11
D77 2
RB751V_SOD323
RX_CLK
RX_DV
RX_ERR
TX_CLK
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
U4
V1
U3
V3
TXD3
TXD2
TXD1
TXD0
MII_TXEN
1 10K_0402_5%
W2
W3
U5
Y7
TX_EN
PHY_PD
PHY_RST#
CLK_25M
1 10K_0402_5%
SB_EEDO
SB_EECLK
P2
R3
R2
R4
EE_CS
EE_DI
EE_DO
EE_CK
EC_RSMRST#
AB9
RSMRST#
CLK_SB_14M
A23
OSC_IN
W6
SIO_CLK
1 10K_0402_5%
EC_FLASH#
OVCUR#2
32KHZ_S5_OUT
OVCUR#1
SB_SPKR
<45> EC_FLASH#
<35> OVCUR#2
<29> 32KHZ_S5_OUT
<35> OVCUR#1
<37> SB_SPKR
1 10K_0402_5%
AB2
AA3
W11
AB1
Y4
AA1
BLINK/GPM0
FANOUT1/USBOC2#/GPM2
32KHZ_IN/GPM3
USBOC1#/GPM4
SPEAKER/GPM5
FANOUT0/GPM6
AC1
AC6
AC2
AC3
AC4
AC5
GPIO_X0/AGP_STP#
GPIO_X1/AGP_BUSY#
GPIO_X2/GHI#
GPIO_X3/VGATE
GPIO_X4
GPIO_X5
AGP_STP#_R
1 RB751V_SOD323
AGP_BUSY#_R
GHI
VGATE
IDERSTHD#
IDERSTCD#
1
2
1
@10K_0402_5%
R952
2
<5> CPU_GHI#
F1
F2
G1
G2
T4
<24> CLK_SB_14M
<10,17> AGP_STP#
USB_HSDP1+
USB_FLDP1+
USB_HSDM1USB_FLDM1-
T2
U1
<44> EC_RSMRST#
100K_0402_5%
R951 2
G3
J3
H3
K3
RXD3
RXD2
RXD1
RXD0
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
R950 2
<29> SB_EEDO
<29> SB_EECLK
R112
USB_HSDP2+
USB_FLDP2+
USB_HSDM2USB_FLDM2-
T3
U2
T5
W4
<29> MII_TXEN
+3V
OVCUR#1
H2
H1
J2
J1
T1
USB20P1+
USB20P1USB20P0+
USB20P0-
OVCUR#0
R1003
GPOC0#/SCL0
GPOC1#/SDA0
GPOC2#/SCL1
GPOC3#/SDA1
RTC_IRQ#/PWR_STRP
KBRST#
KBRST# <44>
AC9
AC7
AA11
AB10
AA10
Y11
C21
Y10
AA5
AA6
SB_PM_BATLOW#
LPC_PME#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
PCI_ACT_REQ#
SUS_STAT#
SB_TEST1
SB_TEST0
SB_AC_IN
D7
1 RB751V_SOD323
ACIN
ACIN <44,48,51>
SB_EC_SMI#
D8
1 RB751V_SOD323
EC_SMI#
EC_SMI# <44>
SB_SCI#
D9
1 RB751V_SOD323
SCI#
SCI# <44>
D10
1 RB751V_SOD323
LID_OUT#
LID_OUT# <44>
Y5
AA4
AB3
Y6
W5
Y8
AA7
AB6
SB_GA20
SB_KBRST#
SB_AC_IN
SB_EC_SWI#
LPC_SMI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#
AA12
W12
Y12
AB12
AA8
SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
PWR_STRP
AB17
AC16
AB15
AB16
AC15
Y16
AA17
AA16
AC17
Y15
AA15
IDEI ORDYA
IDEIRQA
IDESAA0
IDESAA1
IDESAA2
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15
AC18
AA18
AC19
AA19
AC20
AA20
AC21
AB21
AA21
Y20
AB20
Y19
AB19
Y18
AB18
Y17
IDEDA0
IDEDA1
IDEDA2
IDEDA3
IDEDA4
IDEDA5
IDEDA6
IDEDA7
IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15
SIDE_IORDY
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DACK#
SIDE_DRQ
SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#
AA23
AA22
AC23
Y21
AB23
Y22
W21
Y23
W20
AC22
AB22
IDEI ORDYB
IDEIRQB
IDESAB0
IDESAB1
IDESAB2
IDEDACK#B
IDEREQB
IDEIOR#B
IDEIOW#B
IDECS#B1
IDECS#B3
W23
V21
V23
U21
U23
T21
T23
R21
R20
T22
T20
U22
U20
V22
V20
W22
IDEDB0
IDEDB1
IDEDB2
IDEDB3
IDEDB4
IDEDB5
IDEDB6
IDEDB7
IDEDB8
IDEDB9
IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15
PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#
SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15
AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SYNC
AC_RST#
SPDIF_OUT
E1
E2
Y1
Y2
Y3
E3
V5
E5
2
D14
+3VS
R934 1
OSCLIN
1
2
R1184
0_0402_5%
+2.5V
4.7K_0402_5%
R1188
Q4
SUS_STAT#
R69
4.7K_0402_5%
MMBT3904_SOT23
1
NB_SUS_STAT# <8>
+3V
IDEIORDYB <30>
IDEIRQB <30>
IDESAB0 <30>
IDESAB1 <30>
IDESAB2 <30>
IDEDACK#B <30>
IDEREQB <30>
IDEIOR#B <30>
IDEIOW#B <30>
IDECS#B1 <30>
IDECS#B3 <30>
GHI
AGP_STP#_R
AGP_BUSY#_R
SB_GA20
1
2
3
4
8
7 RP107
6
5 10K_0804_8P4R_5%
SB_KBRST#
LPC_PME#
SB_EC_SMI#
SB_SCI#
1
2
3
4
8
7 RP108
6
5 10K_0804_8P4R_5%
SB_LID_OUT#
SB_EC_THERM#
SB_PM_BATLOW#
SB_EC_SWI#
1
2
3
4
8
RP109
7
6
5 10K_0804_8P4R_5%
LPC_SMI#
SB_AC_IN
PCI_ACT_REQ#
1
2
3
4
8
RP110
7
6
5 10K_0804_8P4R_5%
PWRBTN_OUT#
SLP_S3#
SLP_S5#
1
2
3
4
8
7
6
5
10K_0804_8P4R_5%
1
2
3
4
8
7
6
5
2.2K_0804_8P4R_5%
+3VALW
IDEDB[0..15] <30>
RP11
+3VS
SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
RP12
+3V
AC97_RST#
AC97_SYNC_R
R119
SPDIF_OUT
AC97_BITCLK
33_0402_5% AC97_SDOUT
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
33_0402_5% AC97_SYNC
AC97_RST#
AC97_BITCLK <36,42>
AC97_SDOUT <29,36,42>
AC97_SDIN0 <36>
AC97_SDIN1 <42>
AC97_SYNC <29,36,42>
AC97_RST# <36,42>
R111
RP140
+3VS
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
RP13
M10@4.7K_0402_5%
R1186
Q3
3
8.2K_0402_5%
+3VS
AGP_STP#
AGP_BUSY#
SB_TEST0
SB_TEST1
SPDIF_OUT <29>
1
2
3
4
8
7
6
5
8.2K _8P4R_0804_5%
1
2
3
4
8
7
6
5
8.2K _8P4R_0804_5%
A
M10@10K_0402_5%
R1187
AC97_BITCLK
M10@MMBT3904_SOT23
1
R1176
8.2K_0402_5%
AGP_SUS_STAT# <17>
Title

SB200M(2/4) - IDE/USB/MII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALSize
Date:
4
R68
10K_0402_5%
AGP_BUSY# <10,17>
2 1K_0603_5%
+2.5V
2 1
IDERSTCD#
1
RB751V_SOD323
GND
IDEDA[0..15] <30>
4.7K_0402_5%
R1185
AGP_BUSY#
3
2N7002 1N_SOT23
S
1
Q89
1 OE
C1010
0.1U_0402_10V6K
VTT_PWRGD <24,46>
IDERSTHD#
1
RB751V_SOD323
SUS_STAT#
AGP_BUSY#_R
48MHZ_4P_FN4800002
OUT 3
VDD
+2.5V
2 10K_0402_5%
IDERST_CD#
<30> IDERST_CD#
SMB_CK_CLK2 <14,15,24>
SMB_CK_DAT2 <14,15,24>
+2.5V
South bridge SB200
X2
4
AC97_SDOUT_R R117
R121 1
2
D13
R1183
10K_0402_5%
IDERST_HD#
<30> IDERST_HD#
+3VS
2 10K_0402_5%
+3V
2
G
R120 1
SB_LID_OUT#
PWR_STRP <29>
IDEIORDYA <30>
IDEIRQA <30>
IDESAA0 <30>
IDESAA1 <30>
IDESAA2 <30>
IDEDACK#A <30>
IDEREQA <30>
IDEIOR#A <30>
IDEIOW#A <30>
IDECS#A1 <30>
IDECS#A3 <30>
33_0402_5%
+3VS
SLP_S3# <44>
SLP_S5# <44>
PWRBTN_OUT# <44>
SB_PWRGD <46>
USB_HSDP3+
USB_FLDP3+
USB_HSDM3USB_FLDM3-
1 RB751V_SOD323
<35> USB20P3-
K2
K1
L2
L1
USB20P3+
CLK_SB_14M
<35> USB20P3+
GA20_IN/GEVNT0#
KB_RST#/GEVNT1#
SMB_ALERT#/GEVNT2#
LPC_PME#/GEVNT3#
LPC_SMI#/GEVNT4#
GEVENT5#/ETH_VALERT#
GEVENT6#/ETH_FALERT#
GEVENT7#/ETH_CALERT#
D6
@15P_0402_50V8J
USB_HSDP4+
USB_FLDP4+
USB_HSDM4USB_FLDM4-
SB_KBRST#
C74
L4
L3
M4
M3
SB_EC_THERM#
2 1
USB20P4-
AB4
USB20P4+
@10_0402_5%
ACPI / WAKE UP EVENTS
R71
USB_HSDP5+
USB_FLDP5+
USB_HSDM5USB_FLDM5-
USB INTERFACE
USB20P5-
PME#/EXT_EVNT0#
RI#/EXT_EVNT1#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
PCI_REQACT#
SUS_STAT#
TEST1
TEST0
PRIMARY ATA 66/100
<42> USB20P5-
M2
M1
N2
N1
ETHERNET MII
USB20P5+
AC97_BITCLK
<42> USB20P5+
TALERT#/ETH_TALERT#
Part 2 of 3
EEPROM
OVCUR#0
<35> OVCUR#0
SB200 SB
USBCLK/CLK48
USB_RCOMP
USB_VREFOUT
USB_ATEST1
USB_ATEST0
USBOC0#/GPM7
CLK / RST
P3
R1
P1
N4
N3
P4
GPIO_XTRA GPIO
SECONDARY ATA 66/100
AC97
@0_0402_5%
OSCLIN
<24> CLK_SB_48M
R63
USB_RCOMP
12.4K_0603_1%
R1293
Document Number
Rev
0.1
LA-2411
, 07, 2004
Sheet
1
27
of
65
+3VS
+3VS
0.1U_0402_10V6K
C23
D
C24
22U_1206_16V4Z_V1
22U_1206_16V4Z_V1
2
C25
C26
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C27
C28
2
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C29
C30
C31
C32
C33
C34
C35
C36
+3VS
C41
C42
C43
0.1U_0402_10V6K
1
C44
C45
C46
C47
C38
C39
0.1U_0402_10V6K
ATI request
C873
C874
C875
C876
C877
C48
2
0.1U_0402_10V6K
2
2
2
2
2
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_16V7Z
22U_1206_16V4Z_V1
C37
0.1U_0402_16V7Z
0.1U_0402_10V6K
U3C
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
+2.5VS
C40
0.1U_0402_16V7Z
0.1U_0402_16V7Z
0.1U_0402_16V7Z
+2.5VS
+2.5VS
ATI request
+2.5V
0.1U_0402_16V7Z
0.1U_0402_10V6K
C49
22U_1206_16V4Z_V1
C
C50
C51
0.1U_0402_10V6K
C52
2
2
2
0.1U_0402_10V6K
C53
C878
0.1U_0402_10V6K
0.1U_0402_16V7Z
C879
+3V
C54
22U_1206_16V4Z_V1
C55
2
2
0.1U_0402_10V6K
C56
C57
+2.5V
C58
C882
0.1U_0402_10V6K
C881
0.1U_0402_16V7Z
0.1U_0402_16V7Z
0.1U_0402_10V6K 0.1U_0402_10V6K
1
C880
ATI request
+3V
ATI request
CLOSE TO
L6,H6,J6
+2.5V
C883
0.1U_0402_16V7K
0.1U_0402_16V7K
C885
C886
C966
0.1U_0402_16V7K
0.1U_0402_16V7K
+3V_AVDDC
0.1U_0402_16V7K
+3V_AVDDC
ATI request
0.01U_0402_16V7Z
R60
+3V
+3V_AVDDC
FBM-10-201209-260-T_0805
+3V
C59
C60
C980
C981
E11
E12
E15
E7
E8
F11
F12
F15
F16
F17
F7
F8
G18
G19
H18
H19
M18
M19
N18
N19
T18
T19
U18
U19
V17
V18
W17
W18
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
J10
J11
J13
J14
K15
K9
L15
L9
N15
N9
P15
P9
R10
R11
R13
R14
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
P6
R6
V13
W13
V12
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
STB_2.5V
L6
H6
J6
VDD_USB
VDD_USB
VDD_USB
P5
AVDDC
T6
U6
V9
V10
V11
W9
W10
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
STB_3.3V
F4
J4
K5
F3
K4
L5
AVDDTX0
AVDDTX1
AVDDTX2
AVDDRX0
AVDDRX1
AVDDRX2
SB200 SB
Part 3 of 3
POWER
C887
2
1U_0603_10V6K
0.1U_0402_10V6K
+5VS
10U_0805_10V6K
+3V_AVDDUSB
1000P_0402_16V7K
R1114
22U_1206_16V4Z_V1
C65
C66
C67
C68
C93
2
2
2
2
2
2
2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C94
C95
2
2
470P_0402_50V7K
C888
47U_B_6.3VM
D19
+2.5VS
1U_0603_10V6K
AVSSCK
A22
A21
AVDD_CK
+2.5VALW
Y9
+3VALW
AA9
0.1U_0402_10V6K
South bridge SB200

C70
0.1U_0402_10V6K
+2.5V_AVDDCK
680P_0402_50V7K
FBM-10-201209-260-T_0805
C889
1
2
A
S5_3.3V
+2.5V_AVDDCK
0.01U_0402_16V7Z
R62
1
S5_2.5V
M5
J5
G4
K6
H4
F5
ATI request
+2.5VS
N5
5V_VREF
C69
+2.5V_AVDDCK
AVSSC
D1
1
E10
E13
E14
E6
E9
F10
F13
F14
F18
F6
F9
G6
J12
J15
J18
J19
J9
K10
K11
K12
K13
K14
K18
K19
L10
L11
L12
L13
L14
L18
L19
M10
M11
M12
M13
M14
M15
M6
M9
N10
N11
N12
N13
N14
N6
P10
P11
P12
P13
P14
P18
P19
R12
R15
R18
R19
R9
V14
V15
V16
V19
V6
V7
V8
W14
W15
W16
W19
W7
W8
H5
G5
AVSSRX2
AVSSRX1
AVSSRX0
AVSSTX2
AVSSTX1
AVSSTX0
VREF_CPU
1
C64
1K_0402_5%
1
RB751V_SOD323 C843
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 680P_0402_50V7K 1000P_0402_50V7K
FBM-10-201209-260-T_0805
1
1
C62 C63
D90
2
+3V_AVDDUSB
R61
+3V
+3VS
ATI request
+3V_AVDDUSB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_USB
VSS_USB
C71
1U_0603_10V6K
C72
C982
2
0.1U_0402_10V6K
C983
C96
2
2
470P_0402_50V7K
C98
C99
22U_1206_16V4Z_V1
2
2
680P_0402_50V7K
1000P_0402_16V7K
Title

SB200M(3/4) - PWR
5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
28
of
65
+3VS
+3VS
+3V
+3V
+3V
+3VALW
+3V
@10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5%
R36
R37
R38
R39
R41
R42
R43
R44
R45
R46
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
R55
R56
R57
R58
R35
R34
10K_0402_5%
2
+3V
+3VS
+3V
+3V
+3VALW
<27> PWR_STRP
<27> SB_EEDO
<27> SB_EECLK
<27,36,42> AC97_SYNC
<27,36,42> AC97_SDOUT
<27> SPDIF_OUT
PWR_STRP
MANUAL
PWR ON
STRAP
HIGH
IGN DEBUG
EEDO
USE
DEBUG
STRAPS
R51
R52
R54
10K_0402_5%
10K_0402_5%
10K_0402_5%
@10K_0402_5%@10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5%
EECK
ROM ON
PCI BUS
REQUIRED SYSTEM STRAPS
R50
2
B
R49
10K_0402_5%
R48
@10K_0402_5% 10K_0402_5%
R47
<27> MII_TXEN
<27> MII_TXD3
<27> MII_TXD2
<27> MII_TXD1
<27> MII_TXD0
<27> 32KHZ_S5_OUT
AC_SYNC
AC_SDOUT
SPDIF_OUT
INIT ACTIVE
HIGH
33MHz NB
BUS
SIO 24MHz
SPEEDSTEP
CPU_STP#
ENABLE
SPEED
STEP
DE FAULT
AUTO
PWR
ON
STRAP
LOW
FREQLTCH
TX_EN
ROM ON
LPC
BUS
INIT ACTIVE
LOW (PIII)
HI SPEED
A-LINK
SIO 48MHz
DISABLE
SPEED
STEP
DE FAULT
DE FAULT
DE FAULT
DE FAULT
DE FAULT
DE FAULT
ETHERNET TXD[3:0]
32KHZ_S5
32KHZ
OUTPUT
FROM SB200
(INT RTC)
DISABLE
CPU FREQ
SETTING
DE FAULT
IGNORE
DEBUG
STRAPS
R59
PROCESSOR FREQ MULTIPLIER
DE FAULT
ENABLE CPU
FREQSETTING
32KHZ INPUT
TO SB200
(EXT RTC)
+3VS
High : ENE910
1
Low : NS591L
R953
10K_0402_5%
<26,31,33,34,41> PCI_AD26
R967
@10K_0402_5%
Title

SB200M(4/4) - STRAPS
5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
29
of
65
+5VS
I1
SD_IDERST#
HDD_LED#
CDLED#
74HCT08PW_TSSOP14
I0
I1
<27> IDERST_HD#
10
I1
ACT_LED# <44>
74HCT08PW_TSSOP14
I0
HDD/CD-ROM Module
+5VS
3
U1C
9
U1A
I0
<27> IDERST_CD#
<11,26,31,33,34,38,41,44> PCI_RST#
14
U1B
4
HD_IDERST#
C1
1000P_0402_50V7K
C3
C4
C5
74HCT08PW_TSSOP14
Placea caps. near HDD CONN.

U1D
IDEDA[0..15]
<27> IDEDA[0..15]
IDEDA14 4
IDEDA0 3
IDEDA15 2
IDEDA1 1
RP1
5 PD_D14
6 PD_D0
7 PD_D15
8 PD_D1
33_0804_8P4R_5%
IDEDA11 4
IDEDA10 3
IDEDA5 2
IDEDA4 1
RP2
5 PD_D11
6 PD_D10
7 PD_D5
8 PD_D4
33_0804_8P4R_5%
IDEDA7 4
IDEDA8 3
IDEDA6 2
IDEDA9 1
RP3
5 PD_D7
6 PD_D8
7 PD_D6
8 PD_D9
33_0804_8P4R_5%
IDEDA3 4
IDEDA12 3
IDEDA2 2
IDEDA13 1
RP4
5 PD_D3
6 PD_D12
7 PD_D2
8 PD_D13
33_0804_8P4R_5%
12
I0
13
I1
4
3
2
1
<27> IDEDACK#A
<27> IDECS#A1
<27> IDEIOR#A
<27> IDEIOW#A
R18
10K_0402_5%
1
R3 2
HD_IDERST#
R4 1
PD_DREQ#
PD_DACK#
PD_CS#1
PD_IOR#
PD_IOW#
R15
1
2
10K_0402_5%
+5VS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
PD_DREQ#
PD_IOW#
PD_IOR#
PD _IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#
+5VS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PCSEL R9
IDESAB0
IDESAB1
+5VS
C11
4
3
2
1
RP5
PD_A0
5
PD_A2
6
PD_CS#3
7
PD_A1
8
33_0804_8P4R_5%
4
3
2
1
RP6
SD_SBA0
5
SD_SBA1
6
SD_SBA2
7
SD_SCS3#
8
33_8P4R_0804_5%
R8
4.7K_0402_5%
R969 1
<27> IDEIORDYA
2 33_0402_5%
5 SD_D6
6 SD_D10
7 SD_D8
8 SD_D7
33_0804_8P4R_5%
IDEDB3
4
IDEDB12
3
IDEDB2
2
IDEDB13
1
RP10
5 SD_D3
6 SD_D12
7 SD_D2
8 SD_D13
33_0804_8P4R_5%
4
3
RP1252
1
+5VS
+5VS
10K_0402_5%
R614
470_0402_5%
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
CDROM_R <36>
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ
SD_SIOR#
+5VS
SD_DACK#
R1110 1
SD_SBA2
SD_SCS3#
W=80mils
2 @10K_0402_5%
+5VS
+5VS
+5VS
C610 0.1U_0402_10V6K
1
2
+5VS
R613 @100K_0402_5%
CD-ROM CONN.
+5VS
R32
1
5
6
7 33_0804_8P4R_5%
8
+5VS
W=100mils
W=100mils
5.6K_0402_5%
2
SD_DREQ
C14
2
10U_0805_16V4Z
SD_SIOW#
SD_SIOR#
SD_SCS1#
SD_DACK#
C15
2
1U_0603_10V6K
C16
C17
1000P_0402_50V7K
2
0.1U_0402_10V6K
Placea caps. near CDROM CONN.
SD_IRQ15
+5VCD trace to CONN W=100mils
C18
2
10U_0805_16V4Z
C19
2
1U_0603_10V6K
C20
C21
1000P_0402_50V7K
2
0.1U_0402_10V6K
2
A
Placea caps. near CDROM CONN.
+5VCD trace to CONN W=100mils

R33
8.2K_0402_5%
SD_SIORDY
2 33_0402_5%
SD_CSEL
33_0603_1%
33_0603_1%
R970 1
R31
+5VS
<27> IDEIORDYB
SD_DREQ 1
C22
<27> IDEIRQB
R26
R24
IDEDB6
4
IDEDB10
3
IDEDB8
2
IDEDB7
1
RP9
<27> IDEREQB
SD_SIOW#
SD_SIORDY
SD_IRQ15
SD_SBA1
SD_SBA0
SD_SCS1#
CDLED#
4.7K_0402_5%
CDROM_R
5 SD_D0
6 SD_D15
7 SD_D1
8 SD_D14
33_0804_8P4R_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SD_IDERST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0
IDEDB0
4
IDEDB15
3
IDEDB1
2
IDEDB14
1
RP8
<27> IDEIOW#B
<27> IDEIOR#B
<27> IDECS#B1
<27> IDEDACK#B
<36> CDROM_L
CD_AGND <36>
JP2
CDROM_L
R25
5 SD_D5
6 SD_D9
7 SD_D4
8 SD_D11
33_0804_8P4R_5%
CD_AGND
R611 2
1
10K_0402_5%
PD _IORDY
IDEDB[0..15]
IDEDB5
4
IDEDB9
3
IDEDB4
2
IDEDB11
1
RP7
@47P_0402_25V8K
C12 1
2
1 @10U_0805_6.3V6M
+3VS
<27> IDEDB[0..15]
2 470_0402_5%
PD_A2
PD_CS#3
2
<27> IDESAB0
<27> IDESAB1
<27> IDESAB2
<27> IDECS#B3
IDESAA0
IDESAA2
IDECS#A3
IDESAA1
1
C9
1U_0603_25V4Z
2
+3VS
<27> IDESAA0
<27> IDESAA2
<27> IDECS#A3
<27> IDESAA1
1
C8
4.7U_0805_10V4Z
2
OCTEK_HDD-22HG2_REVERSE
5.6K_0402_5%
C7
1U_0603_25V4Z
JP1
2 33_0402_5%
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
R968
8.2K_0402_5%
2
R19
C6
4.7U_0805_10V4Z
2
PD_IRQA
33_0603_1%
1
<27> IDEIRQA
33_0603_1%
RP124
5
6
7 33_0804_8P4R_5%
8
+5VS
11
<27> IDEREQA
R11
+5VS
74HCT08PW_TSSOP14
C2
10U_0805_16V4Z 10U_0805_16V4Z 1U_0603_10V6K 0.1U_0402_10V6K

2
2
2
2
2 33P_0402_25V8K
Title
HDD & CDROM Connector

Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
30
of
65
C1039
@18P_0402_50V8K
+3VS
R1305
43K_0402_5%
<32> SM_CD#
<44> CARD_LED#
R20
1
+3VS
+3VS
2
1
PCI_RST#
<11,26,30,33,34,38,41,44> PCI_RST#
<26,33,34,41> PCI_FRAME#
<26,33,34,41> PCI_IRDY#
<26,33,34,41> PCI_TRDY#
<26,33,34,41> PCI_DEVSEL#
<26,33,34,41> PCI_STOP#
<26,33,34,41> PCI_PERR#
<26,33,41> PCI_SERR#
<26,33,34,41> PCI_PAR
<26> PCI_REQ#2
<26> PCI_GNT#2
<26> CLK_PCI_PCM
CLK_PCI_PCM
23V_PCM_SUSP
10K_0402_5%
2 PCM_ID
100_0402_5%
PCI_PIRQA#
SD_PULLHIGH
PCI_PIRQB#
1
R1209
PCI_AD20 1
R1211
<10,17,26,34> PCI_PIRQA#
<26> PCI_PIRQB#
<26,38,44> SIRQ
10K_0402_5%
SDOC#
<32> SDOC#
PCI_RST#
G4
J4
K1
K3
L1
L2
L3
M1
M2
A1
B1
H1
PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK
L8
L11
RIOUT#_PME#
SUSPEND#
F4
R1304
@0_0805_5%
+VCC_5IN1
1
R1306
1
R1208
1
R1210
1
R1212
1
R1213
1
R1214
SD_PULLHIGH
2
0_0805_5%
SDCM_XDALE
2
43K_0402_5%
SDDA0_XDD7
2
43K_0402_5%
SDDA1_XDD0
2
43K_0402_5%
SDDA2_XDCL
2
43K_0402_5%
SDDA3_XDD4
2
43K_0402_5%
1
R1215
1
R1216
1
R1307
SDCD#
2
@43K_0402_5%
SDCD#
SDWP
SDPWREN#
<32> SDCD#
<32> SDWP
<32> SDPWREN#
<24> CLK_SD_48M
R1219
2 33_0402_5%
SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
1
<32> SDCK_XDWE#
<32> SDCM_XDALE
<32> SDDA0_XDD7
<32> SDDA1_XDD0
<32> SDDA2_XDCL
<32> SDDA3_XDD4
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
MFUNC7
M10
GRST#
B4
C8
D12
H11
L9
L6
N4
K2
G1
F3
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
C1030
0.1U_0402_16V4Z
S1_D[0..15] <32>
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3
CCBE3#/REG#
CCBE2#/A12
CCBE1#/A8
CCBE0#/CE1#
B7
A11
E11
H13
S1_REG#
S1_A12
S1_A8
S1_CE1#
CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCLK/A16
B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12
C5
D5
S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
A16_CLK 1
R1207
S1_BVD1
S1_WP
D11
S1_A19
CINT#/READY_IREQ#
D6
S1_RDY#
SPKROUT
CAUDIO/BVD2_SPKR#
M9
B5
PCM_SPK#
S1_BVD2
A4
L12
D9
C6
A2
E10
J13
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14
CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19
CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14
SD/MMC/MS/SM
E7
VCC_SD
E8
F8
G7
SDCD#
SDWP/SMWPD#
SDPWREN33#
H5
SDCLKI
F6
E5
E6
F7
F5
G6
SDCLK/SMWE#
SDCMD/SMALE
SDDAT0/SMDATA7
SDDAT1/SMDATA0
SDDAT2/SMCLE
SDDAT3/SMDATA4
G5
GND_SD
IDSEL:
PCI_AD20
2
C1029
0.1U_0402_16V4Z
S1_D[0..15]
B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13
IDSEL
K8
N9
K9
N10
L10
N11
M11
J9
+3VS
A
A7
G13
M12
N12
CBE3#
CBE2#
CBE1#
CBE0#
+VCC_5IN1
Close chip termenal
E1
J3
N1
N5
MSINS#
MSPWREN#/SMPWREN#
MSBS/SMDATA1
MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3
H7
J8
H8
E9
G9
H9
G8
F9
SMBSY#
SMCD#
SMWP#
SMCE#
H6
J7
J6
J5
1
C1031
0.1U_0402_16V4Z
1
C1032
0.1U_0402_16V4Z
1
C1033
0.1U_0402_16V4Z
C1034
0.1U_0402_16V4Z
+S1_VCC
S1_IOWR# <32>
S1_IORD# <32>
C1035
0.1U_0402_16V4Z
1
C1036
0.1U_0402_16V4Z
1
C1037
0.1U_0402_16V4Z
C1038
0.1U_0402_16V4Z
S1_OE# <32>
S1_CE2# <32>
S1_REG# <32>
S1_CE1# <32>
S1_RST <32>
S1_WAIT# <32>
S1_INPACK# <32>
S1_WE# <32>
S1_A16
2
33_0402_5%
S1_BVD1 <32>
S1_WP <32>
S1_CD1#
S1_RDY# <32>
PCM_SPK# <37>
S1_BVD2 <32>
S1_CD2# <32>
S1_CD1# <32>
S1_VS2 <32>
S1_VS1 <32>
XD_MS_PWREN#
MSBS_XDD1
1
MSD0_XDD2
R1217
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
2
33_0402_5%
S1_CD2#
C1040
10P_0402_50V8J
C1041
10P_0402_50V8J
Closed to Pin L12
MSINS# <32>
XD_MS_PWREN# <32>
MSBS_XDD1 <32>
MSCLK_XDRE# <32>
MSD0_XDD2 <32>
MSD1_XDD6 <32>
MSD2_XDD5 <32>
MSD3_XDD3 <32>
MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
XDBSY# <32>
XDCD# <32>
XDWP# <32>
XDCE# <32>
Closed to Pin A4
Close chip termenal
MSD3_XDD3
MSBS_XDD1
R1206
@10_0402_5%
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
1
C1028
0.1U_0402_16V4Z
1
R1218
1
R1220
1
R1221
1
R1222
1
R1223
2
@43K_0402_5%
2
@43K_0402_5%
2
@43K_0402_5%
2
@43K_0402_5%
2
@43K_0402_5%
R1308
2.2K_0402_5%
CB714_LFBGA169
<26,33,34,41>
<26,33,34,41>
<26,33,34,41>
<26,33,34,41>
S1_A[0..25] <32>
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CARDBUS
CLK_PCI_PCM
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
S1_A[0..25]
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
C2
C1
D4
D2
D1
E4
E3
E2
F2
F1
G2
G3
H3
H4
J1
J2
N2
M3
N3
K4
M4
K5
L5
M5
K6
M6
N6
M7
N7
L7
K7
N8
1
C1027
0.1U_0402_16V4Z
+3VS
D3
H2
L4
M8
K11
F12
C10
B6
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
VCCA2
VCCA1
PCI_AD[0..31]
VPPD1
VPPD0
PCI Interface
VCCD1#
VCCD0#
M13
N13
1
U37
<26,29,33,34,41> PCI_AD[0..31]
+3VS
+S1_VCC
+3VS
<32> VPPD0
<32> VPPD1
<32> VCCD0#
<32> VCCD1#
SDWP
2
@43K_0402_5%
MSINS#
2
@43K_0402_5%

Title
5
PCMCIA Controller ENE CB714

Size
Document Number
Custom
Date:
R ev
0.1
LA-2411
, 07, 2004
Sheet
1
31
of
65
PCMCIA Power Controller

CardBus Socket
JP29
S1_A[0..25]
<31> S1_A[0..25]
C1044
VCC
VCC
VCC
12V
13
12
11
40mil
+S1_VPP
+5VS
0.1U_0402_16V4Z
C1048
4.7U_0805_10V4Z
C1049
5
6
VCCD0
VCCD1
VPPD0
VPPD1
1
2
15
14
C1043 0.1U_0402_16V4Z
1
2
C1045 10U_0805_10V4Z
1
2
C1046 0.01U_0402_25V4Z
1
2
C1047 1U_0603_10V4Z
Close to
CardBus Conn.
OC
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#
<31> S1_CE1#
+S1_VCC
<31> S1_OE#
1
C1050
C1051
10U_0805_10V4Z 0.1U_0402_16V4Z
2
2
VCCD0# <31>
VCCD1# <31>
VPPD0 <31>
VPPD1 <31>
<31> S1_WE#
<31> S1_RDY#
+S1_VCC
+S1_VPP
S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP
+S1_VPP
CP-2211_SSOP16
C1054
4.7U_0805_10V4Z
1
C1055
0.01U_0402_25V4Z
R1224
10K_0402_5%
SHDN
3.3V
3.3V
GND
C1053
16
4.7U_0805_10V4Z
3
4
2
C1052
10
S1_D[0..15]
<31> S1_D[0..15]
5V
5V
+3VS
0.1U_0402_16V4Z
VPP
20mil
1
2
C1042 0.1U_0402_16V4Z
<31> S1_WP
+3VS
JP31
SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
<31> XDWP#
SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
10
11
12
13
14
15
16
17
XDBSY#
MSCLK_XDRE#
XDCE#
SDCK_XDWE#
XDWP#
SDDA2_XDCL
SDCM_XDALE
2
3
4
7
8
5
6
18
70
+VCC_5IN1
XDCD#
1
69
9
67
68
D0_XD(P10)
D1_XD(P11)
D2_XD(P12)
D3_XD(P13)
D4_XD(P14)
D5_XD(P15)
D6_XD(P16)
D7_XD(P17)
R/B#_XD(P2)
RE#_XD(P3)
CE#_XD(P4)
WE#_XD(P7)
WP#_XD(P8)
CLE_XD(P5)
ALE_XD(P6)
VCC_XD(P18)
VCC_XD
XD INTERFACE
<31>
<31>
<31>
<31>
<31>
<31>
<31>
<31>
MSBS_XDD1
SDIO_MS(P4)
SCLK_MS(P8)
INS_MS(P6)
BS_MS(P2)
VCC_SM(P12)
VCC_SM(P22)
VSS_SM(P1)
VSS_SM(P10)
GND_SM(P18)
46
55
57
48
58
WP1_SM
WP2_SM
CD1_SM
CD2_SM
41
42
43
44
DAT0_SD(P7)
DAT1_SD(P8)
DAT2_SD(P9)
CD/DAT3_SD(P1)
23
22
30
29
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
CLK_SD(P5)
CMD_SD(P2)
25
28
SDCK_XDWE#
SDCM_XDALE
VDD_SD(P4)
VSS1_SD(P6)
VSS2_SD(P3)
26
27
24
WP_SD
GND_SD
CD_SD
19
20
21
SDCK_XDWE#
<31> SDCK_XDWE#
C1056
@10P_0402_50V8K
XDBSY# <31>
XDCD# <31>
CD/GND_XD(P1)
GND_XD
VSS_XD(P9)
GND0
GND1
S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#
S1_CD1# <31>
S1_CE2# <31>
S1_VS1 <31>
S1_IORD# <31>
S1_IOWR# <31>
+S1_VCC
+S1_VPP
S1_VS2 <31>
S1_RST <31>
S1_WAIT# <31>
S1_INPACK# <31>
S1_REG# <31>
S1_BVD2 <31>
S1_BVD1 <31>
S1_CD2# <31>
xD PU and PD. Close to Socket
1
R1232
1
R1235
1
R1236
2 MSCLK_XDRE#
43K_0402_5%
2 SDCK_XDWE#
2.2K_0402_5%
2
43K_0402_5%
1
R1238
XDBSY#
2
43K_0402_5%
R1225
@0_0402_5%
SDDA2_XDCL <31>
SDCM_XDALE <31>
XDCE# <31>
MSCLK_XDRE# <31>
SDCK_XDWE# <31>
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
72
74
76
78
80
82
84
+VCC_5IN1
SD CLK
1
CLE_SM(P2)
ALE_SM(P3)
CE_SM(P21)
RE_SM(P20)
WE_SM(P4)
WP_SM(P5)
R/B_SM(P19)
CD/VSS_SM(P11)
LVD_SM(P17)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
GND
GND
GND
GND
GND
GND
GND
FOX_WZ21131-G2-P4
XDCD# <31>
<31> MSINS#
34
38
36
32
SDDA2_XDCL
SDCM_XDALE
XDCE#
MSCLK_XDRE#
SDCK_XDWE#
XDWP#
XDBSY#
XDCD#
XDCD#
2
@43K_0402_5%
XDCE# <31>
XDBSY# <31>
+VCC_5IN1
MS CLK
MSCLK_XDRE#
<31> MSCLK_XDRE#
SDWP
S1_WP
2
43K_0402_5%
S1_OE#
2
47K_0402_5%
S1_RST
2
47K_0402_5%
S1_CE1#
2
47K_0402_5%
S1_CE2#
2
47K_0402_5%
R1226
@0_0402_5%
SM_CD# <31>
C1057
@10P_0402_50V8K
+3VS
+VCC_5IN1
R1233
10K_0402_5%
SDWP
SDWP <31>
SDCD#
SDCD# <31>
<31> SDPWREN#
<31> XD_MS_PWREN#
PRO_FIT068-20-3100
+S1_VCC
Reserve for Debug.
MSD0_XDD2
MSCLK_XDRE#
53
59
51
61
63
66
65
47
62
1
R1237
RSVD_MS(P5)
RSVD_MS(P7)
60
64
54
49
45
50
52
56
35
37
IO 1_SM(P6)
IO 2_SM(P7)
IO 3_SM(P8)
IO 4_SM(P9)
IO 5_SM(P13)
IO 6_SM(P14)
IO 7_SM(P15)
IO 8_SM(P16)
MSD2_XDD5
MSD3_XDD3
+VCC_5IN1
SM INTERFACE
VSS_MS(P1)
VSS_MS (P10)
VCC_MS(P3)
VCC_MS(P9)
SD INTERFACE
31
40
33
39
MS INTERFACE
MSD1_XDD6
SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
GND
GND
GND
GND
GND
GND
GND
1
R1227
1
R1228
1
R1229
1
R1230
1
R1231
SD PWR Control
+3VS
+VCC_5IN1
+3VS
U60
1
2
3
4
GND
IN
IN
EN#
OUT
OUT
OUT
OC#
0.1U_0402_16V4Z
+S1_VCC
U38
R1234
10K_0402_5%
8
7
6
5
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
69
71
73
75
77
79
81
83
SDOC# <31>
TPS2041ADR_SO8
+VCC_5IN1
1
C1151
10U_0805_10V4Z
C1152
0.1U_0402_16V4Z
C1153
0.1U_0402_16V4Z
C1155
0.1U_0402_16V4Z
C1156
0.1U_0402_16V4Z

Title
PCMCIA Socket
Size
Document Number
Custom
R ev
0.1
LA-2411
Date:
, 07, 2004
Sheet
32
of
65
+LANVDD
LINK_10_100_1000#
+LANVDD
R1259
C1076
8110S@0.1U_0402_16V4Z
PR1-
RJ45_TX+
PR1+
RJ45_RX+
PR2+
PR3+
PR3-
PR2-
PR4+
PR4-
RJ45_RX-
0.1U_0402_16V4Z
PCI_AD19
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
R1274 1
2 100_0402_5%
92
77
60
44
C/BE#0
C/BE#1
C/BE#2
C/BE#3
46
IDSEL
<26,31,34,41> PCI_PERR#
<26,31,41> PCI_SERR#
70
75
PERR#
SERR#
<26> PCI_REQ#1
<26> PCI_GNT#1
30
29
REQ#
GNT#
<26,41> PCI_PIRQD#
25
INTA#
31
PME#
27
<11,26,30,31,34,38,41,44> PCI_RST#
28
65
<26> CLK_PCI_LAN
<26,38,41,44> PCI_CLKRUN#
R1282
@10_0402_5%
1
C1105
@15P_0402_50V8D
21
38
51
66
81
91
101
119
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
35
52
80
100
GND
GND
GND
GND
GND
NC
NC
VCC
13
5
6
7
8
R1281
75_0402_1%
+LANVDD
C1079 1
0.1U_0402_16V4Z
AT93C46-10SI-2.7_SO8
RJ45_GND
1
1000P_1206_2KV7K
10
120
NC/HSDAC+
NC/HG
NC/LG2
NC/LV2
11
123
124
126
9
13
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
22
48
62
73
112
118
CTRL25
8110S@0.1U_0402_16V4Z
R1271 8110S@0_0805_5%
1
2
1
1
+LANVDD
C1085
C1086
@0_0402_5%
8110S@0.1U_0402_16V4Z
R1272 2
1
2
2
CTRL25
CTRL18
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
26
41
56
71
84
94
107
AVDD25/HSDACRTL8100C_QFP128
24
45
64
110
116
Pulse H0013
C1091
0.1U_0402_16V4Z
10
RJ45_TXRJ45_TX+
R1279
75_0402_1%
R1280
75_0402_1%
RJ45_GND
C1092
0.1U_0402_16V4Z
Place as close to
LAN Chip
2
25MHZ_20P
C1090
27P_0402_50V8J
C1093
10U_0805_10V4Z
C1101
0.1U_0402_16V4Z
C1106
2
2
C1094
0.1U_0402_16V4Z
C1102
0.1U_0402_16V4Z
C1107
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
C1111
C1112
2
2
1
2
C1095
0.1U_0402_16V4Z
C1103
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1104
0.1U_0402_16V4Z
C1108
0.1U_0402_16V4Z
C1113
C1096
1
2
C1097
0.1U_0402_16V4Z
C1098
0.1U_0402_16V4Z
C1099
0.1U_0402_16V4Z
R1283 1
2 8100C@0_0805_5%
+LANVDD
R1285 1
2 8110S@0_0805_5%
+V2.5_LAN
R1286 1
2 8110S@0_0805_5%
+V1.8_LAN
R1287 1
2 8100C@0_0805_5%
+V2.5_LAN
C1109
0.1U_0402_16V4Z
8110S@0.1U_0402_16V4Z
2
2
C1114
C1115
1
+V1.8_LAN
4
8110S@0.1U_0402_16V4Z

C1117
2 8100C@0.1U_0402_16V4Z
Title
RJ45_RXRJ45_RX+
16
15
14
13
12
11
10
9
X2
1
1
1
1
8110S@0.1U_0402_16V4Z 8110S@0.1U_0402_16V4Z
8110S@0.1U_0402_16V4Z
R1290 1
12
2 8100C@0_0805_5%
+V2.5_LAN
1
1
C1116
8100C@0.1U_0402_16V4Z 2
RX+
RXCT
NC
NC
CT
TX+
TX-
+LANVDD
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
R1277
49.9_0402_1%
Y5
1
RD+
RDCT
NC
NC
CT
TD+
TD-
125
32
54
78
99
C1082
R1278
49.9_0402_1%
C1088
0.1U_0402_16V4Z
Place as close to
Magnetic
1
C1089
27P_0402_50V8J
R1276
49.9_0402_1%
1
2
+V1.8_LAN
R1273
8110S@0_0805_5%
C1087
2 8110S@0.1U_0402_16V4Z
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
TXD-/MDI0TXD+/MDI0+
1 15K_0402_5%
R1275
49.9_0402_1%
RTT3/CRTL18
3
7
20
16
R1268 2
5.6K_0603_1%
R64 5.6K for 8100C

2.49K for 8110S
X1 2
AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL
NC/AVDDL
1
2
3
4
5
6
7
8
R1266
1K_0402_5%
NC/VSS
NC/VSS
NC/AVDDH
NC/HV
LANGND
1
R1270 2
U63
RXIN-/MDI1RXIN+/MDI1+
105
23
127
72
74
FOX_JM36113-L1H7
4.7U_0805_10V4Z
2
LWAKE
ISOLATE#
RTSET
NC/SMBCLK
NC/SMBDATA
88
C1100
2
+5VS
X1
X2
R1284
75_0402_1%
C1080
0.1U_0402_16V4Z
14
15
18
19
NC/M66EN
DO
DI
SK
CS
TXD+/MDI0+
TXD-/MDI0RXIN+/MDI1+
RXIN-/MDI1-
X1
X2
CLK
CLKRUN#
GND/VSS
GND/VSS
GND/VSS
ACTIVITY#
LINK_10_100_1000#
121
122
RST#
4
17
128
1
2
5
6
4
3
2
1
117
115
114
113
EEDO
EEDI
EESK
EECS
LED0
LED1
LED2
NC/LED3
NC/MDI2+
NC/MDI2NC/MDI3+
NC/MDI3-
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
<34,41,44,45> ONBD_LAN_PME#
108
109
111
106
TXD+/MDI0+
TXD-/MDI0RXIN+/MDI1+
RXIN-/MDI1-
76
61
63
67
68
69
<26,31,34,41> PCI_PAR
<26,31,34,41> PCI_FRAME#
<26,31,34,41> PCI_IRDY#
<26,31,34,41> PCI_TRDY#
<26,31,34,41> PCI_DEVSEL#
<26,31,34,41> PCI_STOP#
EEDO
AUX/EEDI
EESK
EECS
PCI_CBE#[0..3]
<26,31,34,41> PCI_CBE#[0..3]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
LAN I/F
104
103
102
98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33
PCI I/F
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
U62
Power
<26,29,31,34,41> PCI_AD[0..31]
U39
+LANVDD
PCI_AD[0..31]
1 3.6K_0402_5%
LED_GREEN
LED_ORANGE
RJ45_TX-
C1078
R1260
C1075
8110S@4.7U_0805_10V4Z
C1074
0.1U_0402_16V4Z
1U_0603_10V4Z
C1077
C1073
22U_1206_10V4Z
JP54
1
SHLD2
+LANVDD
1 300_0402_5%
+LANVDD
R1257
+LANVDD
14
8110S@2SB1188_SOT89
Q123
+V2.5_LAN
+V1.8_LAN
12
CTRL18
Q125
2SB1188_SOT89
G
1
CTRL25
Q124
SI2301DS_SOT23
ACTIVITY#
R1258
@0_1206_5%
<44> EN_WOL#
1 300_0402_5%
+LANVDD
11
+3VALW
LDE_YELLOW-
LDE_YELLOW+
SHLD1
Gigabit Ethernet RTL8110S

Size
Document Number
Rev
0.1
LA-2411
, 07, 2004
Date:
G
Sheet
33
H
of
65
+3VS
0.1U_0402_16V4Z
C683
C684
1
C685
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C686
C687
0.1U_0402_16V4Z
C688
0.1U_0402_16V4Z
C689
C690
0.1U_0402_16V4Z
C691
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
PCI_AD[0..31]
<26,29,31,33,41> PCI_AD[0..31]
+3VS
31
47
91
100
108
118
126
6
13
23
33
112
22
38
1
2
3
4
A0
A1
A2
GND
8
7
6
5
VCC
WC
SCL
SDA
EECK_LAN
EEDI_LAN
2
R715
560_0402_5%
AT24C02N-10SC-2.7_SO8
+3V_1394
EECS
26
27
28
29
C694
C695
R721
54.9_0402_1%
54.9_0402_1%
C701
0.33U_0603_16V4Z
R5
@4.7K_0402_5%
JP33
4
3
2
1
+3VS
EEDI_LAN
EECK_LAN
+3VS
R722
6
5
FOX_UV31413-4R1-TR
54.9_0402_1%
R1311
1K_0402_5%
6
5
1394_PME# <33,41,44,45>
4
3
2
1
R723
54.9_0402_1%
34
XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-
PM & Test
PME#
R720
C693
1
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
61
65
66
79
80
56
C692
0.1U_0402_16V4Z
GND
GND
GND
GND
GND
GND
0.1U_0402_16V4Z
2
2
59
62
72
73
86
87
PVA
PVA
PVA
PVA
PVA
PVA
EEPROM EEDO
EEDI/SDA
I/F
EECK/SCL
60
63
TPB0M
TPB0P
TPA0M
TPA0P
TPBIAS0
67
68
69
70
71
C702
270P_0402_25V8K
R1312
1K_0402_5%
XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0
R727
4.99K_0603_1%
Note:These components need to close to chip pins.
2
R716
6.34K_0402_1%
XCPS
XREXT
C705
47P_0402_50V8J
B
X3
PHYRESET#
XI 1
55
XO
24.576MHz_16P_3XG-24576-43E1
XO
OSC
1394
Differential Pairs
58
NC
XI
R726
@10_0402_5%
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
PAR
REQ#
GNT#
INTA#
PCIRST#
PCICLK
57
2 R717
105
100_0402_1% 120
121
123
124
125
127
128
93
92
R1310
2
88
0_0402_5% 89
CLK_PCI_1394
90
I2CEN
CARDEN
CBE0#
CBE1#
CBE2#
CBE3#
IEEE 1394
VT6301S
43
44
PCI_AD16 1
<26,31,33,41> PCI_FRAME#
<26,31,33,41> PCI_IRDY#
<26,31,33,41> PCI_TRDY#
<26,31,33,41> PCI_DEVSEL#
<26,31,33,41> PCI_STOP#
<26,31,33,41> PCI_PERR#
<26,31,33,41> PCI_PAR
<26> PCI_REQ#0
<26> PCI_GNT#0
1
<10,17,26,31> PCI_PIRQA#
<11,26,30,31,33,38,41,44> PCI_RST#
<26> CLK_PCI_1394
12
1
119
104
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
Power
PCI Bus
<26,31,33,41>
<26,31,33,41>
<26,31,33,41>
<26,31,33,41>
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
25
24
20
19
18
16
15
14
11
10
9
8
7
4
3
2
117
116
115
114
113
109
107
106
103
102
101
98
97
96
95
94
41
42
45
48
49
50
37
51
52
53
54
40
39
35
74
75
76
77
78
64
81
82
83
84
85
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PVD
PVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U42
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
46
36
99
110
122
5
17
32
111
21
30
+3VS
U33
L44
FCM2012C-800_0805
VT6301S-CD_LQFP128
C703
@18P_0402_50V8K
XO
XI
2
C700
0.1U_0402_16V4Z
C699
10P_0402_50V8K
R1315
1M_0402_5%
C698
10P_0402_50V8K
2
+3VS
R711
4.7K_0402_5%

Title
IEEE 1394 CONTROLLER

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
34
of
65
+USB_AS
W=40mils
1
C315 +
150U_D2_6.3VM
C316
2
C317
1000P_0402_50V7K
1
0.1U_0402_10V6K
JP20
<27> USB20P1<27> USB20P1+
+5VALW
1
2
3
4
USB20P1USB20P1+
+USB_AS
U14
C1008
4.7U_0805_10V4Z
1
2
3
4
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
@2.2P_0402_50V8C
8
7
6
5
OVCUR#1 <27>
C1134
suyin_020167mr004s511zu_4p
C1133
2
@2.2P_0402_50V8C
G528_SO8
1
R896
OVCUR#2 <27>
0_0402_5%
+USB_AS
SYSON#
W=40mils
1
C312 +
150U_D2_6.3VM
C313
2
C314
1000P_0402_50V7K
0.1U_0402_10V6K
JP19
2
<27> USB20P2<27> USB20P2+
@2.2P_0402_50V8C
C1136
1
2
3
4
USB20P2USB20P2+
C1135
2
@2.2P_0402_50V8C
+USB_CS
W=40mils
1
C307 +
150U_D2_6.3VM
C308
2
C309
1000P_0402_50V7K
0.1U_0402_10V6K
+5VALW
JP18
+USB_CS
U13
C1002
4.7U_0805_10V4Z
1
2
3
4
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
8
7
6
5
OVCUR#0 <27>
1
2
3
4
USB20P0USB20P0+
@2.2P_0402_50V8C
C1138
C1137
G528_SO8
1
R894
<47> SYSON#
<27> USB20P0<27> USB20P0+
2
0_0402_5%
OVCUR#3 <26>
2
@2.2P_0402_50V8C
SYSON#
+USB_CS
W=40mils
1
C1001 +
150U_D2_6.3VM
C1000
2
C999
1000P_0402_50V7K
0.1U_0402_10V6K
JP48
<27> USB20P3<27> USB20P3+
1
2
3
4
USB20P3USB20P3+
@2.2P_0402_50V8C
2
4
C1140
C1139
2
@2.2P_0402_50V8C
Title

USB2.0 Connector
1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
35
of
65
+5VS
+5VAMP
40mil
U46
L29 1
2
KC FBM-L11-201209-221LMAT_0805
L30 1
2
KC FBM-L11-201209-221LMAT_0805
SENSE or ADJ
CNOISE
GND
R771
+VDDA
+VDDA
DELAY
ERROR
SD
R736
150K_0603_1%
2
SI9182DH-AD_MSOP8
MODE
Stuff
No-Stuff
C717
10U_0805_10V4Z
14.318MHz External
24.576MHz Crystal
or External Colck
1
C715
22U_1206_10V4Z
+AUD_VREF
1
C720
0.1U_0402_16V4Z
1
1
C716
10U_0805_10V4Z
VOUT
VIN
R737
51K_0603_1%
C1017
1U_0603_10V4Z
10mil
C1018
0.1U_0402_16V4Z
+AVDD_AC97
40mil
1
2
L31
CHB2012U170_0805
+VDDA
C1023
C1024
10U_0805_10V4Z
0.1U_0402_16V4Z
+3VS
1
<30> CDROM_R
<30> CD_AGND
2
1
1
2
2
1
1
2
2
1
1
2
CDROM_R_R
10K_0402_5%
R762
2.4K_0402_5%
C747
2
0_0805_5%
1
R1198
2
0_0805_5%
1
DVDD1
HP_OUT_L
39
LINE_IN_L
HP_OUT_R
41
C992
2 1U_0603_10V4Z
24
LINE_IN_R
C734
2 1U_0603_10V4Z
18
CD_L
CDROM_RC_R
20
CD_R
CD_GNA C736
2 1U_0603_10V4Z
C DGNDA
19
CD_GND
C737
2 1U_0603_10V4Z
MICIN
21
MIC1
C904
2 1U_0603_10V4Z
22
MIC2
C749
2 1U_0603_10V4Z
13
PHONE
<37> MONO_IN
R1200
+3VS
C905
0.1U_0402_16V4Z
MDC_RC_SPK
12
@47K_0402_5% PC_BEEP
<27,42> AC97_RST#
11
<27,29,42> AC97_SYNC
10
5
R771
0_0402_5%
<37> EAPD
1
R1197
DVDD2
38
JD1
23
0.01U_0402_16V7K
2
0_0805_5%
37
17
<27,29,42> AC97_SDOUT
1
R1196
LINE_OUTR <37>
MONO_OUT/VREFOUT3
2 1U_0603_10V4Z
MDC_R_SPK
LINE_OUTL <37>
2 4.7U_0805_10V4Z
HP_SENSE
2
1
C1019
@0.1U_0402_16V4Z
2 1U_0603_10V4Z
R761
2 4.7U_0805_10V4Z
C986 1
+AUD_VREF
<42> MD_SPK
C985 1
36
C735
<37> MIC_IN
LINE_OUT_L
CDROM_RC_L
C984
1000P_0402_50V7K
LINE_OUT_R
C991
CDROM_R_L
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2.7K_0402_5%
2.7K_0402_5%
JD2
BIT_CLK
SDATA_IN
XTL_IN
C10
1
R1202
27P_0402_50V8J
2
R1201
1 22_0402_5%
1 22_0402_5%
AC97_BITCLK <27,42>
AC97_SDIN0 <27>
R1205
@1M_0402_5%
1
XTL_OUT
AFILT1
29
AFILT2
30
C1020
AFILT1 1
C1021
AFILT2 1
1000P_0402_50V7K
2
1000P_0402_50V7K
2
47
SPDIFI/EAPD
48
SPDIFO
4
7
DVSS1
DVSS2
28
27
DCVOL
32
2 C1022
1U_0603_10V4Z
NC
VREFOUT2
VAUX
SCK
SDA
31
33
34
43
44
2 C750
1U_0603_10V4Z
2 C751
@1U_0603_10V4Z
NC
AVSS1
AVSS2
40
26
42
C1025
@22P_0402_50V8J
R1143
@10_0402_5%
R7
1M_0402_5%
AUD_REF
C973
@15P_0402_50V8J
+AUD_VREF
SDATA_OUT
NC
XTLSEL
CLK_14M_CODEC
+AVDD_AC97
VREF
SYNC
CLK_14M_CODEC <24>
C1026
@22P_0402_50V8J
0_0402_5%
1
@24.576MHz_16P_3XG-24576-43E1
VREFOUT
RESET#
45
46
R1295
2
Y6
R748
R749
R751
R752
R755
R757
16
35
0.1U_0402_16V4Z
<37> LINE_IN_L
<37> LINE_IN_R
<30> CDROM_L
2
0_0402_5%
NBA_PLUG 1
R1199
<37> NBA_PLUG
AUX_R
C989
AUX_L
15
C752
1000P_0402_50V7K
C990
0.1U_0402_16V4Z
14
C729
C730
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
AVDD2
AVDD1
U47
25
1
C745
1U_0603_10V4Z
C746
0.1U_0402_16V4Z
ALC250_LQFP48
GND
GNDA

Title
AC97 CODEC
A
Size
Custom
Date:
Document Number
Rev
0.1
LA-2411
, 07, 2004
G
Sheet
36
H
of
65
JP34
SPKL+
SPKLSPKR+
SPKR-
+5VAMP
+5VAMP
1
1
1
1
2
2
2
2
FBM-11-160808-700T_0603
FBM-11-160808-700T_0603
FBM-11-160808-700T_0603
FBM-11-160808-700T_0603
L65
L66
L67
L68
R973
100K_0402_5%
C1129
@220P_0402_50V7K
R971
W=40Mil
1
C1130
C1131
2
ACES_85205-0400
1
2
3
4
C1132
@220P_0402_50V7K
SHUTDOWN#
@220P_0402_50V7K
@220P_0402_50V7K
VOL_AMP
PIN 6,20 ACTIVE
C774
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
Pin 2
R972
1.5K_0402_1%
PIN 5,23 ACTIVE
LOW
C773
D
2
Q119
EAPD
2
G
2N7002_SOT23
EAPD <36>
NBA_PLUG
VOL_AMP
C894
0.47U_0603_16V4Z
LEFT_2
1
2
RIGHT_2
1
2
0.47U_0603_16V4Z
C895
2
3
4
21
5
23
6
20
<36> NBA_PLUG
LINE_OUTR
<36> LINE_OUTR
2
C896 0.47U_0603_16V4Z
HP_L
1
2
C890 1
17
1
C1014
BYPASS
+5VAMP
LINE_IN_R-1
LINE_IN_L-1
2
0.1U_0402_16V4Z
SPKLSPKR+AUD_VREF
1
12
13
24
C1011
1U_0603_10V4Z
TPA0232PWP_TSSOP24
HP_R
C1012
C1013
EXT.
MICPHONE
JACK
2
R1245
2.2K_0402_5%
R1246
@2.2K_0402_5%
JP50
5
1
1
0.47U_0603_16V4Z
22
15
14
11
9
16
10
8
<36> LINE_IN_L
C892
0.047U_0603_16V7K
C891
0.47U_0603_16V4Z 0.47U_0603_16V4Z
Internal MIC
SPKL+
SPKR+
LINE_OUTL
<36> LINE_OUTL
PVDD SHUTDOWN#
PVDD
SE/BTL#
VDD
PC-BEEP
BYPASS
HP/LINE#
LOUTVOLUME
ROUTLOUT+
LIN
ROUT+
RIN
LLINEIN
RLINEIN
GND
LHPIN
GND
RHPIN
GND
GND
CLK
2 100K_0402_5%
7
18
19
R974 1
NBA_PLUG
L25 1
2
FBM-11-160808-700T_0603
L24 1
2
FBM-11-160808-700T_0603
<36> LINE_IN_R
U52
HIGH
(0.65V -> 10dB )
10K_0402_5%
+5VAMP
1
2
3
4
MIC1
2
2 0.1U_0402_16V4Z
LINE_IN_R-1
3
6
2
1
INT_MIC
1
2
<36> MIC_IN
@WM-64PCY_2P
C257
220P_0402_50V7K
LINE_IN_L-1
1
2
L23
FBM-11-160808-700T_0603 1
C1062
220P_0402_50V7K
AMP_1-1470184-2
C1063
220P_0402_50V7K
+3VALW
1
+3VALW
+3VALW
R732
10K_0402_1%
C713
1U_0603_10V6K
560_0402_5%
2
0.22U_0603_10V7K
SPKR+
10K_0402_1%
SPKL+
FBM-11-160808-700T_0603
L28
INTSPK_R1-3 1
2
NBA_PLUG
INTSPK_R1-4
INTSPK_L1-3 1
INTSPK_L1-4
3
6
2
1
INTSPK_L1-2
14
1
R733
R731
1
2
6
5
150U_D2_6.3VM
47_0402_5%
C1059
R1241
1
2 INTSPK_R1-2 1
2
C714 2
C1058
150U_D2_6.3VM
1 1U_0603_10V6K
R1240
47_0402_5%
2
L27
FBM-11-160808-700T_0603
R735
C1060
330P_0402_50V7K
10K_0402_1%
O
G
I
7
0.1U_0402_10V6K
12
C721
2
1 1
R739
2
R1063
1
2 MONO_IN1 1
39K_0603_1%
R738
1
Q56
2SC2411K_SOT23
C719
2
C1061
330P_0402_50V7K
MONO_IN <36>
1U_0603_25V4Z
2
10K_0402_5%
2
B
1U_0603_10V6K 560_0402_5%
13
<31> PCM_SPK#
U32F
14
+3VALW
C979
AMP_1-1470184-2
C712
JP51
+VDDA
U45A
<44> BEEP#
@100K_0402_1%
14
R729
U18B
U45C
O
7
C722
2
1 1
R741
2
1U_0603_10V6K 560_0402_5%
<27> SB_SPKR
14
+3VALW
R742
10K_0402
D46
4
RB751V_SOD323
2

Title
AMP & Audio Jack

A
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
37
of
65
SUPER I/O SMsC FDC47N217

+3VS
RP151
1
+3VS
+3VS
10
12
13
14
LAD0
LAD1
LAD2
LAD3
LPC_FRAME#
LPC_DRQ#1
15
16
LFRAME#
LDRQ#
17
18
PCI_RESET#
LPCPD#
PCI_RST#
<11,26,30,31,33,34,41,44> PCI_RST#
1
2 LPCPD#
+3VS
R787 10K_0402_5%
PCI_CLKRUN#
<26,33,41,44> PCI_CLKRUN#
CLK_PCI_SIO
<26> CLK_PCI_SIO
S IRQ
<26,31,44> SIRQ
1
2 IO_PME#
+3VS
R798
10K_0402_5%
CLK_14M_SIO
<24> CLK_14M_SIO
R1173
1 10K_0402
1 = M11
0 = UMA
R1174
1 @10K_0402
M11_UMA_DET#
R1291
1 10K_0402
M11P_M11C_DET#
R1292
1 @10K_0402
19
20
21
6
9
MDC_DET#
<42> MDC_DET#
R796
R792
R795
R793
1
1
1
1
CLK14
23
24
25
27
28
29
30
31
32
33
34
35
36
40
1 = M11P
0 = M11C
none = UMA
+3VS
CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#
2 1K_0402_5%
2 10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
62
63
64
1
2
3
4
5
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
D CD#1
IRRX2
IRTX2
IRMODE/IRRX3
37
38
39
IRRX
IRTXOUT
IRMODE
INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#
41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61
VTR
VCC
VCC
VCC
VCC
7
11
26
45
54
FIR
CLOCK
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23
8
22
43
52
RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#
SERIAL I/F
<26,44> LPC_FRAME#
<26> LPC_DRQ#1
C789
@10P_0402_25V8K
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VSS
VSS
VSS
VSS
PARALLEL I/F
1
C788
18P_0402_50V8K
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
GPIO
<26,44>
<26,44>
<26,44>
<26,44>
2
1
R791
@10_0402_5%
LPC I/F
U51
R790
10_0402_5%
D CD#1
RI#1
CTS#1
DSR#1
CLK_14M_SIO
CLK_PCI_SIO
POWER
LPC47N217_STQFP64
R794
2 1K_0402_5%
1
2
3
4
8
7
6
5
4.7K_8P4R_1206_5%
+5V
JP49
IRRX <43>
IRTXOUT <43>
IRMODE <43>
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
D CD#1
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
@96212-1011S
IRRX
1
2
R797
@1K_0402_5%
+3VS
C784
4.7U_0805_10V4Z
1 C787
0.1U_0402_16V4Z
C785
2
0.1U_0402_16V4Z
2 C780
2
0.1U_0402_16V4Z
Base I/O Address

* 0 = 02Eh
1 = 04Eh
63
1
3
6
DLAD0
DLAD1
DLAD2
DLAD3
DLPC_CLK_33
DLDRQ1#
DLFRAME#
DCLKRUN#
DSER_IRQ
DSIO_14M
RXD1
TXD1
DRSR1#
RTS1#/SYSOPT0
CTS1#
DTR1#/SYSOPT1
RI1#
DCD1#
52
53
54
55
56
57
58
59
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
D CD#1
IRTX2
IRRX2
IRMODE/IRRX3
49
50
51
IRTXOUT
IRRX
IRMODE
R80
@10K_0402_5%
B
R991
R992
1
1
2
@10K_0402_5%
2
@10K_0402_5%
GND0
GND1
GND2
GND3
GND4
GND5
9
11
13
15
18
26
VTR
LPC_CLK_33
LDRQ1#
LDRQ0#
LFRAME#
CLKRUN#
SERIRQ
PCI_CLK
PCIRST#
SIO_14M
LPCPD#
IO_PME#
27
28
30
32
33
34
35
36
38
39
40
41
43
44
46
61
GPIO
LPC_DRQ#1
LPC_FRAME#
PCI_CLKRUN#
S IRQ
CLK_PCI_SIO
PCI_RST#
CLK_14M_SIO
LPCPD#
IO_PME#
10
12
24
14
16
19
21
22
23
25
47
MDC_DET#
M11_UMA_DET#
M11P_M11C_DET#
GPIO10
GPIO11
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO15
GPIO16
GPIO17
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
SERIAL I/F
LAD0
LAD1
LAD2
LAD3
IR
64
2
4
7
DLPC I/F
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC I/F
3.3V
3.3V
3.3V
3.3V
3.3V
U50
48
5
17
31
42
60
+3VS
8
20
29
37
45
62
@LPC47N207-JN_STQFP64
Title

LPC SUPER I/O VIA VT1211
5
Size
Document Number
R ev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
38
of
65
FM1
FM2
EMI Clip PAD
FM3
FM4
FM5
1
FM6
CF10 CF11 CF12 CF13
CF9
CF8
CF7
CF6
CF5
CF4
CF3
EP1
EMI-126X142
CF2
CF1
CF14 CF15 CF16 CF17 CF18 CF19 CF20 CF21 CF22 CF23 CF24
H5
HOLEA
H10
HOLEA
H7
H8
H9
HOLEA HOLEA HOLEA
H6
HOLEA
H2
H3
H4
HOLEA HOLEA HOLEA
H1
HOLEA
H20
HOLEA
H17
H18
H19
HOLEA HOLEA HOLEA
H16
HOLEA
H12
H13
H14
HOLEA HOLEA HOLEA
H30
HOLEA
H28
HOLEA
H31
HOLEA
1
H27
HOLEA
H26
HOLEA
H22
H23
H24
HOLEA HOLEA HOLEA
H21
HOLEA

Title
SPR Connector
A
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
39
of
65
+5VALW
+5VALW
(GRN)
R890
360_0603_5%
R885
360_0603_5%
R882
360_0603_5%
2 1
R889
360_0603_5%
+5VALW
(GRN)
(GRN)
(GRN)
+5VALW
D62
D63
HT-170UYG-DT GRN_0805
D65
D60
1
<44> CAPSLED#
<44> NUMLED#
<44> MEDIA_LED#
<44> E_MAIL_LED#
+3VALW
+3VALW
JP53
2
+5VALW
EN_BT#
R925
360_0603_5%
1
R923
360_0603_5%
+5VS
<44> TP_DATA
<44> TP_CLK
EN_WL#
<44> EN_WL#
<44> EN_BT#
<44> WL_ON_LED#
<44> BT_ON_LED#
<44> PWR_SUSP_LED#
<44> PWR_LED#
<44> BATT_FULL_LED#
<44> BATT_CHGI_LED#
TP_DATA
TP_CLK
EN_WL#
EN_BT#
WL_ON_LED#
BT_ON_LED#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_85201-2005

Title
LED INDICATOR
5
Size
B
Date:
Document Number
Rev
0.1
LA-2411
, 07, 2004
Sheet
1
40
of
65
LAN RESERVED
<44> WL_ON
0.1U_0402_10V6K
+3VS
C280
C269
4.7U_0805_10V4Z
C270
0.1U_0402_10V6K
1
C271
1000P_0402_50V7K
<26,33> PCI_PIRQD#
<26> PCI_REQ#4
<26> CLK_PCI_MINI
<26> PCI_REQ#3
<26,31,33,34> PCI_AD31
<26,31,33,34> PCI_AD29
<26,31,33,34> PCI_AD27
<26,31,33,34> PCI_AD25
<42> WLAN_BT_DATA
<26,31,33,34> PCI_CBE#3
<26,31,33,34> PCI_AD23
<26,31,33,34> PCI_AD21
<26,31,33,34> PCI_AD19
CLK_PCI_MINI
R302
2
@10_0402_5%
1
C275
@15P_0402_50V8J
<26,31,33,34> PCI_AD17
<26,31,33,34> PCI_CBE#2
<26,31,33,34> PCI_IRDY#
<26,33,38,44> PCI_CLKRUN#
<26,31,33> PCI_SERR#
<26,31,33,34> PCI_PERR#
<26,31,33,34> PCI_CBE#1
<26,31,33,34> PCI_AD14
<26,31,33,34> PCI_AD12
<26,31,33,34> PCI_AD10
<26,31,33,34> PCI_AD8
<26,31,33,34> PCI_AD7
<26,31,33,34> PCI_AD5
<26,31,33,34> PCI_AD3
+5VS
<26,31,33,34> PCI_AD1
+5VS
3
5
7
9
11
WL_ON D89 1
2 RB751V_SOD323 13
15
PCI_PIRQD#
17
W=40mils
19
21
23
CLK_PCI_MINI
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
W=30mils
97
99
101
103
105
107
109
111
113
115
117
119
121
W=30mils
123
1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
LAN RESERVED
RING
W=30mils
PCI_PIRQC#
W=40mils
W=40mils
WLAN_PME#
1
R301
PCI_AD18
2
100_0402_5%
PCI_AD22
PCI_AD18
+5VS
PCI_PIRQC# <26>
PCI_GNT#4 <26>
+3V
PCI_RST# <11,26,30,31,33,34,38,44>
PCI_GNT#3 <26>
WLAN_PME# <33,34,44,45>
WLAN_BT_CLK <42>
PCI_AD30 <26,31,33,34>
C272
C273
0.1U_0402_10V6K
2
1000P_0402_50V7K
C274
0.1U_0402_10V6K
+3VS
C281
4.7U_0805_10V4Z
PCI_AD28 <26,31,33,34>
PCI_AD26 <26,29,31,33,34>
PCI_AD24 <26,31,33,34>
IDSEL : AD18
PCI_AD22 <26,31,33,34>
PCI_AD20 <26,31,33,34>
PCI_PAR <26,31,33,34>
PCI_AD18 <26,31,33,34>
PCI_AD16 <26,31,33,34>
PCI_FRAME# <26,31,33,34>
PCI_TRDY# <26,31,33,34>
PCI_STOP# <26,31,33,34>
PCI_DEVSEL# <26,31,33,34>
PCI_AD15 <26,31,33,34>
PCI_AD13 <26,31,33,34>
PCI_AD11 <26,31,33,34>
C276
PCI_AD9 <26,31,33,34>
PCI_CBE#0 <26,31,33,34>
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
+5VS
4.7U_0805_10V4Z
C277
<26,31,33,34>
<26,31,33,34>
<26,31,33,34>
<26,31,33,34>
1000P_0402_50V7K
1
C278
0.1U_0402_10V6K
+3V
C284
4.7U_0805_10V4Z
W=40mils
+3V
C285
1000P_0402_50V7K
1
C286
2
3
0.1U_0402_10V6K
127
128
JP12
TIP
127
128
AMP_1318644-1

Title
Mini PCI Slot

A
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
41
of
65
RJ11 CONN.
+3VS
+3VS
C301
2
2
@1000P_0402_50V7K
3
4
MD_SPK <36>
5
6
5
6
1
2
100K_0402_5%
R323 1
R325
R326
2
2
2 10K_0402_5%
+3V
L46
0_0603_5%
AC97_SYNC <27,29,36>
AC97_SDIN1 <27>
1 22_0402_5%
1 22_0402_5%
MDC_DET# <38>
MONO_OUT/PC_BEEP AUDIO_PWDN
GND
MONO_PHONE
AUXA_RIGHT
Bluetooth Enable
AUXA_LEFT
GND
CD_GND
+5V
CD_RIGHT
USB Data+
CD_LEFT
USB DataGND
PRIMARY DN
3.3Vaux
5Vd
GND
GND
3.3Vmain
AC97_SYNC
AC97_SDATA_OUT AC97_SDATA_IN1
AC97_RESET#
AC97_SDATA_IN0
GND
GND
AC97_MSTRCLK
AC97_BITCLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
L45
0_0603_5%
JP47
TIP
MRING
AC97_BITCLK <27,36>
ACES_88021-3000
1
2
1
2
MOLEX_53398_0290
1
R327
@10_0402_5%
C977
<27,29,36> AC97_SDOUT
<27,36> AC97_RST#
JP16
3
4
R320
1
@1000P_0402_50V7K
+3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
C302 2
1
2
JP17
0.1U_0402_10V6K
FOXCONN_JM34613-L002-TR
0.1U_0402_10V6K
C978
C305
@22P_0402_25V8K
+5VS
MDC Conn.
2
0_0805_5%
0.1U_0402_10V6K 1000P_0402_50V7K
1000P_0402_50V7K
@220PF_3KV_1808
@220PF_3KV_1808
BT CONNECTOR
+3VALW
C955
<44> BT_ON#
Q99
SI2301DS_SOT23
C954
1
R319
4.7U_0805_10V4Z
C304
+5VMDC
C303
@0.1U_0402_10V6K
1
C298
C299
C300
1
+3V
+3VS
JP43
BT_VCC
<27> USB20P5+
<27> USB20P5<41> WLAN_BT_DATA
<41> WLAN_BT_CLK
R981 1
R980 1
2 0_0402_5%
2 0_0402_5%
R21
R22
2 0_0402_5%
2 0_0402_5%
1
1
USB5+
USB5-
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
BT_VCC
C957
10U_0805_10V3M
C958
0.1U_0402_10V6K
ACES_87213-0800

Title
MDC , Bluetooth & USB CONN.

Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
42
of
65
INT_KBD CONN.
Power BTN
KSI[0..7] <44>
R305 1
D28
KSO[0..15] <44>
CP1
EC_PWR_ON# <48>
SW1
TC010-PS11CET_5P
DAN202U_SC70
R306
C289
D29
D27
@PSOT03C
470_0402_5%
EC_ON
<44> EC_ON
RLZ20A_LL34
22K
2
2
0_0402_5% 22K
1
R307
100P_1206_8P4C_50V8
Q21
DTC124EK_SOT23
1000P_0402_50V7K
CP3
KSO0 1
KSI5 2
KSI6 3
KSI7 4
8
7
6
5
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
D
Q112
@2N7002_SOT23
100P_1206_8P4C_50V8
CP4
8
7
6
5
2
G
S
KSO3 1
KSI4 2
KSO2 3
KSO1 4
FIR Module
100P_1206_8P4C_50V8
CP5
Vishay populate two 4.7 Ohm resistor

Agilent populate one 4.7 Ohm resistor
(60mil)
+3VS
100P_1206_8P4C_50V8
CP6
KSO15 1
8
KSO14 2
7
KSO13 3
6
KSO12 4
5
SW9
2
1
R308
1 (30mil)
ESE11MV9_4P
C291
D30
KSI0 <44>
IRED_C
RXD
VCC
GND
KSI1 <44>
1
3
5
7
9
IRED_A
TXD
SD/MODE
MODE
GND
IRTXOUT
IRMODE
IRTXOUT <38>
IRMODE <38>
USER Button 2
SW10
PTC010-PS11CET_5P
KSO16
HSDL-3603-007_9P
SW11
PTC010-PS11CET_5P
KSO16
KSI2 <44>
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE

MODE: HIGH/LOW SPEED SELECT
USER Button1
SW2
PTC010-PS11CET_5P
KSO16
2
4
6
8
IRRX
+IR_3VS
C294
0.1U_0402_16V4Z
10U_0805_10V4Z
@PSOT03C
Internet Button
SW8
PTC010-PS11CET_5P
2
2
@4.7_1206_5%
C292
(60mil)
U12
<38> IRRX
1
3
KSO16
+IR_ANODE
@150U_D2_6.3VM
R1204
0_1206_5%
Vishay = 47 Ohm
Agilent = 0 Ohm
LID_SW# <44>
100P_1206_8P4C_50V8
Console/E-MAIL Button
R309 4.7_1206_5%
1
2
+3VS
8
7
6
5
KSI3 <44>
1
2
3
4
KSI0
KSO11
KSO10
KSI1
<44> KSO16
ACES_85202-2405
(Left)
2 ON/OFFBTN#
100P_1206_8P4C_50V8
CP2
KSO7 1
8
KSO6 2
7
KSO5 3
6
KSO4 4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+3VALW
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
8
7
6
5
KSO15
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSI4
KSO2
KSO1
KSO0
KSI5
KSI6
KSI7
KSI2 1
KSO9 2
KSI3 3
KSO8 4
JP13
(Right)
+3VALW
ON/OFF# <44>
2 100K_0402_5%
ON/OFF#
ON/OFFBTN# 1
KSO[0..15]
KSI[0..7]

Title
KBD,ON/OFF,T/P,LED & FIR

5
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
1
43
of
65
4.7U_0805_6.3V6K
L32
2
1
FBM-L11-160808-800LMT_0603
1
0.1U_0402_10V6K
1
2
ECAGND
2
1
FBM-L11-160808-800LMT_0603
7
8
9
15
14
13
10
18
19
22
23
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#
2 @0_0402_5%
31
IOPD3/ECSCI#
GA20
KBRST#
5
6
GA20/IOPB5
KBRST/IOPB6
<26,31,38> SIRQ
C327
<26,38> LPC_FRAME#
<26,38> LPC_AD0
<26,38> LPC_AD1
<26,38> LPC_AD2
<26,38> LPC_AD3
<26> CLK_PCI_EC
1000P_0402_50V7K
+3VALW
R332
1
2
47K_0402_5%
2
0.1U_0402_10V6K
SCI#
R984 1
C1070
<27> SCI#
CLK_PCI_EC
EC_RST#
CLK_PCI_EC
<27> GA20
<27> KBRST#
R337
@10_0402_5%
C329
@15P_0402_50V8J
R1162
KBD_DATA 1
KBD_CLK
1
R1163
+5VS
10K_0402_5%
2
2
10K_0402_5%
+5VS
R1169 10K_0402_5%
1
2
1
2
TP_DATA
TP_CLK
KSI[0..7]
KSO[0..15]
<43> KSI[0..7]
<43> KSO[0..15]
2
2
R1170 10K_0402_5%
PS2_DATA
PS2_CLK
+5VS
R1171 10K_0402_5%
1
2
1
2
R1250
1
+3VALW
<40> TP_CLK
<40> TP_DATA
<43> LID_SW#
<42> BT_ON#
10K_0804_8P4R_5%
SD309100200
RP24
1
2
3
4
100K_0402_5%
R1172 10K_0402_5%
+3VALW
RP23
FSEL#
1
8
SELIO#
2
7
FR D#
3
6
EC_SMI# 4
5
EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1
+EC_AVCC
2
C326
U15
VDD
C324
+3VALW
L33
1 0.1U_0402_10V6K
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
71
72
73
74
77
78
79
80
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA
LID_SW#
105
106
107
108
109
TINT#
TCK
TDO
TDI
TMS
110
111
114
115
116
117
118
119
PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7
AD Input
DA0
DA1
DA2
DA3
DA output
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
PWM
or PORTA
PORTB
PORTD-1
IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24/RESET2
PORTE
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46
2
44
24
25
C RY1
C RY2
158
160
PORTJ-1
C RY1
<47> SYSON
<45,47> SUSP#
<53> VR_ON
<31> CARD_LED#
<27> EC_RSMRST#
1
2 C RY2
R340
*
@20M_0603_5%
<10,17> ENBKL
<25> BKOFF#
<45> FSEL#
FSEL#
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15
173
174
47
SEL0#
SEL1#
CLK
4
OUT
IN
32.768KHZ_12.5P_1TJS125DJ2A073
NC
2
NC
10P_0402_25V8K
Y3
2
PC87591L-VPCN01 A2_LQFP176
C331
12P_0402_50V8J
KB910
R341
87591
PORTM
PORTL
R340 no stuff
BID
1
C911
0.1U_0402_10V6K
KSO16 <43>
EC_SMC_1 <45,49>
EC_SMD_1 <45,49>
PCI_RST# <11,26,30,31,33,34,38,41>
PWRBTN_OUT# <27>
EC_SMC_2 <7>
EC_SMD_2 <7>
FANSPEED1 <7>
PME_EC# <33,34,41,45>
EC_THERM# <27>
FANSPEED2 <7>
WL_ON <41>
+3VALW
1
150
151
FR D#
FWR#
SELIO#
152
SELIO#
IOPD4
IOPD5
IOPD6
IOPD7
41
42
54
55
AC_IN
D36
PCI_RST#
ADB[0..7]
1
RB751V_SOD323
ACIN <27,48,51>
R1251
2
@100K_0402_5%
ADB[0..7] <45>
KBA[0..19]
+3VALW
KBA[0..19] <45>
KBA0
R1252
R1253
KBA5
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#
113
112
104
103
48
KBA16
KBA17
KBA18
KBA19
2
1K_0402_5%
2
@1K_0402_5%
2
1K_0402_5%
2
@1K_0402_5%
2
1K_0402_5%
(SHBM)
R336
SELIO# <45>
I/O Address
CAPSLED# <40>
NUMLED# <40>
IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD
(BADDR1)
R335
FRD# <45>
FWR# <45>
2
@1K_0402_5%
(BADDR0)
R334
KBA3
(ENV1)
R333
KBA2
BADDR1(KBA3) BADDR0(KBA2)
2E
2F
4E
4F
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1

Reserved
ENV0 (KBA0)
FSTCHG <50>
Data
Index
ENV1 (KBA1)
0
0
1
1
IRE
OBD
DEV
PROG
TRIS (KBA4)
0
1
0
1
0
0
0
0
SHBM(KBA5)=1: Enable shared memory with host BIOS

TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use
SCI#
1
0_0402_5%
E_MAIL_LED# <40>
MEDIA_LED# <40>
BATT_CHGI_LED# <40>
BATT_FULL_LED# <40>
PWR_SUSP_LED# <40>
PWR_LED# <40>

Title
KBD EC CTRL-ENE910
A
2 10K_0402_5%
KBA4
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
R338
KBA1
143
142
135
134
130
129
121
120
R986
R931
0_0402_5%
PCI_CLKRUN# <26,33,38,41>
ECAGND
1
2
R960 10K_0402_5%
1
2
R959 10K_0402_5%
20M
R929
100K_0402_5%
ON/OFF# <43>
SLP_S5# <27>
120K
C330
PORTK
GND1
GND2
GND3
GND4
GND5
GND6
GND7
R341
0_0402_5%
148
149
155
156
3
4
27
28
@96212-1011S
+3VALW
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
SYSON
SUSP#
VR_ON
SLP_S3# <27>
IOPJ0/RD
IOPJ1/WR0
PORTD-2
ADP_I <49,50>
1
2
3
4
5
6
7
8
9
10
AC_IN
138
139
140
141
144
145
146
147
PORTJ-2
AGND
R1299
IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
2
10K_0402_5%
C328
0.22U_0603_10V7K
11
12
20
21
85
86
91
92
97
98
R1123
2 VR_ON
47K_0402_5%
2 SUSP#
@10K_0402_5%
2 SYSON
@10K_0402_5%
62
63
69
70
75
76
17
35
46
122
159
167
137
R344
<27> EC_SMI#
<30> ACT_LED#
<40> EN_WL#
<27> EC_SWI#
<33> EN_WOL#
<40> EN_BT#
EC_SMI#
96
LID_SW#
2
R342 20K_0402_5%
EC_SMC_2
EC_SMD_2
FANSPEED1
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
10K_0804_8P4R_5%
+3VALW
KSO16
EC_UTXD
EC_USCLK
EC_SMC_1
EC_SMD_1
KSO16
EC_UTXD
EC_USCLK
R331
ACOFF <50>
PM_BATLOW# <27>
EC_ON <43>
LID_OUT# <27>
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
32KX2
WL_ON_LED# <40>
BT_ON_LED# <40>
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
PORTI
32KX1/32KCLKIN
ECAGND
0.01U_0402_16V7K
124
125
126
127
128
131
132
133
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7
1
2
3
4
5
6
7
8
9
10
EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
BATT_OVP <50>
INVT_PWM <25>
BEEP# <37>
168
169
170
171
172
175
176
1
PS2 interface
ADP_IR
1
C325
32
33
36
37
38
39
40
43
IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
PORTH
BID
DAC_BRIG <25>
EN_FAN1 <7>
EN_FAN2 <7>
IREF <50>
26
29
30
JTAG debug port
JP52
99
100
101
102
153
154
162
163
164
165
+5VALW
8
7
6
5
81
82
83
84
87
88
89
90
93
94
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL/RESET2
PORTC
+5VALW
@0_0402_5%
C322
0.1U_0402_10V6K
BATT_TEMPA <49>
AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9
Host interface
Key matrix scan
For EC Tools
+RTCVCC
C323
+3VALW
0_0402_5%
1 R1175
161
R345
+EC_AVCC
2 0_0603_5%
2 @0_0603_5%
VBAT
2
2
2
4.7U_0805_6.3V6K 0.1U_0402_10V6K
R926 1
R927 1
95
+3VALW
+3VALW
+3VS
AVCC
2
1000P_0402_50V7K
1 2
1000P_0402_50V7K
0.1U_0402_10V6K 0.01U_0402_16V7K
1
1
1
1
1
C1071
C318
C319
C320
C321
34
45
123
136
157
166
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
C1072
16
+3VALW
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
44
of
65
OUTPUT
+5VALW
SELIO#
@20K_0402_5%
<44> ADB[0..7]
CP
MR
@SN74HCT273PW_TSSOP20
C334
1
2
@1U_0603_10V6K
KBA[0..19]
+3VALW
+3VALW
+3VALW
SUSP# <44,47>
C336
R354
0.1U_0402_10V6K
+3VALW
R356
4.7K_0402_5%
2
G
10K_0402_5%
10
U18C
Q29
3
S
FWE#
14
P
FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FR D#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
U19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
11
1
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
ADB[0..7]
<44> KBA[0..19]
KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2
AA
LARST#
U18A
R352
+5VALW
D0
D1
D2
D3
D4
D5
D6
D7
10
3
4
7
8
13
14
17
18
VCC
KBA2
14
+3VALW
U17
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
GND
2
AA
<44> SELIO#
C333
2 @0.1U_0402_16V7K
R12
@100K_0402_5%
20
+3VALW
EC_FLASH# <27>
2N7002 1N_SOT23
<33,34,41,44> WLAN_PME#
<33,34,41,44> ONBD_LAN_PME#
<33,34,41,44> MDM_PME#
<33,34,41,44> 1394_PME#
PME_EC# <33,34,41,44>
FWR# <44>
512K8-90_PLCC32
C337
U20
<44> FSEL#
<44> FRD#
CE#
OE#
WE#
D0
D1
D2
D3
D4
D5
D6
D7
25
26
27
28
32
33
34
35
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
RP#
NC
READY/BUSY#
NC0
NC1
10
11
12
29
38
RESET#
GND0
GND1
23
39
R357
100K_0402_5%
U21
2
22
24
9
31
30
C338
0.1U_0402_10V6K
8
7
6
5
<44,49> EC_SMC_1
<44,49> EC_SMD_1
VCC
WC
SCL
SDA
A0
A1
A2
GND
1
2
3
4
FSEL#
FR D#
FWE#
0.1U_0402_10V6K
VCC0
VCC1
AT24C164-10SC_SO8
R359
100K_0402_5%
R358
100K_0402_5%
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
+5VALW
1
+5VALW
+3VALW
1
2
R360
@100K_0402_5%
+3VALW
@SST39VF080-70_TSOP40

Title
BIOS & EC I/O Port

Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
45
of
65
+3VS
1
R601
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
11
U32D
10
R604 1
2 47_0603_5%
U32E
R606
10K_0402_5%
+2.5VS
@2N7002_SOT23
2
SUSP
SB_PWRGD <27>
C607
Q110
2
G
14
P
0.47U_0603_10V7K 9
14
R603
1
2
330K_0603_5%
O
U32C
Q111
3
2
G
<47,53> SUSP
0.1U_0402_16V7K
1K_0402_5%
U32B
R1107
1M_0402_5%
O
7
C606
14
3
1
2
330K_0402_5%
11
R1106
P
14
U18D
O
R605
13
12
<54> VCORE_PWRGD
14
VTT_PWRGD <24,27>
10K_0402_5%
@2N7002_SOT23
R608
1K_0402_5%
NB_PWRGD <8,10>
D
Q52
R610
2N7002_SOT23
47K_0402_5%
2
G
D19
D20
TV_OUT CONNECTOR
@DAN217_SOT23
3
@DAN217_SOT23
+3VS
JP7
TV_CRMA
TV_COMPS
75_0402_5%
L4 1
2 CHB1608B121_0603
TV_LUMAL
L7 1
L8 1
2 CHB1608B121_0603
2 CHB1608B121_0603
TV_CRMAL
TV_COMPSL
1
2
3
4
5
6
7
R189
R188
SUYIN_35138S-07T1-DF
1
1
1
C110 C111
R190
C112
C113 1
1
C114
@68P_0402_50V8K
75_0402_5%
2
2
2
<11,17> TV_CRMA
<11,17> TV_COMPS
TV_LUMA
<11,17> TV_LUMA
C115
@68P_0402_50V8K
@68P_0402_50V8K
75_0402_5%
@68P_0402_50V8K
@68P_0402_50V8K
@68P_0402_50V8K

Title
POWER GOOD & P/S2 CKT

Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
46
of
65
+2.5VALW to +2.5V Transfer
+2.5V to +2.5VS Transfer
+1.5VSP to +1.5VS Transfer

+2.5VS
+2.5VALW
+12VALW
C341
C343
C357
2
100K_0402_5%
10U_0805_6.3V6M
D
D
D
D
1
2
3
4
S
S
S
G
C358
C959
C359
68K_0402_5%
SI4800DY_SO8
2
10U_0805_6.3V6M
10U_0805_6.3V6M
8
7
6
5
R1101
D
D
D
D
1
2
3
4
S
S
S
G
C961
C960
SI4800DY_SO8
2
10U_0805_6.3V6M
10U_0805_6.3V6M
Q31
2N7002 1N_SOT23
C347
Q75
2N7002 1N_SOT23
0.1U_0402_10V6K
0.1U_0402_10V6K
2
G
C360
SUSP
0.1U_0402_10V6K
(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)
+3VALW to +3V Transfer

+3V
+3VALW
8
7
6
5
D
D
D
D
+12VALW
1
2
3
4
S
S
S
G
SI4800DY_SO8
2 10U_0805_6.3V6M
C354
8
7
6
5
R363
10U_0805_6.3V6M
D
D
D
D
+5VALW
1
2
3
4
S
S
S
G
C342
SI4800DY_SO8
2 10U_0805_6.3V6M
95.3K_0603_1%
C356
SUSP
Q74
2N7002 1N_SOT23
+5VALW to +5V Transfer
C346
R369
10U_0805_6.3V6M
10K_0402_5%
Q32
2N7002 1N_SOT23
+5VALW
D
D
D
D
SYSON
<44> SYSON
Q34
2N7002 1N_SOT23
2
G
C625
10U_0805_6.3V6M
C350
D
D
D
D
S
S
S
G
1
2
3
4
SI4800DY_SO8
2 10U_0805_6.3V6M
6.8K_0402_5%
R373
10K_0402_5%
1
C352
C353
10U_0805_6.3V6M
SUSP
<46,53> SUSP
SYSON# 2
G
0.1U_0402_10V6K
1
0.1U_0402_10V6K
1
C627
SUSP
Q76
2N7002 1N_SOT23
0.1U_0402_10V6K
Q73
2N7002 1N_SOT23
2
G
3
8
7
6
5
R901
C626
+5VALW
+5VS
U24
+12VALW
1
2
3
4
S
S
S
G
SI4800DY_SO8
2 10U_0805_6.3V6M
47K_0402_5%
0.1U_0402_10V6K
R904
8
7
6
5
C624
C348
+5V
U36
SYSON#
<35> SYSON#
+5VALW to +5VS Transfer
+5VALW
+12VALW
2
G
0.1U_0402_10V6K
C345
0.1U_0402_10V6K
1
SYSON# 2
G
(6A,240mils ,Via NO.= 12)
+3VS
0.1U_0402_10V6K
0.1U_0402_10V6K
Place close to PJP4
C355
95.3K_0603_1%
2N7002 1N_SOT23
S
R902
C962
U23
C351
U25
0.1U_0402_10V6K
Q108
+3VALW to +3VS Transfer
+3VALW
+12VALW
2
G
SYSON# 2
G
SUSP
1
3
0.1U_0402_10V6K
D
C344
8
7
6
5
R903
SI4800DY_SO8
2 10U_0805_6.3V6M
100K_0402_5%
+1.5VS
U56
1
2
3
4
S
S
S
G
D
D
D
D
1
R362
+1.5VSP
U26
U22
8
7
6
5
+12VALW
+2.5V
+2.5VALW
+12VALW
C844
Q38
2N7002 1N_SOT23
2
G
<44,45> SUSP#
0.1U_0402_10V6K
SUSP 2
G
2N7002 1N_SOT23
Q43
Q115
SUSP 2
G
S
1
R1102
470_0402_5%
470_0402_5%
R372
2N7002 1N_SOT23
2N7002 1N_SOT23
Q102
2N7002 1N_SOT23
SUSP 2
G
SYSON#
1 2
1 2
Q103
2N7002 1N_SOT23
SYSON#
2
G
470_0402_5%
Q109
2N7002 1N_SOT23
SYSON#
2
G
1 2
Q42
R1095
470_0402_5%
Q36
SUSP 2
G
2N7002 1N_SOT23
1 2
Q41
470_0402_5%
+2.5V
R1094
SUSP 2
G
2N7002 1N_SOT23
1 2
Q40
+3V
R1116
470_0402_5%
R378
470_0402_5%
1 2
SUSP 2
G
2N7002 1N_SOT23
1 2
Q39
R377
470_0402_5%
1 2
SUSP 2
G
470_0402_5%
1 2
470_0402_5%
R376
+5V
1
R375
R374
+1.5VS
+1.2VS_VGA
1 2
+5VS
+3VS
+2.5VS
+1.8VS
+1.25VS
Discharge circuit
2N7002 1N_SOT23
2
G
4

Title
DC/DC Circuits
A
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
E
47
of
65
Detector
Vin Detector
18.234 17.841
17.597 17.210
DC_IN
PL1
FBM-L18-453215-900LMA90T_1812
ADPIN 1
DC_IN
1
DC_IN
PR6
82.5K_0603_0.1%
ACIN
<27,46,53>
PACIN
PACIN
<52>
PU1B
LM393M_SO8
PR8
1K_0603_5%
2
8
5
PR7
10K_0805_5%
PR12
10K_0603_5%
PZD1
2
RLZ4.3B_LL34
2
PC10
1000P_0603_16V7K
PR11
19.6K_0603_0.1%
2
1
1
2
PC9
0.047U_0603_16V7K
VS
PR9
22K_0603_1%
2
PR4
1M_0603_0.5%
1
2
PC4
1000P_0402_50V7K
2
1
SINGA_2DC-G213-B04
2
PC3
100P_0603_50V8J
PC2
1000P_0402_50V7K
G
G
PC1
100P_0603_50V8J
2
1
3
4
ADPIN
PCN1
17.449
16.813
PR14
10K_0603_5%
2
1
RTCVREF
3.3V
PR27
1
DC_IN
PD6
B+
PR28
2
2
2
1.5K_1206_5%
N3
1N4148_SOD80
2
1.5K_1206_5%
PD7
PR29
1N4148_SOD80
PD8
1
2
1.5K_1206_5%
BATT+
3
RB751V_SOD323
VL
PR31
PR1
10K_0603_5%
2
PR2
1M_0402_1%
1
B+
VS
VS
OUT
IN
PC23
10U_0805_10V4Z
1
2
PC6
1000P_0402_50V7K
PR5
499K_0603_1%
PR191
499K_0603_1%
PR192
2
G
1
1
N2
GND
D
PQ46
2 PACIN
47K_0603_5%
2N7002_SOT23
PQ47
PC22
PD10
1U_0805_50V4Z
@RLZ16B_LL34
+5VALW
100K
BATT
DTC115EKA_SOT23
200_0603_5%
PR10
10K_0603_5%
2
1
detector
11.489 11.852
9.380
9.658
100K
2
200_0603_5%
VL
G920AT24U_SOT89
CHGRTC
PU3
3.3V
PR43
Precharge detector
15.8
16.339 15.274
13.692
14.145 13.166
200_0603_5%
PR230
PR41
2
1
ACIN
RTCVREF
PC8
1000P_0603_16V7K
22K_0603_5%
RB751V_SOD323
PD1
<7,51,53> MAINPWON
PR3
432K_0603_1%
PC5
0.01U_0603_50V7K
2
PU1A
LM393M_SO8
PC18
0.1U_0805_25V7K
1
RB751V_SOD323
1
2
0.22U_1206_25V7K
PC17
<52> DCSRD
PR39
<45> EC_PWR_ON#
PR38
100K_0603_1%
PD22
1
PQ2
TP0610T_SOT23
PC7
0.1U_0603_16V7K
CHGRTCP
47_1206_5%
11.133
9.025
Title
Detector
A
Size
Date:
Document Number
Rev
0.1
, 07, 2004
Sheet
E
48
of
65
VMB
PCN2
1
PC11
1000P_0402_50V7K
PC12
0.01U_0603_50V7K
PR17
1
2
@1M_0603_1%
PR19
VREF
VS
100_0603_5%
+
-
1
LM393M_SO8
PQ1
@2N7002_SOT23
PR25
PC14
@1000P_0603_50V7K
PC15
@1000P_0603_50V7K
@100K_0603_1%
2
G
6.49K_0603_1%
PR26
1K_0603_5%
PU2A
8
3
H_PROCHOT# <5,26>
+3VALWP
PR193
1
2
@75K_0603_1%
VREF
PR22
2
@11.5K_0603_1%
PR23
2
@200K_0603_1%
PR21
@47K_0603_5%
1
PR24
PC97
@0.01U_0603_50V4Z
ADP_I
<46,52>
SUYIN_200275MR009G130ZL
PR18
100_0603_5%
BATT+
1
2
3
4
5
6
7
TS_A
EC_SMDA
EC_SMCA
TS
SMD
SMC
GND
GND
PL2
1
2
C8B BPH 853025_2P
1
2
BATT+
BATT+
3
PD3
@BAS40-04_SOT23
1
2
BATT_TEMPA <46>
2
EC_SMD_1 <46,47>
EC_SMC_1 <46,47>
PD4
@BAS40-04_SOT23
PH1 near main Battery CONN :

BAT. thermal protection at 80 degree C
Recovery at 45 degree C
@BAS40-04_SOT23
PD5
+5VALWP
PR32
47K_0402_1%
1
2
VL
VS
8
+
O
4
PC13
0.1U_0603_50V4Z
MAINPWON <7,50,53>
PU2B
LM393M_SO8
PR40
PC20
1U_0805_16V7K
1
2
PH1
10K_TH11-3H103FT_0603_1%
1
2
PC21
1000P_0402_50V7K
PR36
16.9K_0603_1%
1
2
PR30
2.15K_0603_1%
VL
150K_0402_1%
PR42
150K_0402_1%

Title
BATTERY CONN / OTP

Size
Date:
A
Document Number
Rev
0.1
, 07, 2004
Sheet
D
49
of
65
4
1
2200P_0402_50V7K
OUTC2 GND
23
<50>
PC33
1
2
+INE2
CS
22
-INE2 VCC(o)
21
PC36
1
2
FB2
VREF
OUT
20
VH
19
PR59
1
2
1K_0603_1%
1500P_0603_50V7K
2
1
10K_0603_1%
1 PR64
FB1
VCC
1
PR60
-INE1
RT
17
+INE1
-INE3
16
10
OUTC1
FB3
15
11
OUTD
CTL
14
+INC1
13
12
PR65
<46>
2 PC37
DTC115EKA_SOT23
0.1U_0805_25V7K
1
2
68K_0603_5%
PL4
1
2
15U_SPC-1204P-150_4A_20%
PR63
PC38
1
2
1
2
47K_0603_1%
1500P_0603_50V7K
DCSRD
PR61
BATT+
0.02_2512_1%
PD14
SKS30-04AT_TSMA
-INC1
ACOFF
100K PQ8
18
LXCHRG
174K_0603_1%
2
100K
PC34
1
2
0.1U_0603_50V4Z
PR62
IREF
ACOFF#
0.1U_0805_25V7K
10K_0603_5%
PC31
1
2
PR57
4700P_0603_50V7K 1K_0603_1%
DCSRD
N18
PC30 2200P_0402_50V7K
1
2
CHGSS
PR51
PQ6
AO4407_SO8
PR54
28.7K_0603_1%
1
1
1SS355_SOD323
<46>
0_0603_5%
DC_IN
MB3887_SSOP24
PC42
PC41
4.7U_1206_25V6K
2
1
24
3
2
1
+INC2
PC39
4.7U_1206_25V6K
2
1
PD13
ACOFF#
-INC2
PQ9
2N7002_SOT23
2
G
VREF
PC35
0.1U_0603_16V7K
PR56
10K_0603_1%
3K_0603_5%
PACIN
PC32
0.1U_0603_16V7K
2
1
PACIN
PR58 2
1
PQ5
AO4407_SO8
5
6
7
8
PR52
47K_0603_1%
PR53
150K_0603_1%
47K_0603_5%
2N7002_SOT23
<50>
ADP_I
PR50
PQ49
DTC115EKA_SOT23
8
7
6
5
4
1
2
PC26
0.1U_0805_25V7K
1
2
3
1
3
PC28
PR48
PU4
PQ50
0.1U_0603_25V7K
Throttling -1 level: ADP_I=1.4V

Throttling +1 level: ADP_I=1.14V
100K
100K
2
G
PC25
4.7U_1206_25V6K
2
1
1
2
PC29
0.1U_0603_25V7K
2
1
10K
0.01_2512_1%(1W)
<46,51>
PC98
1
PR44
47K
PR195
47K_0402_5%
1K_0603_5%
1
PQ48
PL3
FBM-L18-453215-900LMA90T_1812
200K_0603_5%
DTA144YKA_SC70
B++
B+
P3
PR47
PR240
8
7
6
5
1SS355_SOD323
1
2
3
PC24
4.7U_1206_25V6K
2
1
2
PD30
1
2
3
AO4407_SO8
8
7
6
5
1
2
3
Iadp=0~6.5A
8
7
6
5
PR247
15K_0603_5%
PQ61
PQ4
AO4407_SO8
P2
PQ3
AO4407_SO8
DC_IN
PC40
4.7U_1206_25V6K
2
1
100K_0603_1%
IREF=1.096*Icharge
IREF=0.44~3.3V
0.1U_0603_16V7K
PR66
PR67
4.2V
95.3K_0603_0.1%
143K_0603_0.1%
CC=0.4~3A
CV=16.8V(8 CELLS LI-ION)
PR250
95.3K_0603_0.1%
OVP voltage : LI
+3VALWP
VMB
4S2P : 17.4V--> BATT_OVP= 1.94V
CHGSS
(BAT_OVP=0.1111 *VMB)
PQ10
1
1
1
<46>
FSTCHG
100K
2N7002_SOT23
PQ11
100K
DTC115EKA_SOT23
3
-
PC43
0.1U_0603_50V4Z
PR70
499K_0603_1%
2
8
P
PU5A
+ 3
2
G
VL
0
4
<46> BATT_OVP
47K_0603_5%
PR69
340K_0603_1%
PR68
LM358A_SO8
4
PC45
0.01U_0603_50V7K
PR72
105K_0603_0.5%

Title
CHARGER
Size
Date:
A
Document Number
Rev
0.1
, 07, 2004
Sheet
D
50
of
65
B+
PJP23
JUMP_43X118
PC46
4.7U_1206_25V6K
2
1
1
5
6
7
8
47P_0402_50V8J2
2M_0402_1%
PC65
1 2
1
PR82
5
6
7
8
G
S
S
S
4
3
2
1
D
D
D
D
G
S
S
S
4
3
2
1
PC56
1
4.7U_1206_25V6K
PC58
1
4.7U_1206_25V6K
PR243
698_0402_1%
0.47U_0603_16V7K
1
PC72
4.7U_1206_10V7K
10.2K_0603_1%
PC75
100P_0402_50V8J
1
1
PR99
47K_0402_5%
1
+
PC76
150U_D2_6.3VM
PR96
1 PR95
2
0_0402_5%
+5VALWP
MAX1902EAI_SSOP28
PR94
1
2
@0_0402_5%
PC68
PR79
0_0402_5%
PD18
SKS10-04AT_TSMA
VL
D
D
D
D
DL5
2.5VREF
PR78
1.54K_0603_1%
PC73
680P_0402_50V7K
1
2
VS
PQ15
SI4810DY_SO8
PQ13
SI4800DY-T1_SO8
RUN/ON3
DH51
2
PR80
0_0402_5%
TIME/ON5
7
28
12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#
PR92
@300K_0402_5%
1
PR89
10K_0402_5%
DH5
VL
CSH3
CSL3
FB3
SKIP#
SHDN#
1
2
3
10
23
PR2422
1
620_0402_5%
2
PR77
0_0402_5%
21
22
LX3
DL3
100P_0402_50V8J
26
24
PC71
DH3
4
5
18
16
17
19
20
14
13
12
15
9
6
11
GND
0.47U_0603_16V7K
2
1
<27,46,50> ACIN
PR91
3.32K_0603_1%
1
2
PR85 2
1
0_0402_5%
BST3
27
V+
PC67
PR241
1.27K_0603_1%
25
PC57
1
2
1
1
3
B++++
1
2
1
2
PU6
1
2
1.27K_0603_1%
PR97
10K_0402_1%
AC IN 2
G
PR81
PR83
1M_0402_1%
1
2
PD17
SKUL30-02AT_SMA
4.7U_1206_25V6K
8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4
1
PC63
2
1
3
PC70
@150U_D2_6.3VM
PC69
150U_D2_6.3VM
+3VALWP
PQ51
PC61
2N7002_SOT23
10U_SPC-1204P-100_4.5A_20%
DL3
0.1U_0805_25V7K
+12VALWP
PC60
0.1U_0805_25V7K
DH3
PL6
47P_0402_50V8J
PQ14
SI4810DY_SO8
PC54
4.7U_1206_10V7K
1SS355_SOD323
LX3
PR75
0_0402_5%
9U_SDT-1204P-9R0-120_4.5A_20%
LX5
2200P_0402_50V7K
1
PD19
PR74
1
0_0402_5%
1
2
3
4
DH31
FLYBACK
PT1
PC53
1
2
PR239
2.7K_1206_5%
8
7
6
5
VS
PR73
22_1206_5%
PD16
DAP202U_SOT323
VL
PQ12
SI4800DY-T1_SO8
S
S
S
G
D
D
D
D
4.7U_1206_25V6K
PC52
1
4.7U_1206_25V6K
PC51
1
2200P_0402_50V7K
PC50
2
1
0.1U_0805_25V7K
PD15
EC11FS2_SOD106
SNB 2
BST51
470P_0805_100V7K
BST31
PC47
PC48
1
2
B++++
PR100
10K_0402_1%
VL
PC79
@0.047U_0603_16V7K
PR101
806K_0603_1%
MAINPWON <7,50,51>
PC80
0.47U_0603_16V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

Title
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
Size
Document Number
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
Date: , 07, 2004
INC.
5V/3.3V/12V
Rev
0.1
Sheet
D
51
of
65
PJP24
JUMP_43X118
1
2 2
B+
D
+5VALWP
2
PR102
0_0603_5%
+1.25VSP
PJP2
JUMP_43X118
1
2 2
PJP4
JUMP_43X118
1 1
2 2
PJP3
JUMP_43X118
1
2 2
PJP5
JUMP_43X118
1
2 2
4.7U_1206_25V6K
1
2
3
2
1
220U_D2_4VM
PC95
1
2
PR267
@0_0603_5%
+
2
4
3
2
1
PD23
SKS10-04AT_TSMA
4.7U_0805_6.3V6K
PC96
2
1
5
6
7
8
G
S
S
S
PQ19
SI4810DY_SO8
PR268
0_0603_5%
PR117
100K_0603_1%
PR115
15.4K_0603_1%
PR116
100K_0603_1%
+5VALWP
PC211
@100P_0402_50V8K
7
5
13
3
PR114
16.9K_0603_1%
2
1
0.22U_0603_16V7K
1
1
2
+5VALWP
+5VALW
+1.25VS
PJP6
+VCCVIDP
+2.5VALW
PC99
2
PR249
0_0402_5%
PJP1
JUMP_43X118
1 1
2 2
+2.5VALWP
PR108
0_0603_5%
2
ILIM2
ILIM1
2
PR248
VCC_MAX1845 1
2
@0_0402_5%
+2.5VALWP
4.7U_SPC-1204P4R7_5.7A_20%
1
2
15
14
12
PR236
PC92
0.1U_0805_25V7K
1
D
D
D
D
PC91
22
9
UVP
VCC
PGOOD
TON
ON1
11
REF
1
0_0603_5%
SKIP
DH1
+5VALWP
BST2
DH2
LX1
LX2
DL1
DL2
MAX1845EEI_QSOP28 CS2
CS1
OUT1
OUT2
FB2
FB1
ON2
19
18
17
20
16
10
28
1
4
V+ 1U_0805_16V7K
2
1
8 1
7 2
6 3
5
D
D
D
D
27
24
PU7
21
GND
26
PL9
PR106
0_0603_5%
1
2
VDD
BST1
OVP
25
PR107
0_0603_5%
VCC_MAX1845
23
PC90
0.1U_0805_25V7K
2
1
SKS10-04AT_TSMA
2
PQ17
SI4800DY_SO8
2
PR105
0_0603_5%
PQ18
SI4810DY_SO8
S
S
S
G
1
2
3
4
1
4.7U_SPC-1204P4R7_5.7A_20%
PC94
4.7U_0805_6.3V6K
PD21
PC89
0.1U_0805_25V7K
PL8
3
4
PC93
220U_D2_4VM
PC88
4.7U_0805_10V4Z
5
6
7
8
20_0603_1%
SI4800DY_SO8
+1.5VSP
1
2
PR104
8
7
6
5
PQ16
PC87
4.7U_1206_25V6K
PC184
2
1
PR103
0_0603_5%
4.7U_1206_25V6K
PC84
PD20
DAP202U_SOT323
PC85
2200P_0402_50V7K
2
1
PC183
4.7U_1206_25V6K
1
2
PC83
4.7U_1206_25V6K
PC81
2200P_0402_50V7K
+VCCVID
+3VALWP
+3VALW
JUMP_43X39
PJP10
JUMP_43X118
1
2 2
+1.8VS
PJP21
JUMP_43X118
1
2 2
+VGA_CORE
PJP22
JUMP_43X118
1
2 2
PJP8
+12VALWP
+12VALW
+1.8VSP
JUMP_43X39
A
+1.2VS_VGA

Title
DDR POWER 2.5V & 1.5V

5
Size
Document Number
Rev
0.1
B
Date: , 07, 2004
Sheet
1
52
of
65
PR262
LGATE
D
D
D
D
@0.1U_0402_16V7K
GND
G
S
S
S
PC206
22U_1206_6.3V
2
1
PC204
22U_1206_6.3V
2
1
5
6
7
8
D
D
D
D
PC205
22U_1206_6.3V
2
1
+1.2VS_VGA
1
4
3
2
1
APW7057KC-TR_SOP8
+
PQ60
SI4810DY_SO8
1
+
2
PR217
2
1
0_0603_5%
+3VALWP
+VCCVIDP
PHASE
PL16
2.2UH_SPC-1205P-2R2B_13A_30%
1
2
PC189
10U_1206_25VAK
PC188
220U_D2_4VM_R25
2
1
+5VALW
PQ58
SI4800DY-T1_SO8
PC187
@220U_D2_4VM
UGATE
G
S
S
S
4
3
2
1
FB
BOOT
VCC
2
1
1
OCSET
PC209
5
6
7
8
PU31
PQ59
2N7002_SOT23
PD43
1N4148_SOD80
1
PC207
470P_0402_50V7K
2
G
3
SUSP
PR264
0_0402_5%
1
2
1U_0603_6.3V6M
JUMP_43X118
PC203
PC208
0.1U_0402_16V7K
PR263
8.45K_0603_1%
1
PJP20
2
2
10_0603_1%
PC172
4.7U_0805_10V4Z
PU27
1
IN
PG
OUT
GND
PR265
1.74K_0603_1%
1
2
<5,56> VID_PWRGD
PC210
0.1U_0402_16V7K
3.4K_0603_1%
<46>
VR_ON
EN
MIC5258_SOT23-5
PR123
0_0603_5%
PR266
PC171
4.7U_0805_10V4Z
2
PR218
100K_0402_1%
1
M11P: 1.2V--> PR265=1.74K ohm

M9-X: 1.5V-->PR265=3K ohm
PJP18
JUMP_43X118
+2.5V
PR257
1K_0402_1%
2
3
GND
NC
VREF
NC
VOUT
NC
TP
+3VALW
PC194
1U_0603_6.3V6M
+1.25VSP
1
+
2
PC199
@150U_D2_6.3VM
PC197
0.1U_0402_16V7K
PC200
@0.1U_0402_16V7K
PR260
1K_0402_1%
PC201
10U_1206_6.3V7K
PQ57
2N7002_SOT23
2
G
PR259
0_0402_5%
1
2
1
SUSP
37,42
PR261
44.2_0402_1%
2
1
2
APL5331KAC-TR_SO8
PC198
100P_0402_50V8J
VCNTL
PC195
10U_1206_6.3V7K
PC196
4.7U_0805_6.3V6K
PR258
100_0402_1%
1
1
VIN
PC193
10U_1206_6.3V7K
ADJUST
+1.8VSP
PU29
+3VS
PU30
APL1085UC-TR_TO252
3 VIN VOUT 2
PJP19
JUMP_43X118
1 1
2 2

Title
VGA/1.8V/VCCVID/1.25V
A
Size
Document Number
Rev
0.1
Date: , 07, 2004
Sheet
E
53
of
65
PR269
@100K_0402_1%
2
1CORE_REF
+5VS_CORE
For Prescott: Pop PR167

For Northwood: Pop PR269
PR160
1
2
20K_0402_1%
PR1612
1
3
PR167
100K_0402_1%
1
1
1
2
VCCSENSE <5>
2
@0_0402_5%
PR245
1
+
PC202
100U_25V_M
PC130
100U_25V_M
PC212
100U_25V_M
PC120
0.1U_0805_25V7K
PC119
2200P_0402_50V7K
10U_1206_25VAK
PC118
2
1
10U_1206_25VAK
1
+
2
G
S
1
PR164
499_0402_1%
PC135
0.1U_0805_25V7K
1
2
PC134
2200P_0402_50V7K
10U_1206_25VAK
PC133
2
1
OAIN-
10U_1206_25VAK
PC132
2
1
10U_1206_25VAK
OAIN+
PL13
0.5U_CXZM1350-R50_35A_20%
1
2
B+
+VCC_CORE
CM<57>
2N7002_SOT23
3
1 PR159 2 OAIN+
100K_0402_1%
PC117
2
1
10U_1206_25VAK
PC116
2
1
5
5
1
<4,5,6,7,8,26,57>
2 CM0_0402_5%
PR163
1
2 CM+
0_0402_5%
PR166
PQ45
2N7002_SOT23
PQ44
2N7002_SOT23
PR133
10K_0402_5%
1
2
C
E
100P_0402_50V8J
2
0_0402_5%
PC138 PR156
1
2
0_0402_5%
PR157
PR155
0_0603_5%
1
2
3
2
1
CS-
PC142
@100P_0603_50V8G
PC140
PC180
<57>
3
2
1
MAX1546
PQ30
SI7392DP_SO8
DLS
CS+
<57>
22.6_0402_1%
PR111
2 1
150_0402_1%
PC124
CM+
<57>
+CPU_B+
2
1
PD29
SKS30-04AT_TSMA
37
100P_0603_50V8J
PC139
2200P_0402_50V7K
VROK
OFS
PD27
SKS30-04AT_TSMA
PR110
0.47U_0603_16V7K
PR153
PQ43
499_0402_1%
PQ32
SI7886DP_SO8
CMP
D0
PR146
1K_0603_1%
38
D1
3
2
1
39
CSN
CMN
PC129
@4700P_0402_25V7K
PQ31
SI7886DP_SO8
D2
<48> VCORE_PWRGD
OAIN-
BSTM
PC128
0.22U_0603_16V7K
PR145
0.001_2512_5%
1
2
H_BOOTSELECT<4>
40
D3
PD26
PC131
2
1
CSP
D4
PGND
31
PR173
1K_0603_1%
PR244
0_0402_5% +VCC_CORE
1
2
+VCC_CORE
32
D5
OAIN+
SKS30-04AT_TSMA
3
2
1
@100K_0402_1%
1 PR109 2
1
2 19
0_0402_5% PR220
1
2 20
0_0402_5% PR221
1
2 21
0_0402_5% PR222
1
2 22
0_0402_5% PR223
1
2 23
0_0402_5% PR224
1
2 24
0_0402_5% PR225
25
7
PR162
1K_0603_1%
PC141
DLS
OAIN+
OAIN-
PC182
1000P_0402_50V7K
PL11
FBM-L18-453215-900LMA90T_1812
34
2
G
PQ40
S
2N7002_SOT23
PL12
0.5U_CXZM1350-R50_35A_20%
2
1
PQ29
SI7886DP_SO8
33
LXS
100K_0402_1%
DLM
DHS
FB
CCI
15
+5VS_CORE
DAP202U_SOT323
PD28
14
1 PR154
5 3
2
1
30
35
PQ27
SI7392DP_SO8
PR143
0_0603_5%
1
2
3
2
1
VDD
BSTS
<57>
GNDS
BSTM
2
0.22U_0603_16V7K
GND
13
2
G
+CPU_B+
PQ28
SI7886DP_SO8
29
PQ26
2
DLM
2
G
PC181
470P_0402_50V7K
OAIN-
1K_0603_1%
OAIN+
PC115
11
27
28
PR141
2
0_0402_5%
CCV
PR15
0_0402_5%
PR158
2.87K_0603_1%
LXM
DHM
1
2
26
12
BSTM
VCC
SUS
V+
3
36
1 PR171
SKIP#
12
2
1
1
OAIN+
ILIM
PC122
1
2
VCCSENSE
PR152
@1.74K_0402_1%
1 2
18
PC125
PC136
470P_0402_50V7K
FB
PR170
0_0402_5%
REF
SKIP
100P_0603_50V8J
VID5
<5>
VID4
<5>
VID3
<5>
VID2
<5>
VID1
<5>
VID0
<5>
S1
PR148
PR149
0_0402_5%
<5>
17
16
@0_0402_5%
2.2U_0805_16V4Z
PC123
1U_0603_16V6K
S0
0_0402_5%
PC126
1000P_0402_50V7K
+VCCVID
270P_0402_50V7K
PR246
SHDN#
10
1 PR147 2
10_0603_1%
TON
0.22U_0603_16V7K
PC114
PR144
61.9K_0402_1%
+5VS_CORE
TIME
PR140
100K_0402_1%
CORE_REF
PR138
2
@0_0402_5%
PR139
1
2
0_0402_5%
<5,55> VID_PWRGD
<5> VSSSENSE
PU9
<57> CORE_REF
PQ20
2N7002_SOT23
PR180
30.1K_0603_1%
PR137
1
2
PR227
2
0_0402_5%
DPRSLPVR
<26>
2
G
PR136
100K_0402_1%
2.87K_0603_1%
PR132
2
0_0402_5%
MMBT3904_SOT23
PR135
100K_0402_1%
2
1
+5VS_CORE
FB
D
SKIP#
0.47U_0603_16V7K
1. When mode control signal is

high/ low, the VR will operate to
Northwood/ Prescott load line.
2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.
CORE_REF <57>
150K_0402_1%
PR165
100K_0402_1%
FB
H_BOOTSELECT=0 NORTHWOOD
H_BOOTSELECT=1 PRESCOTT
1 PR168 2
9.31K_0603_1%
2
G
PQ33
CPUCLK_STP# <5,11,26>
2N7002_SOT23
PJP14
+5VS
+5VS_CORE
JUMP_43X79
Title
CPU_CORE(1)
Size
A3
Date:
Document Number
, 07, 2004
Rev
0.1
Sheet
54
of
65
<56>
+5VS_CORE
DLM
PR172
PD33
+CPU_B+
PC155
CM+
<56>
CM-
<56>
13
MAX1980
1000P_0603_16V7K
3
2
1
PC144
0.1U_0805_25V7K
PC148
2200P_0402_50V7K
2
1
2
0.47U_0603_16V7K
SKS30-04AT_TSMA
PC152
DLS
12
1000P_0603_16V7K
CM-
GND
PR210
49.9K_0402_1%
1
PC169
CS+
<56>
MAX1980
1000P_0603_16V7K
PD42
SKS30-04AT_TSMA
1
+VCC_CORE
PC166
1
2
0.47U_0603_16V7K
PC163
0.1U_0805_25V7K
200K_0603_1%
DD/
ILIM
13
1
2 1
2
PC167
PR206
19
2200P_0402_50V7K 20K_0402_1%
PQ39
SI7886DP_SO8
CSCM+
PC168
3
2
1
3
2
1
2
9
CS+
PGND
COMP
2200P_0402_50V7K
6
2
PC162
2
1
10
10U_1206_25VAK
15
DL
PC161
2
1
LX
TON
PL15
0.5U_CXZM1350-R50_35A_20%
2
1
10U_1206_25VAK
POL
0.22U_0603_16V7K
PC160
2
1
1 PR199 2
0_0603_5% PC164
10U_1206_25VAK
14
PC159
2
1
16
DH
PR204
BST
VCC
PR200
0_0603_5%
1
2
1K_0603_1%
2
1
LIMIT
12
PQ37
SI7392DP_SO8
17
PQ38
SI7886DP_SO8
PD41
@1SS355_SOD323
1
18
V+
3
2
1
PR2012
0_0603_5%
VDD
PR188
0_0603_5%
+VCC_CORE
PU11
11
TRIG
PC165
2
0.22U_0603_16V7K
2
1 2
PR198
10_0603_1%
2 2
PR196
0_0603_5%
+CPU_B+
20
PC158
2.2U_0805_16V4Z
PD39
1SS355_SOD323
+5VS_CORE
PQ35
SI7886DP_SO8
CM-
3
2
1
2
CM+
+VCC_CORE
SKIP#
<56>
PC170
1000P_0603_16V7K
12
PC156
PR189
49.9K_0402_1%
100P_0603_50V8J
2
1
GND
PD36
PQ36
SI7886DP_SO8
PC154
1K_0603_1%
2
1
CS-
1
5
ILIM
DD/
1
2 1
2
PC153
PR183
19
2200P_0402_50V7K 20K_0402_1%
200K_0603_1%
8
PR184
PR207
3
2
1
9
CS+
PGND
10U_1206_25VAK
10
PL14
0.5U_CXZM1350-R50_35A_20%
1
2
PC147
2
1
DL
10U_1206_25VAK
LX
15
1 PR177 2
0_0603_5% PC150
0.22U_0603_16V7K
PC146
2
1
14
PC145
2
1
16
DH
PR181
BST
VCC
PR174
0_0603_5%
1
2
10U_1206_25VAK
LIMIT
PR17827
1
POL
0_0603_5%
PC151
3 TON
0.22U_0603_16V7K
6 COMP
PD35
@1SS355_SOD323
1
6> CORE_REF
PQ34
SI7392DP_SO8
17
V+
+VCC_CORE PR187
0_0603_5%
PU10
10_0603_1% 18
PR176
12
VDD
2.2U_0805_16V4Z
2
1
2
PC149
1 2
1
11
TRIG
20
0_0603_5% 1SS355_SOD323
100P_0603_50V8J
<4,5,6,7,8,26,56>
CS-
SKIP#
<56>

Title
+CPU_CORE(2)
Size
Document Number
Date: , 07, 2004
Rev
0.1
Sheet
55
of
65
Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
D
Title
54,55,
wrong layout
56,57
pad
56
DPRSLPVR
Date
Request
Owner
03/25/2003
03/25/2003
Compal
Issue Description
Solution Description
Rev.
change to correct layout pad on PU7,

PU11, PU16 and PQ24
Reserve two resistors for voltage of Deep-sleeper mode
Reserver PR231, PR232, PR233, PR234

for deeper-sleeper mode voltage setting
Compal
Reserve a jumper for power consumption measurement
Add PJP14
0.2
Compal
Change the netname +5VS_CORE for power

consumption measurement
Change Netname of +5VS_CORE
0.2
0.2
Compal
PU8, PU9, PU10,
0.2
56
CPU VR-Cont.
57
CPU VR-Cont.
51
RTC charger
03/25/2003
Compal
use two resistors for RTC charger protection
Add PR230
55
1.2VS_VGA
03/25/2003
Compal
re-layout 1.2V_VGA requested by ME
55
1.2VS_VGA
03/26/2003
Compal
re-located both PL10 and PQ21, PQ23

as well as 1.2VS_VGA related power circitry
Add PJP15
55
+1.25VSP
03/26/2003
Compal
Change power time-sequence of 1.25VSP input power
+1.5VALWP
03/27/2003
Compal
Reserve Force PWM function of 1.5V/2.5V

and add a PR236 for SUSP# signal
54
03/25/2003
03/25/2003
0.2
wrong layout pad
0.2
0.2
Change VD, and VDD of PU16 from +2.5VALWP

to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
Add PR237, PR238 for force PWM function control,
and add PR236 for SUSP# signal
0.2
0.2

Title
Changed-List History-1
Size
Document Number
Rev
0.1
LA-2411
Date:
5
, 07, 2004
Sheet
1
56
of
65
BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >
1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.
-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)
2.Modify the Audio related schematic for Customer request . <Page 37> 92.03.17.
-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)
3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request .
<Page 26,27,36,44> 92.03.18.
-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,
U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)
-Add R1048,R1050,R1052 . (Modify CKT&Layout)
4.Modify the Audio related schematic for Customer request . <Page 37,38> 92.03.20.
-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)
-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)
-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)
-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)
5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.
-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)
-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)
6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.
-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) .
(Modify CKT,BOM&Layout)
-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net .
-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)
7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request .
<Page 10> 92.03.21.
-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.
-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)
-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)
9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.
-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
10. Modify the ON1 related to speed up the power sequence for ATI request . <Page 48,54> 92.03.23.
-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);
Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)
11. Modify power source CAP.'s value by Brian . <Page 26,49> 92.03.24.
-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348
from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)
-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)
12. Del Via Hole on schematic for ME modify . <Page 41> 92.03.24.
-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)
13.Modify the MiniPCI and BlueTooth conn related for Customer request . <Page 43,44> 92.03.24.
-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)
-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
14.Swap the USB20*P3* and USB20*P5* for Customer request . <Page 44> 92.03.24.
A-TEST SMT BUILT
-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)
15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.
-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;
Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;
R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;
R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)
16.Modify the schematic H_BOOTSELECT related by Power Team . <Page 04> 92.03.25.
-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) .
-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% .
(Modify CKT&BOM)
17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.
-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),
C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)
18. Modify power source Resistor and CAP.'s value for power sequence . <Page 49> 92.03.26.
-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K
to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)
-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)
-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)
19. Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.
-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)
20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.
-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)
21. Change the Resistor's value for ATI recommend . <Page 17 > 92.03.26.
-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)
22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.
-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)
23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.
-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
24. Change the power sequence related part's power source by Brian . <Page 5,37,48> 92.03.27.
-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)
25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.
-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K .
(Modify CKT&BOM)
-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)
26. Modify the SPDIF related schematic for Customer request . <Page 37,41> 92.03.28.
-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)
27. Modify the NEC USB2.0 Controller Chip related schematic for Customer request . <Page 36> 92.03.28.
-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) .
-Add R1104(@0_0402_5%) . (Modify CKT&Layout)
-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)
28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.
-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)
29. Modify the related schematic after Brian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.
-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)
30. Modify the related schematic after Layout check <Page 44> 92.03.31.
-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)
31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.
-Update JP40 . (Modify CKT&Layout)
32. Modify the schematic for cost down . <Page 10,12,26,37,> 92.04.04.
-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)
----PLEASE SEE NEXT PAGE

Title

H/W2 EE Dept. PIR SHEET(1)
1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
57
of
65
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18.
> define sequence error. <Page 35> 92.04.08.
1.1394 Connector JP33 Pin
-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EE
Circuit)
2.LED Circuit to Power Button(PRES)modify . <Page 42, Page 46> 92.04.09.

-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)
-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)
3.Add +1.2VS_VGA Discharge Circuit. <Page 49> 92.04.09.
-Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)
4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.
-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18.
> Footprint error. <Page 40> 92.04.09.
1.FDD Connector JP38 PCB
-Check JP38 ACES_85201-2605_26P. (Modify Layout)
2.Power Switch U53 PCB Footprint error. <Page 12> 92.04.09.
-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)
1
3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.

-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)
4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.
-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES
85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)
5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep. <Page 31> 92.04.09.
5. Change BOM & Layout LED D57 Footprint . <Page 42> 92.04.15.
-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)
6. MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.

-Update BOM add R326. (Modify EE Circuit)
6. Change Layout Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.

-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)
7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.
-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)
-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)
7. Change Layout FrontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.

-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)
8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.
2
9. Add SUSP# pull Down. <Page 46> 92.04.14.

-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)
10. Add CPUCLK_STP# pull High Circuit. <Page 26, 5> 92.04.14.
-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)
-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)
-Add CPUCLK_STP# serial resistor R1125 to Q96.2. (Modify EE Circuit)
11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.
12. SIO Circuit All Power Plan +3V -> +3VS. <Page 39> 92.04.15.
13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.
-Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)
-Update BOM R1046 -> @. (Modify EE Circuit)
14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.
3
15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.
16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.
17. Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.
18. Change BOM C191 4.7U -> 2.2U. <Page 17> 92.04.17.
19. Change BOM C202,C931 10U -> 2.2U. <Page 20> 92.04.17.
20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.
21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.
22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.
23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.
24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.
25. Change BOM C966 22U -> 0.1U. <Page 18> 92.04.18.
26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.
27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.
28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.

Title

1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
58
of
65
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >
29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.
30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->
AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.
1
31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.
32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.
33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.
34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.
35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.
36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull
High +3V. <Page 41> 92.04.21.
37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.
38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.
39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.
40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.
41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.
42. Change BOM R40 @ -> Del @, R53 -> @. <Page 29> 92.04.23.
43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.
44. Change BOM R230 -> @. <Page 4> 92.04.23.
45. EMI add R1144 for SSOUT. <Page 10> 92.04.24.
46. EMI change D73, D74, D75, D76 part. <Page 38> 92.04.24.
47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.
48. Change BOM R623 10K -> 0. <Page 25> 92.04.28.
49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.
BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >

3
1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.

2. Change C963 -> @. <Page 41> 92.04.28.
3. Change C974 -> @. <Page 17> 92.04.28.
4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.
5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.
6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.
7. DEL R761,R762 <Page 37> 92.04.28.

Title

1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
59
of
65
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR

<92.05.07.~92.05.30. >
It em
Fixed Issue
1
Reason for change
PAGE
Prevent CPUCLK_STP# abnormal state happened
Prevent power leakage
M.B. V er.
Modify List
0 .5
Cha nge R1125 from 4.7K to 12K
26
Delete R1126
29
Change R40 from 10K to 1K
Change the power of U8 from +3VS to +3VALW
0 .5
Power saving
Change the power of Fans from +5VALW to +5VS
0 .5
ATI recommendation
Add C9 74
0 .5
Add VGA DRAM size detect function
17
Add R 1149 for 128MB VGA DRAM (un-populate for 64MB)
0 .5
Add CS1# for Hynix 8Mx32 VGA DRAM
Add Nets: NMCSA1# and NMCSB1#
0 .5
Change M9+X VGA_CO RE from +1.5VS to individual power source
21
Delete JOPEN3
0 .5
Delete useless components
Delete R538
0 .5
25
Delete C96
27
Delete Q114, Add R1145
1 8 , 19,
2 2 , 23
Update with Item23
Solve power leakage from CRT
25
Change R619.1 and R622.1 net from +5VS to CRT_VCC
0 .5
10
Prevent DPRSLPVR abnormal state happened
26
Change R 1001 from 100K to 47K, R1002 from 0 to 47K
0 .5
11
Using rechargeable RTC battery for HP's request
26
Delete D66, D71 and D72; Add D9 1 (BAS40-04, the same as LA-1761 D30); Change
BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1)
0 .5
12
Prevent +5V drop while plug SPR for HP's request
41
Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798
from 2 2u to @10u; Change C801 from 1000p to @1000p
0 .5
13
Enhance brightness of blue LEDs
4 2 , 45
Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,
R885, R 888, R889, R890, R925 and R1136 to 220
0 .5
44
3
14
Solve PWR_ACTIVE LED function fail issue
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;
Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 to
PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to
PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS
42
Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56)
46
Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; Change
U15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to
PWR_ACTIVE _PAV#
0 .5
15
Solve M10 can't power up issue
49
Change R1101 from 100K to 56K; Change R901 from 91K to 27K
0 .5
16
Add discharge components
49
Add R372, R1095 , R1102, Q36, Q103 and Q109
0 .5
17
Material change for ME's request
44
Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-176 1 JP2)
0 .5
18
Using NEC USB2.0 to support BT for HP's request
44
Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5-
0 .5
19
Increase MONO_IN voltage level
37
Ch ange R738 from 2.4K to 10K
0 .5
20
Decrease Audio AMP Gain
38
C hange R971 from 100K to @100K; Change R973 from @100K to 100K
0 .5
Title

1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
60
of
65
BHR60 from SI-1 to DB(15.4")

REV:0.4 -> 0.5
It em LA-1811
Fixed Issue
HW PIR <92.05.07.~92.05.30. >
Reason for change
21
PAGE
RTL8 101L no need transistor for 3.3V to 2.5V anymore
34
REALTEK recommendation
M.B. V er.
Modify List
0 .5
Delete Q55, R944 and C668

Change R704 f rom 5.6K_0402_5% to 5.6K_0402_1%
22
Connector Spec. change for ME's request
44
Change PC B Footprint from SUYIN_020167MR004SX01ZR_4P to

suyin_020167mr004s511zu_4p for JP18 , JP19 and JP20
0 .5
23
Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT
25
Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150
0 .5
24
Delete useless components with BOM
0 .5
Add SB to control H_PROCHOT# for HP's request
26
Add Q118 and R1 151
0 .5
26
Add components for EMI
37
Add R1 152
0 .5
40
Add L65 ~ L78
40
Add L79 ~ L97
Solve DOS cold-boot shunt down issue
Delete C256
0 .5
Decrease overshoot & undershoot
25
Add R1153 a nd R1154
0 .6
29
Change SB GPIO 0 and GPIO2 pull-down to GND
26
Delete RP126; Add R1155~ R1157
0 .6
30
Only 0603 size in SAP for 5.6K_1%
34
Change component size of R704 from 0402 to 0603
0 .6
31
The pin-definition of FDD conn. was error on rev0.5 M/B
40
Correct the pin-definition for JP38
0 .6
32
VIA recommendation
40
Change RP119 from 1K to 330; Delete RP121; Add R? and R?
0 .6
33
Enhance brightness of Docking LEDs
41
Ch ange R880 from 10K to 470
0 .6
34
To support wake-up function with TP
44
Change TP power from +5VS to +5V
0 .6
35
Delete R535, R536, R9 91 and R992
0 .6
12
Delete U 53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17
Delete Q15 and R251
20
Delete R1022
24
Delete R211 and R216
25
Delete C93~C95 a nd C930
BHR60 from DB to SI LA-1811

2 8 REV:0.5 -> 0.6
HW PIR <92.06.20.~92.07.03. >
Delete R574, R1086 and C952

Delete R210 for UMA only
25
27
10
24
26
Delete Q113, R1124 and D91; Add D93
27
Delete RP149, RP150, R1145 and Q114
29
Delete R53
37
Delete L45, R1019, Y6, R756, C740 and C741
38
Delete R1142
39
Delete RP153 and R1132
36
To improve RTC accuracy
26
Change Y1 f rom +/-20ppm to +/-10ppm
37
Solve Cardbus controller can't reset well issue
31
Delete R905, R941 and C906; Connect U37 .C11 to G_RST#
38
Add components for EMI
37
Add L98 and L99
39
Improve Audio quality
40
Add components for ID & ME
41
Modify +5V power-up timing to lead +3V
0 .6
0 .6
0 .6
40
Add C97 5, C976, CP15~CP17
37
Delete C753~C756; Add R1165~R1168 and C979
38
Add R1158 and R116 4; Exchange the nets of JP41.2 and JP41.3
41
Add R1 161
42
Add D92
49
Ch ange R904 from 91K to 47K

Title
0 .6

1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
61
of
65
BHR60 from SI-1 to PV LA-1811

REV:0.6
It em
Fixed Issue-> 0.7
HW PIR <92.07.03.~92.08.08. >
Reason for change
42
PAGE
Correct Y1 and Y3 pin-out
Modify List
26
M.B. V er.
Using pin-1 and pin-2 of these crystals
0 .7
46
Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95
43
ATI Product Advisory, refer to PA_218IXP0T1
44
44
Solve CD-ROM audio noise issue
30
Delete C11
45
Solve audio noise issue
37
Change R733. 1 from +5VS to +5VAMP_CODEC
0 .7
46
F or E MI
38
Add L100, L101, L102 and L103
0 .7
47
For FIR detect
39
Add R1173(no fir) and R1174(with FIR)
0 .7
48
ATI recommendation
27
Change RP12 from 10K to 2.2K
0 .7
46
Add R1 175
0 .7
0 .7
49
46
Delete D69 and D70
0 .7
50
To support wake-up function with TP
46
Delete RP154; Add R1169, R1170 , R1171 and R1172
0 .7
51
Solve M10 can't power up issue
49
Delete C844
0 .7
52
Improve Tr and Tf of H-sync/V-sync for high resolution CRT
25
Decrease the R,L,C value
53
Modify brightness of LEDs
42
Ch ange R901 from 27K to 6.8K
0 .7
Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre.
0 .7
45
54
Fast power on for battery only
55
Change R306 from 100K to 470; Delete Q112
0 .7
Improve contact
Move JP2(CD- ROM conn.) right 0.65mm
0 .7
56
Correct Caps. LED and Numl. LED placement
Exchange the placement of these LEDs
0 .7
57
Solve audio noise issue
Cut the bridge between AGND and DGND in GND1 layer
0 .7
58
Reserve for EMI
37
Add JOPEN6, JOPE N7 and JOPEN8
0 .7
59
Improve USB2.0 signal quality
36
Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2
0 .7
60
Reserve VRAM detect function for ATI recommendation
17
Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS
1 .0
61
F or E MI
38
48
36
7
24
26
28
37
41
25
Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A)1 . 0

Delete C110~C115
C hange L89, R1079 & R1080 to CHB1608U301
Ad d C855, C856, C907 and C908
Change L11 & L12 to MBV2012301YZT
Change PCI clock damping resisters to 39 ohm
Add C873~C881, C980~C 983; Change R60~R62 to MBV2012301YZT
Delete R769 & R770; Add C984 ~C992 & L104
Add L105
Add C993 & C994
62
Reduce GHI# "LOW" voltage level
Change R527 to 300 ohm
63
Fix "Pop" sound during boot up
64
For PCBA skew reducing
65
TI recommendation
66
Solve audio L/R swap issue
67
45
37
Improve NIC transmit return loss
1 .0
Add C9 79
1 .0
Change R885, R888, R890, R1136 and R925 to 130
1 .0
32
Add R1 177
1 .0
37
Change R750 & R753 to 27 ohm
1 .0
44
Delete R327 & C305
34
Ch ange U41 to NS0019
45
42
1 .0
Title

1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
62
of
65
BHR60 LA-1811 REV:1.0 ->1A

It em
HW PIR
Fixed Issue
Reason for change
67
PAGE
M.B. V er.
Modify List
reserve Hynix DDR blue screen issue when boot to Win XP
16
Add R1 180
1A
F or E MI
43
Connect MiniPCI clamp (pin1 27 and pin128) to GND
1A
For EC NS97551 +3VALW undershoot issue
46
Add D94 a nd R1178
1A
46
Delete JP21
47
Delete JP22
Reserve for when you connect the dock station cable in unit playing an audio
occur a speaker switch
46
Add R1179 a nd C995
1A
The region is ME height limited zero
54
Delete PJP10 than short it directly
1A
68
1
69
Delete unnecessary component
70
71
72
1A
73
74
75
76
2
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Title

1
Size
Document Number
Rev
0.1
LA-2411
Date:
, 07, 2004
Sheet
5
63
of
65

Item Page#
D
56
DPRSLPVR
Request
Owner
03/25/2003
03/25/2003
Compal
Compal
Issue Description
Rev.
wrong layout pad
change to correct layout pad on PU7,

PU11, PU16 and PQ24
Reserve two resistors for voltage of Deep-sleeper mode
Reserver PR231, PR232, PR233, PR234

for deeper-sleeper mode voltage setting
Add PJP14
0.3
CPU VR-Cont.
57
CPU VR-Cont.
51
RTC charger
03/25/2003
Compal
use two resistors for RTC charger protection
Add PR230
55
1.2VS_VGA
03/25/2003
Compal
re-layout 1.2V_VGA requested by ME
55
1.2VS_VGA
03/26/2003
Compal
re-located both PL10 and PQ21, PQ23

as well as 1.2VS_VGA related power circitry
Add PJP15
55
+1.25VSP
03/26/2003
Compal
54
+1.5VALWP
10
54
+1.5VALWP
11
56
CPU DPRSLPVR
12
54 55
56
13
56
15
50
50
16
51
17
51
18
52
19
20
PWR JUMP
CPU DPRSLPVR
Vin DETECTOR
Precharge
Battery OTP
03/25/2003
03/25/2003
03/27/2003
Compal
Compal
Compal
04/16/2003
Compal
04/16/2003
Compal
04/16/2003
Compal
04/18/2003
Compal
04/30/2003
04/30/2003
Compal
Compal
0.2
PU8, PU9, PU10,
56
14
54,55,
wrong layout
56,57
pad
Date
Title
Change the netname +5VS_CORE for power

consumption measurement
Reserve Force PWM function of 1.5V/2.5V

and add a PR236 for SUSP# signal
change 1.5V time sequence
0.3
Change Netname of +5VS_CORE
0.3
0.3
C
0.3
0.3
Change VD, and VDD of PU16 from +2.5VALWP

to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin
for test
Add PR237, PR238 for force PWM function control,
and add PR236 for SUSP# signal
0.3
0.3
0.4
Change DPRSLPVR design
Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode0.4
For DFX issuse
Change power JUMP SIZE to follow new jump role
to make ACIN to enable to pull low
Reserve DPRSLPVR function

and add a PR136 for +5VS_CORE signal
Change PR8 form 10k_0603 to 0K_0603
BOM error
Change PR1 from 10k_0603 to 100k_0603
Change DPRSLPVR design
0.4
0.4
0.4
Change PC20 from .22u to 1u ;PR40&PR42 from 100k to

150k; PC80 from 1u to .47u
To change feekbeck time
04/30/2003
Compal
04/30/2003
Compal
change component
Change PU3 from S-81233SGUP-T1
Battery_OVP
04/30/2003
Compal
To avoide the BATT_OVP output to oscillate
Delet PC44&PR71
53
5V/3.3V/12V
04/30/2003
Compal
BOM error
Change PD16 from EC31Q04
53
5V/3.3V/12V
04/30/2003
Compal
To improve the 3V output ripple Voltage
0.4
0.4
to S-812C33AUA-C2N
0.4
0.4
to EC11FS2
0.4
Delet PC77
0.4

Title
Size
Document Number
Rev
0.1
LA-2411
Date:
5
, 07, 2004
Sheet
1
64
of
65

Item Page#
Title
Date
Request
Owner
Issue Description
Rev.
55
1.2VS_VGA
22
50
Precharge
detector
23
51
21
24
56,57
25
52
26
55
27
Colok THROTTLING
CPU_CORE(1&2)
04/30/2003
05/16/2003
Compal
Compal
BOM errors
Add
PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)
System can't power on by battery
05/16/2003
Compal
05/16/2003 Compal
Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form

84.5K to 11.5K
To modify the circuit
Change the freqeuce 300k to 200k
To modify the charger circuit
1.2VS_VGA
05/16/2003
Compal
To modify the circuit for 1.2VS_VGA &1.5VS_VGA
07/4/2003
Compal
56
CPU_CORE
29
56,57
CPU_CORE(1&2)
30
50
DC_in
31
52
Charger
32
53
3V/5V/12V
07/4/2003
07/4/2003
08/4/2003
08/4/2003
08/4/2003
Compal
To modify the DCR sense
To improve the CPU_CORE effecient
Compal
For Gibson issue ,add two schottky diodes
Compal
To modify the Precharge circuit
Compal
add PR124(11.5k_0603)
0.5
Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)

,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet
PR86,PR88,PR90,PR93
To modify THE CPU Load line form -1.5mV/A to -2.2mV/A
Compal
0.5
Add PR194(1K)
0.5
,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)
Compal
28
0.6
Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC
0.6
add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)

0.7
Add PD30(1SS355_SOD323)
To solve the DCR sense for 5V OCP issue
,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA_S
0.7
change PR81(1.27k) ,PR78(1.54K),PR79(0_0402)

,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add
PR241(1.24k),PR242(620 ohm),PR243(698 ohm)
56
CPU_CORE
08/4/2003
Compal
34
52
Charger
08/4/2003
Compal To improve the charger feedback loop for charger noise issueChange PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603)
52
2004.05.31
To modify THE CPU Load line form -2.2mV/A to

-1.5mV/A, and senes CPU VCC and VSS
change 2.5V from fix to adjust
0.6
Change PR158,PR180 from 2k to 3.4k
33
35
0.5
delet PR138 ; add PR187(0_0603)&PR188(0_0603)
05/16/2003
3V/5V/12V
0.5
Change PR5 from 150k to 180k
Charger
53
0.4
Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k
0.7
Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)

and PR245(0 ohm)
0.7
0.7
Add pr267, PR268 and PC211

Title
Size
Document Number
Rev
0.1
LA-2411
Date:
5
, 07, 2004
Sheet
1
65
of
65

Compal Confidential: Schematics Document DT Transport or Prescott Ufcpga With ATI-RC300M+SB200 Core Logic

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A

Compal Electronics, Inc.

Intel Northwood/Prescott Processor

CRT & TV-OUT Conn.

W/O EXT VGA CHIP

W/EXT VGA CHIP

W/O EXT VGA CHIP

2.5V DDR- 200/266

VGA DDR x2 CHB

VGA DDR x2 CHA

AMP & Audio Jack

MDC & BT Conn

BGA 457 pin

Power On/Off CKT.

SUPER I/O SMC 207

Power Circuit DC/DC

Compal Electronics, Inc.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

The voltage for Processor VID select

1.25V switched power rail for DDR Vtt

1.2V I/O power rail for ATI-VGA M9+X/M10P.

1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.

1.8V switched power rail for ATI-RS300M/RC300M NB.

2.5V always on power rail

2.5V system power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V system power rail for SB,LAN,CardReader and HUB.

3.3V switched power rail

5V always on power rail

5V system power rail .

5V switched power rail

12V always on power rail

: means Analog Ground

Board ID Table for AD channel

Wireless LAN(MINI PCI) AD18

I2C / SMBUS ADDRESSING

CLOCK GENERATOR (EXT.)

Compal Electronics, Inc.

FERR#/PBE# Pull-up 62ohm

ITPCLKOUT1 Pull-up 56ohm

Pull-up 2.43K ohm

BOOTSELECT CPU determine

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Reference Intel document

Compal Electronics, Inc.

Prescott Processor in uFCPGA478

Place near SB200 (U6)

Place near CPU

for mobile CPU

Note: Please change to 10uH, DC current

51.1 Ohm for Northwood,

2.H_VCCIOPLL,HVCCA,HVSSA trace wide

1.Place cap within 600 mils of

PLL Layout note :

If CPU is P4 , Change the resistor

Close to the ITP

GTL Reference Voltage

2. Place R_A and R_B near CPU.

1. +CPU_GTLREF Trace wide

Close to the CPU