Yamaha RX v459, DSP Ax459, HTR 5935, HTR 5940

AV RECEIVER/AV AMPLIFIER
RX-V459/HTR-5940/DSP-AX459 HTR-5935
SERVICE MANUAL
IMPORTANT NOTICE
This manual has been provided for the use of authorized YAMAHA Retailers and their service personnel. It has been assumed that basic service procedures inherent to the industry, and more specifically YAMAHA Products, are already known and understood by the users, and have therefore not been restated.
WARNING:
Failure to follow appropriate service and safety procedures when servicing this product may result in personal injury, destruction of expensive components, and failure of the product to perform as specified. For these reasons, we advise all YAMAHA product owners that any service required should be performed by an authorized YAMAHA Retailer or the appointed service representative. IMPORTANT: The presentation or sale of this manual to any individual or firm does not constitute authorization, certification or recognition of any applicable technical capabilities, or establish a principle-agent relationship of any form. The data provided is believed to be accurate and applicable to the unit(s) indicated on the cover. The research, engineering, and service departments of YAMAHA are continually striving to improve YAMAHA products. Modifications are, therefore, inevitable and specifications are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please contact the distributor's Service Division.
WARNING:
Static discharges can destroy expensive components. Discharge any static electricity your body may have accumulated by grounding yourself to the ground buss in the unit (heavy gauge black wires connect to this buss). IMPORTANT: Turn the unit OFF during disassembly and part replacement. Recheck all work before you apply power to the unit.
I CONTENTS
TO SERVICE PERSONNEL ...................................... 23 FRONT PANELS ........................................................ 35 REAR PANELS .......................................................... 59 REMOTE CONTROL PANELS .................................... 10 SPECIFICATIONS / ................................ 1112 INTERNAL VIEW ......................................................... 13 DISASSEMBLY PROCEDURES / ......... 1415 SELF DIAGNOSIS FUNCTION (DIAG) / ........................................ 1637 AMP ADJUSTMENT / ........................... 38 DISPLAY DATA ..................................................... 3940 IC DATA ................................................................. 4150 PIN CONNECTION DIAGRAM .............................. 5152 BLOCK DIAGRAMS .............................................. 5355 PRINTED CIRCUIT BOARDS ................................ 5668 SCHEMATIC DIAGRAMS ...................................... 6975 REPLACEMENT PARTS LIST .............................. 7795 REMOTE CONTROL .............................................. 9697 ADVANCED SETUP .................................................... 98 REPLACEMENT PARTS LIST FOR CARBON RESISTORS .... 99
100998
2006 All rights reserved. This manual is copyrighted by YAMAHA and may not be copied or redistributed either in print or electronically without permission.
P.O.Box 1, Hamamatsu, Japan

'06.02
I SELF DIAGNOSIS FUNCTION (DIAG)

This unit has self diagnosis functions that are intended for inspection, measurement and location of faulty point. There are 23 DIAG menu items, each of which has submenu items. Listed in the table below are menu items and sub-menu items. Note that not all menu items listed will apply to the models covered in this service manual. No. 1 2 3 4 MAIN MENU BYPASS RAM THR PRO LOGIC SPEAKERS SET 1. 2. 1. 2. 1. 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. 1. 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 1. 2. 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. 4. 5. 6. 7. 8.
23
No.
MAIN MENU 9. 10. 11. 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 1. 2. 1. 2. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 1. 2. 3. 4. 5. 6. 7. 1. XM Tone / 32k ISO Tone / 32k XM / DT Bus Power : OFF DOCK : OK/NG
SUB MENU
13 16
iPod IF STATUS
XCH-INPUT
6 7
MIC CHECK (Not applied to these models / ) DISPLAY CHECK
SUB MENU ANALOG BYPASS DSP BYPASS RAM MARGIN RAM FULL BIT Pro Logic FRONT : SMALL 0dB CENTER : NONE LFE/B : FRNT Pres Mix : 5ch Front GAIN 1 Front GAIN 2 SURR B Check XCH_INPUT_6 XCH_INPUT_8 LIMIT SET (Not applied to these models / ) MIC CHECK --dB STRAIGHT (Initial display) VFD DISP OFF VFD DISP ALL VFD DIMMER CHECK PATTERN TEST ALL TEST FRNT L TEST CENTER TEST FRNT R TEST SURR R TEST SB R (Not applied to these models / ) TEST SB L TEST SURR L TEST PRES L (Not applied to these models / ) TEST PRES R (Not applied to these models / ) TEST LFE PRESET INHI (memory initialization inhibited) PRESET RSRV (memory initialized) PS1/PS2 DC/TH IMP SW/POWER LIMITER DISP PANEL KEY I2C Read Check DIGITAL THR CVBS DIGITAL THR Y/C ANALOG BYPASS TEST PATTERN LOOP BACK CVBS LOOP BACK Y/C 1k -1dB / 44.1k 1k -61dB / 44.1k Mute / 44.1k XM Tone / 44.1k ISO Tone / 44.1k 1k -1dB / 32k 1k -61dB / 32k Mute / 32k
17 18 19
DSP BUS CHECK SWFR CUT OFF (HTR-5935 model) PROTECTION SETTING (Not applied to these models / )
MANUAL TEST
20
PROTECTION HISTORY
9 10
FACTORY PRESET AD DATA CHECK
21
SOFT SW
11
VIDEO (Not applied to these models / )
22
ROM VER / SUM / PORT
12
XM STATUS (U,C models)
23
TI (DSP) BOOT ( Not applied to these models / )
DSP STATUS (5Byte) DECODE MODE (2Byte) (Not applied to these models / ) DIR INFO (5Byte) (Not applied to these models / ) Pc (2Byte) (Not applied to these models / ) CHS 1 (5Byte) (Not applied to these models / ) CHS 2 (1Byte) (Not applied to these models / ) DEC INFO (5Byte) (Not applied to these models / ) BSI 1 (5Byte) (Not applied to these models / ) BSI 2 (5Byte) (Not applied to these models / ) BSI 3 (5Byte) (Not applied to these models / ) BSI 4 (5Byte) (Not applied to these models / ) BSI 5 (5Byte) (Not applied to these models / ) BSI 6 (5Byte) (Not applied to these models / ) BSI 7 (5Byte) (Not applied to these models / ) BSI 8 (1Byte) (Not applied to these models / ) Mute Trigger (5Byte) (Not applied to these models / ) Digital Info (5Byte) (Not applied to these models / ) TI (DSP) BUS CHECK RDS IC CHECK L CUT OFF H CUT OFF PS L PS H DC L DC H TEMP PL_J_8_L PL_J_8_H PL_U_8_L PL_U_8_H PL_U_N_L PL_U_N_H PL_G_8_L PL_G_8_H PL_G_N_L PL_G_N_H HISTORY 1 HISTORY 2 HISTORY 3 HISTORY 4 SW MODE : PCB/MODEL/FNC MODEL : 759SE-5935 DEST. : J/UC/R/T/K/A/BGE/L TUNER DEST : J/UC/ATKBG/RL TUNER TYPE : NRM/RDS/XM VIDEO FORMAT : NTSC/PAL ZONE2 EXIST : EXIST/NOT AAC EXIST : EXIST/NOT TUNER EXIST : EXIST/NOT ZONE2 AMP EXIST : EXIST/NOT OSD EXIST : EXIST/NOT YPAO EXIST : EXIST/NOT MICROPROCESSOR VERSION SUM ALL / PROGRAM OPE / DSP / XM VERSION PORT TI (DSP) FLASH VERSION TI (DSP) FLASH SUM EEPROM SUM TI (DSP) FLASH BOOT
16
Starting DIAG
Press the STANDBY/ON key while simultaneously pressing those two keys of the main unit as indicated in the figure below.

STANDBY/ON
Keys of main unit /
Turn on the power while pressing these keys.
Starting DIAG in the protection cancel mode

If the protection function works and causes hindrance to trouble diagnosis, cancel the protection function as described below, and it will be possible to enter the DIAG mode. (The protection functions other than the excess current detect function will be disabled.) Press the STANDBY/ON key while simultaneously pressing those two keys indicated in the figure above. At this time, keep pressing those two keys for 3 seconds or longer. In this mode, the SLEEP segment of the FL display of the main unit flashes to indicate that the mode is DIAG mode with the protection functions disabled.

STANDBY/ON 3 FL SLEEP
CAUTION!
Using this product with the protection function disabled may cause damage to itself. Use special care for this point when using this mode.
Canceling DIAG
1 Before canceling DIAG, execute setting for FACTORY PRESET of DIAG menu No.9 (Memory initialization inhibited or Memory initialized). * In order to keep the user memory stored, be sure to select PRESET INHIBITED (Memory initialization inhibited). 2 Turn off the power by pressing the STANDBY/ON key of the main unit.

N o . 9 FACTORY PRESET/ P R E S E T INHIBITED STANDBY/ON
17
Display provided when DIAG started

On the FL display of the main unit, an opening message (including the version and the protection history) appears for a few seconds followed by the diagnostic menu display (1. ANALOG BYPASS).

FL 1 . ANALOG BYPASS
When there is no history of protection function:

Opening message /
When there is no protection history
DIAG menu display /
After a few seconds
NO PROTECT
1.ANALOG BYPAS
Version (1 alphabet)
1
When there is a history of protection function:

The FL display appears as shown below depending on the type of the protection function. The protection function worked due to excessive current through the amplifier. Causes could be a short at the speaker terminal or a defect in the amplifier. The protection function activates immediately to turn off the power, with no history display at turn-on, if the amplifier is defective. The protection function worked due to a defect or overload in the power supply. If the power is turned on with the abnormality unsolved, the protection function works in about 1 second to turn off the power. The protection function worked due to a DC voltage appearing at the speaker terminal. A cause could be a defect in the amplifier. If the power is turned on with the abnormality unsolved, the protection function works in about 3 seconds to turn off the power.
I PROTECT
PS1 PRT:000 A
or
PS2 PRT:000 A
DC PRT:000 A
18
The protection function worked due to the temperature limit being exceeded. Causes could be poor ventilation or a defect related to the thermal sensor. If the power is turned on with the abnormality unsolved, the protection function works in about 1 second to turn off the power.
TMP PRT:000 A
For detection of each protection function (except I-PROTECT) , refer to DIAG MENU No.10 AD DATA.
No. 10 AD DATA
History of protection function

When the protection function has worked, its history is stored in memory with a backup. Even if no abnormality is noted while servicing the unit, an abnormality which has occurred previously can be defined as long as the backup data has been stored. The history of the protection function is cleared when DIAG is cancelled by selecting PRESET RESERVED (Memory initialized) of DIAG menu No.9 or when the backup data is erased.
No.9 PRESET RESERVED
Display during menu operation

During the DIAG operation, the menu list described in the section of the startup screen appears on the monitor screen and the function at work is indicated on the FL indicator. The contents displayed during the function operation are described later in the Details of DIAG menu section.

FL
Operation procedure of DIAG menu and SUB-MENU

There are 23 MENU items, each of which has some SUBMENU items.

No.123
DIAG menu selection

Main unit: Select the menu using (Reverse) keys of PROGRAM. (Forward) and
PROGRAM
SUB-MENU selection
Main unit: Select the sub-menu using (Reverse) keys of PRESET/TUNING. (Forward) and
PRESET/TUNING
Keys of main unit /

DIAG menu selection
SUB-MENU selection
Reverse
Forward
Reverse Forward

Reverse Forward

U, C models
R, T, K, A, G, E, L, J models
19
Functions in DIAG mode

In addition to the DIAG menu items, functions as listed below are available. Input selection Center/Rear/Rear Center/Sub-woofer level adjustment Speaker relay control of A and B Muting Power on/off Master volume * Functions related to the tuner and the set menu are not available. * It is possible to confirm Menu No.16 IF STATUS while keeping the signal process (operation status) of each DIAG menu by using the INPUT MODE key of the main unit.

A/B / INPUT MODE No.16 IF STATUS
Initial settings used to start DIAG

The following settings are used when starting DIAG. When DIAG is canceled, these settings are restored to those before starting DIAG. Master volume: -20 dB Input: DVD (MULTI CH INPUT OFF) Effect level: 0 dB Audio mute: OFF Speaker relay of A and B: ON Speaker setting: LARGE / BASS OUT = SWFR DIAG menu: BYPASS (1. ANALOG BYPASS)

-20 dB DVDMULTI CH INPUT 0 dB A/BON LARGE / BASS OUT = SWFR BYPASS (1. ANALOG BYPASS)
20
Details of DIAG menu

1. BYPASS
Using the sub-menu, it is possible to select analog bypass output or DSP bypass output. ANALOG BYPASS

1. BYPASS
ANALOG BYPASS/DSP BYPASS ANALOG BYPASS
1.ANALOG BYPAS
Reference data INPUT: DVD ANALOG SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume SPEAKERS OUT FRONT L/R +13.0 dBm CENTER - SURROUND L/R SURROUND BACK L/R - -
DSP BYPASS
SUBWOOFER OUTPUT -
Both ch, -20 dBm +6.0 dB DSP BYPASS
1.DSP BYPASS
Reference data INPUT: DVD ANALOG SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume SPEAKERS OUT FRONT L/R +13.5 dBm CENTER - SURROUND L/R SURROUND BACK L/R - - SUBWOOFER OUTPUT -
Both ch, -20 dBm +6.0 dB ANALOG BYPASS
XMDT
(J) FL / FR (J)
DIR
LC89057
DSP
(DECODE) (POST PROCESSING)
C / SW TI D70Y SL / SR
(U, C, R, T, K, A, G, E, L)
A/D
PCM1803
SBL / SBR
DRAM
ROM
(Shaded items not used in this example)
DSP BYPASS
XMDT
(J) FL / FR (J)
DIR
LC89057
DSP
(U, C, R, T, K, A, G, E, L)
A/D
PCM1803
SBL / SBR
DRAM
ROM
21
2. RAM THROUGH
Using the sub-menu, it is possible to select margin output or full-bit output. RAM MARGIN Following head margin is reserved. FRONT +15.0 dB CENTER +13.5 dB
2. RAM THROUGH
MARGIN/Full Bit
RAM MARGIN
SURROUND +9.0 dB
SURROUND BACK +7.5 dB
SUBWOOFER +21.0 dB
2.RAM MARGIN
Reference data INPUT: DVD ANALOG SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume SPEAKERS OUT FRONT L/R +13.5 dBm CENTER +13.5 dBm SURROUND L/R SURROUND BACK L/R +13.5 dBm +13.5 dBm
RAM FULL BIT SW
SUBWOOFER OUTPUT +2.0 dBm
Both ch, -20 dBm +6.0 dB
RAM FULL BIT No head margin is reserved except SW. FRONT 0 dB CENTER 0 dB
SURROUND 0 dB
SURROUND BACK 0 dB
SUBWOOFER +21 dB
2.RAM FULL BIT

Reference data INPUT: DVD ANALOG SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume SPEAKERS OUT FRONT L/R +13.5 dBm CENTER +13.5 dBm
XMDT
SUBWOOFER OUTPUT +2.0 dBm
SURROUND L/R SURROUND BACK L/R +13.5 dBm +13.5 dBm
(J) FL / FR (J)
DIR
LC89057
DSP
(U, C, R, T, K, A, G, E, L)
A/D
PCM1803
SBL / SBR
DRAM
ROM
(Shaded items not used in this example) When input source is stereo, signal is assigned as below.
2ch
Front L Center / Surround L / Surround Back L, R Front R Surround R Front L +10 dB SWFR
22
3. PRO LOGIC
Dolby PRO LOGIC is applied to input stereo source.
3. PRO LOGIC
2chDolby PRO LOGIC
3.PRO LOGIC
Reference data INPUT: DVD ANALOG SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume FRONT L/R +13.5 dBm -20.0 dBm SPEAKERS OUT SUBWOOFER CENTER SURROUND L/R SURROUND BACK L/R OUTPUT - +16.5 dBm
XMDT
(J) FL / FR (J)
Each ch, -20 dBm +6.0 dB Both ch, -20 dBm +6.0 dB
- -
- -
- -
DIR
LC89057
DSP
(U, C, R, T, K, A, G, E, L)
A/D
PCM1803
SBL / SBR
DRAM
ROM
4. SPEAKERS SET
The analog switch settings for each sub-menu are as shown in the table below. Sub-menu 1 FRNT: SML 0 dB 2 CENTER: NONE 3 LFE/B: FRNT 4 Pre Mix: 5ch 5 Front GAIN 1 6 Front GAIN 2 7 SURR B Check LARGE: FRONT L/R SMALL LARGE LARGE CENTER LARGE NONE SMALL
4. SPEAKERS SET

SUR. L/R LARGE LARGE SMALL
SUR.B L/R LARGE LARGE SMALL
LFE/BASS SWFR SWFR FRONT

This mode is used with a speaker with high bass reproduction performance (a large unit). Full bandwidth signals are output. SMALL: This mode is used with a speaker with low bass reproduction performance (a small unit). The signals of 80 Hz or less are mixed into the channel specified by LFE/BASS. NONE: This mode is used with no center speaker. The center content is reduced by 3 dB and distributed to FRONT L/R. SWFR: LFE of 5.1ch signal or LFE/BASS lower than 90Hz is output through SUBWOOFER OUT. FRONT: LFE of 5.1ch signal or LFE/BASS lower than 90Hz is distributed to FRONT L/R.
LARGE SMALL 80 HzLFE/ B A S S NONE -3 dBFRONT L/R SWFR 5.1chLFE90HzLFE/BASS SUBWOOFER OUT FRONT 5.1chLFE90HzLFE/BASS FRONT L/R
23
4.FRNT:SML 0dB
4.CENTER:NONE
4.LFE/B:FRNT
4.Pres Mix:5ch
4.Front GAIN 1
4.Front GAIN 2
4.SURR B check
Reference data INPUT: DVD ANALOG (Both ch) SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Sub-menu 1 FRONT: SML 0dB 2 CENTER: NONE 3
Input level Both ch, -20 dBm Both ch, -20 dBm Both ch, -20 dBm Both ch, -20 dBm Both ch, -20 dBm Both ch, -20 dBm Both ch, -20 dBm Both ch, -20 dBm
Volume
SPEAKER OUT SUBWOOFER FRONT L/R CENTER SURROUND L/R SURROUND BACK L/R OUTPUT +5.5 dBm +2.0 dBm - - -0.5 dBm +2.0 dBm +2.0 dBm -
+6.0 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +6.0 dB +10.5 dBm - +13.5 dBm +13.5 dBm +6.0 dB - +13.5 dBm +13.5 dBm +13.5 dBm +6.0 dB +20.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +6.0 dB - +13.5 dBm +18.5 dBm - +6.0 dB +20.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +6.0 dB +20.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +6.0 dB - - - +13.5 dBm
LFE/B: FRNT (1 kHz) LFE/B: FRNT (50 Hz)
4 Pres Mix: 5ch 5 Front Gain 1 6 Front Gain 2 7 SURR B check
24
5. XCH INPUT
The signal input through the multi ch input is output. The speaker impedance can be selected. XCH INPUT_6 (ohms)
5. XCH INPUT
CH 68 XCH INPUT_6 ohms
5.XCH INPUT_6
Reference data INPUT: MULTI CH INPUT SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume FRONT L/R +13.5 dBm SPEAKERS OUT SUBWOOFER CENTER SURROUND L/R SURROUND BACK L/R OUTPUT +13.5 dBm +13.5 dBm - -10.0 dBm
XCH INPUT_8 (ohms)
XCH INPUT_8 ohms
5.XCH INPUT_8
Reference data INPUT: MULTI CH INPUT SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz Input level Volume SPEAKERS OUT FRONT L/R +13.5 dBm CENTER +13.5 dBm SURROUND L/R SURROUND BACK L/R +13.5 dBm - SUBWOOFER OUTPUT -10.0 dBm
LIMIT SET Not applied to these models.
LIMIT SET
XXXXXXXXXXXX__
6. MIC CHECK
Not applied to these models.
6. MIC CHECK
6.MIC CHK --dB
25
7. DISPLAY CHECK
This program is used to check the FL display section. The display condition varies as shown below according to the sub-menu operation. The signal route is STRAIGHT.
7. DISPLAY CHECK
FL STRAIGHT
Checking FL display section / FL

Blinking /
Initial display /
All segments OFF /
All segments ON (dimmer 100%) / 100%
All segments ON (dimmer 50%) / 50%

Lighting of segments in lattice / Lighting in lattice /
Short /
Normal /
Segment conditions of the FL driver and the FL tube are checked by turning ON and OFF all segments. Next, the operation of the FL driver is checked by using the dimmer control. Then a short between segments next to each other is checked by turning ON and OFF all segments alternately (in lattice). (In the above example, the segments in the second row from the top are shorted.) 26
FLFL FL / 2
8. MANUAL TEST
The test noise based THX is output to the channel specified by the sub-menu from the DSP. The noise frequency for LFE is 35 to 250 Hz. Other than that, the center frequency is 800 Hz.
8. MANUAL TEST
DSPTHX LFE35250 Hz 800 Hz
8.TEST ALL
8.TEST FRNT L
8.TEST CENTER
8.TEST FRNT R
8.TEST SURR R
8.TEST SB R
8.TEST SB L
8.TEST SURR L
8.TEST PRES L
8.TEST PRES R
8.TEST LFE
9. FACTORY PRESET
This menu is used to reserve/inhibit initialization of the backup RAM (Parameters and set menu contents, etc. of the sound field program).
9. FACTORY PRESET
RAM /
9.PRESET INHI
PRESET INHIBIT (Initialization inhibited) / PRESET INHIBIT RAM initialization is not executed. Select this sub-menu to protect the values set by the user.
Note: The protection history will not be erased using PRESET INHIBIT. RAM
9.PRESET RSRV
PRESET RESERVED (Initialization reserved) / PRESET RESERVED Initialization of the back-up RAM is reserved. (Actually, initialization is executed the next time that the power is turned on.) Select this sub-menu to reset to the original factory settings or to reset the RAM. Use PRESET RESERVED to erase the protection history.
RAM RAM
CAUTION: Before setting to the PRESET RESERVED, write down the existing preset memory. Content of the Tuner in a table as shown below. (This is because setting to the PRESET RESERVED will cause ALL user memory contents to be erased.)
Preset group A B C D E P1 P2 P3
PRESET RESERVED
P4
P5
P6
P7
P8
27
PRESET STATIONS /
STATION PAGE NO. 1 2 3 4 5 6 7 8 FM FACTORY PRESET DATA (MHz) U, C 87.5 90.1 95.1 98.1 107.9 88.1 106.1 107.9 R, T, K, A, G, E, L 87.50 90.10 95.10 98.10 108.00 88.10 106.10 108.00 J 76.0 83.0 84.0 86.0 90.0 78.0 88.0 82.1 STATION PAGE NO. 1 2 3 4 5 6 7 8 AM FACTORY PRESET DATA (kHz) U, C, R, T, K 630 1080 1440 530 1710 900 1350 1400 A, G, E, L 630 1080 1440 531 1611 900 1350 1404 J 630 1080 1440 531 1611 900 1350 1404
A/C/E
B/D
10. AD DATA CHECK

This menu is used to display the A/D conversion value of the Microprocessor which detects panel keys of the main unit and protection functions in using the sub-menu. During audio signal processing, the condition before execution is maintained. When K0/K1 menu is selected, keys become non-operable due to detection of the values of all keys. However, it is possible to advance to the next sub-menu by turning the VOLUME of the main unit. When using this function, note that turning the VOLUME more than 1 click would cause the volume value to change. * The figures in the diagram are given as reference only. PS1/PS2 (Power supply voltage protection detection) Power supply voltage protection value (Normal value: PS1: 17 to 66, PS2: 25 to 46) PS1: Detects +5S and +5.3X (U, C models). PS2: Detects 12V, 5V, +5D, +3.3D and +5i. * If PS is out of the normal value range, the protection function works to turn off the power. (Reference voltage: 5 V=100 %)
10. AD DATA CHECK

MicroprocessorA/D K0/K1 VOLUME 1
PS1/PS2 PS1: 1766PS2: 2546 PS1+5S PS212V5V+5D+3.3D+5i PS 5V=100%
PS1:039 2:044
DC/TH (protection detection/temperature detection) DC: DC detect protection value (Normal value: 5 to 36) * If DC is out of the normal value range, the protection function works to turn off the power. (Reference voltage: 5 V=100 %) TH: Detects the temperatur of the heat sink. Temperature detected value (Normal value: 9 to 177) U, C, T, K, A, G, E, J models (Normal value: 9 to 167) R, L models (Reference voltage: 5 V=255)
DC/TH/ DC DC 536 DC 5V=100% TH : 9177 5V=255
DC:007 TH098
28
IMP SW/POWER LIMIT (impedance/power limiter detection) IMP: Not applied to these models. PL: Power limiter detection value The voltage value of pin No. 92 of IC451 is displayed, using 5V/256 as standard. The port (No. 3) output is controlled by using the input voltage value of pin No. 92 of IC451.
IMP SW/POWER LIMIT / IMP PL IC451 925V/256 IC451 92 3
IMP:8 PL:245
PANEL KEY (K0/K1) (Panel key of main unit) [Remote control code: ] A/D of the key fails to function properly when the standard value is deviated by 8. In this case, check the constant of partial pressure resistor, solder condition, etc. Refer to table. (Reference voltage: 5 V=100 %)
PANEL KEY (K0/K1) A/D8 5V=100%
K0:100 K1:100
Display (%) 0-6 7 - 13 14 - 21 22 - 31 32 - 41 42 - 53 54 - 63 64 - 72 73 - 80 81 - 88 89 - 95 96 - 100
K0 PROGRAM PROGRAM BASS/TREBLE BASS/TREBLE + INPUT MODE STRAIGHT TONE CONTROL PRESET/TUNING SPEAKERS B SPEAKERS A KEY OFF
K1 MULTI CH INPUT FM/AM A/B/C/D/E PRESET PRESET MEMORY TUNING MODE
KEY OFF
29
11. VIDEO
11. VIDEO
12. XM STATUS (U, C models)

Perform the output check of XM Radio Antenna connected to the XM terminal. 1k -1dB/44.1k The test tone (1kHz, -1dB/44.1kHz) is output.
12. XM STATUS UC models

XMXM Radio Antenna 1k -1dB/44.1k 1kHz-1dB/44.1kHz
1k - 1dB/44
1k -61dB/44.1k The test tone (1kHz, -61dB/44.1kHz) is output.
1k -61dB/44.1k 1kHz-61dB/44.1kHz
1k -61dB/44
Mute /44.1k Nothing is output.
Mute /44.1k
Mute
/44
XM Tone/44.1k The XM tone (44.1kHz) is output.
XM Tone/44.1k XM 44.1kHz
XM
Tone/44
ISO Tone/44.1k The ISO tone (44.1kHz) is output.
ISO Tone/44.1k ISO 44.1kHz
ISO Tone/44
1k -1dB/32k The test tone (1kHz, -1dB/32kHz) is output.
1k -1dB/32k 1kHz-1dB/32kHz
1k - 1dB/32
1k -61dB/32k The test tone (1kHz, -61dB/32kHz) is output.
1k -61dB/32k 1kHz-61dB/32kHz
1k -61dB/32
30
Mute /32k Nothing is output.
Mute /32k
Mute
/32
XM Tone/32k The XM tone (32kHz) is output.
XM Tone/32k XM 32kHz
XM
Tone/32
ISO Tone/32k The ISO tone (32kHz) is output.
ISO Tone/32k ISO 32kHz
ISO Tone/32
XM/DT Bus Power: OFF The power of XM module is turned off.
XM/DT Bus Power: OFF XMOFF
Bus Power:OFF
13. iPod
13. iPod
13.DOCK:NG NNN
31
16. IF STATUS (Input function status)

Using the sub-menu, the status data is displayed one after another in the hexadecimal notation. During signal processing, the status before execution of this menu is maintained. * Numeric values in the figure example are for reference. DST: DSP status
16. IF STATUS
16
DSTDSP
DST:3300020000
5th byte 4th byte 3rd byte 2nd byte 1st byte
<1st byte> Digital input/output setting value Upper 4 bits: REC OUT selected / lower 4 bits: INPUT selected
Value 0 1 2 3 4 8 9 Choice
1 4 bit REC OUT / 4 bit INPUT

Preset name MD/CD-R DVD DTV/CBL CD
NONE OPT FRONT OPT 1 OPT 2 OPT 3 COAX 1 COAX 2
DSP-AX459 model
RX-V459/HTR-5940/HTR-5935 models
<2nd byte> / 2 Fs information of reproduction signal /

Fs
<3rd byte> / 3 Audio code mode information of reproduction signal /
Display 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Audio code 1+1 1/0 2/0 3/0 2/1 3/1 2/2 3/2 2/3 3/3 3/4 over 6.1 Milti-Mono Milti-PCE Unknown Undefined
<4th byte> / 4 Format information of reproduction signal /
Display 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
Fs (kHz) Analog 32 kHz 44.1 kHz 48 kHz 64 kHz 88.2 kHz 96 kHz 128 kHz 176.4 kHz 192 kHz Unknown NRM Unknown DBL Unknown QUAD Unknown Undefined
Display Signal format 00 Analog 01 Err 10 PCM Audio 20 Digital Data 21 IEC1937 22 None PCM 23 Unknown 50 dts 51 dts-CD 52 dts 96/24 54 dts-ES (Matrix) 58 dts-ES (Discrete) 5C dts-ES (Both) 60 AAC C0 Dolby Digital C1 Dolby Digital Karaoke C4 Dolby Digital EX FF Undefined
32
<5th byte> / 5 Signal processing status information /
bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Fs (kHz) Digital mute 6.1 (7.1) processing Analog mute PCM through dts analog mute
DMD: Decoder mode information Not applied to these models.
DMD
DMD:03C00000
DIF: DIR information Not applied to these models.
DIFDIR
DIF:0001000600
PC: Preamble C information Not applied to these models.
PCPreamble C
PC :0000
CS1, 2: Channel status information Not applied to these models.
CS12
CS1:0000000000
CS2:00
DEI: Decoder information Not applied to these models.
DEI
DEI:0808000600
BS1-8: Bit stream information Not applied to these models.
BS1-8
BS1:0000000000
BS8:00
MTT: Mute Trigger Not applied to these models.
MTTMute Trigger
MTT:0018001820
33
DGI: Digital information Not applied to these models.
DGIDIGITAL
DGI:EE6464F95E
17. DSP BUS CHECK

This menu is used to self-diagnose whether or not the bus connection for the TI (DA70Y) and the external ROM/RAM is made properly. When no error is detected, "NoEr" appears on display.
17. DSP BUS CHECK

TI DA70Y ROM/RAM NoEr
TI
BUS:NoEr
or
No error detected.
TI
BUS:Boot
When this indication is displayed with in seconds or displayed alternately NoEr and Boot, it is highly possible that there are errors.
NoEr
RDS
IC:OK
or No applied to these models.
RDS
IC:NG
18. SWFR CUT OFF (HTR-5935 model)

The cut off frequency setting of LFE.
18. SWFR CUT OFF HTR-5935 model

LFE STRAIGHT40 Hz200 Hz 10 Hz STRAIGHT40 Hz200 Hz 10 Hz
Low-pass filter setting. It can be selected 40 Hz to 200 Hz every 10 Hz by the STRAIGHT key. High-pass filter setting. It can be selected 40 Hz to 200 Hz every 10 Hz and through by the STRAIGHT key.
18.LFE LPF 200
18.LFE HPF THR
19. PROTECTION SETTING

19. PROTECTION SETTING
PS_Lo:
0043
PL_6_N_H:0154
20. PROTECTION HISTORY

Four protection histories are display.
20. PROTECTION HISTORY

4
20-1:NoPRT
20-4:NoPRT
34
21. SOFT SW
Note) Changing the function setting may hinder the proper operation. This menu is used to switch the function settings on P.C.B. through the software so as to activate the product. The protection function follows the P.C.B. settings. When connected to AC or in the maker preset state, the unit is initialized to the P.C. B. setting. Display of each function after initialization varies depending on settings on P.C.B. The operation mode can be changed by selecting the submenu and then using the STRAIGHT key.
21. SOFT SW
P.C.B. P.C.B.AC P.C.B. P.C.B. STRAIGHT
SW MODE: PCB, MODEL or FNC can be selected.
SW MODEPCBMODELFNC
21.SW
:PCB
MODEL SETTING: 759SE, V659, H5960, V559, H5950, V459 or H5935 can be selected. (SW MODE: Selectable when MODEL has been selected.)
MODEL SETTING759SEV659H5960V559 H5950V459H5935 SW MODEMODEL
21.MODEL:V459
DESTINATION: J, U, C, R, T, K, A, B, G (E) or L can be selected. (SW MODE: Selectable when MODEL has been selected.)
DESTINATIONJUCRTKABG E L SW MODEMODEL
21.DEST :G
TUNER DESTINATION: J, UC, ABG or RL can be selected. (SW MODE: Selectable when FNC has been selected.)
TUNER DESTINATIONJUCABGRL SW MODEFNC
21.TuDst:ABG
TUNER TYPE: NRM, RDS or XM can be selected. (SW MODE: Selectable when FNC has been selected.)
TUNER TYPENRMRDSXM SW MODEFNC
21.TuDyp:RDS
VIDEO FORMAT: NTSC or PAL can be selected. (SW MODE: Selectable when FNC has been selected.)
VIDEO FORMATNTSCPAL SW MODEFNC
21.VIDEO:PAL
35
ZONE2: NOT or EXIST can be selected. (SW MODE: Selectable when FNC has been selected.)
ZONE2NOTEXIST SW MODE FNC
21.ZONE2:EXIST
AAC: NOT or EXIST can be selected. (SW MODE: Selectable when FNC has been selected.)
AACNOTEXIST SW MODEFNC
21.AAC
:NOT
TUNER: NOT or EXIST can be selected. (SW MODE: Selectable when FNC has been selected.)
TUNERNOTEXIST SW MODE FNC
21.TUNER:EXIST
ZONE2 AMP: NOT or EXIST can be selected. (SW MODE: Selectable when FNC has been selected.)
ZONE2 AMPNOTEXIST SW MODEFNC
21.Z2Amp:NOT
OSD: NOT or EXIST can be selected. (SW MODE: Selectable when FNC has been selected.)
OSDNOTEXIST SW MODEFNC
21.OSD
:EXIST
YPAO: NOT or EXIST can be selected. (SW MODE: Selectable when FNC has been selected.)
YPAONOTEXIST SW MODE FNC
21.YPAO :NOT
36
22. SOFTWARE VERSION

The version, checksum and the port specified by the microprocessor are displayed. The signal is processed using EFFECT OFF. The checksum is obtained by adding the data at every 16 bits for each program area and expressing the result as a 4-figure hexadecimal data. * Numeric values in the figure example are for reference.
22. SOFTWARE VERSION

OFF 16416
VER. AOO8
Software version of microprocessor /
CHECK SUM:1F4A
Checksum value of microprocessor /
0:18 D:23 X:A9
Software modules version of microprocessor /
O: Operation
D: DSP
X: XM
PORT:00000100
The condition of ports for model detection /
TI VER.10
Software version of TI (DSP) / TI DSP
TiSUM:41A234F5
Checksum value of TI (DSP) / TI DSP
EE SUM:0000
Checksum value of EEPROM / EEPROM (Not applied to these models. / )
PORT:00000100
Model type 0 Model type 1 Model type 2 Model type 3
Type3 Type2 1 1 Type1 1 1 Type0 1 0 Model RX-V459 DSP-AX459 HTR-5940 HTR-5935
23. TI (DSP) BOOT

The rewriting mode of TI (DSP) software. (Not applied to these models.)
23. TI DSP BOOT

TI DSP
23.TI BOOT ?
37
I AMP ADJUSTMENT /
Confirmation of Idling Current of MAIN (1) P. C. B.
Right after power is turned on, confirm that each measured voltage across the terminals of R1149 (FRONT Lch), R1150 (FRONT Rch), R1153 (CENTER), R1154 (SURROUND Lch), R1152 (SURROUND Rch), R1151 (SURROUND BACK) is between 0.1 mV and 10.0 mV. If it exceeds 10.0 mV, open (cutoff) R1104 (FRONT Lch), R1106 (FRONT Rch), R1112 (CENTER), R1114 (SURROUND Lch), R1110 (SURROUND Rch), R1108 (SURROUND BACK) and reconfirm the voltage. Attention If the measured voltage exceeds 10.0 mV. after an amplifier repair, first check for a defective component before cutting the bias resistor. Confirm that the voltage is 0.2 mV-15.0 mV. after 60 minutes.
1
R1149 FRONT Lch R1150 FRONT Rch R1153 CENTER R1154 SURROUND Lch R1152 SURROUND Rch R1151 SURROUND BACK 0.1 mV10.0 mV. 10 mVR1104 FRONT Lch R1106 FRONT Rch R1112 CENTER R1114 SURROUND Lch R1110 SURROUND Rch R1108 SURROUND BACK 10.0 mV. 600.2 mV15.0 mV.
0.1mV ~ 10.0mV (DC)
0.1mV ~ 10.0mV (DC)
R1149 (FRONT Lch) R1150 (FRONT Rch) R1153 (CENTER)
R1154 (SURROUND Lch) R1152 (SURROUND Rch) R1151 (SURROUND BACK Rch)
Cut off R1104 (FRONT Lch) R1106 (FRONT Rch) R1112 (CENTER) R1114 (SURROUND Lch) R1110 (SURROUND Rch) R1108 (SURROUND BACK Rch)
38
RX-V459/HTR-5940/DSP-AX459
I DISPLAY DATA
G V3000 : HNA-17MM03T (WG474000)
G ANODE CONNECTION
1
P1 P2
17G
16G S1
15G S1 W1 W2 4g 1a 1b 1c 1d 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 3g 3b 3a
14G 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5
13G~1G 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 3-6 4-6 5-6 1-7 2-7 3-7 4-7 5-7
PATTERN AREA
P3 P4 P5 P6
G PIN CONNECTION Pin No. 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
Connection F2 F2 NP NP P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 Pin No. 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Connection P32 P33 P34 P35 P36 P37 NX NX NX NX NX NX NX 17G 16G 15G 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP F1 F1
Note : 1) Fn ..... Filament pin 2) nG ..... Grid pin 3) Pn ..... Anode pin 4) NP ..... No pin 5) NX ..... No extended pin
G GRID ASSIGNMENT
17G 16G 15G
P17 P18 P19 P20 P21 P22

1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G 13G 14G
P23 P24 P25 P26
R1 R2 R3 R4 R5
3-5 4-5 5-5 1-6 2-6 3-6 4-6
1-1 1-2 1-3 1-4 1-5 1-6 1-7
2-1 3-1 4-1 5-1 2-2 3-2 4-2 5-2 2-3 3-3 4-3 5-3 2-4 3-4 4-4 5-4
W1
P27 P28
S1
P29 P30
5-6 1-7 2-7 3-7 4-7 5-7
(16G)
2-5 3-5 4-5 5-5 2-6 3-6 4-6 5-6 2-7 3-7 4-7 5-7
P31 P32
R1
W2
R2
P33
R5
1a
(1G~14G)
2a
S1
R4 R3
P34 P35 P36 P37
4g
1f
1g
1b
3a 3b
3b 3g 3a
(17G)
1e 1d
1c
(15G)
39
HTR-5935
I DISPLAY DATA
G V3000 : 17-BT-26GNK (WG473900) G ANODE CONNECTION
1
1P 2P
1G~13G 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 3-6 4-6 5-6 1-7 2-7 3-7 4-7 5-7
14G 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 3-6 4-6 5-6 1-7 2-7 3-7 4-7 5-7
15G S2 S26 S27 S22 1a 1b 1c 1d 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g S23 S24 S25
16G S1 S6 S7 S8 S9 S10 S11 S12
17G
PATTERN AREA
3P 4P 5P 6P
G PIN CONNECTION Pin No. 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
7P 8P 9P 10P 11P 12P 13P 14P 15P 16P
Connection F2 NX NP NP P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 Pin No. 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
S20
Connection P32 P33 P34 P35 P36 P37 NX NX NX NX NX NX NX 17G 16G 15G 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP NX F1
Note : 1) F1, F2 ..... Filament pin 2) NP ..... No pin 3) NX ..... No extend pin 4) 1G~17G ..... Grid pin
G GRID ASSIGNMENT
17G 16G 15G
17P 18P 19P 20P 21P 22P

1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G 13G 14G
S21
S3 S5 S4 S15
23P 24P
S13 S14
S16 S17 S18 S19
1-1 1-2 1-3 1-4 1-5 1-6 1-7
2-1 3-1 4-1 5-1
S1
2-2 3-2 4-2 5-2 2-3 3-3 4-3 5-3 2-4 3-4 4-4 5-4 2-5 3-5 4-5 5-5 2-6 3-6 4-6 5-6
25P 26P
S6
S7
S8
S9
S10
S11
S12
S13
S14
27P 28P 29P
(16G)
(15G)
30P 31P
2-7 3-7 4-7 5-7
(1G~14G)
S16 S18
S15
1g
2f 1b 1a
S2
2b 2a
s25 s24 s23 s24 s25
32P 33P 34P 35P 36P
S19 S17 S20 S21
S22
1f 1e 1d
2g
(17G)
2d 1c 2e 2c
37P
S26 S27
40
I IC DATA
IC2 : M30625MHP-A98GP (DSP P.C.B.) Microprocessor
P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7/AN7_KI3 P10_6/AN6_KI2 P10_5/AN5_KI1 P10_4/AN4_KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
M16C/62P Group (M16C/62P)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
P12_5 P12_6 P12_7 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P13_0 P13_1 P13_2 P13_3 P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P13_4 P13_5 P13_6 P13_7 P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 VSS
NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2.
VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/OUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 P14_1 P14_0 BYTE CNVSS P8_7_XCIN P8_6_XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN(1) P7_0/TXD2/SDA2/TA0OUT(1) P6_7/TXD1/SDA1 VCC1 P6_6/RXD1/SCL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
<VCC2 ports> (4) Internal peripheral functions Timer (16 bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit D/A converter (10 bit x 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (8 bit x 8 channels) Watchdog timer (Polynomial: X16+X12+X5+1)
<VCC1 ports> (4) Watchdog timer (15 bits)
Port P8
XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Clock synchronous serial I/O (8 bit x 2 channels) Memory ROM (1) RAM (2)
<VCC1 ports> (4)
Port P8_5
M16C/60 series 16-bit CPU core Watchdog timer (15 bits) DMAC (2 channels) D/A converter (8 bit x 2 channels) <VCC1 ports> (4) Port P11 (3) 8 Port P14 (3) 2
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Port P9 Port P10
Multiplier <VCC2 ports> (4) Port P12 (3) 8 Port P13 (3) 8
NOTES: 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. Ports P11 to P14 exist only in 128-pin version. 4. Use M16C/62PT on VCC1=VCC2.
41
IC2
: M30625MHP-A98GP (DSP P.C.B.) Microprocessor

Port Name Terminal Name I/O PowerOn Pure Direct Standby MCU MCU MCU MCU O O I SO O SO O DA O O O SO O SI O SO O O O O O O MCU MCU MCU MCU O O I O MCU MCU MCU MCU MCU MCU MCU MCU MCU MCU MCU MCU IRQ O IRQ O IRQ O O O O O O O O O O O O I O O O O O SI O SO O I SO I SO MCU MCU I SO I SO MCU MCU O O SO O SO O SO O SI O SI O I O I O O O O O O O O O O O O O Function AD reference AD power supply FL Driver CE MODEL distinction 0 FL Driver TxD FL Driver CLOCK Limiter control output XM/DT BUS POWER CONTROL (U model) Serial data output to DIR, TI (DA70Y), DAC / DIR: 4M, LSBF/TI: 1M, MSBF Serial data input from DIR, TI (DA70Y) Serial clock output to DIR, TI (DA70Y) DAC Reset I2C device of CONV Reset signal to Net-module Vss : When single chip mode is used Vss : When single chip mode is used, Vcc : When flash writing is used MUTE of TI decoder DSP DA70Y (HI=MUTE) TI BUSY detection / CDDA writing DATA input Reset Oscillation output Ground for microprocessor Oscillation input Power supply +5V for microprocessor No used, connect Vss Interrupt of TI decoder DSP DA70Y Interrupt of DIR Chip enable of DIR Chip enable of TI decoder DSP DA70Y Chip enable of DAC (2ch/8ch common) DIR reset Reset of TI decoder DSP DA70Y TI DA601 Serial Ready / WCK input for CDDA writing EEPROM CE Control of flash writing XMDT IC RxDU (U model) XMDT IC TxDU Data transmission terminal of AF220 Power supply +5V for microprocessor Flash ROM RxD Ground for microprocessor Clock transmission terminal signal output for AF220 BUSY signal output for AF220 serial data output for iPod Serial data input for iPod iPod detection IPod accessories power detection YST amp control (HTR-5935 model) IMPEDANCE control / B voltage control SURROUND BACK SP relay output CENTER and SURROUND SP relay output FRONT B SP relay output
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Vref Vref Avcc Avcc P97/Adtrg/Sin4 CEFD MOD0 P96/ANEX1/SOUT4 DTFD P95/ANEX0/CLK4 CKFD P94/DA1/TB4in LC P93/DA0/TB3in XMPWR P92/TB2in/SOUT3 SDM P91/TB1in/SIN3 SDD P90/TB0in/CLK3 SCK /ICCNV P141 P140 NW_RST BYTE BYTE CNVss CNVss P87/Xcin MUTETI P86/Xcout /TIBUSY /RESET /RES Xout Xout Vss Vss Xin Xin Vcc1 Vcc P85/NMI NMI P84/INT2 /INTTI P83/INT1 /INTDIR P82/INT0 /VSY P81/TA4in/U /CSDIR P80/TA4out/U /CSTI P77/TA3in /CSDAC P76/TA3out /ICDIR P75/TA2in/W /ICTI P74/TA2out/W /SPIRDY P73/CTS2/RTS2/TA1in/V /CEEEP P72/CLK2/TA1out/V FET P71/RXD2/SCL2/TA0in/TB5in DRXM P70/TXD2/SDA2/TA0out DTXM P67/TXD1/SDA1 SDA TXDF Vcc1 Vcc P66/RXD1/SCL1 SCL RXDF Vss Vss P65/CLK1 N.C. CLKF P64/CTS1/RTS1/CTS0/CLKS1 BSY P63/TXD0/SDA0 TXDi TXDNW P62/RXD0/SCL0 RXDi RXDNW P61/CLK0 iPDET P60/CTS0/RTS0 iPAP P137 Z2RY YST P136 /4ohm P135 SBRY P134 SPC P57/RDY/CLKout SPB
Sleep MCU MCU O O O O O O O O O O MCU MCU O O MCU MCU MCU MCU MCU MCU O O O O O O O O O O O O O I MCU I MCU O
O O O O O O O O O O O O
42
IC2

Port Name P56/ALE P55/HOLD P54/HLDA P133 P132 P131 P130 P53/BCLK P52/RD P51/WRH/BHE P50/WRL/WR P127 P126 P125 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/A19 P42/A18 P41/A17 P40/A16 P37/A15 P36/A14 P35/A13 P34/A12 P33/A11 P32/A10 P31/A9 P124 P123 P122 P121 P120 Vcc2 P30/A8 Terminal Name SPA /EMP PRI PSV PRY MASTER /BLK ISA ISB TONEA /CE TONEB VRA VRB VIA VIB VIC S/V /CES MOD1 SVIDD BYPASS /INTCNV /VR1 /VR2 /PURD /MON CPNTD CMP0 CMP1 CBYPASS /CNONE TRIG TMT SDRN Vcc SCKN Vss SDTN RDSE /ICXM SCKP SDTP CEP SDRP /ST TUNED PDET /PSW REM /HP /MTHP /MTFS /MTCT /MTSW /MTZ2 CKEV I/O PowerOn Pure Direct Standby O O I I O O O O O I O O O I O I O I O I I O I O I O O O O O O O O O O O O O O O O I I O O O O O I O O O O O O O O O O O O O I O O O O O O O O O O O O O O O O O O I O MCU MCU O O O O O MCU MCU O O O O O O O O O O O O O O O I+ O I+ O I+ O IRQ IRQ IRQ IRQ IRQ IRQ I O O O O O O O O O O O O O Function FRONT A SP relay output For FLASH writing (LO) Protection overcurrent detection Power Save Power relay output MASTER ON/OFF FL Driver turning off INPUT Selector Rotary A INPUT Selector Rotary B Tone Control Rotary A For FLASH writing (HI) Tone Control Rotary B Volume Rotary A Volume Rotary B VIDEO Selector A VIDEO Selector B VIDEO Selector C OSD Enable MODEL distinction 1 S-Video Signal Detector VIDEO Bypass/ conversion change VIDEO Rec Out 1 MUTE
No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Sleep O O O O O O O O O O O O O O O O O O O O O O I O O O O O O O O O MCU O O MCU O O O O O O O O O O O O O O O O O O O O
VIDEO Mon Out MUTE Component Signal Detector (DVD) Component Selector 0 Component Selector 1 Component Mon Out MUTE DC TRIGGER input TUNER MUTE RDS RxDBG Power supply +5V for microprocessor RDS IC Clock (G model) Ground for micro-processor RDS IC TxD (G model) RDS Enable (G model) DABIC IC reset (U model) PLL IC Clock PLL IC TxD PLL IC Enable PLL IC RxD TUNER /ST TUNED Power Down DETECT INT Interrupt MASTER / MAIN / Zone2 Power SW Remote Control input HEAD PHONE detection HEAD PHONE MUTE input MUTE Front/Surround, PreOUT MUTE Center MUTE SW Zone 2 MUTER Electron volume IC Clock
87 Vss 88 P27/A7 89 P26/A6 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 P25/A5 P24/A4 P23/A3 P22/A2 P21/A1 P20/A0 P17/D15/INT5 P16/D14/INT4 P15/D13/INT3 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6
43
IC2

Port Name P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P117 P116 P115 Terminal Name DTEV CKZ2 DTZ2 N.C. N.C. CKEX DTEX CKBD DTBD MOD2 DTSEL CKSEL CESEL MOD4 ICEV CEEV MOD3 PRV2 PRV1 PRD PLDET THM ADKEY0 ADKEY1 Avss DEST I/O PowerOn Pure Direct Standby O O O O O O O O O O O O O O O O O O I O O O O O O I O O O O I AD O AD O AD O AD O AD O AD O AD O MCU MCU AD O Function Electron volume IC DATA Zone2 Selector (BD3841) Clock (R model) Zone2 Selector (BD3841) DATA (R model)
No. 106 107 108 109 110 111 112 113 114
Sleep O O O O O O O O O O O O
EX. INPUT Selector Clock EX. INPUT Selector DATA
MODEL distinction 2
115 P114 116 P113 117 P112 118 P111 119 P110 120 121 122 123 124 125 126 127 128 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 Avss P100/AN0
MODEL distinction O O O O O O O O O MCU O
AD protection power-supply voltage detection AD protection DC detection AD POWER LIMITTER detection AD temperature detection AD Key 0 AD Key 1 Ground for AD AD model detection
RX-V459/HTR-5940/DSP-AX459/HTR-5935 Key Input(A-D) Pull-Up Resistance 10 k-Ohms

+1.0k +1.0k +4.7k +0.0k +1.5k +2.2k +3.3k +6.8k +10.0k +4.7k +22.0k Ohm ~1.0 ~0.7 ~3.1 ~0.3 ~1.5 ~2.0 ~2.6 ~3.7 ~4.0 ~3.4 ~4.4 V PURE ADKEY0 PROGRAM PROGRAM BASS/TREBLE BASS/TREBLE INPUT MODE STRAIGHT TONE CONTROL PRESET/TUNING SPEAKER B SPEAKER A > < DIRECT 94pin/AN2 + + ADKEY1 MULTI CH PRESET/TUNING PRESET/TUNING FM/AM A/B/C/D/E MEMORY TUNING MODE 95pin/AN1 INPUT < >
MODEL Distinction Port /

Pin 3 69 114 119 117 Function P97/Adtrg/Sin4 P43/A19 P115 P110 P112 Name CEFD/MOD0 CES/MOD1 DTBD/MOD2 CEEV/MOD3 CESEL/MOD4 RX-V459/HTR-5940/DSP-AX459 1 1 1 0 0 HTR-5935 0 1 1 0 0
Distinction for AD Port / Pull-Up Resistance 10 k-Ohms

Ohm V A-D (5V=255) DEST 129pin 0.0k 0-0.2 0-13 J 1.2k 0.3-0.8 14-40 U, C 2.7k 0.9-1.3 41-68 4.7k 1.4-1.8 69-92 R 6.8k 1.8-2.2 93-115 T 10.0k 2.3-2.7 116-140 K 15.0k 2.8-3.3 141-170 A 27.0k 3.4-3.8 171-198 47.0k 3.9-4.3 199-221 G, E 100.0k 4.4-4.7 222-244 L 4.8-5.0 245-255
44
IC56
: LC89057W-VF4-E (DSP P.C.B) Digital Audio Interface Transceiver
DO DI CE CL XMODE DGND DVDD TMCK/PIO0 TBCK/PIO1 TLRCK/PIO2 TDATA/PIO3 TXO/PIOE
37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25
RERR INT CKST AUDIO/VO EMPHA/UO DGND DVDD XIN XOUT XMCK DVDD DGND
24 23 22 21 20 19 18 17 16 15 14 13
LC89057W-VF4-E
SDIN SLRCK SBCK RDATA RLRCK DVDD DGND RBCK RMCK AGND AVDD LPF
1 2 3 4 5 6 7 8 9 10 11 12
EMPHA/UO
AUDIO/VO
RXOUT *RX0 RX1 RX2 RX3 DGND DVDD *RX4 RX5/VI *RX6/UI DVDD DGND
*: Pull-down resistor internal
32
33
35
40
39
38
RXOUT 1 RX0 RX1 RX2 RX3 RX4 RX5/VI RX6/UI

2 3 4 5 8 9 10 24
Cbit, Ubit Input Selector
Microcontroller I/F
XMODE
41 37 36
INT
CE
CL
CI
DO RERR RDATA SDIN RMCK RBCK RLRCK SBCK SLRCK
Demodulation & Lock Detect
Data Selector
21
LPF 13 TMCK/PIO0 TBCK/PIO1 TLRCK/PIO2 TDATA/PIO3

44 45 46 47
PLL Clock Selector
Modulation & Parallel Port
1/N
16 17 20 22 23
TXO/PIOEN 48
29 28 27 34
XMCK
XOUT
CKST
XIN
45
IC56
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
: LC89057W-VF4-E (DSP P.C.B) Digital Audio Interface Transceiver

Name RXOUT RX0 RX1 RX2 RX3 DGND DVDD RX4 RX5/VI RX6/UI DVDD DGND LPF ACDD AGND RMCK RBCK DGND DVDD RLRCK RDATA SBCK SLRCK SDIN DGND DVDD XMCK XOUT XIN DVDD DGND EMPHA/UO AUDIO/VO CKST INT RERR DO DI CE CL XMODE DGND DVDD TMCK/PIO0 TMCK/PIO1 TLRCK/PIO2 TLRCK/PIO3 TXO/PIOEN I/O O Is I Is Is Function Input bi-phase selection data output pin TTL-compatible digital data input pin Coaxial-compatible digital data input pin with built-in amplifier TTL-compatible digital data input pin TTL-compatible digital data input pin Digital GND Digital power supply TTL-compatible digital data input pin TTL-compatible digital data / Validity flag input pin for modulation TTL-compatible digital data / User data input pin for modulation PLL digital power supply PLL digital GND PLL loop filter connection pin PLL analog power supply PLL analog GND R system clock output pin (256fs, 512fs, XIN, VCO) R bit clock input/output pin Digital GND Digital power supply R LR clock input/output pin (fs) Serial audio data input pin S bit clock output pin (32fs, 64fs, 128fs) S LR clock output pin (fs/s, fs, 2fs) Serial audio data input pin Digital GND Digital power supply Oscillation amplifier output pin Crystal resonator connection output pin Crystal resonator connection, external supply clock input pin (24.576 MHz or 12.288 MHz) Digital power supply Digital GND Emphasis information / U data output / Chip address setting pin Non-PCM output / V flag output / Chip address setting pin Clock switch transition period signal / Demodulation master or slave function switch pin Microcontroller interrupt output / Modulation or general-purpose I/O switch pin PLL clock error, data error flag output Microcontroller I/F read data output pin (3-state) Microcontroller I/F write data input pin Microcontroller I/F chip enable input pin Microcontroller I/F clock input pin System reset input pin Digital GND Digital power supply Modulation 256fs system clock input / General-purpose I/O input/output pin Modulation 64fs bit clock input / General-purpose I/O input/output pin Modulation fs clock input / General-purpose I/O input/output pin Modulation serial audio data input / General-purpose I/O input/output pin Modulation data output / General-purpose I/O enable input pin
Is Is Is
O O/I
O/I O O O Is
O O I
I/O I/O I/O I/O O O Is Is Is Is
I/O I/O I/O I/O O/I
1) Input/output I or O = -0.3 to 3.6V, Is = -0.3 to 5.5V 2) Pins 32 and 33 are latch address setting input pins when pin 41 = "L". 3) Pin 34 is a demodulation function master or slave setting input pin when pin 41 = "L". 4) Pin 35 is a modulation function or general-purpose I/O function switch setting input pin when pin 41 = "L". 5) Perform ON/OFF for all power supplies with the same timing as a latch-up countermeasure.
46
IC60
: D70YE101RFP250 (DSP P.C.B) Decoder/Post Processor * No replacement part available. /
Vss SPI0_SIMO SPI0_SOMI/I2C0_SDA DVDD AXR0[0] Vss AXR0[1] AXR0[2] AXR0[3] Vss AXR0[4] AXR0[5]/SPI1_SCS AXR0[6]/SPI1_ENA AXR0[7]/SPI1_CLK CVDD Vss DVDD AXR0[8]/AXR1[5]/SPI1_SOMI AXR0[9]/AXR1[4]/SPI1_SIMO CVDD Vss AXR0[10]/AXR1[3] AXR0[11]/AXR1[2] CVDD Vss AXR0[12]/AXR1[1] AXR0[13]/AXR1[0] DVDD AXR0[14]/AXR2[1] AXR0[15]/AXR2[0] ACLKR0 Vss AFSR0 ACLKX0 AHCLKR0/AHCLKR1 AFSX0
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
SPI0_CLK/I2C0_SCL SPI0_SCS/I2C1_SCL Vss SPI0_ENA/I2C1_SDA EM_OE DVDD EM_RW CVDD EM_CS[2] Vss EM_RAS EM_CS[0] EM_BA[0] Vss EM_BA[1] EM_A[10] DVDD EM_A[0] CVDD EM_A[1] EM_A[2] Vss EM_A[3] CVDD EM_A[4] EM_A[5] Vss DVDD EM_A[6] EM_A[7] Vss CVDD EM_A[8] EM_A[9] EM_A[11] DVDD
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
Vss EM_CKE EM_CLK Vss DVDD EM_WE_DQM[1] EM_D[8] CVDD EM_D[9] EM_D[10] Vss EM_D[11] DVDD EM_D[12] EM_D[13] CVDD EM_D[14] EM_D[15] Vss CVDD EM_D[0] EM_D[1] DVDD EM_D[2] EM_D[3] Vss EM_D[4] EM_D[5] CVDD EM_D[6] DVDD EM_D[7] Vss EM_WE_DQM[0] EM_WE EM_CAS
D1 Data R/W C67x+CPU D2 Data R/W Program Fetch
Vss AHCLKX0/AHCLKX2 AMUTE0 AMUTE1 AHCLKX1 Vss ACLKX1 CVDD ACLKR1 DVDD AFSX1 AFSR1 Vss RESET Vss CVDD CLKIN Vss TMS CVDD TRST OSCVss OSCIN OSCOUT OSCVDD Vss PLLHV TDI TDO Vss DVDD EMU[0] CVDD EMU[1] TCK Vss
256 64 256 64 Memory Controller 256
Program/Data RAM 256K Bytes Program/Data ROM Page1 256K Bytes Program/Data ROM Page2 256K Bytes Program/Data ROM Page3 256K Bytes 32
JTAG EMU 32 32 32 32 32 32 32 32 32 32 32 32 McASP0 16 Serializes
McASP DMA Bus
McASP1 6 Serializes McASP2 2 Serializes DIT Only SPI1 SPI0 I2C0 I2C1 RT1 PLL
I/O
INT
256
PMP DMP 32 32 32 32
High-Performance Crossbar Switch 32 32 32
I/O Interrupts MAX0 Out
CONTROL
MAX1
Events in EMIF
dMAX
Peripheral Interrupt and DMA Events
Peripheral Configuration Bus
Program Cache 32K Bytes
256
256
CSP
32
47
IC60
: D70YE101RFP250 (DSP P.C.B) Decoder/Post Processor

SIGNAL NAME Ground(Vss) AHCLKX0/AHCLKX2 AMUTE0 AMUTE1 AHCLKX1 Ground(Vss) ACLKX1 Core Supply (CVpp) ACLKR1 IO Supply (DVpp) AFSX1 AFSR1 Ground(Vss) RESET Ground(Vss) Core Supply (CVpp) CLKIN Ground(Vss) TMS Core Supply (CVpp) TRST OSCVss OSCIN OSCOUT OSCVpp Ground(Vss) PLLHV TDI TDO Ground(Vss) IO Supply (DVpp) EMU[0] Core Supply (CVpp) EMU[1] TCK Ground(Vss) EM_CAS EM_WE EM_WE_DQM[0] Ground(Vss) EM_D[7] IO Supply (DVpp) EM_D[6] Core Supply (CVpp) EM_D[5] EM_D[4] Ground(Vss) EM_D[3] EM_D[2] IO Supply (DVpp) EM_D[1] EM_D[0] Core Supply (CVpp) Ground(Vss) EM_D[15] TYPE(1) PULL(2) GPIO(3) IO IO IO IO IO IO IO IO IO Y Y Y Y Y Y Y Y N DESCRIPTION McASP0 and McASP2 Transmit Master Clock McASP0 MUTE Output McASP1 MUTE Output McASP1 Transmit Master Clock McASP1 Transmit Bit Clock McASP1Receive Bit Clock McASP1 Transmit Frame Sync (L/R Clock) McASP1Receive Frame Sync (L/R Clock) Device reset pin
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
IO IO IO PWR IO O PWR PWR IO OZ
IPU IPU IPU IPU
N N N N N N N N N N
Alternate clock input (3.3-V LVCMOS Input) Test mode Select Test Reset Oscillator Vss tap point (for filter only) 1.2-V Oscillator Input 1.2-V Oscillator Output Oscillator 1.2-V Vpp tap point (for filter only) PLL 3.3-V Supply Input (requires external filter) Test Data In Test Data Out
IO IO IO O O O IO IO IO IO IO IO IO IO
IPU IPU IPU -
N N N N N N N N N N N N N N
Emulation Pin 0 Emulation Pin 1 Test Clock SDRAM Column Address Strobe SDRAM Write Enable Write Enable or Byte Enable for EM_D[7:0] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits]
IO
EMIF Data Bus [lower 16 Bits]
48
IC60

SIGNAL NAME EM_D[14] Core Supply (CVpp) EM_D[13] EM_D[12] IO Supply (DVpp) EM_D[11] Ground(Vss) EM_D[10] EM_D[9] Core Supply (CVpp) EM_D[8] EM_WE_DQM[1] IO Supply (DVpp) Ground(Vss) EM_CLK EM_CKE Ground(Vss) IO Supply (DVpp) EM_A[11] EM_A[9] EM_A[8] Core Supply (CVpp) Ground(Vss) EM_A[7] EM_A[6] IO Supply (DVpp) Ground(Vss) EM_A[5] EM_A[4] Core Supply (CVpp) EM_A[3] Ground(Vss) EM_A[2] EM_A[1] Core Supply (CVpp) EM_A[0] IO Supply (DVpp) EM_A[10] EM_BA[1] Ground(Vss) EM_BA[0] EM_CS[0] EM_RAS Ground(Vss) EM_CS[2] Core Supply (CVpp) EM_RW IO Supply (DVpp) EM_OE SPI0_ENA/I2C1_SDA Ground(Vss) SPI0_SCS/I2C1_SCL SPI0_CLK/I2C0_SCL Ground(Vss) SPI0_SIMO TYPE(1) PULL(2) GPIO(3) DESCRIPTION IO N EMIF Data Bus [lower 16 Bits] IO IO IO IO IO IO O N N N N N N N EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] EMIF Data Bus [lower 16 Bits] Write Enable or Byte Enable for EM_D[15:8]
PIN NO. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
O O
N N
SDRAM Clock SDRAM Clock Enable
O O O
N N N
EMIF Address Bus EMIF Address Bus EMIF Address Bus
O O
N N
EMIF Address Bus EMIF Address Bus
O O O O O O O O O O O O O O IO IO IO IO
N N N N N N N N N N N N N N Y Y Y Y
EMIF Address Bus EMIF Address Bus EMIF Address Bus EMIF Address Bus EMIF Address Bus EMIF Address Bus EMIF Address Bus SDRAM Bank Address and Asynchronous Memory LOW-Order Address SDRAM Bank Address and Asynchronous Memory LOW-Order Address SDRAM Chip Select SDRAM Row Address Strobe Asynchronous Memory Chip Select Asynchronous Memory Read/not Write SDRAM Output Enable SPI0 Enable (Ready) or I2c1 Serial Data SPI0 Slave Chip Select or I2c1 Serial Clock SPI0 Serial Clock or I2c0 Serial Clock SPI0 Data Pin Slave In Master Out
49
IC60

SIGNAL NAME TYPE(1) PULL(2) GPIO(3) SPI0_SOMI/I2C0_SDA IO Y IO Supply (DVpp) AXR0[0] IO Y Ground(Vss) AXR0[1] IO Y AXR0[2] IO Y AXR0[3] IO Y Ground(Vss) AXR0[4] IO Y AXR0[5]/SOI1_SCS IO Y AXR0[6]/SPI1_ENA IO Y AXR0[7]/SPI1_CLK IO Y Core Supply (CVpp) Ground(Vss) IO Supply (DVpp) AXR0[8]/AXR1[5]/SPI1_SOMI IO Y AXR0[9]/AXR1[4]/SPI1_SIMO Core Supply (CVpp) Ground(Vss) AXR0[10]/AXR1[3] AXR0[11]/AXR1[2] Core Supply (CVpp) Ground(Vss) AXR0[12]/AXR1[1] AXR0[13]/AXR1[0] IO Supply (DVpp) AXR0[14]/AXR2[1] AXR0[15]/AXR2[0] ACLKR0 Ground(Vss) AFSR0 ACLKX0 AHCLKR0/AHCLKR1 AFSX0 IO Y DESCRIPTION SPI0 Data Pin Slave Out Master In or I2C0 Serial Data McASP0 Serial Data 0 McASP0 Serial Data 1 McASP0 Serial Data 2 McASP0 Serial Data 3 McASP0 Serial Data 4 McASP0 Serial Data 5 or SPI1 Slave Chip Select McASP0 Serial Data 6 or SPI1 Enable (Ready) McASP0 Serial Data 7 or SPI1 Serial Clock
PIN NO. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
McASP0 Serial Data 8 or McASP1 Serial Data 5 or SPI1 Data Pin Slave Out Master In McASP0 Serial Data 9 or McASP1 Serial Data 4 or SPI1 Data Pin Slave In Master Out
IO IO
Y Y
McASP0 Serial Data 10 or McASP1 Serial Data 3 McASP0 Serial Data 11 or McASP1 Serial Data 2
IO IO IO IO IO IO IO IO IO
Y Y Y Y Y Y Y Y Y
McASP0 Serial Data 12 or McASP1 Serial Data 1 McASP0 Serial Data 13 or McASP1 Serial Data 0 McASP0 Serial Data 14 or McASP2 Serial Data 1 McASP0 Serial Data 15 or McASP2 Serial Data 0 McASP0 Receive bit Clock McASP0 Receive Frame Sync (L/R Clock) McASP0 Transmit Bit Clock McASP0 and McASP1 Receive Master Clock McASP0 Transmit Frame Sync (L/R Clock)
50
I PIN CONNECTION DIAGRAM

ICs
BD3816K1
64 65 41 40 17
37 36 25 24
BD3841FS
TC74HC4051AF TC74HC4052AF TC74HC4053AF NJM2581M
F2602E-01 YAC523-EVR2
LA7106M-TLM-E PCM1780DBQR PCM1781DBQR PCM1803DBR
32
16 14 7 1
48 1 12 13
8 16 1
80 1 24
25
BD3816K1
LA73050-TLM-E
LC72722PM
LC89057W-VF4A-E
24 25 13 12
LM61CIZ THERMAL
18 12 36 IN COM OUT 1 1 37 48 24 36 1 +VS VOUT GND
M30625MHP-A98GP
M66003-0131FP
NE5532DR OP AMP
NJM2068LD NJM2068MD-TE2 NJM4556AL
NJM2388F05 5.0V NJM2388F33
102 103
65 64
48 49
33 32 8 1 4
8
128 1
39 38
64 1 16
17
1
1 4
NJM2581M VIDEO AMP
NJM2885DL1-18 NJM2885DL1-33
NJM4565M (TE1)
NJM7812FA
NJM78M05DL1A (TE1)
NJM7805FA 5V NJM79M05FA NJM79M12FA
2:GND 14 1 7 8 1:IN 3:OUT 1 4 3: IN 2: COM 1: OUT 1 3 3: COM 2: IN 1: OUT
NJU7311AM NJU7312AM NJU7313AM
PCM1680DBQR
R1172S121D-E2-F
RH5RE58AA-T1-FA
1: Vin 2: GND 3: Vout 3
SN74AHC1G08DCKR
4 5 1 3
6 1 15 30 1 28
14
SN74AHCT08PWR
SN74AHCT1G32DCKR
4
14 1
5 1
51
SN74LV157APWR SN74LVU04APWR
SN74LV245APWR TRAN
TC4013BP FF TC74VHCU04FT INVER
W9816G6CH-7 SDRAM
YAC520-EE2
50
26
10 14 7 1 20 1 14 1 1 25 7 20 1
10
S29AL004D70TF1020
48
24
25
Diodes
1N4002S RB441Q-40 T-77 1SS133,176 RB441Q-40 T-77 1SS270A 1SS355 1SS380 1T2 MTZJ13A 13V MTZJ15A 15V MTZJ15B 15V Anode MTZJ2.4B 2.4V MTZJ27B 27V MTZJ30A 30V MTZJ5.1C 5.1V
Cathode
D2SBA20 1.5A 200V D5SB20 5A 200V
MA8030-L 2.9V MA8051-M 5.1V MA8056-M 5.6V MA8068-L 6.6V MA8068-M 6.8V MA8075-H 7.7V MA8091-M 9.1V MA8100-M 10V
RB500V-40 RB501V-40 UDZ 3.6BTE-17 3.6V UDZ5.1B 5.1V
MA8082-H 8.5V
Anode
Cathode
S1NB20 1A 200V S1NB60 1.0A 600V

Anode + ~ ~
~ ~ + Cathode
Transistors
2SA1015 Y 2SC3326 A,B 2SA933S Q,R 2SC3837K T146 N,P 2SA949 O,Y 2SC3906K T146 R,S 2SC1740S QRS 2SC1815 Y 2SC1890A D,E 2SC2229 O,Y 2SC2240 GR,BL 2SB1257 2SB1274 Q,R,S 2SA1695 O,P,Y 2SC4468 O,P,Y 2SD1915F S,T 2SD2014 2SK2158-T2B-A 2SK246 Y 2SK3288 2SK3850 2SA1708 S,T 2SA1770 S,T 2SC4488 S,T 2SC4614 S,T 2SD1938F S,T
CB
BC
BC
2SA1037K Q,R,S 2SC2412K Q,R,S DTA114ES DTC114EKA DTC114ES DTC124EKA DTC144ES
C E B
52
J RX-V459/DSP-AX459/HTR-5935
I BLOCK DIAGRAMS
AUDIO BLOCK DIAGRAM
DSP
MD/CD-R DVD
See page 69-71 SCHEMATIC DIAGRAM

DSP-AX459 model 4 5 8
LC89057W DIR IC56 RX2
D70YE001RFP250 Decoder / Post Prosessor IC60 AXR0[4] 131 AXR0[11]
Post Prosessor
Input Selector
RX3 RX4 R, T, K, A, G, E, L models 21 J206
DIGITAL
DTV/CBL 6 DVD Buffer SN74LVU04APWR *VDD=5V IC52
Decoder
AXR0[3] AXR0[2] AXR0[1] AXR0[0]
117 116 115 113
FL/FR C/SW SL/SR SB
6 11 12 13
D/A FL/FR D/A C/SW D/C SL/SR D/A SB 8ch DAC PCM1680 IC68
27, 26 22, 21 20, 19 16
IC71 IC72 IC73 IC74
DAFL/DAFR DAC/DASW DASL/DASR DASB
RX5
RDA 130 U, C models
AXR1[3]
RX-V459, HTR-5940, HTR-5935 models MD/CD-R
DSP-AX459 model
RXOUT
RX-V459, DSP-AX459, HTR-5940 models
11 3A XM 18, 19 XMDT 37 I2S IC55 U, C models 10 3B Selector SN74LV157APWR IC58 3Y
16M SDRAM IC64
4M ROM IC66
Selector SN74LV157APWR 3 IC67 1B 2 1Y 1A 9 2ch ADC 1, 2 PCM1803 IC70 IC76 Att. -9dB ADL/ADR 4
OPERATION
Extension Selector BD3841FS IC202
See page 73 SCHEMATIC DIAGRAM

PORTABLE V-AUX AUDIO L/R 5, 6
FUNCTION
19, 20
MAIN
4
23, 24 26- 32
IC211 Muting Q2012, 201 C3039, 3041 NJM4556AL 53, 54 Tone Control Center Surround L/R Surround Back SW Selector / Volume BD3816K1 IC200 76- 79 15- 19, 21 Center Mix LFE Mix 51 49, 50 48 46 Muting Q2019 RY103 C1108 CENTER Muting Q2014, 201 FRONT RY101 C1117, 1118 FRONT B L/R IC207 RY100 C1115, 1116 FRONT A L/R HEAD PHONE
Input Selector
FM/AM
2- 13 CD MD/CDR
7ch Selector
FM/AM TUNER (11) 7.2MHz
74, 75
ANALOG
DVD DTV/CBL DVR
Input Gain Master Volume Output Gain
(0dB to 7dB) (-95dB to 0dB) (0dB to 17dB)
CENTER
REC OUT
Muting Q2016, 201 MD/CDR DVR
SURR.
RY104 C1119, 1114 SURROUND L/R
Muting Q2018
SURR.BACK
RY102 C1111
SURROUND BACK
MULTI CH INPUT
FL/FR IC205 C/SW MUTE CONTROL SL/SR Muting Q2009, 201
HTR-5935 model SW RY102 C1111 SUB WOOFER
YST
SPEAKER RELAY
SUBWOOFER OUT
POWER AMP
53
SPEAKER OUT
RX-V459/DSP-AX459/HTR-5935 1
VIDEO BLOCK DIAGRAM
BYPASS
OUTPUT AMP LA73050 IC401 CVBS 3 6dB 33
DVD DTV/CBL DVR V-AUX
INPUT SELECTOR 74HC4051 15 14 12 1 5 CVBS
OPERATION
3 IC402 CVBS
6dB
29
C Y
DVR OUT
6dB
31 RX-V459, DSP-AX459, HTR-5940 models

/VR1
DVD
DTV/CBL
15 14 12 1 5
Y CVBS 12 24
3 IC403
6dB
DVR 15 14 12 1 5 C
17
6dB
20
C Y
3 IC404
15
6dB
22 RX-V459, DSP-AX459, HTR-5940 models

/MON
MONITOR OUT
U, C, R, T, K, A, G, E, L models
Y Pb/Cb Pr/Cr
VIA VIB VIC
Y Pb/Cb Pr/Cr
FUNCTION
Y Cb Cr

Y Cb Cr
DVD
L1/L2/L3
L1/L2/L3
J model
J model
Y Pb/Cb Pr/Cr
DTV/ CBL
Y Cb Cr L1/L2/L3 COMP0 COMP1 /CBYPASS Y
6dB
J model U, C, R, T, K, A, G, E, L models
Y Y/ Cb/ Cr 2, 4, 5, 15, 14, 11 IN
BYPASS
6
DVR
Pb/Cb Pr/Cr
Input Selector 74HC4052 IC287(Cb, Y) IC288(Cr, L1) IC289(L3, L2)
Cb
6dB
3, 13
Cr
6dB IC290 OUTPUT AMP NJM2581
2, 4, 5, 15, 14, 11
Y Cb Cr L1/L2/L3 L1/L2/L3 IN
3, 13
L1/L2/L3 OUT
J model
54
/MON /CNON
J RX-V459/DSP-AX459/HTR-5935
CONTROL/POWER BLOCK DIAGRAM

POWER DETECT MODEL DETECT DEST. DETECT
DSP
/RESET
POWER TRANSFORMER
RY105
C1105 C1104
/4ohms
PLDET
PRV2
PRV1
PRI
3/ 69/ 114 /117/ 119
D133
C1107
2
IR REMOTE U3000
98
C1106
/HP
OPERATION
THM
PRD
+B
120
121
122
123
124
128
17
53
96
99
-B RY105
D1041, 1402, 1044, 1045
6 55 51/ 50/ 49/ 48/ 46
LIMITER CONTROL POWER RELAY SPEAKER RELAY MUTE CONTROL POWER SAVE /4ohms
C1100
+BL
VOLUME SW300
63/ 64
100- 104 54 47
C1101
INPUT SELECTOR SW301
58/ 59
-BL
TONE CONTROL/ DSP PROGRAM SW302
60/ 62
XMPWR
-30V Q1068
-VP
Microprocessor M30627 IC2

MAIN POWER SW SW323
97
8-10/ 15/ 16/ 23/ 24/ 26- 31 12/ 42- 45 34/ 35
FL1
DSP
FL2
Net-module XM
+12V IC104
D1035
+12
69/ 84/ 86/ 88/ 89/ 117
RDS
83/ 90- 95
C1082
TUNER
C1083
-12V IC105 +5V IC51
-12
25/ 65- 68, 70- 74, 76- 81
Tack SW SW302, 304, 306, 309- 319, 321, 322, 324 FL DISPLAY V3000 FL DRIVER IC301
125/ 126 115/ 116/ 111- 117 3/ 4/ 5/ 57
VIDEO SELECTOR SELECTOR/VOLUME
MAIN
+5A
DSP
18
XL1 16MHz
20
+5V IC102
+5D +3.3V IC54 +3.3V +1.2V IC53 +1.2V
RY301
F3001
DG
F3000/J3002
C1087
+3.3V IC306
D1036
+3.3D
TE300
C1088
-5V IC103 +5V IC106
-5V
+5V
IC300, 302, 303
Power Detector /Reset Q3006, 3002
6
D3016 Q3007
D3 +5BU T3000 s10

RY301
VE
+5.5V IC1
D2 +5M D1 Q1 +5S
D3018
U, C models
C1109 D1046
Q3003
+5.3V IC100 XMPWR
+5.3X
XGND
7
POWER RELAY POWER SAVE
55
SCHEMATIC DIAGRAMS
DSP 1/3
1
RX-V459/HTR-5940/HTR-5935/DSP-AX459
DSP
POINT A-1 Pin 18 of IC2 POINT B-2 1 / Pin7, 2 / Pin8 of CB3
POWER ON (connect the power cable)

to FUNCTION (1)_CB200
Page 72
C2
5.0 -11.9 4.9
5.0 5.0 4.9 4.9 4.9 0 0 0 0 0 4.3
IC1 : RH5RE58AA-T1-FA Voltage regulator

VIN 2 3 VOUT
4
5.0 5.2 0 5.0 5.0 0.1 5.0
5.0 0.1 0.1 0.1 4.9 5.0 5.0 0.1 4.9 -11.9 0 0 0 0 4.9
Vref
5.0
4.9
4.9
4.9
4.9
0.1
1 GND
5.0 -11.9 4.9
5.0 0.1 0 0
0.1 4.8 5.0 5.0 5.0 4.9
to OPERATION (1)_CB309
0 0
5.0 5.0 4.3
C9
MICRO PROCESSOR
0 0 0 0 0 0 0 0
0.1 5.0 5.0 4.9 4.9 0 0 5.9 0 0 0.2
IC4, 5 : SN74AHCT1G32DCKR Single 2-input positive-OR gate

A B GND 1 2 3 4 Y 5 Vcc
Page 73
M30625MHP-A98GP
4.9 0 0 0 5.0
2.7 2.0 0.4 5.0 1.0 5.2
A-1
0 0 4.3 0
0.1 0 0 5.0 0.1 3.3 0.1
4.9
5.0
6
0.4 2.7
5.2
IC6 : SN74AHC1G08DCKR 2-input positive-AND gate

A 1 2 3 4 Y 5 Vcc
0 1.2
0 0.2
2.0
B
0 4.9 2.5 2.4 4.9 5.2 4.9 5.0 5.0 5.0 0 0 0
GND
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0 0.6 4.9 4.9 4.9 4.8 0.5 0.1
5.0
5.0
I3
to FLASH WRITER
5.0 5.0 0 0
5.0
Page 72
IC2 : M30625MHP-A98GP 2-input positive-AND gate
5.0
0.1
5.0
0.1 5.0 5.0 0.1 5.0 5.0
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6 Port P7 <VCC1 ports> (4) 8
<VCC2 ports> (4) Internal peripheral functions Timer (16 bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit D/A converter (10 bit x 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (8 bit x 8 channels) Watchdog timer (Polynomial: X16+X12+X5+1)
Watchdog timer (15 bits) Port P8 XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Clock synchronous serial I/O (8 bit x 2 channels) Memory ROM (1) RAM (2)
to OPERATION (4)_W3009
<VCC1 ports> (4)
Port P8_5
XX
M16C/60 series 16-bit CPU core
Page 73
Watchdog timer (15 bits)
R0H R1H R2 R3 A0 A1 FB
R0L R1L
DMAC (2 channels)
5.0 5.0 5.2 4.3 5.2 5.8 4.9 0.1 0.1 5.1 5.0
to MAIN (1)_W1026
10.1 0
5.8 5.8
5.2
D/A converter (8 bit x 2 channels) <VCC1 ports> (4) Port P11 (3) 8 Port P14 (3) 2
SB USP ISP INTB PC FLG
Port P9
B-2
Port P10
Multiplier <VCC2 ports> (4) Port P12 (3) 8 Port P13 (3) 8
Page 74
H2
4.9
to MAIN (1)_W1007
NOTES: 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. Ports P11 to P14 exist only in 128-pin version. 4. Use M16C/62PT on VCC1=VCC2.
Page 74
H1
10
# All voltages are measured with a 10M/V DC electronic volt meter. # Components having special characteristics are marked s and must be replaced with parts having specifications equal to those originally installed. # Schematic diagram is subject to change without notice.
69
DSP 2/3
IC61, 62 : SN74AHCT1G32DCKR Single 2-input positive-OR gate
A B GND 1 2 3 4 Y 5 Vcc
DSP
IC63 : SN74AHCT08PWR Quadruple 2-input positive-AND gates

1A 1B 1Y 2A 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc 4B 4A 4Y 3B 3A 3Y
3.3
100/16
100/16
1.3 1.3 0
100/16
3.1 3.1 0
3.3
5.0
3.3
3.3
5.0
POINT A-1 Pin 28 of IC55

3.2 0.1 3.1 0.9
POINT A-2 Pin 29 of IC56
2B 2Y
3.3 0
5.0
3.1
0.1 0 0 4.0 0.3 0 3.3 0.3 3.3
3.3 3.3 0 0
GND
DIR
3.3
3.3 1.6 1.5
IC64 : W9816G6CH -7 512K x 2 banks x 16 bits SDRAM

CLK 35 CLOCK BUFFER
0.1 5.0 0
0.6 0 3.3 0 0
&6
A-2
1.7 3.3
CKE 34
CS 18
3.3
1.7
1.7
1.7
3.3
4.0 0
RAS 17 CAS 16
COMMAND DECODER
CONTROL SIGNAL GENERATOR
COLUMN DECODER R O W D E C O D E R CELL ARRAY BANK #0 2 DQ0 3 DQ1 5 DQ2 6 DQ3 SENSE AMPLIFIER 8 DQ4
3.3
0.5
0.1
5.0
5.0
5.0
5.0
5.0
0.6
0.5
5.0 5.0
5.0
5.0
4.9
5.0
WE 15
A10 20
DIGITAL IN
0.3 0 4.9
3.3
3.3
3.3
3.3
0.9
3.5
FL/FR C/SW PL/PR ANALOG IN SL/SR SBL/SBR
0.1
3.1
3.2
0.1
0.1
0.1
0.1
9 DQ5 A0 21 A3 24 A4 27 A9 32 BA 19 MODE REGISTER ADDRESS BUFFER REFRESH COUNTER DQ BUFFER 11 DQ6 12 DQ7 39 DQ8 40 DQ9 42 DQ10 43 DQ11 45 DQ12
0.3 0 4.9
REFRESH COUNTER COLUMN COUNTER R O W D E C O D E R CELL ARRAY BANK #1 COLUMN DECODER
46 DQ13 48 DQ14 49 DQ15
4
5.0 2.4 2.4 0.6 0
14 LDQM SENSE AMPLIFIER 36 UDQM
4.9
BUFFER
3.1 0.9 3.3 0.1 1.3 3.3 3.3
IC66 : S29AL004D70TF1020 4M-bit COMS 3.0 volt-only boot sector flash memory
RY/ BY# VCC VSS RESET# Sect or Sw itc hes Erase V olt ag e Generat or DQ0DQ15 (A- 1)
4.9
SELECTOR
0 0 0 0 0 3.3 1.2
In put/ Out put Buff ers
1.2
3.3
1.2
3.3
5
0 1.7 0.1 0 0 5.4
XM
0.4
1.7
1.7
1.7
1.7
1.7
1.7
1.7
0.5
WE# BYTE#
3.3
State Contr ol Comm and Regi st er
PGM Vo ltage Generator Chip Enab le Out put Enable Logic STB Data Lat ch
0 0 0 0 3.3
CE# OE#
0 0.1
0 0 0 1.2 1.7 0.1 1.5 1.5 1.5 1.5 3.3 0 1.7 0 3.3 3.5 0.2 3.3 0 1.2 0 1.9 3.5 1.8 0 0 0 3.5 0 1.8 0.2 0 3.5 0 3.3 3.3 3.5 0 0 0 0 1.7 0 3.3 1.2 0 0 0 3.5 3.5 3.5 0 0 3.3 3.3 3.3 0 0 3.5 3.5 3.3 3.3 1.8 0.2 0.2 1.2 3.3 3.3 0 0 0 1.2
STB Addr ess La t ch
Y-Decoder
Y- Gating
3.3
VCC De te ct or Tim er
1.2 3.3 0 3.3 0 3.3 0 3.3 0.4 3.3 0.1 1.2 0.1 0.1 0 3.0 1.2 1.6 1.8 3.3 0.2 0.1 0 0.2 0.2 3.3 0.2 0.1 0 0.1 0.1 3.3 3.3 1.2 3.3 1.2 1.2 3.3 1.2 3.3 0 0 0 0 0 0 2.9 3.3 3.3 2.9 3.3 0 3.3 0.4 0.1 0.1 0.1 3.0 0.1 0.1 2.9 2.8 1.8 1.6 0 2.9 1.7
S29AL004D70TF1020
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A0 A17
X- Decoder
Cell M atrix
A-1
16M SDRAM
4M ROM
XMDT
0 0.1 0.1 0 0.2 0.2 3.3 0.1 0.2 0 0.2 0.2 3.3 3.3 3.3 0.1 0 0 0.1 0.4 0.1 0.1 2.9 0 3.3 0 0.1 0.1 0.1 0.1 0.2 0.1 0.2 0.2 3.3 0.1 0.2 0.2 0 0 2.8 1.8 1.6 3.0 0.1 0.1 0.1 0.2 0.2 0.1 0.2 0.2 3.3 0 3.3 3.3
No replacement part available.
0 3.3 2.8 2.9 0 1.2 0.1 0.1 0.1 3.3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
0.2
1.8
IC65 : SN74LV245APWR Octal bus transceiver with 3-state outputs

DIR 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND 10 20 Vcc 19 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8
3.3
3.3
1.7
0.1
0.1
0.1
0.2
0.2
0.1
0.2
0.1
0.2
0.2
0.1
0.2
0.2
0.2
3.3
2.9
3.3
0.1
3.3
IC56 : LC89057W-VF4A-E Digital audio interface transceiver
IC58 : SN74LV157APWR Quadruple 2-line to 1-line data selectors/multiplexers

INT CL CE CI 35 48 39 38 XMODE 41
1A 1B 2 3 5 6 7 2Y 4 1Y
IC59 : SN74AHC1G08DCKR 2-input positive-AND gate

A B 1 2 3 4 Y 5 Vcc
9
IC52 : SN74LVU04APWR Hex inverters
1A 1 1Y 2 2A 3 2Y 4 3A 5
14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y
IC53 : R1172S121D-E2-F Power supply
EMPHA/UO AUDIO/VO 32 33
IC54 : NJM2885DL1-33 Low dropout voltage regulator

VIN 1 3 VOUT
RXOUT 1 RX0 2 RX1 3 RX2 4 RX3 5 RX4 8 RX5/VI 9 RX6/UI 10 LPF 13 Input Selector
Cbit, Ubit
Microcontroller I/F
37 DO 36 RERR
2A 2B
VDD
VOUT
Bandgap Reference
3A 11 3B 10 4A 14 9 3Y
Thermal Protection
Demodulation & Lock detect
Data Selector
21 RDATA
A/B 1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC G 4A 4B 4Y 3A 3B 3Y
GND
24 SDIN PLL Clock Selector 1/N 16 RMCK 17 RBCK 20 RLRCK 22 SBCK 23 SLRCK
4B 13 G 15 A/B 1
12 4Y
10
3Y 6 GND 7
GND
TMCK/PIO0 44 TBCK/PIO1 45 TLRCK/PIO2 46 TDATA/PIO3 47 Modulation & Parallel Port
Vref
Current Limit
CE
GND
TXO/PIOEN 48 29 XIN 28 27 34
XOUT XMCK CKST
70
DSP 3/3
1
Page 72 D2 Page 74 J7 to FUNCTION (1)_CB202 to MAIN (2)_W1004
DSP
2
IC71-74, 75, 76 : NJM4565M Dual operational amplifier
V+
2, 6
INPUT +INPUT
1, 7 3, 5
OUTPUT
8.8
5.1
8.8 0
5.1
V
4
LC89057W-VF4A-E LC89057W-VF4AD-E
5.0
1.7 1.3 0 3.3 1.7
1.7 0 0
5.0
ANALOG IN
11.8
IC70 : PCM1803DBR Stereo A/D converter
2.5
3.3 2.5 0 5.0 2.5 2.5 2.5 2.5
2.5
0 0
0 0
3.3 3.3 0 0 0
VINL
Delta-Sigma Modulator Serial Interface
BCK LRCK DOUT
0 2.5 -11.9
0 0
VREF1 Reference VREF2
2ch DAC
0 0 11.8 0
FRONT L
x1/64, x1/128 Decimation Filter With High-Pass Filter
Mode/ Format Control
FMT0 FMT1 MODE0 MODE1 BYPAS TEST OSR
VINR
Delta-Sigma Modulator
FRONT L
5.0 3.3 3.1 1.7 1.7 2.5 2.5 2.6 0 5.1 2.5 2.5 2.5 2.5 0 5.1 2.5 0 0 11.8 0 0 0 0 -11.9
Power Supply
Clock and Timing Control
PDWN SCKI
5
C/SW SL/SR
VCC
AGND DGND
VDD
1.7 1.7 5.0 0 1.7 1.7 0.5 0
CENTER
IC69 : PCM1781DBQR Audio digital-to-analog converter SUB WOOFER

BCK LRCK Audio Serial Port Output Amp and Low-Pass Filter VOUTL
0 0
DIGITAL IN
0
8ch DAC
0 0 0 -11.9
DATA
DAC 4 /8 Oversampling Digital Filter With Function Control
6
3.3 0.1 0.1 1.7 0 0 0 0 1.7 1.7 1.7 1.7 1.7 1.7 3.3
SURROUND L SBL/SBR
0 0 11.8 0
(FMT) MS (DEMP0) MC (DEMP1) MD (MUTE) Serial Control Port
Enhanced Multilevel Delta-Sigma Modulator
VCOM
DAC
Output Amp and Low-Pass Filter
VOUTR
(TEST)
System Clock System Clock Manager
FL/FR
SELECTOR
7
0 0
0 -11.9
SCK
Zero Detect
Power Supply
ZEROL/NA (1)
ZEROR/ZEROA (1) (ZEROA)
VCC
0 0
11.8 0
(1) Open-drainoutputforthePCM1782 NOTE: Signal names in parentheses ( ) areforthe PCM1781.
0 0
0 -11.9
8
BCK LRCK
IC68 : PCM1680DBQR Audio digital-to-analog converter
AGND
SURROUND BACK L
DAC
Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter Outp ut A mp and Low-P ass Filter
VOUT1
DAC
VOUT2
IC51 : NJM78M05DL1A Voltage regulator
IC67 : SN74LV157APWR Quadruple 2-line to 1-line data selectors/multiplexers

1A 1B 2 3 5 6 7 2Y 4 1Y
DATA1 (1, 2) DATA2 (3, 4) DATA3 (5, 6) DATA4 (7, 8)
Serial Input I/F DAC

8 Oversampling Digital Filter With Function Controller
VOUT3
INPUT
2A
Enhanced Multilevel DeltaSigma Modulator
DAC
VCOM VOUT4
9
OUTPUT
2B
3A 11 3B 10 4A 14 4B 13 12 4Y 9 3Y
A/B 1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC G 4A 4B 4Y 3A 3B 3Y
DAC
VOUT5
MS/ADR MC/SCL MD/SDA Function Control I/F DAC
VOUT6
DAC
VOUT7
MSEL DAC System Clock SCK

Syst em Clock
VOUT8
COMMON
G 15 A/B 1
Manager
Zero Detect
Power Supply
ZERO1
ZERO2
DGND
VCC1
VCC2
VDD
10
AGND1
AGND2
71
FUNCTION
Page 69 B3 Page 71 C1 Page 73 G6 to DSP_CB56 to OPERATION (5)_W3007
to DSP_CB1
0.1 0.1 0.1 0.1 0.1 0.1 0 7.1 0.1 0.1 -6.9
EXTENSION SELECTOR
0 0 0 0 0 0 0 0
0.1 0
0.1 0.1 0 0
Page 73
J3
Page 69
B7
to DSP_CB2
IC200 : BD3816K1 7-channel volume IC for 7-channel

65 GOUTFR 79 ROUTC2 78 ROUTC1 77 ROUTB2 76 ROUTB1 80 AGND13 73 AGND12 70 AGND11 75 ROUTA2 74 ROUTA1 66 THGND 67 MUTE 72 VCC 71 VEE
69 DA
68 CL
LOGIC
REC C REC B REC A
0.1
0.1
0.1
0.1
AGND1 1
64 VINFR 63 GOUTFL
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
SUB WOOFER
0.1 0 0
SURROUND BACK L/R

0.2 0.3 0.2 5.5 5.8 2.5
INA1 2
BD3816K1
INA2 3 INB1 4
62 VINFL 61 AGND10 60 TNF1 TREBLE 59 TNF2 58 BNFA1

Output mode select
4
0.1 0.1 0.1 0.1
0.1 0.1 0 0.1 0.1 0.1
C-2
4.9
INB2 5 INC1 6
Input select
ING SW
0.1 0 0.1 0 0.1 0.1 0.1 1.0
1.0
INC2 7
2.5 2.5 2.5 2.5
3.2
3.2
5.3
1.0
2.7
0.7 0.1 0 0 0 0 0 0.7 0.1 0.1 0 -4.9 0
5.0
2.5
IND1 8 IND2 9
BASS
57 BNFB1 56 BNFA2 55 BNFB2
3.1
3.1
0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
0.1 0 0.1 0.1 0.1
0.1 0.1 0.1 4.9 4.9 4.9
FUNCTION (4)
INE1 10 INE2 11 INF1 12 INF2 13 AGND2 14

FRL select
Master Volume
+ +
54 OUTFR 53 OUTFL 52 AGND9 51 OUTC 50 OUTSR 49 OUTSL 48 OUTCB 47 AGND8 46 OUTSW 45 AGND7 44 VINC 43 GOUTC 42 VINSR 41 GOUTSR
0.1 0.1 0
SURROUND L
0 0 0 0 0 0 0 0
CENTER
11.9 6.5 5.8
INDVDFR 15 INDVDFL 16
0.6 0.6
ANALOG IN
0.1 0.1 0.1 0.1 0.1 0
to TUNER
FRONT L
0 0 0
0.1 6.5
INDVDC 17 INDVDSR 18
0.1
10.6 7.1 7.8
0.6
0.6
OUTPUT AMP
0.7 5.0 0.1 0.1 0.5 0.5 0.1 0.6 0 0.6 2.9 0 -4.9 0 -4.9 0 0 -4.9 5.0 0.1 5.0 0.1 5.0 0.1 0.1 0.7 0.1 0.1 0 -4.9
7.1
-6.9
0.1
INDVDSL 19 INDVDCB 20 INDVDSW 21 AGND3 22 OUT1 23 OUT2 24

6.1ch select
0.1
0.1
0.1
0.1
0.1
7.8
00
0.1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
-7.7
INDSPFL
INDSPSR
INDSPCB
INDSPFR
INDSPSL
INDSPSW
GOUTSW
GOUTCB
GOUTSL
OUT1
INDSPC
VINSW
VINCB
AGND4
-7.6
-6.9
-10.7
2.9 2.9
4.9 5.0
RECC1
RECC2
RECA1
RECA2
RECB1
RECB2
INPUT SELECTOR
10.1 9.4 9.4 0.1 0.1 0 0.8
IC202 : BD3841FS Function switch

DGND OUT2 BIAS VCC VEE INI1 INI2 DA CL
32
31
30
29
28
27
26
25
AGND5
24
23
AGND6
22
21
20
19
VINSL
18
17
0.1 0.1
5.0 0.7 0.1 0.1 0.1 0.1 0 -5.0 0 0.6 0.6 0.1 0.1 5.0
5.0
5.0
LOGIC
E9
0.1 0.1 0.4 0.3
0.1
+ + + +
0 0.1
0.8
7
-10.8
-10.1 -10.1
F-SW1
INPUT SELECTOR INPUT SELECTOR
1
INA1
F-SW2
0.1 0.1
0.1
Page 73
2
INA2
3
INB1
4
INB2
5
INC1
6
INC2
7
IND1
8
IND2
9
INE1
10
INE2
11
INF1
12
INF2
13
ING1
14
ING2
15
INH1
16
INH2
F-SW1: INPUT FUNCTION 1 F-SW2: INPUT FUNCTION 2
11.9 0 0 0 0.1 -11.9
0 0.1 -11.9
to MAIN (1)_W1028
B3
0 0
0 -12.0
Page 74
FUNCTION (3)
R, L models
IC209 : LC72722PM RDS signal processor

FL OUT
5
0 0
C IN
6 PLL (57 kHz) VREF CLOCK RECOVERY (1187.5 Hz) 14 VDDD
to MAIN (1)_W1027
VDDA 3
REFERENCE VOLTAGE
B2
VSSA 4 MPX IN 2 DO CL DI CE T1 T2 T3 T4
20 21 22 23 7 8 9 10 ANTIALIASING FILTER 57 kHz bpf (SCF)
VREF
15 VSSD DATA DECODER 19 RDS-ID
0.1 -11.9 0.1 -11.9 11.9 0 0 0 0 0.1 0.1 0.8 -11.9 0 -11.9 0 0.1 -11.9 0.1
Page 74
SMOOTHING FILTER
CCB
RAM (24 BLOCK DATA) MEMORY CONTROL
ERROR CORRECTION (SOFT DECISION) CLK (4.332 MHz)
SYNC / EC CONTROLLER
18 SYNC 24 SYR
0 0
TEST
OSC/DIVIDER
SYNC DETECT-1
SYNC DETECT-2
9 FUNCTION (1)
IC286-288, 289 : TC74HC4052AF Analog multiplexers/demultiplexers IC211 : NJM4556AL Dual operational amplifier
V+
8
to POWER TRANSFORMER
11 16 17 13 12
X IN
FUNCTION (2)
Page 73
D2
Page 73
L3
INH
6
VCC
16
IC290 : NJM2581M Video amplifier

BINARY TO 1-OF-4 DECODER WITH INHIBIT
VIN1
1
IC291 : TC74VHCU04FT Hex inverters

75 Driver
14
IC205, 207 : NJM4565M Dual operational amplifier

V+
8
10
2, 6
A 10 B 9 GND 8 VEE 7 0X 12
1, 7
LEVEL CONVERTER
6dB AMP
V+1
1A 1 1Y 2
14 VCC 13 6A 12 6Y
NEE1
BIAS
13
VOUT1
2A 3
SW SW
13
INPUT +INPUT
OUTPUT
VIN2
6dB AMP
75 Driver
12
V+2
1X 2X 3X 0Y
14 15 11 1 5 2 4
2Y 4 3A 5 3Y 6 GND 7
2, 6
11 5A 10 5Y 9 4A 8 4Y
X OUT
T5 T6 T7
3, 5
SW SW SW SW
3
X-COM
VEE2
BIAS
11
VOUT2
INPUT +INPUT
1, 7 3, 5
OUTPUT
VIN3
6dB AMP
75 Driver
10
V+3
V
4
1Y 2Y 3Y
SW SW
Y-COM
INHIBIT 0 0 0 0 1
B 0 0 1 1 X
A 0 1 0 1 X
0x, 0y 1x, 1y 2x, 2y 3x, 3y NONE
VEE3
BIAS
VOUT3
V
4
PowerSave
REF
GND
72
OPERATION
1
IC251 : LA73050-TLM-E Analog amplifier

U, C, T, K, A, G, J models to POWER TRANSFORMER
2
to POWER CABLE
Page 72 J9 R, L models to FUNCTION (3)_W3005A,W3005B
N.C.
36
N.C.
N.C.
35
N.C.
VIN1
34
+VCC1
+Vcc
Page 74
J8
Page 72
H3
Page 72
C9
DCCNT1
6dB
DR
33
VOUT1
to MAIN (2)_W1006
GND
32
GND
VIN2
31
VOUT2
6dB
DR
30
RX-V459/DSP-AX459 models RX-V459/DSP-AX459 models
MUTE1
N.C.
VIN3
29
6dB
DR
VOUT3
220K
N.C.
28
-VCC1
N.C.
10
27
-VCC2
N.C.
11
26
N.C.
VIN4
12
25
+VCC2
+Vcc
to DSP_CB3
B8
DCCNT2
13
6dB
DR
24
VOUT4
Page 69
GND
14
23
GND
VIN5
D3015 VU99500 MA8091-M9.1V VU99500 MA8091-M9.1V VU99470 MA8082-H8.5V VU99500 MA8091-M9.1V VU99500 MA8091-M9.1V VU99500 MA8091-M9.1V VU99500 MA8091-M9.1V VU99500 MA8091-M9.1V
15
22
VOUT5
6dB
s13
DR
21
MUTE2
16
N.C.
VIN6
17
20
6dB
DR
VOUT6
-VCC4
18
19
-VCC3
OPERATION (4)
TC74HC4051AF
IC253~255 : TC74HC4051AF Analog multiplexers/demultiplexers

4 6 COM 7 1 2 3 4 5 6 7 8 16 VCC 15 2 14 1 13 0 12 3 11 A 10 B 9 C
Page 74
H7
to MAIN (1)_W1029
OPERATION (1)
to TRANSFORMER
5 INH VEE
TC74HC4051AF
GND
no_use (HTR-5935 model)
6
TC74HC4051AF
IC301 : M66003-0131FP FL display driver

Display code RAM (8-bit x 60)
Code write
CGROM (35 bit x 166)
44
SEG00 SEG25 SEG26 SEG34
E1
FL DRIVER
6800P 6800P
no_use (HTR-5935 model)
Segment output circuit

dot data write
19 17 9
Page 72
CS 2 SCK 3 SDATA 4
Serial receive circuit
data
CGROM (35 bit x 16)
Code/ command control circuit
45 52 51
SEG35 DIG11/ SEG42 DIG12/ SEG41 DIG13/ SEG40 DIG14/ SEG39 DIG15/ SEG38 DIG16/ SEG37 DIG17/ SEG36 DIG00
code select
XIN
XOUT 6
Clock generator
timing clock
Display controller
scan pulse
Segment digit select/ output circuit
50 49 48 47 46
7
Digit output circuit
63
RESET 1 Vcc1 Vcc2 18 Vss 5 Vp 64

8
53
DIG10
OPERATION (5) OPERATION (3)
RX-V459/HTR-5940/ DSP-AX459 models HTR-5935 model
RX-V459/HTR-5940/DSP-AX459 models
IC302 : TC4013BP Dual D-type flip flop
OPERATION (2)
RESET1 4 SET1 6
100K
1 Q1 2 Q1
CL CL CL CL CL CL
HTR-5935 models
DATA1 5
Page 69
B5
Page 72
E7
CLOCK1 3
to DSP_CB5
RESET2 10 SET2 8 DATA2 9 CL CL CLOCK2 11 VSS 7 VDD 14
OPERATION (6)
13 Q2 12 Q2
CL CL CL CL
10
73
MAIN
MAIN (1)
FRONT L
1.1 59.9 1.1 0.6 59.9 0.6 0 59.9 59.8
Page 69
B9
to DSP_CB9
0.1
58.8 1.1 58.2 -0.4 1.0 -1.0 -1.0 0.1 0.6 59.6
HTR-5935 models: 100
Page 69
B9
to DSP_CB4
2
4.7/50
58.2
59.3 0
-0.5
0 -0.6 -0.6 0 -0.5 -0.5 -1.0 -1.0 -60.1 0 0 -57.2 -60.1 0.1 0
MAIN (5)
0.1 5.0 0 0 0 0.1
SUBWOOFER
Page 72 E8
-57.2 -57.7 -58.3
IC100, 102, 106 : NJM2388F Low dropout voltage regulator with ON/OFF control
Vin
1 2 Vout
0 0 0.1 0
58.8 58.2 1.1
0 0.1 59.9 0.6 0.6 0.1 -1.0 0 0.6 0.1 59.6 59.9 1.1 1.1 1.1
0.1
Page 72
E8
4.7/50
58.2
59.3 0 -0.4 -1.0 -0.6 0 -0.5
0.1
no use(RX-V459/DSP-AX459 models)
Bandgrap Reference ON/OFF control Over Voltage Protection Thermal Over Current Protection Protection
0 -0.6
Cont
0 -0.5 -1.0 -57.2 -57.2 -57.7 -58.3 36.8 36.8 36.8 36.8 36.8 -1.0 -60.1 -60.1 -0.5 0.1
GND
RX-V459/DSP-AX459 models
SURROUND BACK L/R
59.9 1.1 1.1 1.1 58.8 58.2 1.1 -0.4 -1.0 -1.0 0.6 59.9
10.0
10.2
36.8
8.2
0 0
59.6
10.0
0.6
4.7/50
0 -0.6 -0.6
4.8 4.3 4.8 -0.5 -1.0 -1.0 -60.1 -60.1 0 -57.7 -57.2 -0.5 0 0
10.2
58.2
59.3
4.8 4.3
8.2
4.2 0.1 0 4.8 4.2 10.5
-57.2 -58.3
CENTER
59.9 58.8 1.1 1.1 58.2 1.1 -0.4 -1.0 1.1 0.6 59.9 0.6 0 0 0 36.9 -0.6 0 0 0 0 -28.6 -60.1 -60.1 -29.2 0 -57.7 -57.2 36.9 36.9 -29.2 0.1 0 59.9 1.1 58.7 58.2 1.1 1.1 1.1 59.9 0.6 0.6 0 0 0 60.0 0 -60.1 59.6 0.1 36.9 0 -36.5 -37.5 0 59.6
58.2
4.7/50
59.5 0
-1.0
0 -0.6
-0.5 -1.0 -1.0 -57.2
-0.5
38.6
10.5
IC101: LM61CIZ Temperature sensor
IC103 : NJM79M05FA Voltage regulator

COMMON
AC56.7
SURROUND L/R
-58.3
to TRANSFORMER
OUTPUT
-0.4 -1.0 -1.0
6
4.7/50
58.2 0 -0.5
59.3 0 -0.5 0 0 -60.1 -60.1 0 -57.7 -57.2 -58.3
AC88.7
C5
INPUT
-1.0 -57.2 -1.0
Page 73
-0.5
-0.5
MAIN (4)
-58.2
4.7/50
1.1 1.1 1.1 -59.4 0 -1.0 -13.6 -0.4 -1.0
1.1 59.9 0.6 0.6 0 0 0 59.6
-0.1
-0.1
AC32.0
-59.1 -58.2
59.9
20.4
IC104 : NJM7812FA Voltage regulator

INPUT
0 -13.6
-21.1
AC19.8
30.4 20.4 -0.1 -0.1 -0.5 -1.0 -0.5 -1.0 -60.1 -57.7 0 -57.2 -57.2 -58.3 -13.6 -54.2 -14.1 -48.7 -59.4 -14.1 4.5 4.2 0 0 0 0 0 0 4.8 4.2 0.1 0.1 -16.9 0 -59.4 59.4 30.3 23.2 -21.0 0 -12.0 -60.1 20.4 0 11.9 0 -21.1 0 0 13.8 13.3
OUTPUT
AC23.1
COMMON
Page 71
D1
to DSP_CB57
Page 74
H9
IC105 : NJM79M12FA Voltage regulator

COMMON
to TRANSFORMER
to MAIN (1)_W1002A
11.2 5.0 0
11.2 5.0 0
-58.9
11.2 3.3 0
0.9
5.0
HTR-5935 model
-58.3 -60.1
Page 73
I3
OUTPUT
0
11.8 11.2 11.8 11.5
11.8 -12.9 0 -5.0
INPUT
5.0 0
9
Page 75 B4 Page 74 J8
MAIN (2)
IC107 : NJM2388F Low dropout voltage regulator with ON/OFF control

Vin
1 2 Vout
YST_CB500
to MAIN (2)_W1002B
Bandgrap Reference ON/OFF control Over Voltage Protection
Cont
Thermal Over Current Protection Protection
10
GND
74
YST
1
HTR-5935
SUBWOOFER
to MAIN (1)_CB101
Page 74
C9
YST
IC500 : NJM2068LD Dual operational-amplifier

V+
8
2, 6 INPUT +INPUT 3, 5
OUTPUT
1, 7
V
4
10
75
Service News
YAMAHA CORPORATION RX-V459/HTR-5940 HTR-5935 P.O. BOX1, HAMAMATSU, JAPAN
Audio
BULLETIN NO. DATE
RELATED BULLETIN NO.
E-1075
October 2006
Service Manual Correction

Please make the correction on your Service Manual as follows.
ERROR Page69
Contents: SCHEMATIC DAIGRAMS DSP 1/3 Location: IC2 (MICRO PROCESSOR) Port.120 Error Description: 2.7V
CORRECT
Correct Description: 1.8V

Yamaha RX v459, DSP Ax459, HTR 5935, HTR 5940

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Yamaha RX v459, DSP Ax459, HTR 5935, HTR 5940

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AV RECEIVER/AV AMPLIFIER

P.O.Box 1, Hamamatsu, Japan

I SELF DIAGNOSIS FUNCTION (DIAG)

MIC CHECK (Not applied to these models / ) DISPLAY CHECK

FACTORY PRESET AD DATA CHECK

VIDEO (Not applied to these models / )

ROM VER / SUM / PORT

XM STATUS (U,C models)

TI (DSP) BOOT ( Not applied to these models / )

Keys of main unit /

Turn on the power while pressing these keys.

Starting DIAG in the protection cancel mode

Display provided when DIAG started

When there is no history of protection function:

DIAG menu display /

After a few seconds

When there is a history of protection function:

History of protection function

No.9 PRESET RESERVED

Display during menu operation

Operation procedure of DIAG menu and SUB-MENU

DIAG menu selection

Keys of main unit /

Functions in DIAG mode

Initial settings used to start DIAG

Details of DIAG menu

Both ch, -20 dBm +6.0 dB DSP BYPASS

Both ch, -20 dBm +6.0 dB ANALOG BYPASS

(Shaded items not used in this example)

(Shaded items not used in this example)

SURROUND BACK +7.5 dB

SUBWOOFER OUTPUT +2.0 dBm

Both ch, -20 dBm +6.0 dB

2.RAM FULL BIT

SUBWOOFER OUTPUT +2.0 dBm

Both ch, -20 dBm +6.0 dB

SURROUND L/R SURROUND BACK L/R +13.5 dBm +13.5 dBm

(Shaded items not used in this example)

SUR. L/R LARGE LARGE SMALL

SUR.B L/R LARGE LARGE SMALL

LFE/BASS SWFR SWFR FRONT

LFE/B: FRNT (1 kHz) LFE/B: FRNT (50 Hz)

4 Pres Mix: 5ch 5 Front Gain 1 6 Front Gain 2 7 SURR B check

Both ch, -20 dBm +6.0 dB

XCH INPUT_8 (ohms)

XCH INPUT_8 ohms

Both ch, -20 dBm +6.0 dB

LIMIT SET Not applied to these models.

6.MIC CHK --dB

Checking FL display section / FL

All segments OFF /

All segments ON (dimmer 100%) / 100%

All segments ON (dimmer 50%) / 50%

Lighting of segments in lattice / Lighting in lattice /

10. AD DATA CHECK

10. AD DATA CHECK

PS1/PS2 PS1: 1766PS2: 2546 PS1+5S PS212V5V+5D+3.3D+5i PS 5V=100%

DC/TH/ DC DC 536 DC 5V=100% TH : 9177 5V=255

IMP SW/POWER LIMIT / IMP PL IC451 925V/256 IC451 92 3

PANEL KEY (K0/K1) A/D8 5V=100%

Display (%) 0-6 7 - 13 14 - 21 22 - 31 32 - 41 42 - 53 54 - 63 64 - 72 73 - 80 81 - 88 89 - 95 96 - 100

K1 MULTI CH INPUT FM/AM A/B/C/D/E PRESET PRESET MEMORY TUNING MODE