-R

http://www.mcst.ru

 SPARC
RISC
3
V7, V8: 32-
V9: 64-

SUN
Fujitsu
Gaisler Research

 MCST-R 1



SPARC
V8
RISC-
3-

32

32/64/128

 MCST-R 2

0.5, 3

0.35, 4

0.13, 8

1313

1010

55

, .

~2.1

~2.8

~4.2

80

150

500

Cache, I/D/L2(external)

4kB/8kB/512kB

8kB/16kB/1MB

16kB/32kB/4MB

, MIPS/MFLOPS

62/22

140/63

520/200

3.3

1.0/2.5

304-pin PQFP

480-pin BGA

376-pin BGA

1998

2001

2004

ATMEL ES2, France

Tower Semi, Israel

TSMC, Taiwan

 MCST-R 3

4 SPARC V8
: 0.50.13um
: 80500 MHz
V8: MCST R500S

( RISC)
: TSMC 0.13um LVLK
: 500 MHz

V9

1 GHz
ccNUMA

MCST-4R:
MCST-4R

CORE0

CORE1

CORE2

CORE3

L2

IS Link 0

IS Link 1

IS Link 2

System
Link
Controller 0

System
Link
Controller 1

System
Link
Controller 2

Coherency
Controller

Memory
Controller

Host
Bridge

IO Link
Controller

Switch
6x6

DDR2 SDRAM

4
2 Mb - L2

DDR2
4-
ccNUMA


( )

LVDS

IO Link

MCST-4R: SPARC

//

MCST-R
mx

mx

ADD

MUL

FRF

DC

ADD

DIV

CU

MMU

IU0

L2CI

IU1

RF

IU1
//

IC

L2 cache

SPARC V9
SIMD VIS

7-

IU0:

MCST-4R: 1

: 2

integer+integer
integer+memory
integer+floating point
integer+control transfer

//
L1

1
3
6

4
5
2
9
11/18
8

MCST-4R: 2
F0

F1

C0

fetch0

fetch1

decode

execute

cache0

C1
cache1

W
write-back
RF

RF

iDATA

dDATA
IQ

dTAG

iTAG

dTLB
iTLB
LSQ

BP

X0
FRF

X1

X2

X3

X4

W
FRF

MCST-4R:
64- , 40

-

L2

- MOESI L1
L2
L2 256
TLB
L1
L2
10

MCST-4R: - TLB

-:

Cache

L1I

L1D

L2

Size

16K

32K

2M

Block size

64

64

64

Protection

Parity

Parity

ECC

Policy

WB

WB

Associativity

32

TLB
TLB :

8

TLB :

11

MCST-4R: ccNUMA

ccNUMA
3- ,

16 ,

1GT
-


RDMA

MCST-4R
DDR2 SDRAM

DDR2 SDRAM
SPI

-4R

-4R

SOUTH
BRIDGE

SPD

Ethernet

-4R

-4R

SATA

USB
DDR2 SDRAM

DDR2 SDRAM
PCI-Express

PCI

12

Boot
PROM

MCST-4R: 1
: Standard cell, Synopsys
:
5 (4 1
)
3 (2 1 )

1 GHz

RTL
(
- )

(
FPU)
//
13

MCST-4R: 2

Deterministic fractional ratio clocking for DDR2

Other domains have integer clock ratio

LVDS DLL
DLL standard cell, SPICE

: 7.6 mm
: ~115 mm

14

MCST-4R:

RTL
FPGA

-

DUT2(tu)

tracer

iq_model

DUT1(ic)

bp_model

mu_model

code
array

testbench

15

MCST-4R: FPGA
FPGA ALTERA Stratix2
10 FPGA :

4 : MCST-R ( )
4 : L2
1 :
1 :

:

( L2)

: 50 MHz
Linux
FPGA : Linux
L2 FPU
16

MCST-4R:

JTAG







( )

MCST-4R JTAG

17

MCST-4R:
/++
-, -
VLIW
,
VLIW
VIS


, - GCC

Linux-SPARC64 MCST-4R

18


1 GHz TSMC 90nm standard cell

2010 .

19


,
,

20