Single Chip Encryptor/Decryptor Core

Implementation oI AES Algorithm

ABSTRACT
This paper presents a single chip encryptor/ decryptor core implementation oI Advanced
Encryption Standard (AES-Rijndael) cryptosystem. The suggested architecture is capable oI
handling all possible combinations oI standard bit lengths (128,192,256) oI data and key. The
Iully rolled innerpipelined architecture ensures lesser hardware complexity. The architecture
does reutilize precomputed blocks, in the sense that the same hardware is shared during
encryption and decryption as much as possible. The design has been implemented on Xilinx
XCVe1000-8bg560 device. The perIormance oI the architecture has been compared with existing
results in the literature and has been Iound to be the most eIIicient (throughput/area)
implementation oI the AES algorithm
Project overview:
1. Behavioral/RTL modeling oI Design blocks.
2. Design oI stimulus modules to test the Iunctionality oI Design blocks.
3. Synthesizes design to extract Gate level net list.
Tools used:
or simulation--------------------------Modelsim SE 6.3I
or synthesis----------------------------Xilinx ISE 9.2i
ardware used--------------------------Spartan 3E