BTS

(C) IV

(S)

11

002

B.Tech Degree IV Semester (Sapplementarf Examination January 2011

EE 402
Time : 3 Hours PART - A (Answer ZE! questiont
Subtract using 2's conplement

LOGIC DESIGN
Ma-ximurn Ma.ks : 100

(2006Schede)

(8x5=

40)

G)
(b) (c) (d)
(e)

(D

1001 1.1011-

1001.1100

(iD

(Dse2),-(2D21),

(0
(c) (h)

Design and set up a 4 : I MUX using gates. Design and implement a half adder cirouir. Explain carry look ahead adder Cornpare PLA and PAL Wdte notes on EPROM and EEPROM Define fan - in and fan out What is lristat logic?

PART _ B

It.

(a)

(4x15=60)
convert

o
o)
III-

(378.93)10 ro

octar

(iD
OR

(259s.675)," to

h*

(5) (10)

Design and sel up a BCD to Excess 3 converterReduce the tuncrion

zn

(1,4,6,7,9,11,12,13,16,17,22,24,25,26,30)
(lS)

using Quine -Mclusky

method. gales.
OR

ry. v.
vL VII' Vn.

(a)

(b)
(a)

Explain a serial Explain astable and monostable multivibrators using

adder.

(5)

(r0)
(5) (10) (5)

(b)
(a)

(b)

multiplication. gates. Compare conbinational and sequenlial circuits. What is Raca dound condition? How can we eliminate it? Witb a neat diasram explain JK Mrsrer Srave nip nop.
Explain any one method ofbinary Design and irnpleme.t a tull adder circuit usingNAND

(t0)
(5)

OR
(a)

List the differences between synchronous countrs and as),nchronous

Design and set up a mod

(b) (a) (b)

(a)

l2

synohronous counter usjng JK

flip

couniers. flop. gate.

00)
(s) (10) (5) 0 0)

Explain a 2 input CMOS NOR Wha. is interfacing? Explair how CMOS gate can be interfaced with TTL Explain sourcing and sinking Explain TTL NAND gate using Tolrn

sare.

rx.

currnts.
,
pole

OR

o)

configuration.