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Circuit Analysis I

FE Examination
Preparation Courses
Engineering and Science Services
The American University in Cairo
Hanna Kirolous, 2009
Circuit Analysis I FE-Exam
Course Outline
Introduction
1
Voltage, Current, Energy and Power
Voltage and Current Sources
Basic circuits laws
Simple resistive circuits
Techniques of Circuit Analysis 2
Mesh-current method
Node-voltage method
Thevenin's theorem
Norton's theorem
maximum power transfer theorem
Inductive and Capacitive Circuits. 3
Transients in RC and RL Circuits.
4
Basic Concepts of AC Analysis and Phasors.
5
Circuit Analysis I FE-Exam
Course Outline
Power and Energy: 1
t d
W d
P =
Watts
Joules
t d
q d
q d
W d
P =
Voltage
(VOLTS)
Current
(AMPERES)
I V P =
Circuit Analysis I FE-Exam
Introduction
Voltage and Current: 2
E
q
I
+
V
Circuit Analysis I FE-Exam
Introduction
Voltage and Current Sources: 3
E
q
I
+
V
+
s
V
Circuit Analysis I FE-Exam
Introduction
Ideal Voltage Source:
+

s
V
s
I
Ideal Current Source:
Independent Ideal Sources:
Circuit Analysis I FE-Exam
Introduction
Ideal Voltage-Controlled
Voltage Source:
x s
V V =
Dependent Ideal Sources:
+

x s
I V =
+

Ideal Current-Controlled
Voltage Source:
Circuit Analysis I FE-Exam
Introduction
Ideal Voltage-Controlled
Current Source:
x s
V I o =
Dependent Ideal Sources:
x s
I I | =
Ideal Current-Controlled
Current Source:
Circuit Analysis I FE-Exam
Introduction
Basic Circuits Laws: (Ohms Law) 4
I
+

V R
R I V =
I
+

V R
R I V =
R
V
R I I V P
2
2
= = =
Circuit Analysis I FE-Exam
Basic Laws
Basic Circuits Laws: (Kirchhoffs Laws) 4
c
I
+
s
V
g
R
g g g
R I V =
L
I
+

L
V
c
R
L
R
c
V
g
I
+
g
V
a b
c
c c c
R I V =
L L L
R I V =
s
I
Circuit Analysis I FE-Exam
Basic Laws
Basic Circuits Laws: (Kirchhoffs Laws) 4
Kirchhoffs Current Law:
The algebraic sum of all the currents at any node in a circuit
equals zero
Kirchhoffs Voltage Law:
The algebraic sum of all the voltages around any closed
path in a circuit equals zero
Circuit Analysis I FE-Exam
Basic Laws
Basic Circuits Laws: (Kirchhoffs Current Law) 4
c
I
+
s
V
g
R
0 =
c g
I I
L
I
+

L
V
c
R
L
R
c
V
g
I
+
g
V
a b
c
At node a
0 =
L c
I I
At node b
0 =
s L
I I
At node c
s
I
Circuit Analysis I FE-Exam
Basic Laws
Basic Circuits Laws: (Kirchhoffs Voltage Law) 4
c
I
+
s
V
g
R
0 =
L c g s
V V V V
L
I
+

L
V
c
R
L
R
c
V
g
I
+
g
V
a b
c
s
I
For Loop abca
Circuit Analysis I FE-Exam
Basic Laws
0
5 4 2 1
= + i i i i
Application on Kirchhoffs Current Law
0
3 2 1
= + +
b a
i i i i i
0
4 3
= +
c b
i i i i
0
5
= + +
c a
i i i
At node a
At node b
At node c
At node d
Circuit Analysis I FE-Exam
Basic Laws
0
3 4 2 1
= + + u u u u u
b
Application on Kirchhoffs Voltage Law
For loop a
For loop b
For loop c
For loop d
0
5 3
= + + u u u
a
0
5 6 4
= u u u u u
c b
0
7 2 1
= + +
d c a
u u u u u u
Circuit Analysis I FE-Exam
Basic Laws
o
i
Example 1:
a) Find
b) Check power
balance
For loop abca:
At node b:
0 6
1
= + i i
o
0 50 10 120
1
= + + i i
o
A i 3
1
= A i
o
3 =
W P
abs
900 3 150 3 30 3 120 = + + =
W P
del
900 6 150 = =
Circuit Analysis I FE-Exam
Basic Laws
o
u
Example 2:
Find
For loop abca:
At node b: 0 5 = +
A A o
i i i
o
i i 20 5 500 + =
A
A i 4 =
A
A i
o
24 =
A
= i i
o
6
V i
o o
480 20 = = u
Circuit Analysis I FE-Exam
Basic Laws
u
Example 3:
a) Find and
2 1 1
30 i i i = +
2
3
1
3
10 6 10 54 1 5 i i + = +
A i 25
1
=
1 2
31i i =
V 2 = u
1
i
b) Check power balance
+

+

+
2
i
3
1 1
10 ) 186 54 ( 6 + = i i
1
3
1
3
31 10 6 30 10 8 . 1 8 i i + = +u
Circuit Analysis I FE-Exam
Basic Laws
u
Example 3:
a) Find and
mW i i P
del
15 . 6 30 8 ) 1 5 (
1 1
= + + =
, 25
1
A i =
V 2 = u
1
i
b) Check power balance
+

+

+
2
i
mW
i i i i P
abs
15 . 6
30 2 ) 30 ( 10 8 . 1 ) 31 ( 10 6 10 54
1
2
1
3 2
1
3 2
1
3
=
+ + + =
Circuit Analysis I FE-Exam
Basic Laws
Simple Resistive Circuits
5
Resistors in Series
Resistors in Parallel
Voltage Dividers
Current Dividers
Circuit Analysis I FE-Exam
Resistive Circuits
Resistors in Series
2
I
+
s
V
1
R
eq s
R I R R R I V V V V = + + = + + = ) (
3 2 1 3 2 1
3
I
+

3
V
3
R
2
V
1
I
+
1
V
a b
c
I
2
R
I I I I = = =
3 2 1
eq
R
s
V

I
3 2 1
R R R R
eq
+ + =
Circuit Analysis I FE-Exam
Resistive Circuits
Resistors in Parallel
2
I
+

s
V
1
R
eq
s
R
V
R
V
R
V
R
V
I I I I = + + = + + =
3
3
2
2
1
1
3 2 1
3
I
+

3
V
3
R
2
V
1
I
+

1
V
I
2
R
s
V V V V = = =
3 2 1
eq
R
s
V

I
3 2 1
1 1 1 1
R R R R
eq
+ + =
Circuit Analysis I FE-Exam
Resistive Circuits
Resistors in Parallel (special case)
1
R
2 1
2 1
2 1
1 1 1
R R
R R
R R R
eq
+
=
+ =
2
R
eq
R
2 1
2 1
R R
R R
R
eq
+
=
Circuit Analysis I FE-Exam
Resistive Circuits
The Voltage Divider
1
R
2 1
R R
V
I
+
=
2
R
V
+

+
+

1
V
2
V
I
2 1
1
1 1
R R
R
V R I V
+
= =
2 1
2
2 2
R R
R
V R I V
+
= =
Circuit Analysis I FE-Exam
Resistive Circuits
1
R
2 1
2 1
R R
R R
I R I V
eq
+
= =
2
R
The Current Divider
I
1
I
2
I
V
+

2 1
2
1 2 1
2 1
1
1
1
R R
R
I
R R R
R R
I
R
V
I
+
=
+
= =
2 1
1
2 2 1
2 1
2
2
1
R R
R
I
R R R
R R
I
R
V
I
+
=
+
= =
Circuit Analysis I FE-Exam
Resistive Circuits
c) Power dissipated by the resistor
u
Example:
a) Find
b) Power delivered by the
source
V 60 12 5 = = u
O 10
u
+

u
+

W P
del
300 60 5 = =
Circuit Analysis I FE-Exam
Resistive Circuits
Example:
A I 3
30 20
30
5
1
=
+
=
c) Power dissipated by the
resistor
O 10
u
+

1
I
1
I
2
I
1
I
2
I A I 4 . 2
16 64
64
3
2
=
+
=
W I P 6 . 57 10 ) 4 . 2 ( ) 10 (
2 2
2 10
= = =
O
Circuit Analysis I FE-Exam
Resistive Circuits
Circuit Analysis I FE-Exam
Capacitance & Inductance
The Capacitor
u Q
d
A
c
+

u
Q
Q
u C Q =
Capacitance in Farad
For a parallel-plate Capacitor
d
A
C
c
=
Circuit Analysis I FE-Exam
Capacitance & Inductance
The Capacitor as a circuit element
u C Q =
Capacitors can NOT conduct DC current
Voltage across a capacitor can NOT
change instantaneously
t d
d
C
t d
Q d
i
u
= =
t d t i d C ) ( = u
t d t i
C
d
t t
} }
=
0
) (
) 0 (
) (
1
u
u
u ) 0 ( ) (
1
) (
0
u u + =
}
t d t i
C
t
t
Power and energy in a Capacitor
u i p =
t d
d
C i p
u
u u = =
(
(

+ =
}
) 0 ( ) (
1
) (
0
u t d t i
C
i t p
t
t d
C d
2
2
1 u
=
t d
C d
t d
w d
p
2
2
1 u
= =
2
2
1
u C w=
Circuit Analysis I FE-Exam
Capacitance & Inductance
The Inductor
t d
i d
t d
d
=
|
u
Inductance in Henrys
Faradays Law
t d
i d
L = u
Circuit Analysis I FE-Exam
Capacitance & Inductance
Transformers
Circuit Analysis I FE-Exam
Capacitance & Inductance
The Inductor as a circuit element
For DC current inductor is short-circuit
Current in an inductor can NOT change
instantaneously
dt i d L u =
t d t
L
i d
t t i
i
} }
=
0
) (
) 0 (
) (
1
u ) 0 ( ) (
1
) (
0
i t d t
L
t i
t
+ =
}
u
t d
i d
L = u
Circuit Analysis I FE-Exam
Capacitance & Inductance
Power and energy in an Inductor
u i p =
t d
i d
i L i p = = u
t d
i L d
2
2
1
=
t d
Li d
t d
w d
p
2
2
1
= =
2
2
1
i L w=
(
(

+ = =
}
) 0 ( ) (
1
) ( ) (
0
i t d t
L
t i t p
t
u u u
Circuit Analysis I FE-Exam
Capacitance & Inductance
Inductors in series
3 2 1
u u u u + + =
dt
di
L
dt
di
L
dt
di
L
3 2 1
+ + =
dt
di
L L L ) (
3 2 1
+ + =
dt
di
L
eq
=
3 2 1
L L L L
eq
+ + =
Circuit Analysis I FE-Exam
Capacitance & Inductance
Inductors in series
Circuit Analysis I FE-Exam
Capacitance & Inductance
Inductors in parallel
3 2 1
i i i i + + =
) 0 ( ) (
1
) 0 ( ) (
1
) 0 ( ) (
1
3
0
3
2
0
2
1
0
1
i dt t
L
i dt t
L
i dt t
L
t t t
+ + + + + =
} } }
u u u
| | ) 0 ( ) 0 ( ) 0 ( ) (
1 1 1
3 2 1
0
3 2 1
i i i dt t
L L L
t
+ + +
|
|
.
|

\
|
+ + =
}
u
) 0 ( ) (
1
0
i dt t
L
t
eq
+ =
}
u
3 2 1
1 1 1 1
L L L L
eq
+ + =
Circuit Analysis I FE-Exam
Capacitance & Inductance
Inductors in parallel
Circuit Analysis I FE-Exam
Capacitance & Inductance
Capacitors in series
Circuit Analysis I FE-Exam
Capacitance & Inductance
Capacitors in parallel
Circuit Analysis I FE-Exam
Capacitance & Inductance
Mutual Inductance
Circuit Analysis I FE-Exam
Capacitance & Inductance
Current & Dot Convention of Mutually coupled coils
When the reference Currents leave (or enter) the dots in
both coils they induce voltages of the same polarity as the
self inductance
Circuit Analysis I FE-Exam
Capacitance & Inductance
Dot Convention
Circuit Analysis I FE-Exam
Capacitance & Inductance
Current & Dot Convention of Mutually coupled coils
t d
i d
M
t d
i d
L R i
g
2 1
1 1 1
+ = u
t d
i d
M
t d
i d
L R i
1 2
2 2 2
0 + =
Circuit Analysis I FE-Exam
Capacitance & Inductance
Energy Calculations
2 1
2
2 2
2
1 1
2
1
2
1
) ( i i M i L i L t w + + =
Circuit Analysis I FE-Exam
Capacitance & Inductance
Circuit Analysis I FE-Exam
RL & RC Responses
RL & RC
Responses
Natural
Response
Step
Response
General
Method
The Natural Response of an RL Circuit
0 = + R i
t d
i d
L t d
L
R
i
i d
=
} }
=
t t i
i
t d
L
R
i
i d
0
) (
) 0 (
t
L
R
i
t i
i
=
) (
) 0 (
ln
For 0 > t
Circuit Analysis I FE-Exam
RL & RC Responses
The Natural Response of an RL Circuit
t
L
R
i
t i
i
=
) (
) 0 (
ln t
L
R
i
t i
=
) 0 (
) (
ln
t
L
R
e i t i

= ) 0 ( ) (
Circuit Analysis I FE-Exam
RL & RC Responses
The Natural Response of an RL Circuit
t
L
R
e i t i

= ) 0 ( ) (
) 0 ( i
Circuit Analysis I FE-Exam
RL & RC Responses
) 0 ( i
The Natural Response of an RL Circuit
t
L
R
e i t i

= ) 0 ( ) (
R i = u

>
s
=

0 ) 0 (
0 0
t e R i
t
t
L
R
R i ) 0 (
) (t u
Circuit Analysis I FE-Exam
RL & RC Responses
) 0 ( i
The time-constant of an RL Circuit

>
s
=

0 ) 0 (
0 0
) (
t e R i
t
t
t
L
R
u

>
s
=

0 ) 0 (
0 ) 0 (
) (
t e i
t i
t i
t
L
R
R
L
= Constant Time t

>
s
=

0 ) 0 (
0 ) 0 (
) (
/
t e i
t i
t i
t t

>
s
=

0 ) 0 (
0 0
) (
/
t e R i
t
t
t t
u
Circuit Analysis I FE-Exam
RL & RC Responses
The switch has been closed for a long time before it is opened at t=0. Find:
Example:
0 for ) ( and ) ( ), ( > t t t i t i
o o L
u
Circuit Analysis I FE-Exam
RL & RC Responses
Example:
O 10 40 10 2 0 = + = > // R t for
eq
Circuit Analysis I FE-Exam
RL & RC Responses
A 20 ) ( i
L
=
+
0
s . R / L
eq
2 0 = = t
A e 20 e ) ( i ) t ( i
-5t -t/
L L
= =
t
0
A e 4 i ) t ( i
5t -
L o
=
+
=
40 10
10
V e 1 ) t ( i ) t (
-5t
o o
60 40 = = u
The Natural Response of an RC Circuit
0 = +
R t d
d
C
u u
t d
RC
d 1
=
u
u
} }
=
t t
t d
RC
d
0
) (
) 0 (
1
u
u
u
u
t
RC
t
1
ln
) (
) 0 (
=
u
u
u
For 0 > t
Circuit Analysis I FE-Exam
RL & RC Responses
The Natural Response of an RL Circuit
t
RC
t 1
) 0 (
) (
ln =
u
u
t
RC
e t
1
) 0 ( ) (

=u u
t
RC
t
1
ln
) (
) 0 (
=
u
u
u
RC = Constant Time t
t
u u
/
) 0 ( ) (
t
e t

=
Circuit Analysis I FE-Exam
RL & RC Responses
The Natural Response of an RL Circuit
t
u u
/
) 0 ( ) (
t
e t

=
) 0 ( u
) (t u
Circuit Analysis I FE-Exam
RL & RC Responses
The switch has been closed for a long time before it is opened at t=0. Find:
The expression for for
Example:
) (t u
0 > t
Circuit Analysis I FE-Exam
RL & RC Responses
Example:
V ) ( i ) (
2
200 50 0 0 = =
+ +
u
0 > t
Circuit Analysis I FE-Exam
RL & RC Responses
2
i
mA . ) ( i 4
50 20 80
80
5 7 0
2
=
+ +
=
+
ms . C R 20 10 4 0 10 50
6 3
= = =

t
, V e e ) ( ) t (
t / t 50
200 0
+
= =
t
u u
The Step Response of an RL Circuit
t /
) 0 ( ) (
t
s s
e
R
V
i
R
V
t i

|
.
|

\
|
+ =
Circuit Analysis I FE-Exam
RL & RC Responses
The Step Response of an RL Circuit
|
.
|

\
|

=
t /
1 ) (
t
e
R
V
t i
s
0 ) 0 ( = i For
Circuit Analysis I FE-Exam
RL & RC Responses
The Step Response of an RL Circuit
dt
di
L ) t ( = u
t /
) 0 ( ) (
t
s s
e
R
V
i
R
V
t i

|
.
|

\
|
+ =
( )
t
u
/
) 0 ( ) (
t
s
e R i V t

=
Circuit Analysis I FE-Exam
RL & RC Responses
The Step Response of an RC Circuit
RC = t
( )
t
u u
/
) 0 (
t
s C s C
e R I R I

+ =
Circuit Analysis I FE-Exam
RL & RC Responses
The Step Response of an RC Circuit
For 0 > t
RC = t
( )
t
u u
/
) 0 (
t
s C s C
e R I R I

+ =
dt
d
C i
C
u
=
t
u
/
) 0 (
) (
t
C
s
e
R
I t i

|
.
|

\
|
= For
+
> 0 t
Circuit Analysis I FE-Exam
RL & RC Responses
General Solution for Step & Natural Responses:
t /
) 0 ( ) (
t
TH
TH
TH
TH
e
R
V
i
R
V
t i
+
|
|
.
|

\
|
+ =
( )
t
u u
/
) 0 (
t
TH C TH C
e V V
+
+ =
TH
R L/ = t C R
TH
= t
Circuit Analysis I FE-Exam
RL & RC Responses
General Solution for Step & Natural Responses:
t / ) (
) ( ) (
o
t t
TH
TH
o
TH
TH
e
R
V
t i
R
V
t i

|
|
.
|

\
|
+ = ( )
t
u u
/ ) (
) (
o
t t
TH o C TH C
e V t V

+ =
When switching occurs at
o
t t =
final
i
final
i initial
i
final
u
final
u
initial
u
( )
t / ) (
) ( ) (
o
t t
f o f
e x t x x t x

+ =
Circuit Analysis I FE-Exam
RL & RC Responses
General Solution for Step & Natural Responses:
( )
t / ) (
) ( ) (
o
t t
f o f
e x t x x t x

+ =
Circuit Analysis I FE-Exam
RL & RC Responses
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
The Sinusoidal Voltage Signal
( ) | e u + = t V
m
cos
Amplitude
Period
Angular Frequency (rad/s)
Phase Angle
T
f
1
=
f t e 2 =
The Sinusoidal Voltage Signal
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
The Root Mean Square (rms)
( ) | e u + = t V
m
cos
( )
}
+ =
T
m rms
t d t V
T
V
0
2 2
cos
1
| e
2
m
rms
V
V =
For a sinusoidal Signal:
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
The Phasor
( ) | e u + = t V
m
cos
Amplitude
u u
u
sin cos j e
j
+ =
{ }
u
u
j
e 9 = cos
( )
{ }
| e
u
+
9 =
t j
m
e V
{ }
| e j t j
m
e e V 9 =
| j
m
e V V
Eulers Identity:
We Define phasor voltage:
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
The Phasor
( ) | e u + = t V
m
cos
Sinusoidal Form in time domain
| j
m
e V V
Phasor Form in Complex
(frequency) Domain
( )

20 10 cos 10
5
+ = t u

20
10
j
e V
| Z =
m
V

20 10Z =
( )

20 10 sin 10
5
+ = t u

70
10
j
e V


70 10 Z =
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
The Phasor Forms
| j
m
e V V
Phasor in Polar Form
| Z =
m
V
Phasor in Rectangular Form
| | sin cos
m m
jV V V + =
m
V
|
9

Phasor Diagram
| cos
m
V
| sin
m
V
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Inverse Phasor Transform
| j
m
e V V
To retrieve time domain voltage from frequency domain form
| Z =
m
V
( ) | e + = t V
m
cos
| j
m
e V
t j
e
e
{ 9
}
= ) (t u
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Circuit Elements in Frequency Domain
I. Resistors:
V
|
9

R I V =
I
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Circuit Elements in Frequency Domain
II. Inductors:
I L j V e =
|
9

I
V
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Circuit Elements in Frequency Domain
III. Capacitors:
V
|
9

I
I
C j
V
e
1
=
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Impedance
Impedance
X j R Z + =
I Z V =
Resistance Reactance
I
V
+

Z
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Impedance
Impedance
I Z V =
Resistance Reactance
I
V
+

Z
Resistor
Inductor
Capacitor
R
R
0
L j e
0
L e
C j e
1
C e
1
0
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Admittance
Admittance
B j G Y + =
V Y I =
Conductance Susceptance
I
V
+

Y
Z
Y
1
=
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Admittance
Admittance
Z
Y
1
=
Conductance Susceptance
I
V
+

Y
Resistor
Inductor
Capacitor
R
1
0
L j e
1
R
G
1
=
L e
1
C j e
0
0
C e
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Impedance
( ) V 25 4000 cos 30 ) (

+ = t t u
Find:
) (t i

25 30Z = V
O =

=

50
10 5 4000
6
j
j
C
j
Z
e

115 6 . 0
90 50
25 30
Z =
Z
Z
= =
Z
V
I
( ) A 115 4000 cos 6 . 0 ) (

+ = t t i
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Kirchhoffs Laws
Time Domain Frequency Domain
Voltage Law
Current Law
0
2 1
= + + +
n
u u u 0
2 1
= + + +
n
V V V
0
2 1
= + + +
n
i i i 0
2 1
= + + +
n
I I I
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis
Series & Parallel Simplifications
I Z V
ab ab
=
n
Z Z Z Z + + + =
2 1 ab
I Z V
eq ab
=
n
Z Z Z Z
1 1 1 1
2 1 ab
+ + + =
n
Y Y Y Y + + + =
2 1 ab
Circuit Analysis I FE-Exam
Sinusoidal Steady-State Analysis

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