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  • Presentation 1

    Загружено:

    Marinescu Alexandru
    2 просмотров13 страниц
    UNIVERSITATEA 3POLITEHNICA' DIN TIMI OARA FACULTATEA DE ELECTRONIC I TELECOMUNICA II Etape Spectrum Design Architect ic layout Spectrum Load technology Optimeze Set constrains Optimize timing Spectrum Report delay Design Architect file > Import Verilog Open schematic Simulation Create viewpoint Adk_dve 11 January 2012 Design Architect Generate simbol Prepare for layout Check and save ic layout.

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    UNIVERSITATEA 3POLITEHNICA' DIN TIMI OARA FACULTATEA DE ELECTRONIC I TELECOMUNICA II Etape Spectrum Design Architect ic layout Spectrum Load technology Optimeze Set constrains Optimize timing Spectrum Report delay Design Architect file > Import Verilog Open schematic Simulation Create viewpoint Adk_dve 11 January 2012 Design Architect Generate simbol Prepare for layout Check and save ic layout.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PPTX, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    2 просмотров13 страниц

    Presentation 1

    Загружено:

    Marinescu Alexandru
    UNIVERSITATEA 3POLITEHNICA' DIN TIMI OARA FACULTATEA DE ELECTRONIC I TELECOMUNICA II Etape Spectrum Design Architect ic layout Spectrum Load technology Optimeze Set constrains Optimize timing Spectrum Report delay Design Architect file > Import Verilog Open schematic Simulation Create viewpoint Adk_dve 11 January 2012 Design Architect Generate simbol Prepare for layout Check and save ic layout.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PPTX, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 13

    UNIVERSITATEA POLITEHNICA DIN TIMI OARA FACULTATEA DE ELECTRONIC I TELECOMUNICA II

    TIMISOARA
    11 January 2012

    obiectiv

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    Interfata Rs232
     uPC Interface  TX:

    - TX data; - TX request; - TX end of send; RX: - RX data; - RX data ready (data valid);

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    Etape
    Spectrum

    Design Architect

    IC layout

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    Spectrum Load technology Optimeze Set constrains


    Optimize timing

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    Spectrum Report delay

    Generate verilog netlist

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    Design architect
    File > Import Verilog Open schematic

    Simulation Create viewpoint Adk_dve


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    Design architect
    Generate simbol

    Prepare for layout

    Check and save

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    IC layout
    Create a std-cell based logic block in IC Station
     

    Invoke: adk_ic In IC Station palette, select:Create Cell Cell name:cell1 Attach library: ADK/technology/ic/process/tsmc035 Process: ADK/technology/ic/process/tsmc035 Rules file: ADK/technology/ic/process/tsmc035.rul es

    EDDM schematic viewpoint: rs232/layout

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    IC layout

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    Ic layout

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    Va multumesc pentru atentie

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    13

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