Motorola Semiconductor Technical Data CPU12 Reference Guide: Order This Document by CPU12RG/D Rev. 1

Motorola Semiconductor Technical Data CPU12 Reference Guide
7 15
0 7 D
0 0
8-BIT ACCUMULATORS A AND B

OR
16-BIT DOUBLE ACCUMULATOR D
15
INDEX REGISTER X
15
INDEX REGISTER Y
15
SP
STACK POINTER
15
PC
PROGRAM COUNTER
S X H I N Z V C
CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE MASK (DISABLE) IRQ INTERRUPTS HALF-CARRY (USED IN BCD ARITHMETIC) MASK (DISABLE) XIRQ INTERRUPTS RESET OR XIRQ SET X, INSTRUCTIONS MAY CLEAR X BUT CANNOT SET X STOP DISABLE (IGNORE STOP OPCODES) RESET DEFAULT IS 1
Figure 1. Programming Model
CPU12 MOTOROLA CPU12 Reference Guide
Reference Guide 1
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Order this document by CPU12RG/D Rev. 1
CPU12 Reference Guide R E Q U I R E D Stack and Memory Layout

SP BEFORE INTERRUPT RTNLO RTNHI HIGHER ADDRESSES
YLO
YHI XLO
A G R E E M E N T
XHI
A B SP AFTER INTERRUPT CCR LOWER ADDRESSES
STACK UPON ENTRY TO SERVICE ROUTINE IF SP WAS ODD BEFORE INTERRUPT SP +8 SP +6 SP +4 RTNLO YLO XLO A CCR RTNHI YHI XHI B SP +9 SP +7 SP +5 SP +3 SP +1 SP 1
STACK UPON ENTRY TO SERVICE ROUTINE IF SP WAS EVEN BEFORE INTERRUPT SP +9 SP +7 SP +5 SP +4 SP +1 SP 1 RTNHI YHI XHI B RTNLO YLO XLO A CCR SP +10 SP +8 SP +6 SP +4 SP +2 SP
SP +2 SP SP 2
Interrupt Vector Locations

$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFC0$FFF1 Power-On (POR) or External Reset Clock Monitor Reset Computer Operating Properly (COP Watchdog Reset Unimplemented Opcode Trap Software Interrupt Instruction (SWI) XIRQ IRQ Device-Specic Interrupt Sources
Reference Guide 2 CPU12 Reference Guide
CPU12 MOTOROLA
CPU12 Reference Guide
Notation Used in Instruction Set Summary

Explanation of Italic Expressions in Source Form Column
abc A or B or CCR abcdxys A or B or CCR or D or X or Y or SP. Some assemblers also allow T2 or T3. abd A or B or D abdxys A or B or D or X or Y or SP dxys D or X or Y or SP msk8 8-bit mask, some assemblers require # symbol before value opr16i 16-bit immediate value opr8a 8-bit address used with direct address mode opr16a 16-bit address value oprx0_xysp Indexed addressing postbyte code: oprx3,xys Predecrement X or Y or SP by 1 . . . 8 oprx3,+xys Preincrement X or Y or SP by 1 . . . 8 oprx3,xys Postdecrement X or Y or SP by 1 . . . 8 oprx3,xys+ Postincrement X or Y or SP by 1 . . . 8 oprx5,xysp 5-bit constant offset from X or Y or SP or PC abd,xysp Accumulator A or B or D offset from X or Y or SP or PC oprx3 Any positive integer 1 . . . 8 for pre/post increment/decrement oprx5 Any value in the range 16 . . . +15 oprx9 Any value in the range 256 . . . +255 oprx16 Any value in the range 32,768 . . . 65,535 page 8-bit value for PPAGE, some assemblers require # symbol before this value rel8 Label of branch destination within 256 to +255 locations rel9 Label of branch destination within 512 to +511 locations rel16 Any label within 64K memory space trapnum Any 8-bit value in the range $30-$39 or $40-$FF xys X or Y or SP xysp X or Y or SP or PC opr8i 8-bit immediate value
Reference Guide 3
A G R E E M E N T
R E Q U I R E D
CPU12 Reference Guide R E Q U I R E D

Address Modes IMM IDX Immediate Indexed (no extension bytes) includes: 5-bit constant offset Pre/post increment/decrement by 1 . . . 8 Accumulator A, B, or D offset IDX1 9-bit signed offset (1 extension byte) IDX2 16-bit signed offset (2 extension bytes) [D, IDX] Indexed indirect (accumulator D offset) [IDX2] Indexed indirect (16-bit offset) INH Inherent (no operands in object code) REL 2s complement relative offset (branches) Machine Coding
dd 8-bit direct address $0000 to $00FF. (High byte assumed to be $00). ee High-order byte of a 16-bit constant offset for indexed addressing. eb Exchange/Transfer post-byte. See Table 3 on page 23. ff Low-order eight bits of a 9-bit signed constant offset for indexed addressing, or low-order byte of a 16-bit constant offset for indexed addressing. hh High-order byte of a 16-bit extended address. ii 8-bit immediate data value. jj High-order byte of a 16-bit immediate data value. kk Low-order byte of a 16-bit immediate data value. lb Loop primitive (DBNE) post-byte. See Table 4 on page 24. ll Low-order byte of a 16-bit extended address. mm 8-bit immediate mask value for bit manipulation instructions. Set bits indicate bits to be affected. pg Program page (bank) number used in CALL instruction. qq High-order byte of a 16-bit relative offset for long branches. tn Trap number $30$39 or $40$FF. rr Signed relative offset $80 (128) to $7F (+127). Offset relative to the byte following the relative offset byte, or low-order byte of a 16-bit relative offset for long branches. xb Indexed addressing post-byte. See Table 1 on page 21 and Table 2 on page 22.
Reference Guide 4
A G R E E M E N T
CPU12 CPU12 Reference Guide MOTOROLA
Access Detail Each code letter equals one CPU cycle. Uppercase = 16-bit operation and lowercase = 8-bit operation. For complex sequences see the CPU12 Reference Manual (CPU12RM/AD).
f g I i n O Free cycle, CPU doesnt use bus Read PPAGE internally Read indirect pointer (indexed indirect) Read indirect PPAGE value (call indirect) Write PPAGE internally Optional program word fetch (P) if instruction is misaligned and has an odd number of bytes of object code otherwise, appears as a free cycle (f) Program word fetch (always an aligned word read) 8-bit data read 16-bit data read 8-bit stack write 16-bit stack write 8-bit data write 16-bit data write 8-bit stack read 16-bit stack read 16-bit vector fetch 8-bit conditional read (or free cycle) 16-bit conditional read (or free cycle) 8-bit conditional write Special Cases PPP/P Short branch, PPP if branch taken, P if not OPPP/OPO Long branch, OPPP if branch taken, OPO if not
Condition Codes Columns

0 1 ? ! Status bit not affected by operation. Status bit cleared by operation. Status bit set by operation. Status bit affected by operation. Status bit may be cleared or remain set, but is not set by operation. Status bit may be set or remain cleared, but is not cleared by operation. Status bit may be changed by operation but the final state is not defined. Status bit used for a special purpose.
Reference Guide 5
P r R s S w W u U V t T x
A G R E E M E N T
R E Q U I R E D
Instruction Set Summary

Source Form ABA ABX ABY ADCA #opr8i ADCA opr8a ADCA opr16a ADCA oprx0_xysp ADCA oprx9,xysp ADCA oprx16,xysp ADCA [D,xysp] ADCA [oprx16,xysp] ADCB #opr8i ADCB opr8a ADCB opr16a ADCB oprx0_xysp ADCB oprx9,xysp ADCB oprx16,xysp ADCB [D,xysp] ADCB [oprx16,xysp] ADDA #opr8i ADDA opr8a ADDA opr16a ADDA oprx0_xysp ADDA oprx9,xysp ADDA oprx16,xysp ADDA [D,xysp] ADDA [oprx16,xysp] ADDB #opr8i ADDB opr8a ADDB opr16a ADDB oprx0_xysp ADDB oprx9,xysp ADDB oprx16,xysp ADDB [D,xysp] ADDB [oprx16,xysp] ADDD #opr16i ADDD opr8a ADDD opr16a ADDD oprx0_xysp ADDD oprx9,xysp ADDD oprx16,xysp ADDD [D,xysp] ADDD [oprx16,xysp] ANDA #opr8i ANDA opr8a ANDA opr16a ANDA oprx0_xysp ANDA oprx9,xysp ANDA oprx16,xysp ANDA [D,xysp] ANDA [oprx16,xysp] ANDB #opr8i ANDB opr8a ANDB opr16a ANDB oprx0_xysp ANDB oprx9,xysp ANDB oprx16,xysp ANDB [D,xysp] ANDB [oprx16,xysp] Operation (A) + (B) A Add Accumulators A and B (B) + (X) X Translates to LEAX B,X (B) + (Y) Y Translates to LEAY B,Y (A) + (M) + C A Add with Carry to A Addr. Mode INH IDX IDX IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] Machine Coding (hex) 18 06 1A E5 19 ED 89 99 B9 A9 A9 A9 A9 A9 C9 D9 F9 E9 E9 E9 E9 E9 8B 9B BB AB AB AB AB AB CB DB FB EB EB EB EB EB C3 D3 F3 E3 E3 E3 E3 E3 84 94 B4 A4 A4 A4 A4 A4 C4 D4 F4 E4 E4 E4 E4 E4 ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb
OO PP1 PP1
Access Detail
S X H
ll ff ee ff ee ff
A G R E E M E N T
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP
(B) + (M) + C B Add with Carry to B
ll ff ee ff ee ff
(A) + (M) A Add without Carry to A
ll ff ee ff ee ff
(B) + (M) B Add without Carry to B
ll ff ee ff ee ff kk ll ff ee ff ee ff
(A:B) + (M:M+1) A:B Add 16-Bit to D (A:B)
(A) (M) A Logical And A with Memory
ll ff ee ff ee ff
(B) (M) B Logical And B with Memory
ll ff ee ff ee ff
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
CPU12 MOTOROLA
Instruction Set Summary (Continued)

Source Form ANDCC #opr8i ASL opr16a ASL oprx0_xysp ASL oprx9,xysp ASL oprx16,xysp ASL [D,xysp] ASL [oprx16,xysp] ASLA ASLB ASLD 0 C b7 A b0 b7 Arithmetic Shift Left Double ASR opr16a ASR oprx0_xysp ASR oprx9,xysp ASR oprx16,xysp ASR [D,xysp] ASR [oprx16,xysp] ASRA ASRB BCC rel8 BCLR opr8a, msk8 BCLR opr16a, msk8 BCLR oprx0_xysp, msk8 BCLR oprx9,xysp, msk8 BCLR oprx16,xysp, msk8 BCS rel8 BEQ rel8 BGE rel8 BGND BGT rel8 BHI rel8 BHS rel8 B b0 EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH REL DIR EXT IDX IDX1 IDX2 REL REL REL INH REL REL REL 77 67 67 67 67 67 47 57 hh xb xb xb xb xb ll ff ee ff ee ff
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O PPP/P1
Operation (CCR) (M) CCR Logical And CCR with Memory
Addr. Mode IMM EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH
Machine Coding (hex) 10 ii 78 68 68 68 68 68 48 58 59 hh xb xb xb xb xb ll ff ee ff ee ff

P
Access Detail
S X H
0 b7 C Arithmetic Shift Left b0
Arithmetic Shift Left Accumulator A Arithmetic Shift Left Accumulator B
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O O
b7 Arithmetic Shift Right
b0
Arithmetic Shift Right Accumulator A Arithmetic Shift Right Accumulator B Branch if Carry Clear (if C = 0) (M) (mm) M Clear Bit(s) in Memory
24 rr 4D 1D 0D 0D 0D dd hh xb xb xb mm ll mm mm ff mm ee ff mm
rPOw rPPw rPOw rPwP frPwOP PPP/P1 PPP/P1 PPP/P1
Branch if Carry Set (if C = 1) Branch if Equal (if Z = 1) Branch if Greater Than or Equal (if N V = 0) (signed) Place CPU in Background Mode see CPU12 Reference Manual Branch if Greater Than (if Z ' (N V) = 0) (signed) Branch if Higher (if C ' Z = 0) (unsigned) Branch if Higher or Same (if C = 0) (unsigned) same function as BCC (A) (M) Logical And A with Memory
25 rr 27 rr 2C rr 00 2E rr 22 rr 24 rr
VfPPP PPP/P1 PPP/P1 PPP/P1
BITA #opr8i BITA opr8a BITA opr16a BITA oprx0_xysp BITA oprx9,xysp BITA oprx16,xysp BITA [D,xysp] BITA [oprx16,xysp] BITB #opr8i BITB opr8a BITB opr16a BITB oprx0_xysp BITB oprx9,xysp BITB oprx16,xysp BITB [D,xysp] BITB [oprx16,xysp]
IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2]
85 95 B5 A5 A5 A5 A5 A5 C5 D5 F5 E5 E5 E5 E5 E5
ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb
ll ff ee ff ee ff
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP
(B) (M) Logical And B with Memory
ll ff ee ff ee ff
Notes: 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Reference Guide 7
A G R E E M E N T
R E Q U I R E D

Source Form BLE rel8 BLO rel8 Operation Branch if Less Than or Equal (if Z ' (N V) = 1) (signed) Branch if Lower (if C = 1) (unsigned) same function as BCS Branch if Lower or Same (if C ' Z = 1) (unsigned) Branch if Less Than (if N V = 1) (signed) Branch if Minus (if N = 1) Branch if Not Equal (if Z = 0) Branch if Plus (if N = 0) Branch Always (if 1 = 1) Branch if (M) (mm) = 0 (if All Selected Bit(s) Clear) Addr. Mode REL REL Machine Coding (hex) 2F rr 25 rr Access Detail
PPP/P1 PPP/P1
S X H
BLS rel8 BLT rel8 BMI rel8 BNE rel8
REL REL REL REL REL REL DIR EXT IDX IDX1 IDX2 REL DIR EXT IDX IDX1 IDX2 DIR EXT IDX IDX1 IDX2 REL
23 rr 2D rr 2B rr 26 rr 2A rr 20 rr 4F dd mm rr 1F hh ll mm rr 0F xb mm rr 0F xb ff mm rr 0F xb ee ff mm rr 21 rr 4E dd mm rr 1E hh ll mm rr 0E xb mm rr 0E xb ff mm rr 0E xb ee ff mm rr 4C 1C 0C 0C 0C dd hh xb xb xb mm ll mm mm ff mm ee ff mm
PPP/P1 PPP/P1 PPP/P1 PPP/P1 PPP/P1 PPP
A G R E E M E N T
BPL rel8 BRA rel8 BRCLR opr8a, msk8, rel8 BRCLR opr16a, msk8, rel8 BRCLR oprx0_xysp, msk8, rel8 BRCLR oprx9,xysp, msk8, rel8 BRCLR oprx16,xysp, msk8, rel8 BRN rel8 BRSET opr8, msk8, rel8 BRSET opr16a, msk8, rel8 BRSET oprx0_xysp, msk8, rel8 BRSET oprx9,xysp, msk8, rel8 BRSET oprx16,xysp, msk8, rel8 BSET opr8, msk8 BSET opr16a, msk8 BSET oprx0_xysp, msk8 BSET oprx9,xysp, msk8 BSET oprx16,xysp, msk8 BSR rel8
rPPP rfPPP rPPP rffPPP frPffPPP

P
Branch Never (if 1 = 0) Branch if (M) (mm) = 0 (if All Selected Bit(s) Set)
rPPP rfPPP rPPP rffPPP frPffPPP rPOw rPPw rPOw rPwP frPwOP
PPPS
(M) ' (mm) M Set Bit(s) in Memory
(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1) Subroutine address PC Branch to Subroutine
07 rr
BVC rel8 BVS rel8 CALL opr16a, page CALL oprx0_xysp, page CALL oprx9,xysp, page CALL oprx16,xysp, page CALL [D,xysp] CALL [oprx16, xysp]
Branch if Overflow Bit Clear (if V = 0) Branch if Overflow Bit Set (if V = 1) (SP) 2 SP; RTNH:RTNL M(SP):M(SP+1) (SP) 1 SP; (PPG) M(SP); pg PPAGE register; Program address PC Call subroutine in extended memory (Program may be located on another expansion memory page.) Indirect modes get program address and new pg value based on pointer.
REL REL EXT IDX IDX1 IDX2 [D,IDX] [IDX2]
28 rr 29 rr 4A 4B 4B 4B 4B 4B hh ll pg xb pg xb ff pg xb ee ff pg xb xb ee ff
PPP/P1 PPP/P1
gnfSsPPP gnfSsPPP gnfSsPPP fgnfSsPPP fIignSsPPP fIignSsPPP
CBA CLC CLI
(A) (B) Compare 8-Bit Accumulators 0C Translates to ANDCC #$FE 0I Translates to ANDCC #$EF (enables I-bit interrupts)
INH IMM IMM
18 17 10 FE 10 EF
OO
Notes 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
CPU12 MOTOROLA

Source Form CLR opr16a CLR oprx0_xysp CLR oprx9,xysp CLR oprx16,xysp CLR [D,xysp] CLR [oprx16,xysp] CLRA CLRB CLV CMPA #opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysp CMPA oprx9,xysp CMPA oprx16,xysp CMPA [D,xysp] CMPA [oprx16,xysp] CMPB #opr8i CMPB opr8a CMPB opr16a CMPB oprx0_xysp CMPB oprx9,xysp CMPB oprx16,xysp CMPB [D,xysp] CMPB [oprx16,xysp] COM opr16a COM oprx0_xysp COM oprx9,xysp COM oprx16,xysp COM [D,xysp] COM [oprx16,xysp] COMA COMB CPD #opr16i CPD opr8a CPD opr16a CPD oprx0_xysp CPD oprx9,xysp CPD oprx16,xysp CPD [D,xysp] CPD [oprx16,xysp] CPS #opr16i CPS opr8a CPS opr16a CPS oprx0_xysp CPS oprx9,xysp CPS oprx16,xysp CPS [D,xysp] CPS [oprx16,xysp] CPX #opr16i CPX opr8a CPX opr16a CPX oprx0_xysp CPX oprx9,xysp CPX oprx16,xysp CPX [D,xysp] CPX [oprx16,xysp] CPY #opr16i CPY opr8a CPY opr16a CPY oprx0_xysp CPY oprx9,xysp CPY oprx16,xysp CPY [D,xysp] CPY [oprx16,xysp] 0M Operation Clear Memory Location Addr. Mode EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IMM IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 79 69 69 69 69 69 87 C7 Machine Coding (hex) hh xb xb xb xb xb ll ff ee ff ee ff Access Detail
wOP Pw PwO PwP PIfPw PIPPw O O P
S X H
N 0
Z 1
V 0
C 0
0A 0B
Clear Accumulator A Clear Accumulator B
0V Translates to ANDCC #$FD (A) (M) Compare Accumulator A with Memory
10 FD 81 91 B1 A1 A1 A1 A1 A1 C1 D1 F1 E1 E1 E1 E1 E1 71 61 61 61 61 61 41 51 8C 9C BC AC AC AC AC AC 8F 9F BF AF AF AF AF AF 8E 9E BE AE AE AE AE AE 8D 9D BD AD AD AD AD AD ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb hh xb xb xb xb xb
ll ff ee ff ee ff
(B) (M) Compare Accumulator B with Memory
ll ff ee ff ee ff ll ff ee ff ee ff
P rfP rOP rfP rPO frPP fIfrfP fIPrfP rOPw rPw rPOw frPPw fIfrPw fIPrPw O O OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP
(M) M equivalent to $FF (M) M 1s Complement Memory Location
(A) A (B) B
Complement Accumulator A Complement Accumulator B
(A:B) (M:M+1) Compare D to Memory (16-Bit)
ff ee ff ee ff kk ll ff ee ff ee ff kk ll ff ee ff ee ff kk ll ff ee ff ee ff
(SP) (M:M+1) Compare SP to Memory (16-Bit)
jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb
(X) (M:M+1) Compare X to Memory (16-Bit)
(Y) (M:M+1) Compare Y to Memory (16-Bit)
Reference Guide 9
jj dd hh xb xb xb xb xb
kk ll
A G R E E M E N T
P rfP rOP rfP rPO frPP fIfrfP fIPrfP
R E Q U I R E D

Source Form DAA DBEQ abdxys, rel9 Operation Adjust Sum to BCD Decimal Adjust Accumulator A (cntr) 1 cntr if (cntr) = 0, then Branch else Continue to next instruction Decrement Counter and Branch if = 0 (cntr = A, B, D, X, Y, or SP) DBNE abdxys, rel9 (cntr) 1 cntr If (cntr) not = 0, then Branch; else Continue to next instruction Decrement Counter and Branch if 0 (cntr = A, B, D, X, Y, or SP) DEC opr16a DEC oprx0_xysp DEC oprx9,xysp DEC oprx16,xysp DEC [D,xysp] DEC [oprx16,xysp] DECA DECB DES DEX DEY EDIV EDIVS EMACS opr16a 2 (M) $01 M Decrement Memory Location EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IDX INH INH INH INH Special 73 63 63 63 63 63 43 53 hh xb xb xb xb xb ll ff ee ff ee ff
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O PP1
Addr. Mode INH REL (9-bit)
Machine Coding (hex) 18 07 04 lb rr
Access Detail
OfO
S X H
V ?
PPP
REL (9-bit)
04 lb rr
PPP
A G R E E M E N T
(A) $01 A (B) $01 B (SP) $0001 SP Translates to LEAS 1,SP
Decrement A Decrement B
1B 9F 09 03 11 18 14 18 12 hh ll
(X) $0001 X Decrement Index Register X (Y) $0001 Y Decrement Index Register Y (Y:D) (X) Y Remainder D 32 16 Bit 16 Bit Divide (unsigned) (Y:D) (X) Y Remainder D 32 16 Bit 16 Bit Divide (signed) (M(X):M(X+1)) (M(Y):M(Y+1)) + (M~M+3) M~M+3 16 16 Bit 32 Bit Multiply and Accumulate (signed)
ffffffffffO
OffffffffffO
ORROfffRRfWWP
EMAXD oprx0_xysp EMAXD oprx9,xysp EMAXD oprx16,xysp EMAXD [D,xysp] EMAXD [oprx16,xysp] EMAXM oprx0_xysp EMAXM oprx9,xysp EMAXM oprx16,xysp EMAXM [D,xysp] EMAXM [oprx16,xysp] EMIND oprx0_xysp EMIND oprx9,xysp EMIND oprx16,xysp EMIND [D,xysp] EMIND [oprx16,xysp] EMINM oprx0_xysp EMINM oprx9,xysp EMINM oprx16,xysp EMINM [D,xysp] EMINM [oprx16,xysp] EMUL
MAX((D), (M:M+1)) D MAX of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) MAX((D), (M:M+1)) M:M+1 MAX of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) MIN((D), (M:M+1)) D MIN of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) MIN((D), (M:M+1)) M:M+1 MIN of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) (D) (Y) Y:D 16 16 Bit Multiply (unsigned)
IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] INH
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 13
1A 1A 1A 1A 1A 1E 1E 1E 1E 1E 1B 1B 1B 1B 1B 1F 1F 1F 1F 1F
xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff
ORfP ORPO OfRPP OfIfRfP OfIPRfP ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ORfP ORPO OfRPP OfIfRfP OfIPRfP ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ffO
Notes 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. 2. opr16a is an extended address specification. Both X and Y point to source operands.
CPU12 MOTOROLA

Source Form EMULS EORA #opr8i EORA opr8a EORA opr16a EORA oprx0_xysp EORA oprx9,xysp EORA oprx16,xysp EORA [D,xysp] EORA [oprx16,xysp] EORB #opr8i EORB opr8a EORB opr16a EORB oprx0_xysp EORB oprx9,xysp EORB oprx16,xysp EORB [D,xysp] EORB [oprx16,xysp] ETBL oprx0_xysp Operation (D) (Y) Y:D 16 16 Bit Multiply (signed) (A) (M) A Exclusive-OR A with Memory Addr. Mode INH IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IDX Machine Coding (hex) 18 13 88 98 B8 A8 A8 A8 A8 A8 C8 D8 F8 E8 E8 E8 E8 E8 ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb Access Detail
OfO
S X H
V 0
ll ff ee ff ee ff
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP ORRffffffP
(B) (M) B Exclusive-OR B with Memory
ll ff ee ff ee ff
(M:M+1)+ [(B)((M+2:M+3) (M:M+1))] D 16-Bit Table Lookup and Interpolate Initialize B, and index before ETBL. <ea> points at first table entry (M:M+1) and B is fractional part of lookup value (no indirect addr. modes or extensions allowed)
18 3F xb
EXG abcdxys,abcdxys
(r1) (r2) (if r1 and r2 same size) or $00:(r1) r2 (if r1=8-bit; r2=16-bit) or (r1low) (r2) (if r1=16-bit; r2=8-bit) r1 and r2 may be A, B, CCR, D, X, Y, or SP
INH
B7 eb
FDIV IBEQ abdxys, rel9
(D) (X) X; Remainder D 16 16 Bit Fractional Divide (cntr) + 1 cntr If (cntr) = 0, then Branch else Continue to next instruction Increment Counter and Branch if = 0 (cntr = A, B, D, X, Y, or SP)
INH REL (9-bit)
18 11 04 lb rr
OffffffffffO
PPP
IBNE abdxys, rel9
(cntr) + 1 cntr if (cntr) not = 0, then Branch; else Continue to next instruction Increment Counter and Branch if 0 (cntr = A, B, D, X, Y, or SP)
REL (9-bit)
04 lb rr
PPP
IDIV IDIVS INC opr16a INC oprx0_xysp INC oprx9,xysp INC oprx16,xysp INC [D,xysp] INC [oprx16,xysp] INCA INCB INS INX INY
(D) (X) X; Remainder D 16 16 Bit Integer Divide (unsigned) (D) (X) X; Remainder D 16 16 Bit Integer Divide (signed) (M) + $01 M Increment Memory Byte
INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IDX INH INH
18 10 18 15 72 62 62 62 62 62 42 52 hh xb xb xb xb xb ll ff ee ff ee ff
OffffffffffO
OffffffffffO
(A) + $01 A (B) + $01 B (SP) + $0001 SP Translates to LEAS 1,SP (X) + $0001 X Increment Index Register X (Y) + $0001 Y Increment Index Register Y
Increment Acc. A Increment Acc. B
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O PP1
1B 81 08 02
Reference Guide 11
A G R E E M E N T
R E Q U I R E D

Source Form JMP opr16a JMP oprx0_xysp JMP oprx9,xysp JMP oprx16,xysp JMP [D,xysp] JMP [oprx16,xysp] JSR opr8a JSR opr16a JSR oprx0_xysp JSR oprx9,xysp JSR oprx16,xysp JSR [D,xysp] JSR [oprx16,xysp] LBCC rel16 LBCS rel16 LBEQ rel16 LBGE rel16 LBGT rel16 LBHI rel16 LBHS rel16 Operation Subroutine address PC Jump Addr. Mode EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] REL REL REL REL REL REL REL 06 05 05 05 05 05 17 16 15 15 15 15 15 Machine Coding (hex) hh xb xb xb xb xb dd hh xb xb xb xb xb ll ff ee ff ee ff ll ff ee ff ee ff Access Detail
PPP PPP PPP fPPP fIfPPP fIfPPP PPPS PPPS PPPS PPPS fPPPS fIfPPPS fIfPPPS OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1
S X H
(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); Subroutine address PC Jump to Subroutine
A G R E E M E N T
Long Branch if Carry Clear (if C = 0) Long Branch if Carry Set (if C = 1) Long Branch if Equal (if Z = 1) Long Branch Greater Than or Equal (if N V = 0) (signed) Long Branch if Greater Than (if Z ' (N V) = 0) (signed) Long Branch if Higher (if C ' Z = 0) (unsigned) Long Branch if Higher or Same (if C = 0) (unsigned) same function as LBCC Long Branch if Less Than or Equal (if Z ' (N V) = 1) (signed) Long Branch if Lower (if C = 1) (unsigned) same function as LBCS Long Branch if Lower or Same (if C ' Z = 1) (unsigned) Long Branch if Less Than (if N V = 1) (signed) Long Branch if Minus (if N = 1) Long Branch if Not Equal (if Z = 0) Long Branch if Plus (if N = 0) Long Branch Always (if 1=1) Long Branch Never (if 1 = 0) Long Branch if Overflow Bit Clear (if V=0) Long Branch if Overflow Bit Set (if V = 1) (M) A Load Accumulator A
18 24 qq rr 18 25 qq rr 18 27 qq rr 18 2C qq rr 18 2E qq rr 18 22 qq rr 18 24 qq rr
LBLE rel16 LBLO rel16
REL REL
18 2F qq rr 18 25 qq rr
OPPP/OPO1 OPPP/OPO1
LBLS rel16
REL REL REL REL REL REL REL REL REL IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2]
18 23 qq rr 18 2D qq rr 18 2B qq rr 18 26 qq rr 18 2A qq rr 18 20 qq rr 18 21 qq rr 18 28 qq rr 18 29 qq rr 86 96 B6 A6 A6 A6 A6 A6 C6 D6 F6 E6 E6 E6 E6 E6 ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb
OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP OPO OPPP/OPO1 OPPP/OPO1 P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP
LBLT rel16 LBMI rel16 LBNE rel16 LBPL rel16 LBRA rel16 LBRN rel16 LBVC rel16 LBVS rel16 LDAA #opr8i LDAA opr8a LDAA opr16a LDAA oprx0_xysp LDAA oprx9,xysp LDAA oprx16,xysp LDAA [D,xysp] LDAA [oprx16,xysp] LDAB #opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysp LDAB oprx9,xysp LDAB oprx16,xysp LDAB [D,xysp] LDAB [oprx16,xysp]
ll ff ee ff ee ff
(M) B Load Accumulator B
ll ff ee ff ee ff
Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
CPU12 MOTOROLA

Source Form LDD #opr16i LDD opr8a LDD opr16a LDD oprx0_xysp LDD oprx9,xysp LDD oprx16,xysp LDD [D,xysp] LDD [oprx16,xysp] LDS #opr16i LDS opr8a LDS opr16a LDS oprx0_xysp LDS oprx9,xysp LDS oprx16,xysp LDS [D,xysp] LDS [oprx16,xysp] LDX #opr16i LDX opr8a LDX opr16a LDX oprx0_xysp LDX oprx9,xysp LDX oprx16,xysp LDX [D,xysp] LDX [oprx16,xysp] LDY #opr16i LDY opr8a LDY opr16a LDY oprx0_xysp LDY oprx9,xysp LDY oprx16,xysp LDY [D,xysp] LDY [oprx16,xysp] LEAS oprx0_xysp LEAS oprx9,xysp LEAS oprx16,xysp LEAX oprx0_xysp LEAX oprx9,xysp LEAX oprx16,xysp LEAY oprx0_xysp LEAY oprx9,xysp LEAY oprx16,xysp LSL opr16a LSL oprx0_xysp LSL oprx9,xysp LSL oprx16,xysp LSL [D,xysp] LSL [oprx16,xysp] LSLA LSLB LSLD 0 b0 b7 A b7 B C Logical Shift Left D Accumulator same function as ASLD LSR opr16a LSR oprx0_xysp LSR oprx9,xysp LSR oprx16,xysp LSR [D,xysp] LSR [oprx16,xysp] LSRA LSRB 0 b7 Logical Shift Right b0 C b0 Operation (M:M+1) A:B Load Double Accumulator D (A:B) Addr. Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 IDX IDX1 IDX2 IDX IDX1 IDX2 0 b7 C Logical Shift Left same function as ASL b0 EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH CC DC FC EC EC EC EC EC CF DF FF EF EF EF EF EF CE DE FE EE EE EE EE EE CD DD FD ED ED ED ED ED Machine Coding (hex) jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb kk ll ff ee ff ee ff kk ll ff ee ff ee ff kk ll ff ee ff ee ff kk ll ff ee ff ee ff Access Detail
OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP PP1 PO PP PP1 PO PP PP1 PO PP rOPw rPw rPOw frPPw fIfrPw fIPrPw O O O
S X H
V 0
(M:M+1) SP Load Stack Pointer
(M:M+1) X Load Index Register X
(M:M+1) Y Load Index Register Y
Effective Address SP Load Effective Address into SP Effective Address X Load Effective Address into X Effective Address Y Load Effective Address into Y
1B xb 1B xb ff 1B xb ee ff 1A xb 1A xb ff 1A xb ee ff 19 xb 19 xb ff 19 xb ee ff 78 68 68 68 68 68 48 58 59 hh xb xb xb xb xb ll ff ee ff ee ff
Logical Shift Accumulator A to Left Logical Shift Accumulator B to Left
Logical Shift Accumulator A to Right Logical Shift Accumulator B to Right
EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH
74 64 64 64 64 64 44 54
hh xb xb xb xb xb
ll ff ee ff ee ff
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O
Reference Guide 13
A G R E E M E N T
R E Q U I R E D

Source Form LSRD 0 b0 A b7 b7 B Logical Shift Right D Accumulator MAXA oprx0_xysp MAXA oprx9,xysp MAXA oprx16,xysp MAXA [D,xysp] MAXA [oprx16,xysp] MAXM oprx0_xysp MAXM oprx9,xysp MAXM oprx16,xysp MAXM [D,xysp] MAXM [oprx16,xysp] MEM MAX((A), (M)) A MAX of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) (M)). MAX((A), (M)) M MAX of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) (M)). (grade) M(Y); (X) + 4 X; (Y) + 1 Y; A unchanged if (A) < P1 or (A) > P2 then = 0, else = MIN[((A) P1)S1, (P2 (A))S2, $FF] where: A = current crisp input value; X points at 4-byte data structure that describes a trapezoidal membership function (P1, P2, S1, S2); Y points at fuzzy input (RAM location). See CPU12 Reference Manual for special cases. MINA oprx0_xysp MINA oprx9,xysp MINA oprx16,xysp MINA [D,xysp] MINA [oprx16,xysp] MINM oprx0_xysp MINM oprx9,xysp MINM oprx16,xysp MINM [D,xysp] MINM [oprx16,xysp] MOVB #opr8, opr16a1 MOVB #opr8i, oprx0_xysp1 MOVB opr16a, opr16a1 MOVB opr16a, oprx0_xysp1 MOVB oprx0_xysp, opr16a1 MOVB oprx0_xysp, oprx0_xysp1 MOVW #oprx16, opr16a1 MOVW #opr16i, oprx0_xysp1 MOVW opr16a, opr16a1 MOVW opr16a, oprx0_xysp1 MOVW oprx0_xysp, opr16a1 MOVW oprx0_xysp, oprx0_xysp1 MUL MIN((A), (M)) A MIN of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) (M)). MIN((A), (M)) M MIN of 2 Unsigned 8-Bit Values N, Z, V and C status bits reflect result of internal compare ((A) (M)). (M1) M2 Memory to Memory Byte-Move (8-Bit) IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX INH 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 12 19 19 19 19 19 1D 1D 1D 1D 1D 0B 08 0C 09 0D 0A 03 00 04 01 05 02 xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff hh ii ll hh hh xb kk jj ll hh hh xb ll hh ll ll ll hh ll kk hh ll ll ll
OrfP OrPO OfrPP OfIfrfP OfIPrfP OrPw OrPwO OfrPwP OfIfrPw OfIPrPw OPwP OPwO OrPwPO OPrPw OrPwP OrPwO OPWPO OPPW ORPWPO OPRPW ORPWP ORPWO ffO
Operation
Addr. Mode INH b0 C IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] Special 18 18 18 18 18 18 18 18 18 18 01 49
Machine Coding (hex)

O
Access Detail
S X H
N 0
18 18 18 18 18 1C 1C 1C 1C 1C
xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff
OrfP OrPO OfrPP OfIfrfP OfIPrfP OrPw OrPwO OfrPwP OfIfrPw OfIPrPw RRfOw
A G R E E M E N T
ii xb hh xb xb xb jj xb hh xb xb xb
(M:M+11) M:M+12 Memory to Memory Word-Move (16-Bit)
(A) (B) A:B 8 8 Unsigned Multiply
NEG opr16a NEG oprx0_xysp NEG oprx9,xysp NEG oprx16,xysp NEG [D,xysp] NEG [oprx16,xysp] NEGA NEGB NOP
0 (M) M or (M) + 1 M Twos Complement Negate
0 (A) A equivalent to (A) + 1 A Negate Accumulator A 0 (B) B equivalent to (B) + 1 B Negate Accumulator B No Operation
EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH
70 60 60 60 60 60 40 50 A7
hh xb xb xb xb xb
ll ff ee ff ee ff
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O O
Note 1. The first operand in the source code statement specifies the source for the move.
CPU12 MOTOROLA

Source Form ORAA #opr8i ORAA opr8a ORAA opr16a ORAA oprx0_xysp ORAA oprx9,xysp ORAA oprx16,xysp ORAA [D,xysp] ORAA [oprx16,xysp] ORAB #opr8i ORAB opr8a ORAB opr16a ORAB oprx0_xysp ORAB oprx9,xysp ORAB oprx16,xysp ORAB [D,xysp] ORAB [oprx16,xysp] ORCC #opr8i PSHA Operation (A) ' (M) A Logical OR A with Memory Addr. Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM INH 8A 9A BA AA AA AA AA AA CA DA FA EA EA EA EA EA Machine Coding (hex) ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb Access Detail
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P
S X H
V 0
ll ff ee ff ee ff
(B) ' (M) B Logical OR B with Memory
ll ff ee ff ee ff
(CCR) ' M CCR Logical OR CCR with Memory (SP) 1 SP; (A) M(SP) Push Accumulator A onto Stack
14 ii 36
Os
PSHB
(SP) 1 SP; (B) M(SP) Push Accumulator B onto Stack
INH
37
Os
PSHC
(SP) 1 SP; (CCR) M(SP) Push CCR onto Stack
INH
39
Os
PSHD
(SP) 2 SP; (A:B) M(SP):M(SP+1) Push D Accumulator onto Stack
INH
3B
OS
PSHX
(SP) 2 SP; (XH:XL) M(SP):M(SP+1) Push Index Register X onto Stack
INH
34
OS
PSHY
(SP) 2 SP; (YH:YL) M(SP):M(SP+1) Push Index Register Y onto Stack
INH
35
OS
PULA
(M(SP)) A; (SP) + 1 SP Pull Accumulator A from Stack
INH
32
ufO
PULB
(M(SP)) B; (SP) + 1 SP Pull Accumulator B from Stack
INH
33
ufO
PULC
(M(SP)) CCR; (SP) + 1 SP Pull CCR from Stack
INH
38
ufO
PULD
(M(SP):M(SP+1)) A:B; (SP) + 2 SP Pull D from Stack
INH
3A
UfO
PULX
(M(SP):M(SP+1)) XH:XL; (SP) + 2 SP Pull Index Register X from Stack
INH
30
UfO
PULY
(M(SP):M(SP+1)) YH:YL; (SP) + 2 SP Pull Index Register Y from Stack
INH
31
UfO
Reference Guide 15
A G R E E M E N T
R E Q U I R E D

Source Form REV (add if interrupted) Operation MIN-MAX rule evaluation Find smallest rule input (MIN). Store to rule outputs unless fuzzy output is already larger (MAX). For rule weights see REVW. Each rule input is an 8-bit offset from the base address in Y. Each rule output is an 8-bit offset from the base address in Y. $FE separates rule inputs from rule outputs. $FF terminates the rule list. REV may be interrupted. Addr. Mode Special Machine Coding (hex) 18 3A Access Detail
Orf(ttx)O1 ff + Orf
S X H ?
N ?
Z ?
C ?
A G R E E M E N T
REVW (add 2 at end of ins if wts) (add if interrupted)
MIN-MAX rule evaluation Find smallest rule input (MIN), Store to rule outputs unless fuzzy output is already larger (MAX). Rule weights supported, optional. Each rule input is the 16-bit address of a fuzzy input. Each rule output is the 16-bit address of a fuzzy output. The value $FFFE separates rule inputs from rule outputs. $FFFF terminates the rule list. REVW may be interrupted.
Special
18 3B
ORf(tTx)O2 (rffRf)2 fff + ORft
ROL opr16a ROL oprx0_xysp ROL oprx9,xysp ROL oprx16,xysp ROL [D,xysp] ROL [oprx16,xysp] ROLA ROLB ROR opr16a ROR oprx0_xysp ROR oprx9,xysp ROR oprx16,xysp ROR [D,xysp] ROR [oprx16,xysp] RORA RORB RTC
b7 C Rotate Memory Left through Carry
b0
Rotate A Left through Carry Rotate B Left through Carry
EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH
75 65 65 65 65 65 45 55 76 66 66 66 66 66 46 56 0A
hh xb xb xb xb xb
ll ff ee ff ee ff
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O uUnPPP
b0 b7 C Rotate Memory Right through Carry
hh xb xb xb xb xb
ll ff ee ff ee ff
Rotate A Right through Carry Rotate B Right through Carry (M(SP)) PPAGE; (SP) + 1 SP; (M(SP):M(SP+1)) PCH:PCL; (SP) + 2 SP Return from Call
RTI (if interrupt pending)
(M(SP)) CCR; (SP) + 1 SP (M(SP):M(SP+1)) B:A; (SP) + 2 SP (M(SP):M(SP+1)) XH:XL; (SP) + 4 SP (M(SP):M(SP+1)) PCH:PCL; (SP) 2 SP (M(SP):M(SP+1)) YH:YL; (SP) + 4 SP Return from Interrupt
INH
0B
uUUUUPPP uUUUUVfPPP
RTS
(M(SP):M(SP+1)) PCH:PCL; (SP) + 2 SP Return from Subroutine
INH
3D
UfPPP
SBA
(A) (B) A Subtract B from A
INH
18 16
OO
Notes: 1. The 3-cycle loop in parentheses is executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt. 2. The 3-cycle loop in parentheses expands to 5 cycles for separators when weighting is enabled. The loop is executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt.
CPU12 MOTOROLA

Source Form SBCA #opr8i SBCA opr8a SBCA opr16a SBCA oprx0_xysp SBCA oprx9,xysp SBCA oprx16,xysp SBCA [D,xysp] SBCA [oprx16,xysp] SBCB #opr8i SBCB opr8a SBCB opr16a SBCB oprx0_xysp SBCB oprx9,xysp SBCB oprx16,xysp SBCB [D,xysp] SBCB [oprx16,xysp] SEC SEI SEV SEX abc,dxys Operation (A) (M) C A Subtract with Borrow from A Addr. Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM IMM IMM INH 82 92 B2 A2 A2 A2 A2 A2 C2 D2 F2 E2 E2 E2 E2 E2 Machine Coding (hex) ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb Access Detail
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P
S X H
ll ff ee ff ee ff
(B) (M) C B Subtract with Borrow from B
ll ff ee ff ee ff
1C Translates to ORCC #$01 1 I; (inhibit I interrupts) Translates to ORCC #$10 1V Translates to ORCC #$02 $00:(r1) r2 if r1, bit 7 is 0 or $FF:(r1) r2 if r1, bit 7 is 1 Sign Extend 8-bit r1 to 16-bit r2 r1 may be A, B, or CCR r2 may be D, X, Y, or SP Alternate mnemonic for TFR r1, r2
14 01 14 10 14 02 B7 eb
ee ff ll ff ee ff ee ff ll ff ee ff ee ff
STAB opr8a STAB opr16a STAB oprx0_xysp STAB oprx9,xysp STAB oprx16,xysp STAB [D,xysp] STAB [oprx16,xysp] STD opr8a STD opr16a STD oprx0_xysp STD oprx9,xysp STD oprx16,xysp STD [D,xysp] STD [oprx16,xysp] STOP (entering STOP) (exiting STOP) (continue) (if STOP disabled)
(B) M Store Accumulator B to Memory
DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH
5B 7B 6B 6B 6B 6B 6B 5C 7C 6C 6C 6C 6C 6C
dd hh xb xb xb xb xb dd hh xb xb xb xb xb
Pw wOP Pw PwO PwP PIfPw PIPPw PW WOP PW PWO PWP PIfPW PIPPW OOSSSfSs fVfPPP fO OO
(A) M, (B) M+1 Store Double Accumulator
(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP); STOP All Clocks If S control bit = 1, the STOP instruction is disabled and acts like a two-cycle NOP. Registers stacked to allow quicker recovery by interrupt.
18 3E
Reference Guide 17
STAA opr8a STAA opr16a STAA oprx0_xysp STAA oprx9,xysp STAA oprx16,xysp STAA [D,xysp] STAA [oprx16,xysp]
(A) M Store Accumulator A to Memory
DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2]
5A 7A 6A 6A 6A 6A 6A
dd hh xb xb xb xb xb
ll ff ee ff
Pw wOP Pw PwO PwP PIfPw PIPPw
A G R E E M E N T
R E Q U I R E D

Source Form STS opr8a STS opr16a STS oprx0_xysp STS oprx9,xysp STS oprx16,xysp STS [D,xysp] STS [oprx16,xysp] STX opr8a STX opr16a STX oprx0_xysp STX oprx9,xysp STX oprx16,xysp STX [D,xysp] STX [oprx16,xysp] STY opr8a STY opr16a STY oprx0_xysp STY oprx9,xysp STY oprx16,xysp STY [D,xysp] STY [oprx16,xysp] SUBA #opr8i SUBA opr8a SUBA opr16a SUBA oprx0_xysp SUBA oprx9,xysp SUBA oprx16,xysp SUBA [D,xysp] SUBA [oprx16,xysp] SUBB #opr8i SUBB opr8a SUBB opr16a SUBB oprx0_xysp SUBB oprx9,xysp SUBB oprx16,xysp SUBB [D,xysp] SUBB [oprx16,xysp] SUBD #opr16i SUBD opr8a SUBD opr16a SUBD oprx0_xysp SUBD oprx9,xysp SUBD oprx16,xysp SUBD [D,xysp] SUBD [oprx16,xysp] SWI (SPH:SPL) M:M+1 Store Stack Pointer Operation Addr. Mode DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH 5F 7F 6F 6F 6F 6F 6F 5E 7E 6E 6E 6E 6E 6E 5D 7D 6D 6D 6D 6D 6D 80 90 B0 A0 A0 A0 A0 A0 C0 D0 F0 E0 E0 E0 E0 E0 83 93 B3 A3 A3 A3 A3 A3 3F Machine Coding (hex) dd hh xb xb xb xb xb dd hh xb xb xb xb xb dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb ll ff ee ff ee ff ll ff ee ff ee ff ll ff ee ff ee ff Access Detail
PW WOP PW PWO PWP PIfPW PIPPW PW WOP PW PWO PWP PIfPW PIPPW PW WOP PW PWO PWP PIfPW PIPPW P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP VSPSSPSsP1
S X H
V 0
(XH:XL) M:M+1 Store Index Register X
A G R E E M E N T
(YH:YL) M:M+1 Store Index Register Y
(A) (M) A Subtract Memory from Accumulator A
ll ff ee ff ee ff
(B) (M) B Subtract Memory from Accumulator B
ll ff ee ff ee ff kk ll ff ee ff ee ff
(D) (M:M+1) D Subtract Memory from D (A:B)
(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP) 1 I; (SWI Vector) PC Software Interrupt
TAB TAP TBA
(A) B Transfer A to B (A) CCR Translates to TFR A , CCR (B) A Transfer B to A
INH INH INH
18 0E B7 02 18 0F
OO
OO
Note 1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A variation of the sequence (VfPPP) is used for resets.
CPU12 MOTOROLA

Source Form TBEQ abdxys,rel9 Operation If (cntr) = 0, then Branch; else Continue to next instruction Test Counter and Branch if Zero (cntr = A, B, D, X,Y, or SP) TBL oprx0_xysp (M) + [(B) ((M+1) (M))] A 8-Bit Table Lookup and Interpolate Initialize B, and index before TBL. <ea> points at first 8-bit table entry (M) and B is fractional part of lookup value. (no indirect addressing modes or extensions allowed) IDX 18 3D xb
OrrffffP
Addr. Mode REL (9-bit)
Machine Coding (hex) 04 lb rr
Access Detail
PPP
S X H
Test Counter and Branch if Not Zero (cntr = A, B, D, X,Y, or SP) TFR abcdxys,abcdxys (r1) r2 or $00:(r1) r2 or (r1[7:0]) r2 Transfer Register to Register r1 and r2 may be A, B, CCR, D, X, Y, or SP TPA TRAP trapnum (CCR) A Translates to TFR CCR ,A (SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP) 1 I; (TRAP Vector) PC Unimplemented opcode trap INH INH B7 20 18 tn tn = $30$39 or $40$FF
P
INH
B7 eb
or
OfVSPSSPSsP
ff ee ff ee ff
(A) 0 (B) 0
Test A for Zero or Minus Test B for Zero or Minus
TSX TSY TXS TYS WAI (before interrupt) (when interrupt comes)
(SP) X Translates to TFR SP,X (SP) Y Translates to TFR SP,Y (X) SP Translates to TFR X,SP (Y) SP Translates to TFR Y,SP (SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP); WAIT for interrupt
INH INH INH INH INH
B7 75 B7 76 B7 57 B7 67 3E
or or 1
1 1
OSSSfSsf VfPPP
Reference Guide 19
TST opr16a TST oprx0_xysp TST oprx9,xysp TST oprx16,xysp TST [D,xysp] TST [oprx16,xysp] TSTA TSTB
(M) 0 Test Memory for Zero or Minus
EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH
F7 E7 E7 E7 E7 E7 97 D7
hh xb xb xb xb xb
ll
rOP rfP rPO frPP fIfrfP fIPrfP O O
A G R E E M E N T
TBNE abdxys,rel9
If (cntr) not = 0, then Branch; else Continue to next instruction
REL (9-bit)
04 lb rr
PPP
R E Q U I R E D

Source Form WAV (add if interrupt) B Operation Addr. Mode Special Machine Coding (hex) 18 3C Access Detail Off(frrfffff)O SSS + UUUrr S X H ? I N ? Z V ? C ?
Si Fi Y:D
i=1 B
Fi X i=1 Calculate Sum of Products and Sum of Weights for Weighted Average Calculation
Initialize B, X, and Y before WAV. B specifies number of elements. X points at first element in Si list. Y points at first element in Fi list. All Si and Fi elements are 8-bits. If interrupted, six extra bytes of stack used for intermediate values wavr pseudoinstruction XGDX XGDY see WAV Resume executing an interrupted WAV instruction (recover intermediate results from stack rather than initializing them to zero) (D) (X) Translates to EXG D, X (D) (Y) Translates to EXG D, Y INH INH B7 C5 B7 C6
P
A G R E E M E N T
Special
3C
CPU12 MOTOROLA
MOTOROLA CPU12 Reference Guide 21
Table 1. Indexed Addressing Mode Postbyte Encoding (xb)

00 0,X 5b const 01 1,X 5b const 02 2,X 5b const 03 3,X 5b const 04 4,X 5b const 05 5,X 5b const 06 6,X 5b const 07 7,X 5b const 08 8,X 5b const 09 9,X 5b const 0A 10,X 5b const 0B 11,X 5b const 0C 12,X 5b const 0D 13,X 5b const 0E 14,X 5b const 0F 15,X 5b const 10 16,X 5b const 11 15,X 5b const 12 14,X 5b const 13 13,X 5b const 14 12,X 5b const 15 11,X 5b const 16 10,X 5b const 17 9,X 5b const 18 8,X 5b const 19 7,X 5b const 1A 6,X 5b const 1B 5,X 5b const 1C 4,X 5b const 1D 3,X 5b const 1E 2,X 5b const 1F 1,X 5b const 20 1,+X pre-inc 21 2,+X pre-inc 22 3,+X pre-inc 23 4,+X pre-inc 24 5,+X pre-inc 25 6,+X pre-inc 26 7,+X pre-inc 27 8,+X pre-inc 28 8,X pre-dec 29 7,X pre-dec 2A 6,X pre-dec 2B 5,X pre-dec 2C 4,X pre-dec 2D 3,X pre-dec 2E 2,X pre-dec 2F 1,X pre-dec 30 1,X+ post-inc 31 2,X+ post-inc 32 3,X+ post-inc 33 4,X+ post-inc 34 5,X+ post-inc 35 6,X+ post-inc 36 7,X+ post-inc 37 8,X+ post-inc 38 8,X post-dec 39 7,X post-dec 3A 6,X post-dec 3B 5,X post-dec 3C 4,X post-dec 3D 3,X post-dec 3E 2,X post-dec 3F 1,X post-dec 40 0,Y 5b const 41 1,Y 5b const 42 2,Y 5b const 43 3,Y 5b const 44 4,Y 5b const 45 5,Y 5b const 46 6,Y 5b const 47 7,Y 5b const 48 8,Y 5b const 49 9,Y 5b const 4A 10,Y 5b const 4B 11,Y 5b const 4C 12,Y 5b const 4D 13,Y 5b const 4E 14,Y 5b const 4F 15,Y 5b const 50 16,Y 5b const 51 15,Y 5b const 52 14,Y 5b const 53 13,Y 5b const 54 12,Y 5b const 55 11,Y 5b const 56 10,Y 5b const 57 9,Y 5b const 58 8,Y 5b const 59 7,Y 5b const 5A 6,Y 5b const 5B 5,Y 5b const 5C 4,Y 5b const 5D 3,Y 5b const 5E 2,Y 5b const 5F 1,Y 5b const 60 1,+Y pre-inc 61 2,+Y pre-inc 62 3,+Y pre-inc 63 4,+Y pre-inc 64 5,+Y pre-inc 65 6,+Y pre-inc 66 7,+Y pre-inc 67 8,+Y pre-inc 68 8,Y pre-dec 69 7,Y pre-dec 6A 6,Y pre-dec 6B 5,Y pre-dec 6C 4,Y pre-dec 6D 3,Y pre-dec 6E 2,Y pre-dec 6F 1,Y pre-dec 70 1,Y+ post-inc 71 2,Y+ post-inc 72 3,Y+ post-inc 73 4,Y+ post-inc 74 5,Y+ post-inc 75 6,Y+ post-inc 76 7,Y+ post-inc 77 8,Y+ post-inc 78 8,Y post-dec 79 7,Y post-dec 7A 6,Y post-dec 7B 5,Y post-dec 7C 4,Y post-dec 7D 3,Y post-dec 7E 2,Y post-dec 7F 1,Y post-dec 80 0,SP 5b const 81 1,SP 5b const 82 2,SP 5b const 83 3,SP 5b const 84 4,SP 5b const 85 5,SP 5b const 86 6,SP 5b const 87 7,SP 5b const 88 8,SP 5b const 89 9,SP 5b const 8A 10,SP 5b const 8B 11,SP 5b const 8C 12,SP 5b const 8D 13,SP 5b const 8E 14,SP 5b const 8F 15,SP 5b const 90 16,SP 5b const 91 15,SP 5b const 92 14,SP 5b const 93 13,SP 5b const 94 12,SP 5b const 95 11,SP 5b const 96 10,SP 5b const 97 9,SP 5b const 98 8,SP 5b const 99 7,SP 5b const 9A 6,SP 5b const 9B 5,SP 5b const 9C 4,SP 5b const 9D 3,SP 5b const 9E 2,SP 5b const 9F 1,SP 5b const A0 1,+SP pre-inc A1 2,+SP pre-inc A2 3,+SP pre-inc A3 4,+SP pre-inc A4 5,+SP pre-inc A5 6,+SP pre-inc A6 7,+SP pre-inc A7 8,+SP pre-inc A8 8,SP pre-dec A9 7,SP pre-dec AA 6,SP pre-dec AB 5,SP pre-dec AC 4,SP pre-dec AD 3,SP pre-dec AE 2,SP pre-dec AF 1,SP pre-dec B0 1,SP+ post-inc B1 2,SP+ post-inc B2 3,SP+ post-inc B3 4,SP+ post-inc B4 5,SP+ post-inc B5 6,SP+ post-inc B6 7,SP+ post-inc B7 8,SP+ post-inc B8 8,SP post-dec B9 7,SP post-dec BA 6,SP post-dec BB 5,SP post-dec BC 4,SP post-dec BD 3,SP post-dec BE 2,SP post-dec BF 1,SP post-dec C0 0,PC 5b const C1 1,PC 5b const C2 2,PC 5b const C3 3,PC 5b const C4 4,PC 5b const C5 5,PC 5b const C6 6,PC 5b const C7 7,PC 5b const C8 8,PC 5b const C9 9,PC 5b const CA 10,PC 5b const CB 11,PC 5b const CC 12,PC 5b const CD 13,PC 5b const CE 14,PC 5b const CF 15,PC 5b const D0 16,PC 5b const D1 15,PC 5b const D2 14,PC 5b const D3 13,PC 5b const D4 12,PC 5b const D5 11,PC 5b const D6 10,PC 5b const D7 9,PC 5b const D8 8,PC 5b const D9 7,PC 5b const DA 6,PC 5b const DB 5,PC 5b const DC 4,PC 5b const DD 3,PC 5b const DE 2,PC 5b const DF 1,PC 5b const E0 n,X 9b const E1 n,X 9b const E2 n,X 16b const E3 [n,X] 16b indr E4 A,X A offset E5 B,X B offset E6 D,X D offset E7 [D,X] D indirect E8 n,Y 9b const E9 n,Y 9b const EA n,Y 16b const EB [n,Y] 16b indr EC A,Y A offset ED B,Y B offset EE D,Y D offset EF [D,Y] D indirect F0 n,SP 9b const F1 n,SP 9b const F2 n,SP 16b const F3 [n,SP] 16b indr F4 A,SP A offset F5 B,SP B offset F6 D,SP D offset F7 [D,SP] D indirect F8 n,PC 9b const F9 n,PC 9b const FA n,PC 16b const FB [n,PC] 16b indr FC A,PC A offset FD B,PC B offset FE D,PC D offset FF [D,PC] D indirect
Key to Table 1
postbyte (hex)
B0
#,REG
type
source code syntax
type offset used
A G R E E M E N T
R E Q U I R E D

Table 2. Indexed Addressing Mode Summary
Postbyte Code (xb) rr0nnnnn ,r n,r n,r n,r n,r Operand Syntax 5-bit constant offset n = 16 to +15 rr can specify X, Y, SP, or PC Constant offset (9- or 16-bit signed) z- 0 = 9-bit with sign in LSB of postbyte (s) 1 = 16-bit if z = s = 1, 16-bit offset indexed-indirect (see below) rr can specify X, Y, SP, or PC Auto pre-decrement /increment or Auto post-decrement/increment; p = pre-(0) or post-(1), n = 8 to 1, +1 to +8 rr can specify X, Y, or SP (PC not a valid choice) Accumulator offset (unsigned 8-bit or 16-bit) aa - 00 = A 01 = B 10 = D (16-bit) 11 = see accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC 16-bit offset indexed-indirect rr can specify X, Y, SP, or PC Accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC Comments
111rr0zs
rr1pnnnn
A G R E E M E N T
n,r n,+r n,r n,r+ A,r B,r D,r
111rr1aa
111rr011 111rr111
[n,r] [D,r]
CPU12 MOTOROLA
CPU12
LS 0 1 2 3 4 5 6 7 MS 0
AA AB
Table 3. Transfer and Exchange Postbyte Encoding

TRANSFERS 1
BA BB B CCR
2
CCR A CCR B CCR CCR
3
TMP3L A TMP3L B TMP3L CCR TMP3 TMP2 TMP3 D TMP3 X TMP3 Y TMP3 SP
4
BA BB B CCR D TMP2 DD DX DY D SP
5
XL A XL B XL CCR X TMP2 XD XX XY X SP
6
YL A YL B YL CCR Y TMP2 YD YX YY Y SP
7
SPL A SPL B SPL CCR SP TMP2 SP D SP X SP Y SP SP
A CCR
sex:A TMP2 sex:B TMP2 sex:CCR TMP2 sex:A D SEX A,D sex:A X SEX A,X sex:A Y SEX A,Y sex:A SP SEX A,SP sex:B D SEX B,D sex:B X SEX B,X sex:B Y SEX B,Y sex:B SP SEX B,SP sex:CCR D SEX CCR,D sex:CCR X SEX CCR,X sex:CCR Y SEX CCR,Y sex:CCR SP SEX CCR,SP
EXCHANGES LS 0 1 2 3 4 5 6 7 MS 8
AA AB A CCR
9
BA BB B CCR
A
CCR A CCR B CCR CCR
B
TMP3L A $00:A TMP3 TMP3L B $FF:B TMP3
C
BA AB BB $FF A
D
XL A $00:A X XL B $FF:B X
E
YL A $00:A Y YL B $FF:B Y
F
SPL A $00:A SP SPL B $FF:B SP
TMP3L CCR B CCR XL CCR YL CCR SPL CCR $FF:CCR TMP3 $FF:CCR D $FF:CCR X $FF:CCR Y $FF:CCR SP TMP3 TMP2 TMP3 D TMP3 X TMP3 Y TMP3 SP D TMP2 DD DX DY D SP X TMP2 XD XX XY X SP Y TMP2 YD YX YY Y SP SP TMP2 SP D
$00:A TMP2 $00:B TMP2 $00:CCR TMP2 TMP2L A TMP2L B TMP2L CCR $00:CCR D $00:A D $00:B D B CCR $00:A X XL A $00:A Y YL A $00:A SP SPL A $00:B X XL B $00:B Y YL B $00:B SP SPL B $00:CCR X XL CCR $00:CCR Y YL CCR $00:CCR SP SPL CCR
SP X SP Y SP SP
Reference Guide
TMP2 and TMP3 registers are for factory use only.
A G R E E M E N T
R E Q U I R E D
Table 4. Loop Primitive Postbyte Encoding (lb)

00 A 10 A 20 A 30 A 40 A 50 A 60 A 70 A 80 A 90 A A0 A B0 A () B B1 B () B2 A3 D 94 D A4 D B4 B3 D () X B5 X () Y B6 Y () SP B7 (+) () SP
DBEQ
(+) 01
DBEQ
() B 11
DBNE
(+) B 21
DBNE
() B 31
TBEQ
(+) B 41
TBEQ
() B 51
TBNE
(+) B 61
TBNE
() B 71 B 81
IBEQ
(+) B 91
IBEQ
()
IBNE
(+) B A1
IBNE IBNE
DBEQ
(+) 02 03 04
DBEQ
() 12 13 D 14
DBNE
(+) 22 23 D 24
DBNE
() 32 33 D 34
TBEQ
(+) 42 43 D 44
TBEQ
() 52 53 D 54
TBNE
(+) 62 63 D 64
TBNE
() 72 73 D 74 D 84 83 82
IBEQ
(+) 92 93
IBEQ
()
IBNE
(+) A2
A G R E E M E N T
DBEQ
(+) 05
DBEQ
() X 15
DBNE
(+) X 25
DBNE
() X 35
TBEQ
(+) X 45
TBEQ
() X 55
TBNE
(+) X 65
TBNE
() X 75 X 85
IBEQ
(+) X 95
IBEQ
()
IBNE
(+) X A5
IBNE IBNE IBNE IBNE
DBEQ
(+) 06
DBEQ
() Y 16
DBNE
(+) Y 26
DBNE
() Y 36
TBEQ
(+) Y 46
TBEQ
() Y 56
TBNE
(+) Y 66
TBNE
() Y 76 Y 86
IBEQ
(+) Y 96
IBEQ
()
IBNE
(+) Y A6
DBEQ
(+) 07 (+)
DBEQ
()
DBNE
(+)
DBNE
()
TBEQ
(+)
TBEQ
()
TBNE
(+)
TBNE
() SP 87 ()
IBEQ
(+) SP 97
IBEQ
()
IBNE
(+)
SP 17 ()
SP 27 (+)
SP 37 ()
SP 47 (+)
SP 57 ()
SP 67 (+)
SP 77
SP A7
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
(+)
IBEQ
()
IBNE
Key to Table 4
postbyte (hex) (bit 3 is dont care) counter used
B0 () A
_BEQ
branch condition
sign of 9-bit relative branch offset (lower eight bits are an extension byte following postbyte)
Table 5. Branch/Complementary Branch

Branch Test Mnemonic Opcode Boolean Test rm r>m BGT 2E Z + (N V) = 0 r<m rm BGE 2C NV=0 r=m BEQ 27 Z=1 rm r>m rm BLE 2F Z + (N V) = 1 rm r<m BLT 2D NV=1 r>m BHI 22 C+Z=0 rm rm BHS/BCC 24 C=0 r<m r=m BEQ 27 Z=1 rm rm BLS 23 C+Z=1 r>m r<m BLO/BCS 25 C=1 rm Carry BCS 25 C=1 No Carry Negative BMI 2B N=1 Plus Overflow BVS 29 V=1 No Overflow r=0 BEQ 27 Z=1 r0 Always BRA 20 Never For 16-bit offset long branches preceed opcode with a $18 page prebyte. Complementary Branch Mnemonic Opcode BLE 2F BLT 2D BNE 26 BGT 2E BGE 2C BLS 23 BLO/BCS 25 BNE 26 BHI 22 BHS/BCC 24 BCC 24 BPL 2A BVC 28 BNE 26 BRN 21 Comment Signed Signed Signed Signed Signed Unsigned Unsigned Unsigned Unsigned Unsigned Simple Simple Simple Simple Unconditional
CPU12 MOTOROLA
Memory Expansion
Some M68HC12 derivatives support >4 megabytes of program memory. Memory precedence Highest On-chip registers (usually $0000 or $1000) BDM ROM (only when BDM active) On-chip RAM On-chip EEPROM On-chip program memory (FLASH or ROM) Expansion windows (on MCUs with expanded memory) Other external memory Lowest CPU sees 64 Kbytes of address space (CPU_ADDR [15:0]) PPAGE 8-bit register to select 1 of 256 16 Kbyte program pages DPAGE 8-bit register to select 1 of 256 4 Kbyte data pages EPAGE 8-bit register to select 1 of 256 1 Kbyte extra pages Extended address is 22 bits (EXT_ADDR [21:0]) Program expansion window works with CALL and RTC instructions to simplify program access to extended memory space. Data and extra expansion windows (when present) use traditional banked expansion memory techniques. Program window If CPU_ADDR [15:0] = $8000BFFF and PWEN = 1 Then EXT_ADDR [21:0] = PPAGE [7:0]:CPU_ADDR [13:0] Program window works with CALL/RTC to automate bank switching. 256 pages (banks) of 16 Kbytes each = 4 M. Data window If CPU_ADDR [15:0] = $70007FFF and DWEN = 1 Then EXT_ADDR [21:0] = 1:1:DPAGE [7:0]:CPU_ADDR [11:0] User program controls DPAGE value
Reference Guide 25
A G R E E M E N T
R E Q U I R E D

Extra window If CPU_ADDR [15:0] = $000003FF and EWDIR = 1 and EWEN = 1 or CPU_ADDR [15:0] = $040007FF and EWDIR = 0 and EWEN = 1 Then EXT_ADDR [21:0] = 1:1:1:1:EPAGE [7:0]:CPU_ADDR [9:0] User program controls EPAGE value CPU address not in any enabled window EXT_ADDR [21:0] = 1:1:1:1:1:1:CPU_ADDR [15:0]
A G R E E M E N T
CPU12 MOTOROLA
00 0000 30 0000 E window (EWDIR = 1) 3C 0000 0000 0400 07FF 3E FFFF 3F 0000
256 pages of 16 Kbytes each viewed through P-window 256 pages of 4 Kbytes each viewed through D-window
. . .
. . .
DPAGE ($F0) 240 DPAGE ($F1) 241 DPAGE ($F2) 242 DPAGE ($F3) 243 DPAGE ($F4) 244 DPAGE ($F5) 245 DPAGE ($F6) 246 DPAGE ($F7) 247 DPAGE ($F8) 248 DPAGE ($F9) 249 DPAGE ($FA) 250 DPAGE ($FB) 251 DPAGE ($FC) 252 DPAGE ($FD) 253 DPAGE ($FE) 254 DPAGE ($FF) 255
256 pages of 1 Kbyte each viewed through E-window
. . .
224 225 226 227 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 228
E window (EWDIR = 0) 1FFF 2000 PPAGE ($FC) 252
3FFF 4000
5FFF 6000 6FFF 7000 D window 7FFF 8000 3F 7FFF 3F 8000
PPAGE ($FD) 253
P window
9FFF A000
PPAGE ($FE) 254
BFFF C000
3F BFFF 3F C000
DFFF E000
PPAGE ($FF) 255
FFFF CPU_ADDR
3F FFFF EXT_ADDR
Reference Guide 27
A G R E E M E N T
R E Q U I R E D
28 CPU12 Reference Guide MOTOROLA CPU12 Reference Guide
A G R E E M E N T
R E Q U I R E D CPU12 Reference Guide
Table 6. CPU12 Opcode Map (Sheet 1 of 2)

00 IH 01
*5
10
1 20
3 30
3 40 1 IH 3 41 1 IH 3 42
1 50 1 IH 1 51 1 IH 1 52
1 60 1 ID 1 61 1 ID 1 62 1 ID 1 63 1 ID 1 64 1 ID 1 65 1 ID 1 66 1 ID 1 67 1 ID 1 68 1 ID 1 69 1 ID 2 6A 2 ID 2 6B 2 ID 2 6C 2 ID 2 6D 2 ID 2 6E 2 ID 2 6F 2 ID
3-6 70
4 80
1 90
3 A0 2 ID 3 A1 2 ID 3 A2 2 ID 3 A3 2 ID 3 A4 2 ID 3 A5 2 ID 3 A6 2 ID 1 A7 1 IH 3 A8 2 ID 3 A9 2 ID 3 AA 2 ID 3 AB 2 ID 3 AC 2 ID 3 AD 2 ID 3 AE 2 ID 3 AF 2 ID
3-6 B0
3 C0
1 D0
3 E0 2 ID 3 E1 2 ID 3 E2 2 ID 3 E3 2 ID 3 E4 2 ID 3 E5 2 ID 3 E6 2 ID 1 E7 1 ID 3 E8 2 ID 3 E9 2 ID 3 EA 2 ID 3 EB 2 ID 3 EC 2 ID 3 ED 2 ID 3 EE 2 ID 3 EF 2 ID
3-6 F0
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
BGND MEM
IH 02
ANDCC EDIV
BRA BRN
PULX
2 IH 1 31
NEGA COMA INCA

1 IH 3 43 1 IH 2 44
NEGB COMB INCB
NEG COM INC DEC LSR ROL ROR ASR ASL CLR STAA STAB STD STY STX STS
NEG COM INC DEC LSR ROL ROR ASR ASL CLR STAA STAB STD STY STX STS
SUBA
3 IM 4 81 3 IM 4 82
SUBA
2 DI 1 91 2 DI 1 92
SUBA CMPA SBCA SUBD ANDA BITA LDAA NOP EORA ADCA ORAA ADDA CPD CPY CPX CPS
SUBA CMPA SBCA SUBD ANDA BITA LDAA
SUBB
3 IM 3 C1 3 IM 3 C2
SUBB
2 DI 1 D1 2 DI 1 D2
SUBB CMPB SBCB ADDD ANDB BITB LDAB TST EORB ADCB ORAB ADDB LDD LDY LDX LDS
SUBB CMPB SBCB ADDD ANDB BITB LDAB TST EORB ADCB ORAB ADDB LDD LDY LDX LDS
1 IM 5 11 1 IH 1 12
2 RL 11 21 1 RL 3 22 1 RL 3 23 1 RL 1 24 2 RL 4-7 25 2-4 RL 4 26 3 RL 4 27 2 RL - 28 - RL 2 29 2-4 RL 2 2A 2-4 RL 2 2B 2-4 RL 4 2C 4 RL 4 2D 4 RL 5 2E 5 RL 5 2F 5 RL
2-4 EX 3-6 71 2-4 EX 3-6 72 2-4 EX 3-6 73 2-4 EX 3-6 74 2-4 EX 3-6 75 2-4 EX 3-6 76 2-4 EX 3-6 77 2-4 EX 3-6 78 2-4 EX 2-5 79 2-4 EX 2-5 7A 2-4 EX 2-5 7B 2-4 EX 2-5 7C 2-4 EX 2-5 7D 2-4 EX 2-5 7E 2-4 EX 2-5 7F 2-4 EX
2-4 EX 3-6 B1 2-4 EX 3-6 B2 2-4 EX 3-6 B3 2-4 EX 3-6 B4 2-4 EX 3-6 B5 2-4 EX 3-6 B6 2-4 EX 1 B7 1 IH 3-6 B8 2-4 EX 3-6 B9 2-4 EX 3-6 BA 2-4 EX 3-6 BB
2-4 EX 3-6 F1 2-4 EX 3-6 F2 2-4 EX 3-6 F3 2-4 EX 3-6 F4 2-4 EX 3-6 F5 2-4 EX 3-6 F6 2-4 EX 3-6 F7 2-4 EX 3-6 F8 2-4 EX 3-6 F9 2-4 EX 3-6 FA 2-4 EX 3-6 FB 2-4 EX 3-6 FC 2-4 EX 3-6 FD 2-4 EX 3-6 FE 2-4 EX 3-6 FF 2-4 EX
PULY PULA PULB PSHX PSHY PSHA PSHB PULC PSHC PULD PSHD wavr RTS WAI SWI
2 IH
CMPA SBCA
3 IM 4 83 3 IM 4 84
CMPA SBCA
CMPB SBCB
CMPB SBCB
2 IH 3/1 32 2 IH 3/1 33 2 IH 3/1 34 2 IH 3/1 35 2 IH 3/1 36 2 IH 3/1 37 2 IH 3/1 38 2 IH 3/1 39 2 IH 3/1 3A 2 IH 3/1 3B 2 IH 3/1 3C 2 SP 3/1 3D 2 IH 3/1 3E 2 IH 3/1 3F
INY
IH 03
MUL
1 IH 1 13 1 IH 3 14
BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE
1 IH 1 53 1 IH 1 54
2 DI 2 93 3 DI 1 94
3 IM 3 C3 3 IM 3 C4 3 IM 3 C5
2 DI 2 D3 3 DI 1 D4 2 DI 1 D5
DEY
IH 04
EMUL ORCC JSR JSR

3 EX 4 17
DECA LSRA
1 IH 2 45
DECB LSRB
SUBD ANDA
3 IM 4 85
SUBD ANDA
ADDD ANDB BITB
ADDD ANDB BITB
loop JMP
RL 05 ID 06 EX 07
3 IM 3-6 15 2-4 ID 3 16
1 IH 1 55
2 DI 1 95
ROLA
1 IH 2 46 1 IH 2 47
ROLB
1 IH 1 56 1 IH 1 57
BITA
3 IM 4 86
BITA
2 DI 1 96
3 IM 3 C6
2 DI 1 D6
JMP BSR
RL 08
RORA ASRA
1 IH 3 48
RORB ASRB
LDAA
3 IM 4 87
LDAA
2 DI 1 97
LDAB
3 IM 1 C7 2 IH 3 C8 3 IM 3 C9 3 IM 3 CA 3 IM 3 CB 3 IM 3 CC
LDAB
2 DI 1 D7
JSR
2 DI 1 18 1 1 19
CLRA
3 IH 4 88 3 IM 3 89 3 IM 3 8A 3 IM 3 8B
TSTA
1 IH 1 98 2 DI 1 99 2 DI 1 9A 2 DI 1 9B
TFR/EXG CLRB EORA ADCA ORAA ADDA CPD CPY CPX CPS EORB ADCB ORAB ADDB LDD
3 IM 3 CD
TSTB
1 IH 1 D8 2 DI 1 D9 2 DI 1 DA 2 DI 1 DB 2 DI 2 DC
1 IH 1 58
INX
IH 09
page 2 LEAY
1 ID 6 1A 1 ID 8 1B
ASLA
1 IH 2 49
ASLB
1 IH 1 59
EORA ADCA ORAA ADDA

3 IM 3 8C
EORA ADCA ORAA ADDA
EORB ADCB ORAB ADDB LDD
DEX
IH 0A
LSRD CALL CALL BSET
ASLD
1 IH 8 5A
1 IH 3 4A
RTC
IH 0B
LEAX LEAS BSET BCLR BRSET BRCLR
STAA STAB STD

3 DI 4 5D
1 EX 4 DI 2 4B 8-10 5B 1 ID *+9 4C 1 DI 5 4D 2-5 DI 4 5C
RTI
IH 0C ID 0D ID 0E ID 0F ID
1 ID 4-6 1C 3-5 EX 4-6 1D 3-5 EX 4-8 1E 4-6 EX 4-8 1F 4-6 EX
2 DI 2 9C
2-4 EX 3-6 BC 2-4 EX 3-6 BD 2-4 EX 3-6 BE 2-4 EX 3-6 BF 2-4 EX
BSET BCLR BRSET BRCLR
CPD
3 IM 3 8D
CPD
3 DI 2 9D
3 DI 2 DD
BCLR BRSET
1 DI 9 4F 1 DI
STY
3 DI 4 5E
CPY
3 IM 3 8E
CPY
3 DI 2 9E
LDY
3 IM 3 CE
LDY
3 DI 2 DE
1 DI *8 4E
STX STS
CPX
3 IM 3 8F
CPX
3 DI 2 9F
LDX
3 IM 3 CF
LDX
3 DI 2 DF
4 DI 4 5F 4 DI
BRCLR
CPS
3 IM
CPS
3 DI
LDS
3 IM
LDS
3 DI
Table 6. CPU12 Opcode Map (Sheet 2 of 2)

00 IM-ID 01 4 10 5 IH 5 11 12 20 4 30 4 IH 3 31 4 IH 4/3 32 4 IH 4/3 33 4 IH 4/3 34 4 IH 4/3 35 4 IH 4/3 36 4 IH 4/3 37 4 IH 4/3 38 4 IH 4/3 39 4 IH 4/3 3A 4 SP 4/3 3B 4 SP 4/3 3C 4 SP 4/3 3D 10 40 2 IH 10 41 2 IH 10 42 2 IH 10 43 2 IH 10 44 2 IH 10 45 2 IH 10 46 2 IH 10 47 2 IH 10 48 2 IH 10 49 2 IH *3n 4A 2 IH *3n 4B 2 IH *8B 4C 2 IH 8 4D 3 IH *9+5 4E 2 IH 10 4F 3 IH 10 50 2 IH 10 51 2 IH 10 52 2 IH 10 53 2 IH 10 54 2 IH 10 55 2 IH 10 56 2 IH 10 57 2 IH 10 58 2 IH 10 59 2 IH 10 5A 2 IH 10 5B 2 IH 10 5C 2 IH 10 5D 2 IH 10 5E 2 IH 10 5F 2 IH 10 60 2 IH 10 61 2 IH 10 62 2 IH 10 63 2 IH 10 64 2 IH 10 65 2 IH 10 66 2 IH 10 67 2 IH 10 68 2 IH 10 69 2 IH 10 6A 2 IH 10 6B 2 IH 10 6C 2 IH 10 6D 2 IH 10 6E 2 IH 10 6F 2 IH 10 70 2 IH 10 71 2 IH 10 72 2 IH 10 73 2 IH 10 74 2 IH 10 75 2 IH 10 76 2 IH 10 77 2 IH 10 78 2 IH 10 79 2 IH 10 7A 2 IH 10 7B 2 IH 10 7C 2 IH 10 7D 2 IH 10 7E 2 IH 10 7F 2 IH 10 80 2 IH 10 81 2 IH 10 82 2 IH 10 83 2 IH 10 84 2 IH 10 85 2 IH 10 86 2 IH 10 87 2 IH 10 88 2 IH 10 89 2 IH 10 8A 2 IH 10 8B 2 IH 10 8C 2 IH 10 8D 2 IH 10 8E 2 IH 10 8F 2 IH 10 90 2 IH 10 91 2 IH 10 92 2 IH 10 93 2 IH 10 94 2 IH 10 95 2 IH 10 96 2 IH 10 97 2 IH 10 98 2 IH 10 99 2 IH 10 9A 2 IH 10 9B 2 IH 10 9C 2 IH 10 9D 2 IH 10 9E 2 IH 10 9F 2 IH 10 A0 2 IH 10 A1 2 IH 10 A2 2 IH 10 A3 2 IH 10 A4 2 IH 10 A5 2 IH 10 A6 2 IH 10 A7 2 IH 10 A8 2 IH 10 A9 2 IH 10 AA 2 IH 10 AB 2 IH 10 AC 2 IH 10 AD 2 IH 10 AE 2 IH 10 AF 2 IH 10 B0 2 IH 10 B1 2 IH 10 B2 2 IH 10 B3 2 IH 10 B4 2 IH 10 B5 2 IH 10 B6 2 IH 10 B7 2 IH 10 B8 2 IH 10 B9 2 IH 10 BA 2 IH 10 BB 2 IH 10 BC 2 IH 10 BD 2 IH 10 BE 2 IH 10 BF 2 IH 10 C0 2 IH 10 C1 2 IH 10 C2 2 IH 10 C3 2 IH 10 C4 2 IH 10 C5 2 IH 10 C6 2 IH 10 C7 2 IH 10 C8 2 IH 10 C9 2 IH 10 CA 2 IH 10 CB 2 IH 10 CC 2 IH 10 CD 2 IH 10 CE 2 IH 10 CF 2 IH 10 D0 2 IH 10 D1 2 IH 10 D2 2 IH 10 D3 2 IH 10 D4 2 IH 10 D5 2 IH 10 D6 2 IH 10 D7 2 IH 10 D8 2 IH 10 D9 2 IH 10 DA 2 IH 10 DB 2 IH 10 DC 2 IH 10 DD 2 IH 10 DE 2 IH 10 DF 2 IH 10 E0 2 IH 10 E1 2 IH 10 E2 2 IH 10 E3 2 IH 10 E4 2 IH 10 E5 2 IH 10 E6 2 IH 10 E7 2 IH 10 E8 2 IH 10 E9 2 IH 10 EA 2 IH 10 EB 2 IH 10 EC 2 IH 10 ED 2 IH 10 EE 2 IH 10 EF 2 IH 10 F0 2 IH 10 F1 2 IH 10 F2 2 IH 10 F3 2 IH 10 F4 2 IH 10 F5 2 IH 10 F6 2 IH 10 F7 2 IH 10 F8 2 IH 10 F9 2 IH 10 FA 2 IH 10 FB 2 IH 10 FC 2 IH 10 FD 2 IH 10 FE 2 IH 10 FF 2 IH 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2
MOVW MOVW MOVW

ID-ID 03
IDIV FDIV EMACS EMULS EDIVS IDIVS SBA
LBRA LBRN LBHI LBLS LBCC LBCS

2 RL 2 26 2 RL 2 27
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP REV REVW WAV TBL STOP ETBL
4 ID
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
2 RL 12 21 2 RL 13 22 4 RL 3 23 2 RL 12 24 2 RL 12 25
EX-ID 5 IH 02 5 12 4 SP 5 13
MOVW MOVW MOVW ABA

IH 07
IM-EX 6 IH 04 6 14 EX-EX 6 IH 05 5 15 ID-EX 5 IH 06 2 16 2 IH 3 17
LBNE LBEQ LBVC LBVS LBPL LBMI LBGE LBLT LBGT LBLE
DAA
IH 08 IM-ID 09
CBA
2 IH 4 18 4 ID 5 19
2 RL 4-7 28 3-5 RL 4-7 29 3-5 RL 4-7 2A 3-5 RL 4-7 2B 3-5 RL 4-7 2C 3-5 RL 4-7 2D 3-5 RL 4-7 2E 3-5 RL 4-7 2F 3-5 RL
MOVB MOVB MOVB

ID-ID 0B
MAXA MINA EMAXD EMIND MAXM MINM EMAXM
EX-ID 5 ID 0A 5 1A 4 ID 4 1B
MOVB MOVB MOVB TAB

IH 0F
IM-EX 5 ID 0C 6 1C EX-EX 6 ID 0D 5 1D ID-EX 5 ID 0E 2 1E 2 ID 2 1F 2 ID
4 ID 4/3 3E 4 IH 4/3 3F
TRAP TRAP
TBA
IH
EMINM
* Refer to instruction summary for more information. The opcode $04 corresponds to one of the loop primitive instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE.
A G R E E M E N T
R E Q U I R E D
Table 7. Hexadecimal to ASCII Conversion

Hex $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F ASCII NUL SOH STX ETX EOT ENQ ACK BEL beep BS back sp HT tab LF linefeed VT FF CR return SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESCAPE FS GS RS US Hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F ASCII SP space ! Hex $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F $50 $51 $52 $53 $54 $55 $56 $57 $58 $59 $5A $5B $5C $5D $5E $5F ASCII @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ under Hex $60 $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D $6E $6F $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 $7A $7B $7C $7D $7E $7F ASCII
` grave
a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL delete
quote
# $ % &
A G R E E M E N T
apost.
( ) * + , comma
- dash . period
/ 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
Reference Guide 30
CPU12 CPU12 Reference Guide MOTOROLA
Hexadecimal to Decimal Conversion

To convert a hexadecimal number (up to four hexadecimal digits) to decimal, look up the decimal equivalent of each hexadecimal digit in Table 8. The decimal equivalent of the original hexadecimal number is the sum of the weights found in the table for all hexadecimal digits. Table 8. Hexadecimal to/from Decimal Conversion
15 15 Bit 12 11 8 8 7 7 Bit 4 3 0 0
Decimal to Hexadecimal Conversion

To convert a decimal number (up to 65,53510) to hexadecimal, find the largest decimal number in Table 8 that is less than or equal to the number you are converting. The corresponding hexadecimal digit is the most significant hexadecimal digit of the result. Subtract the decimal number found from the original decimal number to get the remaining decimal value. Repeat the procedure using the remaining decimal value for each subsequent hexadecimal digit.
Reference Guide 31
4th Hex Digit Hex Decimal 0 0 1 4,096 2 8,192 3 12,288 4 16,384 5 20,480 6 24,576 7 28,672 8 32,768 9 36,864 A 40,960 B 45,056 C 49,152 D 53,248 E 57,344 F 61,440
3rd Hex Digit Hex Decimal 0 0 1 256 2 512 3 768 4 1,024 5 1,280 6 1,536 7 1,792 8 2,048 9 2,304 A 2,560 B 2,816 C 3,072 D 3,328 E 3,484 F 3,840
2nd Hex Digit Hex Decimal 0 0 1 16 2 32 3 48 4 64 5 80 6 96 7 112 8 128 9 144 A 160 B 176 C 192 D 208 E 224 F 240
1st Hex Digit Hex Decimal 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A 10 B 11 C 12 D 13 E 14 F 15
A G R E E M E N T
R E Q U I R E D
CPU12 Reference Guide R E Q U I R E D N O N - D I S C L O S U R E A G R E E M E N T

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afrmative Action Employer.
How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217, 1-800-441-2447 or 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Ofce, 141, 4-32-1 Nishi-Gotanda, Shinigawa-Ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Mfax, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/
Mfax is a trademark of Motorola, Inc. Motorola, Inc., 1998
CPU12RG/D

Motorola Semiconductor Technical Data CPU12 Reference Guide: Order This Document by CPU12RG/D Rev. 1

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Motorola Semiconductor Technical Data CPU12 Reference Guide: Order This Document by CPU12RG/D Rev. 1

Загружено:

Авторское право:

Доступные форматы

Motorola Semiconductor Technical Data CPU12 Reference Guide

8-BIT ACCUMULATORS A AND B

16-BIT DOUBLE ACCUMULATOR D

Figure 1. Programming Model

CPU12 MOTOROLA CPU12 Reference Guide

Order this document by CPU12RG/D Rev. 1

CPU12 Reference Guide R E Q U I R E D Stack and Memory Layout

Interrupt Vector Locations

Reference Guide 2 CPU12 Reference Guide

CPU12 Reference Guide

Notation Used in Instruction Set Summary

CPU12 MOTOROLA CPU12 Reference Guide

CPU12 Reference Guide R E Q U I R E D

CPU12 CPU12 Reference Guide MOTOROLA

CPU12 Reference Guide

Condition Codes Columns

CPU12 MOTOROLA CPU12 Reference Guide

CPU12 Reference Guide R E Q U I R E D

Instruction Set Summary

(B) + (M) + C B Add with Carry to B

(A) + (M) A Add without Carry to A

(B) + (M) B Add without Carry to B

(A:B) + (M:M+1) A:B Add 16-Bit to D (A:B)

(A) (M) A Logical And A with Memory

(B) (M) B Logical And B with Memory

Reference Guide 6 CPU12 Reference Guide

CPU12 Reference Guide

Instruction Set Summary (Continued)

Operation (CCR) (M) CCR Logical And CCR with Memory

Machine Coding (hex) 10 ii 78 68 68 68 68 68 48 58 59 hh xb xb xb xb xb ll ff ee ff ee ff

0 b7 C Arithmetic Shift Left b0

Arithmetic Shift Left Accumulator A Arithmetic Shift Left Accumulator B

rOPw rPw rPOw frPPw fIfrPw fIPrPw O O O

b7 Arithmetic Shift Right

rPOw rPPw rPOw rPwP frPwOP PPP/P1 PPP/P1 PPP/P1

VfPPP PPP/P1 PPP/P1 PPP/P1

(B) (M) Logical And B with Memory

CPU12 MOTOROLA CPU12 Reference Guide

CPU12 Reference Guide R E Q U I R E D

BLS rel8 BLT rel8 BMI rel8 BNE rel8

PPP/P1 PPP/P1 PPP/P1 PPP/P1 PPP/P1 PPP

rPPP rfPPP rPPP rffPPP frPffPPP

(M) ' (mm) M Set Bit(s) in Memory

(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1) Subroutine address PC Branch to Subroutine

REL REL EXT IDX IDX1 IDX2 [D,IDX] [IDX2]

gnfSsPPP gnfSsPPP gnfSsPPP fgnfSsPPP fIignSsPPP fIignSsPPP

CBA CLC CLI

INH IMM IMM

Reference Guide 8 CPU12 Reference Guide

CPU12 Reference Guide

Instruction Set Summary (Continued)

Clear Accumulator A Clear Accumulator B

0V Translates to ANDCC #$FD (A) (M) Compare Accumulator A with Memory

(B) (M) Compare Accumulator B with Memory

(M) M equivalent to $FF (M) M 1s Complement Memory Location

Complement Accumulator A Complement Accumulator B

(A:B) (M:M+1) Compare D to Memory (16-Bit)

(SP) (M:M+1) Compare SP to Memory (16-Bit)

(X) (M:M+1) Compare X to Memory (16-Bit)

(Y) (M:M+1) Compare Y to Memory (16-Bit)

CPU12 MOTOROLA CPU12 Reference Guide

P rfP rOP rfP rPO frPP fIfrfP fIPrfP

CPU12 Reference Guide R E Q U I R E D