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7 15
0 7 D
0 0
15
INDEX REGISTER X
15
INDEX REGISTER Y
15
SP
STACK POINTER
15
PC
PROGRAM COUNTER
S X H I N Z V C
CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE MASK (DISABLE) IRQ INTERRUPTS HALF-CARRY (USED IN BCD ARITHMETIC) MASK (DISABLE) XIRQ INTERRUPTS RESET OR XIRQ SET X, INSTRUCTIONS MAY CLEAR X BUT CANNOT SET X STOP DISABLE (IGNORE STOP OPCODES) RESET DEFAULT IS 1
Reference Guide 1
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
YLO
YHI XLO
A G R E E M E N T
XHI
A B SP AFTER INTERRUPT CCR LOWER ADDRESSES
STACK UPON ENTRY TO SERVICE ROUTINE IF SP WAS ODD BEFORE INTERRUPT SP +8 SP +6 SP +4 RTNLO YLO XLO A CCR RTNHI YHI XHI B SP +9 SP +7 SP +5 SP +3 SP +1 SP 1
STACK UPON ENTRY TO SERVICE ROUTINE IF SP WAS EVEN BEFORE INTERRUPT SP +9 SP +7 SP +5 SP +4 SP +1 SP 1 RTNHI YHI XHI B RTNLO YLO XLO A CCR SP +10 SP +8 SP +6 SP +4 SP +2 SP
N O N - D I S C L O S U R E
SP +2 SP SP 2
CPU12 MOTOROLA
Reference Guide 3
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
N O N - D I S C L O S U R E
Reference Guide 4
A G R E E M E N T
Access Detail Each code letter equals one CPU cycle. Uppercase = 16-bit operation and lowercase = 8-bit operation. For complex sequences see the CPU12 Reference Manual (CPU12RM/AD).
f g I i n O Free cycle, CPU doesnt use bus Read PPAGE internally Read indirect pointer (indexed indirect) Read indirect PPAGE value (call indirect) Write PPAGE internally Optional program word fetch (P) if instruction is misaligned and has an odd number of bytes of object code otherwise, appears as a free cycle (f) Program word fetch (always an aligned word read) 8-bit data read 16-bit data read 8-bit stack write 16-bit stack write 8-bit data write 16-bit data write 8-bit stack read 16-bit stack read 16-bit vector fetch 8-bit conditional read (or free cycle) 16-bit conditional read (or free cycle) 8-bit conditional write Special Cases PPP/P Short branch, PPP if branch taken, P if not OPPP/OPO Long branch, OPPP if branch taken, OPO if not
Reference Guide 5
N O N - D I S C L O S U R E
P r R s S w W u U V t T x
A G R E E M E N T
R E Q U I R E D
Access Detail
S X H
ll ff ee ff ee ff
A G R E E M E N T
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP
ll ff ee ff ee ff
ll ff ee ff ee ff
ll ff ee ff ee ff kk ll ff ee ff ee ff
N O N - D I S C L O S U R E
ll ff ee ff ee ff
ll ff ee ff ee ff
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
CPU12 MOTOROLA
Addr. Mode IMM EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH
Access Detail
S X H
b0
Arithmetic Shift Right Accumulator A Arithmetic Shift Right Accumulator B Branch if Carry Clear (if C = 0) (M) (mm) M Clear Bit(s) in Memory
24 rr 4D 1D 0D 0D 0D dd hh xb xb xb mm ll mm mm ff mm ee ff mm
Branch if Carry Set (if C = 1) Branch if Equal (if Z = 1) Branch if Greater Than or Equal (if N V = 0) (signed) Place CPU in Background Mode see CPU12 Reference Manual Branch if Greater Than (if Z ' (N V) = 0) (signed) Branch if Higher (if C ' Z = 0) (unsigned) Branch if Higher or Same (if C = 0) (unsigned) same function as BCC (A) (M) Logical And A with Memory
25 rr 27 rr 2C rr 00 2E rr 22 rr 24 rr
BITA #opr8i BITA opr8a BITA opr16a BITA oprx0_xysp BITA oprx9,xysp BITA oprx16,xysp BITA [D,xysp] BITA [oprx16,xysp] BITB #opr8i BITB opr8a BITB opr16a BITB oprx0_xysp BITB oprx9,xysp BITB oprx16,xysp BITB [D,xysp] BITB [oprx16,xysp]
IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2]
85 95 B5 A5 A5 A5 A5 A5 C5 D5 F5 E5 E5 E5 E5 E5
ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb
ll ff ee ff ee ff
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP
ll ff ee ff ee ff
Notes: 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Reference Guide 7
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
S X H
REL REL REL REL REL REL DIR EXT IDX IDX1 IDX2 REL DIR EXT IDX IDX1 IDX2 DIR EXT IDX IDX1 IDX2 REL
23 rr 2D rr 2B rr 26 rr 2A rr 20 rr 4F dd mm rr 1F hh ll mm rr 0F xb mm rr 0F xb ff mm rr 0F xb ee ff mm rr 21 rr 4E dd mm rr 1E hh ll mm rr 0E xb mm rr 0E xb ff mm rr 0E xb ee ff mm rr 4C 1C 0C 0C 0C dd hh xb xb xb mm ll mm mm ff mm ee ff mm
A G R E E M E N T
BPL rel8 BRA rel8 BRCLR opr8a, msk8, rel8 BRCLR opr16a, msk8, rel8 BRCLR oprx0_xysp, msk8, rel8 BRCLR oprx9,xysp, msk8, rel8 BRCLR oprx16,xysp, msk8, rel8 BRN rel8 BRSET opr8, msk8, rel8 BRSET opr16a, msk8, rel8 BRSET oprx0_xysp, msk8, rel8 BRSET oprx9,xysp, msk8, rel8 BRSET oprx16,xysp, msk8, rel8 BSET opr8, msk8 BSET opr16a, msk8 BSET oprx0_xysp, msk8 BSET oprx9,xysp, msk8 BSET oprx16,xysp, msk8 BSR rel8
Branch Never (if 1 = 0) Branch if (M) (mm) = 0 (if All Selected Bit(s) Set)
rPPP rfPPP rPPP rffPPP frPffPPP rPOw rPPw rPOw rPwP frPwOP
PPPS
N O N - D I S C L O S U R E
07 rr
BVC rel8 BVS rel8 CALL opr16a, page CALL oprx0_xysp, page CALL oprx9,xysp, page CALL oprx16,xysp, page CALL [D,xysp] CALL [oprx16, xysp]
Branch if Overflow Bit Clear (if V = 0) Branch if Overflow Bit Set (if V = 1) (SP) 2 SP; RTNH:RTNL M(SP):M(SP+1) (SP) 1 SP; (PPG) M(SP); pg PPAGE register; Program address PC Call subroutine in extended memory (Program may be located on another expansion memory page.) Indirect modes get program address and new pg value based on pointer.
28 rr 29 rr 4A 4B 4B 4B 4B 4B hh ll pg xb pg xb ff pg xb ee ff pg xb xb ee ff
PPP/P1 PPP/P1
(A) (B) Compare 8-Bit Accumulators 0C Translates to ANDCC #$FE 0I Translates to ANDCC #$EF (enables I-bit interrupts)
18 17 10 FE 10 EF
OO
Notes 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
CPU12 MOTOROLA
S X H
N 0
Z 1
V 0
C 0
0A 0B
10 FD 81 91 B1 A1 A1 A1 A1 A1 C1 D1 F1 E1 E1 E1 E1 E1 71 61 61 61 61 61 41 51 8C 9C BC AC AC AC AC AC 8F 9F BF AF AF AF AF AF 8E 9E BE AE AE AE AE AE 8D 9D BD AD AD AD AD AD ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb hh xb xb xb xb xb
ll ff ee ff ee ff
ll ff ee ff ee ff ll ff ee ff ee ff
P rfP rOP rfP rPO frPP fIfrfP fIPrfP rOPw rPw rPOw frPPw fIfrPw fIPrPw O O OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP OP RfP ROP RfP RPO fRPP fIfRfP fIPRfP
(A) A (B) B
ff ee ff ee ff kk ll ff ee ff ee ff kk ll ff ee ff ee ff kk ll ff ee ff ee ff
jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb jj dd hh xb xb xb xb xb
Reference Guide 9
N O N - D I S C L O S U R E
jj dd hh xb xb xb xb xb
kk ll
A G R E E M E N T
R E Q U I R E D
Access Detail
OfO
S X H
V ?
PPP
REL (9-bit)
04 lb rr
PPP
A G R E E M E N T
Decrement A Decrement B
1B 9F 09 03 11 18 14 18 12 hh ll
(X) $0001 X Decrement Index Register X (Y) $0001 Y Decrement Index Register Y (Y:D) (X) Y Remainder D 32 16 Bit 16 Bit Divide (unsigned) (Y:D) (X) Y Remainder D 32 16 Bit 16 Bit Divide (signed) (M(X):M(X+1)) (M(Y):M(Y+1)) + (M~M+3) M~M+3 16 16 Bit 32 Bit Multiply and Accumulate (signed)
ffffffffffO
OffffffffffO
N O N - D I S C L O S U R E
ORROfffRRfWWP
EMAXD oprx0_xysp EMAXD oprx9,xysp EMAXD oprx16,xysp EMAXD [D,xysp] EMAXD [oprx16,xysp] EMAXM oprx0_xysp EMAXM oprx9,xysp EMAXM oprx16,xysp EMAXM [D,xysp] EMAXM [oprx16,xysp] EMIND oprx0_xysp EMIND oprx9,xysp EMIND oprx16,xysp EMIND [D,xysp] EMIND [oprx16,xysp] EMINM oprx0_xysp EMINM oprx9,xysp EMINM oprx16,xysp EMINM [D,xysp] EMINM [oprx16,xysp] EMUL
MAX((D), (M:M+1)) D MAX of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) MAX((D), (M:M+1)) M:M+1 MAX of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) MIN((D), (M:M+1)) D MIN of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) MIN((D), (M:M+1)) M:M+1 MIN of 2 Unsigned 16-Bit Values N, Z, V and C status bits reflect result of internal compare ((D) (M:M+1)) (D) (Y) Y:D 16 16 Bit Multiply (unsigned)
IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] INH
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 13
1A 1A 1A 1A 1A 1E 1E 1E 1E 1E 1B 1B 1B 1B 1B 1F 1F 1F 1F 1F
xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff
ORfP ORPO OfRPP OfIfRfP OfIPRfP ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ORfP ORPO OfRPP OfIfRfP OfIPRfP ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ffO
Notes 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. 2. opr16a is an extended address specification. Both X and Y point to source operands.
CPU12 MOTOROLA
S X H
V 0
ll ff ee ff ee ff
P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP ORRffffffP
ll ff ee ff ee ff
(M:M+1)+ [(B)((M+2:M+3) (M:M+1))] D 16-Bit Table Lookup and Interpolate Initialize B, and index before ETBL. <ea> points at first table entry (M:M+1) and B is fractional part of lookup value (no indirect addr. modes or extensions allowed)
18 3F xb
EXG abcdxys,abcdxys
(r1) (r2) (if r1 and r2 same size) or $00:(r1) r2 (if r1=8-bit; r2=16-bit) or (r1low) (r2) (if r1=16-bit; r2=8-bit) r1 and r2 may be A, B, CCR, D, X, Y, or SP
INH
B7 eb
(D) (X) X; Remainder D 16 16 Bit Fractional Divide (cntr) + 1 cntr If (cntr) = 0, then Branch else Continue to next instruction Increment Counter and Branch if = 0 (cntr = A, B, D, X, Y, or SP)
18 11 04 lb rr
OffffffffffO
PPP
(cntr) + 1 cntr if (cntr) not = 0, then Branch; else Continue to next instruction Increment Counter and Branch if 0 (cntr = A, B, D, X, Y, or SP)
REL (9-bit)
04 lb rr
PPP
IDIV IDIVS INC opr16a INC oprx0_xysp INC oprx9,xysp INC oprx16,xysp INC [D,xysp] INC [oprx16,xysp] INCA INCB INS INX INY
(D) (X) X; Remainder D 16 16 Bit Integer Divide (unsigned) (D) (X) X; Remainder D 16 16 Bit Integer Divide (signed) (M) + $01 M Increment Memory Byte
INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IDX INH INH
18 10 18 15 72 62 62 62 62 62 42 52 hh xb xb xb xb xb ll ff ee ff ee ff
OffffffffffO
OffffffffffO
(A) + $01 A (B) + $01 B (SP) + $0001 SP Translates to LEAS 1,SP (X) + $0001 X Increment Index Register X (Y) + $0001 Y Increment Index Register Y
1B 81 08 02
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
Reference Guide 11
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
S X H
A G R E E M E N T
Long Branch if Carry Clear (if C = 0) Long Branch if Carry Set (if C = 1) Long Branch if Equal (if Z = 1) Long Branch Greater Than or Equal (if N V = 0) (signed) Long Branch if Greater Than (if Z ' (N V) = 0) (signed) Long Branch if Higher (if C ' Z = 0) (unsigned) Long Branch if Higher or Same (if C = 0) (unsigned) same function as LBCC Long Branch if Less Than or Equal (if Z ' (N V) = 1) (signed) Long Branch if Lower (if C = 1) (unsigned) same function as LBCS Long Branch if Lower or Same (if C ' Z = 1) (unsigned) Long Branch if Less Than (if N V = 1) (signed) Long Branch if Minus (if N = 1) Long Branch if Not Equal (if Z = 0) Long Branch if Plus (if N = 0) Long Branch Always (if 1=1) Long Branch Never (if 1 = 0) Long Branch if Overflow Bit Clear (if V=0) Long Branch if Overflow Bit Set (if V = 1) (M) A Load Accumulator A
18 24 qq rr 18 25 qq rr 18 27 qq rr 18 2C qq rr 18 2E qq rr 18 22 qq rr 18 24 qq rr
REL REL
18 2F qq rr 18 25 qq rr
OPPP/OPO1 OPPP/OPO1
LBLS rel16
REL REL REL REL REL REL REL REL REL IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2]
18 23 qq rr 18 2D qq rr 18 2B qq rr 18 26 qq rr 18 2A qq rr 18 20 qq rr 18 21 qq rr 18 28 qq rr 18 29 qq rr 86 96 B6 A6 A6 A6 A6 A6 C6 D6 F6 E6 E6 E6 E6 E6 ii dd hh xb xb xb xb xb ii dd hh xb xb xb xb xb
OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP/OPO1 OPPP OPO OPPP/OPO1 OPPP/OPO1 P rfP rOP rfP rPO frPP fIfrfP fIPrfP P rfP rOP rfP rPO frPP fIfrfP fIPrfP
N O N - D I S C L O S U R E
LBLT rel16 LBMI rel16 LBNE rel16 LBPL rel16 LBRA rel16 LBRN rel16 LBVC rel16 LBVS rel16 LDAA #opr8i LDAA opr8a LDAA opr16a LDAA oprx0_xysp LDAA oprx9,xysp LDAA oprx16,xysp LDAA [D,xysp] LDAA [oprx16,xysp] LDAB #opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysp LDAB oprx9,xysp LDAB oprx16,xysp LDAB [D,xysp] LDAB [oprx16,xysp]
ll ff ee ff ee ff
ll ff ee ff ee ff
Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
CPU12 MOTOROLA
S X H
V 0
Effective Address SP Load Effective Address into SP Effective Address X Load Effective Address into X Effective Address Y Load Effective Address into Y
1B xb 1B xb ff 1B xb ee ff 1A xb 1A xb ff 1A xb ee ff 19 xb 19 xb ff 19 xb ee ff 78 68 68 68 68 68 48 58 59 hh xb xb xb xb xb ll ff ee ff ee ff
74 64 64 64 64 64 44 54
hh xb xb xb xb xb
ll ff ee ff ee ff
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
Reference Guide 13
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Operation
Addr. Mode INH b0 C IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] Special 18 18 18 18 18 18 18 18 18 18 01 49
Access Detail
S X H
N 0
18 18 18 18 18 1C 1C 1C 1C 1C
xb xb ff xb ee ff xb xb ee ff xb xb ff xb ee ff xb xb ee ff
OrfP OrPO OfrPP OfIfrfP OfIPrfP OrPw OrPwO OfrPwP OfIfrPw OfIPrPw RRfOw
A G R E E M E N T
N O N - D I S C L O S U R E
ii xb hh xb xb xb jj xb hh xb xb xb
NEG opr16a NEG oprx0_xysp NEG oprx9,xysp NEG oprx16,xysp NEG [D,xysp] NEG [oprx16,xysp] NEGA NEGB NOP
0 (A) A equivalent to (A) + 1 A Negate Accumulator A 0 (B) B equivalent to (B) + 1 B Negate Accumulator B No Operation
70 60 60 60 60 60 40 50 A7
hh xb xb xb xb xb
ll ff ee ff ee ff
Note 1. The first operand in the source code statement specifies the source for the move.
CPU12 MOTOROLA
S X H
V 0
ll ff ee ff ee ff
ll ff ee ff ee ff
(CCR) ' M CCR Logical OR CCR with Memory (SP) 1 SP; (A) M(SP) Push Accumulator A onto Stack
14 ii 36
Os
PSHB
INH
37
Os
PSHC
INH
39
Os
PSHD
INH
3B
OS
PSHX
INH
34
OS
PSHY
INH
35
OS
PULA
INH
32
ufO
PULB
INH
33
ufO
PULC
INH
38
ufO
PULD
INH
3A
UfO
PULX
INH
30
UfO
PULY
INH
31
UfO
Reference Guide 15
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
S X H ?
N ?
Z ?
C ?
A G R E E M E N T
MIN-MAX rule evaluation Find smallest rule input (MIN), Store to rule outputs unless fuzzy output is already larger (MAX). Rule weights supported, optional. Each rule input is the 16-bit address of a fuzzy input. Each rule output is the 16-bit address of a fuzzy output. The value $FFFE separates rule inputs from rule outputs. $FFFF terminates the rule list. REVW may be interrupted.
Special
18 3B
ROL opr16a ROL oprx0_xysp ROL oprx9,xysp ROL oprx16,xysp ROL [D,xysp] ROL [oprx16,xysp] ROLA ROLB ROR opr16a ROR oprx0_xysp ROR oprx9,xysp ROR oprx16,xysp ROR [D,xysp] ROR [oprx16,xysp] RORA RORB RTC
b0
EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH
75 65 65 65 65 65 45 55 76 66 66 66 66 66 46 56 0A
hh xb xb xb xb xb
ll ff ee ff ee ff
rOPw rPw rPOw frPPw fIfrPw fIPrPw O O rOPw rPw rPOw frPPw fIfrPw fIPrPw O O uUnPPP
N O N - D I S C L O S U R E
hh xb xb xb xb xb
ll ff ee ff ee ff
Rotate A Right through Carry Rotate B Right through Carry (M(SP)) PPAGE; (SP) + 1 SP; (M(SP):M(SP+1)) PCH:PCL; (SP) + 2 SP Return from Call
(M(SP)) CCR; (SP) + 1 SP (M(SP):M(SP+1)) B:A; (SP) + 2 SP (M(SP):M(SP+1)) XH:XL; (SP) + 4 SP (M(SP):M(SP+1)) PCH:PCL; (SP) 2 SP (M(SP):M(SP+1)) YH:YL; (SP) + 4 SP Return from Interrupt
INH
0B
uUUUUPPP uUUUUVfPPP
RTS
INH
3D
UfPPP
SBA
INH
18 16
OO
Notes: 1. The 3-cycle loop in parentheses is executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt. 2. The 3-cycle loop in parentheses expands to 5 cycles for separators when weighting is enabled. The loop is executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt.
CPU12 MOTOROLA
S X H
ll ff ee ff ee ff
ll ff ee ff ee ff
1C Translates to ORCC #$01 1 I; (inhibit I interrupts) Translates to ORCC #$10 1V Translates to ORCC #$02 $00:(r1) r2 if r1, bit 7 is 0 or $FF:(r1) r2 if r1, bit 7 is 1 Sign Extend 8-bit r1 to 16-bit r2 r1 may be A, B, or CCR r2 may be D, X, Y, or SP Alternate mnemonic for TFR r1, r2
14 01 14 10 14 02 B7 eb
ee ff ll ff ee ff ee ff ll ff ee ff ee ff
STAB opr8a STAB opr16a STAB oprx0_xysp STAB oprx9,xysp STAB oprx16,xysp STAB [D,xysp] STAB [oprx16,xysp] STD opr8a STD opr16a STD oprx0_xysp STD oprx9,xysp STD oprx16,xysp STD [D,xysp] STD [oprx16,xysp] STOP (entering STOP) (exiting STOP) (continue) (if STOP disabled)
DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH
5B 7B 6B 6B 6B 6B 6B 5C 7C 6C 6C 6C 6C 6C
dd hh xb xb xb xb xb dd hh xb xb xb xb xb
Pw wOP Pw PwO PwP PIfPw PIPPw PW WOP PW PWO PWP PIfPW PIPPW OOSSSfSs fVfPPP fO OO
(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP); STOP All Clocks If S control bit = 1, the STOP instruction is disabled and acts like a two-cycle NOP. Registers stacked to allow quicker recovery by interrupt.
18 3E
Reference Guide 17
N O N - D I S C L O S U R E
STAA opr8a STAA opr16a STAA oprx0_xysp STAA oprx9,xysp STAA oprx16,xysp STAA [D,xysp] STAA [oprx16,xysp]
5A 7A 6A 6A 6A 6A 6A
dd hh xb xb xb xb xb
ll ff ee ff
A G R E E M E N T
R E Q U I R E D
S X H
V 0
A G R E E M E N T
ll ff ee ff ee ff
ll ff ee ff ee ff kk ll ff ee ff ee ff
N O N - D I S C L O S U R E
(SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP) 1 I; (SWI Vector) PC Software Interrupt
18 0E B7 02 18 0F
OO
OO
Note 1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A variation of the sequence (VfPPP) is used for resets.
CPU12 MOTOROLA
Access Detail
PPP
S X H
Test Counter and Branch if Not Zero (cntr = A, B, D, X,Y, or SP) TFR abcdxys,abcdxys (r1) r2 or $00:(r1) r2 or (r1[7:0]) r2 Transfer Register to Register r1 and r2 may be A, B, CCR, D, X, Y, or SP TPA TRAP trapnum (CCR) A Translates to TFR CCR ,A (SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP) 1 I; (TRAP Vector) PC Unimplemented opcode trap INH INH B7 20 18 tn tn = $30$39 or $40$FF
P
INH
B7 eb
or
OfVSPSSPSsP
ff ee ff ee ff
(A) 0 (B) 0
TSX TSY TXS TYS WAI (before interrupt) (when interrupt comes)
(SP) X Translates to TFR SP,X (SP) Y Translates to TFR SP,Y (X) SP Translates to TFR X,SP (Y) SP Translates to TFR Y,SP (SP) 2 SP; RTNH:RTNL M(SP):M(SP+1); (SP) 2 SP; (YH:YL) M(SP):M(SP+1); (SP) 2 SP; (XH:XL) M(SP):M(SP+1); (SP) 2 SP; (B:A) M(SP):M(SP+1); (SP) 1 SP; (CCR) M(SP); WAIT for interrupt
B7 75 B7 76 B7 57 B7 67 3E
or or 1
1 1
OSSSfSsf VfPPP
Reference Guide 19
N O N - D I S C L O S U R E
TST opr16a TST oprx0_xysp TST oprx9,xysp TST oprx16,xysp TST [D,xysp] TST [oprx16,xysp] TSTA TSTB
F7 E7 E7 E7 E7 E7 97 D7
hh xb xb xb xb xb
ll
A G R E E M E N T
TBNE abdxys,rel9
REL (9-bit)
04 lb rr
PPP
R E Q U I R E D
Si Fi Y:D
i=1 B
Fi X i=1 Calculate Sum of Products and Sum of Weights for Weighted Average Calculation
Initialize B, X, and Y before WAV. B specifies number of elements. X points at first element in Si list. Y points at first element in Fi list. All Si and Fi elements are 8-bits. If interrupted, six extra bytes of stack used for intermediate values wavr pseudoinstruction XGDX XGDY see WAV Resume executing an interrupted WAV instruction (recover intermediate results from stack rather than initializing them to zero) (D) (X) Translates to EXG D, X (D) (Y) Translates to EXG D, Y INH INH B7 C5 B7 C6
P
A G R E E M E N T
Special
3C
N O N - D I S C L O S U R E
Reference Guide 20 CPU12 Reference Guide
CPU12 MOTOROLA
Key to Table 1
postbyte (hex)
B0
#,REG
type
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
111rr0zs
rr1pnnnn
A G R E E M E N T
111rr1aa
111rr011 111rr111
[n,r] [D,r]
N O N - D I S C L O S U R E
Reference Guide 22 CPU12 Reference Guide
CPU12 MOTOROLA
CPU12
LS 0 1 2 3 4 5 6 7 MS 0
AA AB
2
CCR A CCR B CCR CCR
3
TMP3L A TMP3L B TMP3L CCR TMP3 TMP2 TMP3 D TMP3 X TMP3 Y TMP3 SP
4
BA BB B CCR D TMP2 DD DX DY D SP
5
XL A XL B XL CCR X TMP2 XD XX XY X SP
6
YL A YL B YL CCR Y TMP2 YD YX YY Y SP
7
SPL A SPL B SPL CCR SP TMP2 SP D SP X SP Y SP SP
A CCR
sex:A TMP2 sex:B TMP2 sex:CCR TMP2 sex:A D SEX A,D sex:A X SEX A,X sex:A Y SEX A,Y sex:A SP SEX A,SP sex:B D SEX B,D sex:B X SEX B,X sex:B Y SEX B,Y sex:B SP SEX B,SP sex:CCR D SEX CCR,D sex:CCR X SEX CCR,X sex:CCR Y SEX CCR,Y sex:CCR SP SEX CCR,SP
EXCHANGES LS 0 1 2 3 4 5 6 7 MS 8
AA AB A CCR
9
BA BB B CCR
A
CCR A CCR B CCR CCR
B
TMP3L A $00:A TMP3 TMP3L B $FF:B TMP3
C
BA AB BB $FF A
D
XL A $00:A X XL B $FF:B X
E
YL A $00:A Y YL B $FF:B Y
F
SPL A $00:A SP SPL B $FF:B SP
TMP3L CCR B CCR XL CCR YL CCR SPL CCR $FF:CCR TMP3 $FF:CCR D $FF:CCR X $FF:CCR Y $FF:CCR SP TMP3 TMP2 TMP3 D TMP3 X TMP3 Y TMP3 SP D TMP2 DD DX DY D SP X TMP2 XD XX XY X SP Y TMP2 YD YX YY Y SP SP TMP2 SP D
$00:A TMP2 $00:B TMP2 $00:CCR TMP2 TMP2L A TMP2L B TMP2L CCR $00:CCR D $00:A D $00:B D B CCR $00:A X XL A $00:A Y YL A $00:A SP SPL A $00:B X XL B $00:B Y YL B $00:B SP SPL B $00:CCR X XL CCR $00:CCR Y YL CCR $00:CCR SP SPL CCR
SP X SP Y SP SP
Reference Guide
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
DBEQ
(+) 01
DBEQ
() B 11
DBNE
(+) B 21
DBNE
() B 31
TBEQ
(+) B 41
TBEQ
() B 51
TBNE
(+) B 61
TBNE
() B 71 B 81
IBEQ
(+) B 91
IBEQ
()
IBNE
(+) B A1
IBNE IBNE
DBEQ
(+) 02 03 04
DBEQ
() 12 13 D 14
DBNE
(+) 22 23 D 24
DBNE
() 32 33 D 34
TBEQ
(+) 42 43 D 44
TBEQ
() 52 53 D 54
TBNE
(+) 62 63 D 64
TBNE
() 72 73 D 74 D 84 83 82
IBEQ
(+) 92 93
IBEQ
()
IBNE
(+) A2
A G R E E M E N T
DBEQ
(+) 05
DBEQ
() X 15
DBNE
(+) X 25
DBNE
() X 35
TBEQ
(+) X 45
TBEQ
() X 55
TBNE
(+) X 65
TBNE
() X 75 X 85
IBEQ
(+) X 95
IBEQ
()
IBNE
(+) X A5
DBEQ
(+) 06
DBEQ
() Y 16
DBNE
(+) Y 26
DBNE
() Y 36
TBEQ
(+) Y 46
TBEQ
() Y 56
TBNE
(+) Y 66
TBNE
() Y 76 Y 86
IBEQ
(+) Y 96
IBEQ
()
IBNE
(+) Y A6
DBEQ
(+) 07 (+)
DBEQ
()
DBNE
(+)
DBNE
()
TBEQ
(+)
TBEQ
()
TBNE
(+)
TBNE
() SP 87 ()
IBEQ
(+) SP 97
IBEQ
()
IBNE
(+)
SP 17 ()
SP 27 (+)
SP 37 ()
SP 47 (+)
SP 57 ()
SP 67 (+)
SP 77
SP A7
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
(+)
IBEQ
()
IBNE
Key to Table 4
postbyte (hex) (bit 3 is dont care) counter used
B0 () A
_BEQ
branch condition
N O N - D I S C L O S U R E
sign of 9-bit relative branch offset (lower eight bits are an extension byte following postbyte)
CPU12 MOTOROLA
Memory Expansion
Some M68HC12 derivatives support >4 megabytes of program memory. Memory precedence Highest On-chip registers (usually $0000 or $1000) BDM ROM (only when BDM active) On-chip RAM On-chip EEPROM On-chip program memory (FLASH or ROM) Expansion windows (on MCUs with expanded memory) Other external memory Lowest CPU sees 64 Kbytes of address space (CPU_ADDR [15:0]) PPAGE 8-bit register to select 1 of 256 16 Kbyte program pages DPAGE 8-bit register to select 1 of 256 4 Kbyte data pages EPAGE 8-bit register to select 1 of 256 1 Kbyte extra pages Extended address is 22 bits (EXT_ADDR [21:0]) Program expansion window works with CALL and RTC instructions to simplify program access to extended memory space. Data and extra expansion windows (when present) use traditional banked expansion memory techniques. Program window If CPU_ADDR [15:0] = $8000BFFF and PWEN = 1 Then EXT_ADDR [21:0] = PPAGE [7:0]:CPU_ADDR [13:0] Program window works with CALL/RTC to automate bank switching. 256 pages (banks) of 16 Kbytes each = 4 M. Data window If CPU_ADDR [15:0] = $70007FFF and DWEN = 1 Then EXT_ADDR [21:0] = 1:1:DPAGE [7:0]:CPU_ADDR [11:0] User program controls DPAGE value
Reference Guide 25
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
N O N - D I S C L O S U R E
Reference Guide 26 CPU12 Reference Guide
A G R E E M E N T
CPU12 MOTOROLA
00 0000 30 0000 E window (EWDIR = 1) 3C 0000 0000 0400 07FF 3E FFFF 3F 0000
256 pages of 16 Kbytes each viewed through P-window 256 pages of 4 Kbytes each viewed through D-window
. . .
. . .
DPAGE ($F0) 240 DPAGE ($F1) 241 DPAGE ($F2) 242 DPAGE ($F3) 243 DPAGE ($F4) 244 DPAGE ($F5) 245 DPAGE ($F6) 246 DPAGE ($F7) 247 DPAGE ($F8) 248 DPAGE ($F9) 249 DPAGE ($FA) 250 DPAGE ($FB) 251 DPAGE ($FC) 252 DPAGE ($FD) 253 DPAGE ($FE) 254 DPAGE ($FF) 255
. . .
224 225 226 227 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 228
3FFF 4000
P window
9FFF A000
BFFF C000
3F BFFF 3F C000
DFFF E000
FFFF CPU_ADDR
3F FFFF EXT_ADDR
Reference Guide 27
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
N O N - D I S C L O S U R E
28 CPU12 Reference Guide MOTOROLA CPU12 Reference Guide
A G R E E M E N T
*5
10
1 20
3 30
3 40 1 IH 3 41 1 IH 3 42
1 50 1 IH 1 51 1 IH 1 52
1 60 1 ID 1 61 1 ID 1 62 1 ID 1 63 1 ID 1 64 1 ID 1 65 1 ID 1 66 1 ID 1 67 1 ID 1 68 1 ID 1 69 1 ID 2 6A 2 ID 2 6B 2 ID 2 6C 2 ID 2 6D 2 ID 2 6E 2 ID 2 6F 2 ID
3-6 70
4 80
1 90
3 A0 2 ID 3 A1 2 ID 3 A2 2 ID 3 A3 2 ID 3 A4 2 ID 3 A5 2 ID 3 A6 2 ID 1 A7 1 IH 3 A8 2 ID 3 A9 2 ID 3 AA 2 ID 3 AB 2 ID 3 AC 2 ID 3 AD 2 ID 3 AE 2 ID 3 AF 2 ID
3-6 B0
3 C0
1 D0
3 E0 2 ID 3 E1 2 ID 3 E2 2 ID 3 E3 2 ID 3 E4 2 ID 3 E5 2 ID 3 E6 2 ID 1 E7 1 ID 3 E8 2 ID 3 E9 2 ID 3 EA 2 ID 3 EB 2 ID 3 EC 2 ID 3 ED 2 ID 3 EE 2 ID 3 EF 2 ID
3-6 F0
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
BGND MEM
IH 02
ANDCC EDIV
BRA BRN
PULX
2 IH 1 31
NEG COM INC DEC LSR ROL ROR ASR ASL CLR STAA STAB STD STY STX STS
NEG COM INC DEC LSR ROL ROR ASR ASL CLR STAA STAB STD STY STX STS
SUBA
3 IM 4 81 3 IM 4 82
SUBA
2 DI 1 91 2 DI 1 92
SUBA CMPA SBCA SUBD ANDA BITA LDAA NOP EORA ADCA ORAA ADDA CPD CPY CPX CPS
SUBB
3 IM 3 C1 3 IM 3 C2
SUBB
2 DI 1 D1 2 DI 1 D2
SUBB CMPB SBCB ADDD ANDB BITB LDAB TST EORB ADCB ORAB ADDB LDD LDY LDX LDS
SUBB CMPB SBCB ADDD ANDB BITB LDAB TST EORB ADCB ORAB ADDB LDD LDY LDX LDS
1 IM 5 11 1 IH 1 12
2-4 EX 3-6 71 2-4 EX 3-6 72 2-4 EX 3-6 73 2-4 EX 3-6 74 2-4 EX 3-6 75 2-4 EX 3-6 76 2-4 EX 3-6 77 2-4 EX 3-6 78 2-4 EX 2-5 79 2-4 EX 2-5 7A 2-4 EX 2-5 7B 2-4 EX 2-5 7C 2-4 EX 2-5 7D 2-4 EX 2-5 7E 2-4 EX 2-5 7F 2-4 EX
2-4 EX 3-6 B1 2-4 EX 3-6 B2 2-4 EX 3-6 B3 2-4 EX 3-6 B4 2-4 EX 3-6 B5 2-4 EX 3-6 B6 2-4 EX 1 B7 1 IH 3-6 B8 2-4 EX 3-6 B9 2-4 EX 3-6 BA 2-4 EX 3-6 BB
2-4 EX 3-6 F1 2-4 EX 3-6 F2 2-4 EX 3-6 F3 2-4 EX 3-6 F4 2-4 EX 3-6 F5 2-4 EX 3-6 F6 2-4 EX 3-6 F7 2-4 EX 3-6 F8 2-4 EX 3-6 F9 2-4 EX 3-6 FA 2-4 EX 3-6 FB 2-4 EX 3-6 FC 2-4 EX 3-6 FD 2-4 EX 3-6 FE 2-4 EX 3-6 FF 2-4 EX
PULY PULA PULB PSHX PSHY PSHA PSHB PULC PSHC PULD PSHD wavr RTS WAI SWI
2 IH
CMPA SBCA
3 IM 4 83 3 IM 4 84
CMPA SBCA
CMPB SBCB
CMPB SBCB
2 IH 3/1 32 2 IH 3/1 33 2 IH 3/1 34 2 IH 3/1 35 2 IH 3/1 36 2 IH 3/1 37 2 IH 3/1 38 2 IH 3/1 39 2 IH 3/1 3A 2 IH 3/1 3B 2 IH 3/1 3C 2 SP 3/1 3D 2 IH 3/1 3E 2 IH 3/1 3F
INY
IH 03
MUL
1 IH 1 13 1 IH 3 14
BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE
1 IH 1 53 1 IH 1 54
2 DI 2 93 3 DI 1 94
3 IM 3 C3 3 IM 3 C4 3 IM 3 C5
2 DI 2 D3 3 DI 1 D4 2 DI 1 D5
DEY
IH 04
DECA LSRA
1 IH 2 45
DECB LSRB
SUBD ANDA
3 IM 4 85
SUBD ANDA
loop JMP
RL 05 ID 06 EX 07
3 IM 3-6 15 2-4 ID 3 16
1 IH 1 55
2 DI 1 95
ROLA
1 IH 2 46 1 IH 2 47
ROLB
1 IH 1 56 1 IH 1 57
BITA
3 IM 4 86
BITA
2 DI 1 96
3 IM 3 C6
2 DI 1 D6
JMP BSR
RL 08
RORA ASRA
1 IH 3 48
RORB ASRB
LDAA
3 IM 4 87
LDAA
2 DI 1 97
LDAB
3 IM 1 C7 2 IH 3 C8 3 IM 3 C9 3 IM 3 CA 3 IM 3 CB 3 IM 3 CC
LDAB
2 DI 1 D7
JSR
2 DI 1 18 1 1 19
CLRA
3 IH 4 88 3 IM 3 89 3 IM 3 8A 3 IM 3 8B
TSTA
1 IH 1 98 2 DI 1 99 2 DI 1 9A 2 DI 1 9B
TFR/EXG CLRB EORA ADCA ORAA ADDA CPD CPY CPX CPS EORB ADCB ORAB ADDB LDD
3 IM 3 CD
TSTB
1 IH 1 D8 2 DI 1 D9 2 DI 1 DA 2 DI 1 DB 2 DI 2 DC
1 IH 1 58
INX
IH 09
page 2 LEAY
1 ID 6 1A 1 ID 8 1B
ASLA
1 IH 2 49
ASLB
1 IH 1 59
DEX
IH 0A
ASLD
1 IH 8 5A
1 IH 3 4A
RTC
IH 0B
RTI
IH 0C ID 0D ID 0E ID 0F ID
2 DI 2 9C
CPD
3 IM 3 8D
CPD
3 DI 2 9D
3 DI 2 DD
BCLR BRSET
1 DI 9 4F 1 DI
STY
3 DI 4 5E
CPY
3 IM 3 8E
CPY
3 DI 2 9E
LDY
3 IM 3 CE
LDY
3 DI 2 DE
1 DI *8 4E
STX STS
CPX
3 IM 3 8F
CPX
3 DI 2 9F
LDX
3 IM 3 CF
LDX
3 DI 2 DF
4 DI 4 5F 4 DI
BRCLR
CPS
3 IM
CPS
3 DI
LDS
3 IM
LDS
3 DI
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP REV REVW WAV TBL STOP ETBL
4 ID
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP
2 RL 12 21 2 RL 13 22 4 RL 3 23 2 RL 12 24 2 RL 12 25
EX-ID 5 IH 02 5 12 4 SP 5 13
LBNE LBEQ LBVC LBVS LBPL LBMI LBGE LBLT LBGT LBLE
DAA
IH 08 IM-ID 09
CBA
2 IH 4 18 4 ID 5 19
2 RL 4-7 28 3-5 RL 4-7 29 3-5 RL 4-7 2A 3-5 RL 4-7 2B 3-5 RL 4-7 2C 3-5 RL 4-7 2D 3-5 RL 4-7 2E 3-5 RL 4-7 2F 3-5 RL
EX-ID 5 ID 0A 5 1A 4 ID 4 1B
4 ID 4/3 3E 4 IH 4/3 3F
TRAP TRAP
TBA
IH
EMINM
* Refer to instruction summary for more information. The opcode $04 corresponds to one of the loop primitive instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
` grave
a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL delete
quote
# $ % &
A G R E E M E N T
apost.
( ) * + , comma
- dash . period
/ 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
N O N - D I S C L O S U R E
Reference Guide 30
Reference Guide 31
N O N - D I S C L O S U R E
4th Hex Digit Hex Decimal 0 0 1 4,096 2 8,192 3 12,288 4 16,384 5 20,480 6 24,576 7 28,672 8 32,768 9 36,864 A 40,960 B 45,056 C 49,152 D 53,248 E 57,344 F 61,440
3rd Hex Digit Hex Decimal 0 0 1 256 2 512 3 768 4 1,024 5 1,280 6 1,536 7 1,792 8 2,048 9 2,304 A 2,560 B 2,816 C 3,072 D 3,328 E 3,484 F 3,840
2nd Hex Digit Hex Decimal 0 0 1 16 2 32 3 48 4 64 5 80 6 96 7 112 8 128 9 144 A 160 B 176 C 192 D 208 E 224 F 240
A G R E E M E N T
R E Q U I R E D
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CPU12RG/D