] cP1610 16-Bit Microprocessor FEATURES 1S program accesible bit genera purpoee raisers 1 Unltd intrus nesting ane proty resolution 5 Einar ang uni noe DESCRIPTION ‘cessor produc family. tis a complete, 16-bit, single chip, high ‘Spend WOS-SI Miroprceator The Ses 10 ami ab fated win ne Gana Instrument «Chane! fonlmpat ro tdctionnstory ll amber ofthe Series 160 fay rey compute wiht CPS home information centers, programasieclouatr systems, Drocessors. numerical conta! systems and many general ER pity aperensaripunch A/D ADAconverer keyboar, ADLEAD DUAL INLINE. na eteint processing of lpnenumen or bye ote data [ny combination a he program meer, Sta memory. perp ‘GPiGiO SYSTEM DIAGRAMPROCESSOR SIGNALS DATA SUS boots InpevOutpuvtighimpesance caren, and insrictons belween the. micoproctso” rmamory, and peripheral coves, at ‘SToP-STareE6ge-tiggered by negative ransition: used com twltne roning Condon le maroprocease HALT Output HALT nlcate that he micrprocesoris in stopped mode syne Input Master SYNC: Activ low input synchronizes the miroprocessor toe a. 62 leks auting pomer-v nalzaton, Encaos ouput External Branen Condition Adresse 0-3: Adress for one 16 {era cata ata ets vi tw BEX (ranch on xTera) act opt External ranch Congtion Input Retur sgnl tom the one- ‘tdeaalecton made by ESCAO'S. =) BUS CONTROL ‘a, cr, 22 caged to det the sate of bus operations {ene State Flow Slag ‘usKO Input osm Suput BUS Request AUS Acknowledge: BUSRO" quests the mic processor fo rainquah cor! othe bus indefinitely. BUSAK™ Frouma devices hat te bus has bean releases, ‘sono Inout un Osta ReaD: cautes te miroprocesso o “walt” and re fyechronizeto slow memery and peripheral devices. INTERUpLINTeRUp! Mashed: request the miroprocessor 10 rien en nero upon complaton of current matucbon. a Oitst Terminate CurrntIntrup: pul outputted by the micro rocessornrespons ote TE inatucton. for Program Counter nhibi/Tap: AS an input, ais increment tion of th Program Counter suring the Iaructon tech 3 (uence. Asan output generates a pulse diving execution of Softare itera! (sinh mevucton ‘CPI610 INTERNAL BLOCK DIAGRAMns NE cPr610 SIMPLIFIED STATE FLOW DIAGRAM {__—F US CONTROL SIGNALS OR BC2 ACI Signal Decoded Function oO 0 1 ADAR Address Data to. ‘Address Register ‘o-o1s nigh mpedance © 10 1AB—_neruptAdcres fou. BO-D5 8 + Ore Data To Bus bo-DTS = input 7 08 BAR—_—Bus to Aderese Register + 83 Bw. Gata wate + $a Bits Bata ite Srobe 1 Anta temupr Acknowedge