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Thit k v m phng khi RAM 32x8 bit c 2 cng, 1 cng c khng ng b v 1 cng ghi ng b.

y l phn thit k: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -----------------------------------------------------------------------entity dpRAM_aREAD_sWRITE is generic ( DATA_WIDTH :integer := 8; ADDR_WIDTH :integer := 5 ); port ( address_A :in std_logic_vector (ADDR_WIDTH-1 downto 0); data_out_A:out std_logic_vector (DATA_WIDTH-1 downto 0); cs_A :in std_logic; we_A :in std_logic; oe_A :in std_logic;

address_B :in std_logic_vector (ADDR_WIDTH-1 downto 0); data_in_B :in std_logic_vector (DATA_WIDTH-1 downto 0); cs_B :in std_logic; we_B :in std_logic; oe_B :in std_logic; clk :in std_logic ); end entity; -----------------------------------------------------------------------architecture behavioral of dpRAM_aREAD_sWRITE is constant RAM_DEPTH :integer := 2**ADDR_WIDTH; type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0); signal mem : RAM (0 to RAM_DEPTH-1); begin OPERATION : process (clk, address_A, address_B) begin if(address_A /= address_B) then if (cs_A = '1' and we_A = '0' and oe_A = '1') then data_out_A <= mem(conv_integer(address_A));

elsif (rising_edge(clk) and cs_B = '1' and we_B = '1' and oe_B <= '0') then mem(conv_integer(address_B)) <= data_in_B; end if; else if (rising_edge (clk) and cs_B <= '1' and we_B <= '1'and oe_B <= '0' and cs_A = '1' and we_A = '0' and oe_A = '1' ) then mem(conv_integer(address_B)) <= data_in_B; --Cong B se thuc hien ghi truoc, sau do cong A doc ket qua data_out_A <= mem(conv_integer(address_A)); end if; end if; end process OPERATION; end architecture; Cn y l phn test: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------Entity test is End Entity; --------------------------------------------------Architecture structure of test is signal we_A : std_logic; signal cs_A : std_logic; signal oe_A : std_logic; signal address_A : std_logic_vector(4 downto 0):= "01010"; signal data_out_A : std_logic_vector(7 downto 0); signal we_B : std_logic; signal cs_B : std_logic; signal oe_B : std_logic; signal address_B : std_logic_vector(4 downto 0):= "00000"; signal data_in_B : std_logic_vector(7 downto 0):= "01111000"; signal clk : std_logic :='0'; component dpRAM_aREAD_sWRITE is generic ( DATA_WIDTH :integer := 8;

ADDR_WIDTH :integer := 5 ); port(address_A :in std_logic_vector (ADDR_WIDTH-1 downto 0); data_out_A:out std_logic_vector (DATA_WIDTH-1 downto 0); cs_A :in std_logic; we_A :in std_logic; oe_A :in std_logic; address_B :in std_logic_vector (ADDR_WIDTH-1 downto 0); data_in_B :in std_logic_vector (DATA_WIDTH-1 downto 0); cs_B :in std_logic; we_B :in std_logic; oe_B :in std_logic; clk :in std_logic ); end component; begin --create_clock create_clock: process begin wait for 15 ns; clk <= not clk after 50 ns; end process create_clock; OPERATION : process (clk) variable operation_cnt_A : integer := 0; variable operation_cnt_B : integer := 0; begin if (operation_cnt_A < 8) then cs_A <= '1'; we_A <= '0'; oe_A <= '1'; address_A <= address_A - 1; operation_cnt_A := operation_cnt_A + 1; elsif (operation_cnt_B < 8) then if (rising_edge (clk)) then cs_B <= '1'; we_B <= '1'; oe_B <= '0'; address_B <= address_B + 1; data_in_B <= data_in_B + 10; end if;

operation_cnt_B := operation_cnt_B +1; end if; end process OPERATION; memunit: component dpRAM_aREAD_sWRITE generic map (DATA_WIDTH => 8, ADDR_WIDTH => 5) port map (address_A, data_out_A, cs_A, we_A, oe_A, address_B, data_in_B, cs_B, we_B, oe_B, clk); End architecture;

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