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# Binary Subtraction The circuitry required for computers to add binary numbers is relatively simple.

However, since circuitry to subtract binary numbers is very difficult to design and build, another subtraction method would be desirable. The method is subtraction by addition of the 1s or 2s complements of the number. Subtraction by the addition of 1s complement requires much more hardware to implement. Most computers on the market perform subtraction by the addition of 2s complement. Therefore we will concentrate only on subtraction by 2s complement. Binary number 1s complement 2s complement = = = 10111001 01000110 01000111

When subtraction is performed the answer can be positive or negative, depending upon the relative value of the minuend and subtrahend. We must, therefore, in some way account for the sign of the answer. The most significant bit (MSB) is used as the sign bit. If the MSB is a 1, the number represented by the remaining 7 bits is assumed to be negative and is represented by its 2s complement. If the MSB is a 0, the number represented in the remaining seven bits is positive and is equal to the binary equivalent of these seven bits. Example 1: 1710 610 = (1116 616) 00000110 = 616 11111001 = 1s complement of 616 11111010 = 2s complement of 616 00010001 11111010 _________ 100001011 10000 1011 Example 2: 1116 616 in 2s complement

+ 0B16 = + 1110

610 - 1710 or (616 1116) 00010001 = 1116 11101110 = 1s complement of 1116 11101111 = 2s complement of 1116 00000110 (616) 11101111 (1116 in 2s complement) -----------11110101

11110101 = - (00001010 + 1) = - 00001011 = - 0B16 or - 1110 Note: C and N bits will be set. Since bit 7 serves as the sign bit. A 0 in bit 7 indicates a positive number. Thus the maximum positive number an 8-bit processor can represent in 2s complement is 011111112 or 7F16 or 12710. Likewise a 1 in bit 7 indicates a negative number. The minimum negative number that an 8-bit processor can represent in 2s complement is 8016 (10000000). In binary it is 2s complement of 10000000 = - 10000000 = - 8016 = -12810 Thus the maximum possible negative number represented by an 8-bit processor in 2s complement is 10000000. Its 2s complement is (01111111 + 1) = - (10000000) = - 8016 = - 12810 It is possible to (add) or subtract two numbers and get invalid answer, especially when the answer is out of the range of 128 +127 This situation is referred to as 2s complement overflow. If a subtraction (or addition) is performed and 2s complement overflow occurs the V bit will be set to a 1 otherwise it will be cleared. Example: - 8510 9010 = -17510 8510 10101010 10101011 9010 10100101 10100110 = = = = = = 5516 = 010101012 1s comp. of 5516 2s comp. of 5516 5A16 = 010110102 1s comp. of 5A 2s comp. of 5A

10101011 (2s comp. of 5516) + 10100110 (2s comp. of 5A16) -----------------------1 01010001 = + 5116 V bit will be set. C bit will be set. 4D16 + 8816

= +8110