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Abstract Design Fabrication Performance FinFET Layout Conclusion

Double-gate FET (DGFET)

->Reduce Short Channel Effects (SCEs)
->Reduce Drain-Induced-Barrier-Lowering ->Improve Subthreshold Swing S

Medici-predicted DIBL and subthreshold swing versus effective channel length for DG and bulk-silicon nFETs

Three Types of Double-gate FET

Quasi-CMOS structure Relatively simple FAB

WHAT IS Finfet?

Finfet (Fin shaped FET) is a field effect transistor (FET) device structure

and method for forming FETs for scaled semiconductor devices.

A method and system is disclosed for providing access to the body of a

FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization.

The method facilitates formation of FinFET devices form readily-

available bulk semiconductor substrates with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

A finFET device is fabricated using a conventional MOSFET

technology.The device is fabricated in a silicon layer overlying an insulating layer (SIMOX) with the device extending from insulating layer as a fin.

Double gates are provided over the sides of the channel to provide

enhaced drive current and effectively suppressed short channel effects.A plurality of channels can be provided for increased current capacity.

In one embodiment we can also use two transistors that can be stacked

to a fin to provide cmos process having a shared gate

First FinFET - DELTA (DEpleted Lean-channel TrAnsistor)


THE FIRST fabricated fin field-effect transistor (FinFET)-like silicon- on-insulator (SOI) MOS device dates back to 1989, which is known as the fully depleted lean-channel transistor with a silicon film standing vertically.


With the continuous scaling of MOS devices into the 45-nm technology node, nonplanar double-gate (DG) MOSFETs (such as FinFETs) have become attractive for their good control of shortchanneleffects, ideal subthreshold slope, and high current drive. However, parasitic resistive or capacitive components become comparable in magnitude to, or even much larger than intrinsic ones. Large series resistances, which are induced by the narrowfin nature of nonplanar MOSFETs results in degradation of current drive.


Design - Geometry
Hfin >> Tfin Top gate oxide thickness >> sidewall oxide thickness

Effective channel length Leff = Lgate + 2Lext Effective channel width W = Tfin + 2Hfin

Design - Dependence of Vth and S Swing on Hfin

The saturation of Vth roll-off and S is observed when Hfin is increased from 20 nm to 90 nm The critical Hfin needed for saturation is dependent on Tfin For larger Tfin, the critical Hfin is correspondingly larger

Design - Dependence of Vth and S Swing on Tfin

Vth roll-off and S change more and more rapidly as Tfin changing from 10 nm to 60 nm, and slow down after that. Fin thickness reduce can suppress short channel effects, but the variation will change the performance of the device a lot .

Design - Other Optimization

Nonrectangular Fin
Hydrogen annealing to round off the corners

Source-Drain Fin-Extension Doping

Tradeoff regarding SCEs and S/D series resistance

Dielectric Thickness Scaling Threshold Voltage Control Channel doping with symmetric poly-Si gate
Asymmetric poly-Si gate Metal gate

6.5 nm Si fin by Berkeley Team
---- Smallest in 2002


Si fin

Fabrication - Spacer Lithography

The thickness of spacer at the sidewalls determines the fin thickness

Alternative: Electron Beam Lithography (20nm gate length and 15nm fin thickness was achieved)

Easy in concept----Tough to build

Fabrication - Process Flow

(a) SiN is deposited as a hard mask, SiO2 cap is used to relieve the stress. (b) Si fin is patterned (c) A thin sacrificial SiO2 is grown (d) The sacrificial oxide is stripped completely to remove etch damage (e) Gate oxide is grown (f) Poly-Si gate is formed

10 nm gate length, 12 nm fin width

Performance - IV Characteristics

The drive currents are 446 uA/um for n-FinFET and 356 uA/um for p-FinFET respectively The peak transconductance of the p-FinFET is very high (633uS/um at 105 nm Lg), because the hole mobility in the (110) channel is enhanced

Performance - Speed and Leakage

Gate Delay is 0.34 ps for n-FET and 0.43 ps for p-FET respectively at 10 nm Lg Gate leakage current is comparable to planar FET with the same gate oxide thickness

Layouts of FinFETs patterned with directlithography and spacer

lithography are analysed from a circuit density perspective.

Requirements on the height of the fin to obtain competitive layout density

are derived.
Spacer lithography will be required to obtain the layout density target with

reasonable values of fin height.

FinFET like device architectures are expected to enable CMOS scaling to 45nm. In such devices, the current flows on the vertical walls of the fins and hence the effective device width (WEFF) is different from the layout width. One of the primary requirements for FinFETs to be a technology enabler is that they must have at least the same current drive as the planar technology for identical layout area. We analyze the FinFET layouts for two patterning technologies (i) direct lithography patterning (ii)spacer patterning.

Layouts used for comparison are shown in above fig Mesa isolation is adequate for FinFETs and is assumed in the respective layouts.

W is the width of the activeregion and S its length. L is the gate length

There are two components to the layout area (i) width (ii) the length of the active regions. We analyse these components separately. The result will be combined to derive conditions for competitive layout area density.

Device Width
For FinFETs,the effective device width is given by WEFF = 2n HFIN (1) where, n and HFIN are the number and height of the fins respectively. For direct litho patterning the layout width is given by W = (n-1) PRX + WFINM (2) n = 2,3,4,.

Length Of Active Region

In the calculation of the length of the active

area, the dimensions of the source and drain areas are constrained by the contact design rules, which are assumed to be identical for planar and FinFET process technologies.
For direct lithography patterning

S (FFDL) = S + 2 DPCDL

Double-gate FET can reduce Short ChannelEffects and FinFET is the leading DGFET
Optimization design includes geometry, S-D fin-

extension doping, dielectric thickness scaling, threshold voltage control. Fabrication of FinFET is compatible with CMOS process

10 nm gate length, 12 nm fin width device has been

fabricated and shows good performance