Flip Flop and Register

Sequential Circuits Flip-Flops, Registers, and Counters
KAIST
maeng@kaist.ac.kr
What will we learn?

Logic circuits that can store information Flip-Flops, which store a single bit Registers, which store multiple bits Shift registers Counters Design Examples
2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)
Sequential Circuits
Combinational Circuits
circuits without feedback output = f (current inputs)
Sequential Circuits
circuits with feedback output = f (current inputs, past inputs, past outputs) how can we feed the past inputs and outputs into the circuits? basis for building memory into logic circuits
Circuits with feedback

How to control feedback?
what stops values from cycling around endlessly
x1 x2 x3 . . . Sequential Circuit . . .
y1 y2 y3
xn
ym
Control of an alarm system

Sensor Reset Set Memory element On Off Alarm
the simplest case of a sequential circuit

Alarm is on when the sensor generates the Set signal in response to some undesirable events Once the alarm is on, it can only be turned off manually through a reset button
Memory is needed to remember that the alarm has to be active until the reset signal arrives
A simple memory element

The most rudimentary memory element Two inverters form a static memory cell
Assume A=0 and B=1, then the below circuit will maintain these values indefinitely (as long as it has power applied)
How to get a new value into the memory cell?

selectively break feedback path load new value into cell
A B
A controlled memory element

Load
Data TG1
Output
TG2
A memory element with NOR gates

Construct a memory cell using ordinary logic gates
Two NOR gates are connected in cross-coupled style Basic Latch
Two inputs
Set Reset
Reset Set Q
A basic latch built with NOR gates

R Qa S 0 0 1 1 R 0 1 0 1 Qa Qb 0/1 0 1 0 1/0 (no change) 1 0 0
S (a) Circuit t1 1 R 0 1 S 0 1 t2 t3
Qb
(b) Truth table t4 t5 t6 t7 t8 t9 t 10
Qa
? 0 1 ? 0 Time (c) Timing diagram
Qb
Timing Waveform
R S R Q
Timing Waveform
Reset Hold Set Reset
\Q
Set
100
Race
R S Q \ Q
Forbidden State
Forbidden State
10
State Behavior of R-S Latch

S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable
Truth Table Summary of R-S Latch Behavior
QQ 01 QQ 10
QQ 00
QQ 11
11
Theoretical R-S Latch State Diagram

State Diagram
state: possible values transitions: changes based on inputs
SR = 00, 01 SR = 1 0 QQ 01 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 QQ 00 SR = 0 1 SR = 0 0 SR = 0 0, 11 QQ 11 SR = 1 0 SR = 1 1 QQ 10 SR = 00, 10
12
Observed R-S Latch Behavior

SR = 00, 01 SR = 1 0 QQ 01 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 QQ 00 SR = 0 0 SR = 0 0 SR = 1 1 QQ 10 SR = 00, 10
Very difficult to observe R-S Latch in the 1-1 state Ambiguously returns to state 0-1 or 1-0 A so-called "race condition"
2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr) 13
R-S Latch Analysis

Truth Table: Next State = F(S, R, Current State) R-S Latch Revisited S R Qt Q+
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 x x
Derived K-Map:
SR Q( t ) 0 00 0 1 01 0 0 R 11 X X S 10 1 1
hold 0 1 reset set not allowed
Characteristic Equation: Q+ = S + R Q t
S R Q
R-S Latch
Q+
14
Problems of R-S Latch

value stored
The slightest glitch on R or S could cause change in
Control when R and S inputs have effect on value stored

Enable Signal (or clock signal) R and S inputs are active only when Enable = 1
15
Gated SR latch
Control when R and S inputs matters
the latch can be modified to respond to the input signal S and R only when Enable =1
output is stable output is changing
\S \Q
\R Q \enb
Set
Reset
16
Gated SR Latch
17
Gated SR latch with NAND gates
S Q Clk Q R
18
Problems of the Gated S/R Latches

Race condition
How to eliminate the race condition JK Latch JK Master/Slave F/F, D Master/Slave F/F
When cascading level-sensitive Latches

Master/Slave F/Fs Edge-triggered F/Fs
19
Cascading Latches
R
R S
Q Q
R S
Q Q
S clock
How to stop changes from racing through chain?

need to be able to control flow of data from one latch to the next move one latch per clock period have to worry about logic between latches that is too fast
20
How to eliminate the forbidden state?

Gated D latch
eliminate the troublesome situation where
S=R=1
21
How to eliminate the forbidden state? contd

Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle
J S K R R-S latch Q Q \Q \Q
J-K Latch J(t) K(t) Q(t)

0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Q+
0 1 0 0 1 1 1 0
hold 0 1 reset set toggle
Characteristic Equation: Q+ = Q K + Q J
22
J-K Latch: Race Condition

Set
J K Q \Q
Reset
100
Toggle
Race Condition Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop
23
Master/Slave J-K Flipflop

Master Stage
K R R-S Latch J S Q P S \Q \P
Slave Stage
R R-S Latch Q Q \Q \Q
Clk
Sample inputs while clock high

Set J K Clk P \P Q \Q Reset 1's Catch Toggle 100
Sample inputs while clock low
Uses time to break feedback path from outputs to inputs! Uses time to break feedback path from outputs to inputs!
Master outputs Slave outputs
Correct Toggle Operation
24
Master/Slave D Flip-Flop
Master D Clock D Q Qm Slave D Q Qs Q Q
Clk Q
Clk Q
(a) Circuit
Clock D Qm Q = Qs
(b) Timing diagram
Q Q
(c) Graphical symbol
25
positive-edge-triggered D flip-flop
1 P3
P1 5
Clock P2 6
Clock = 0 Output of gate 2 and 3 are high -> P1,P2 high Output is maintained Clock = 1 P3 and P4 are transmitted through gate 2 and 3 to cause P1 = D and P2 = D. Q This sets Q = D and Q = D P3 and P4 must be stable when the clock goes from 0 to 1. After that, the changes in D have no effect.
Q
P4
Clock
(a) Circuit
(b) Graphical symbol
26
Comparison of level-sensitive and edgetriggered D storage elements

D Clock D Q Clk Q D Q Q D Q Q Q a Q a Q b Q b Q c Q c
(a) Circuit
Clock D Q a Q b Q c 2004Spring CS211 Digital Systems & Lab (b) Timing diagram 2007 (jinsoo@cs.kaist.ac.kr) 27
Master-slave D flip-flop with Clear and Preset

Preset D Clock Q
Clear (a) Circuit Preset D Q Q Clear (b) Graphical symbol 2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)
28
Positive-edge-triggered D flip-flop with Clear and Preset

Preset
Q Preset Clock D Q Clear D Clear Q Q
(b) Graphical symbol
(a) Circuit
Synchronous reset for a D flip-flop
Clear D Clock
Q Q
Q Q
30
T Flip-Flop
T D T Q Q Q Q 0 1 Q(t + 1) Q(t ) Q(t ) Q
(b) Truth table

Clock
(a) Circuit
Clock T Q
(d) Timing diagram 2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr) 31
Realizing JK flip-flop with D flip-flop

J D K Clock Q Q Q Q
(a) Circuit
J K Q ( t + 1) 0 0 1 1 0 1 0 1 Q (t) 0 1 Q (t ) J K Q Q
(b) Truth table


32
Timing Methodologies
Set of rules for interconnecting components and clocks
When followed, guarantee proper operation of system
Approach depends on building blocks used for memory elements

For systems with latches: Narrow Width Clocking Multiphase Clocking (e.g., Two Phase Non-Overlapping) For systems with edge-triggered flip-flops: Single Phase Clocking
Correct Timing:
(1) correct inputs, with respect to time, are provided to the FFs (2) no FF changes more than once per clocking event
Definition of Terms
Clock: Periodic Event, causes state of memory element to change rising edge, falling edge, high level, low level Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable
Tsu Input
Th
Clock
There is a timing There is a timing "window" around the "window" around the clocking event clocking event during which the input during which the input must remain stable must remain stable and unchanged and unchanged in order in order to be recognized to be recognized
34
Setup and Hold times for Latches

t su th Clk D Q
tplh
tphl
35
Comparison of latches and F/F

7474
D Q
Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted Timing Diagram:
D
Clk Positive edge-triggered flip-flop
7476
D C Clk Level-sensitive latch Q
Clk Q Q 7474 7476
Bubble here for negative edge triggered device
Behavior the same unless input changes while the clock is high
36
Comparison of latches and F/F

Input/Output Behavior of Latches and Flipflops Type unclocked latch level sensitive latch positive edge flipflop negative edge flipflop master/slave flipflop When Inputs are Sampled always clock high (Tsu, Th around falling clock edge) clock lo-to-hi transition (Tsu, Th around rising clock edge) clock hi-to-lo transition (Tsu, Th around falling clock edge) clock hi-to-lo transition (Tsu, Th around falling clock edge) When Outputs are Valid propagation delay from input change propagation delay from input change propagation delay from rising edge of clock propagation delay from falling edge of clock propagation delay from falling edge of clock
37
Typical Timing Specifications: Flipflops vs. Latches

74LS74 Positive Edge Triggered D Flipflop
D Tsu 20 ns Th 5 ns Tw 25 ns Tplh 25 ns 13 ns T su 20 ns Th 5 ns
Setup time Hold time Clk Minimum clock width Propagation delays (low to high, high to low, max and typical) Q
T phl 40 ns 25 ns
All measurements are made from the clocking event that is, the rising edge of the clock
38
Typical Timing Specifications: Flipflops vs. Latches

74LS76 Transparent Latch
D T su Th 20 5 ns ns Tw 20 ns Tplh C Q 27 ns 15 ns T plh D Q 27 ns 15 ns Tsu 20 ns Th 5 ns
Setup time Hold time Minimum Clock Width Propagation Delays: high to low, low to high, maximum, typical data to output clock to output
Clk
T phl C Q 25 ns 14 ns T phl D Q 16 ns 7 ns
Measurements from falling clock edge or rising or falling data edge

Timing Methodologies
Shift Register S,R are preset, preclear New value to first stage while second stage obtains current value of first stage
IN D Q Q0 D Q Q1
C Q CLK
C Q
Cascaded Flipflops and Setup/Hold/Propagation Delays

100 In
Correct Operation, assuming positive edge triggered FF
Q0 Q1 Clk
40
Cascaded Flipflops and Setup/Hold/Propagation Delays

Why this works: Propagation delays far exceed hold times; Clock width constraint exceeds setup time This guarantees following stage will latch current value before it is replaced by new value Assumes infinitely fast distribution of the clock
In Tsu 20 ns Q0 T plh 13 ns T plh 13 ns Tsu 20 ns
Timing constraints Timing constraints guarantee proper guarantee proper operation of operation of cascaded components cascaded components
Q1 Clk
Th 5 ns
Th 5 ns
41
The Problem of Clock Skew

Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Not possible in real systems! logical clock driven from more than one physical circuit with timing behavior different wire delay to different points in the circuit Effect of Skew on Cascaded Flipflops:
FF0 samples IN FF1 samples Q 0 100
In Q0 Q1 Clk1 Clk2
CLK2 is a delayed version of CLK1
Original State: Q0 = 1, Q1 = 1, In = 0 Because of skew, next state becomes: Q0 = 0, Q1 = 0, not Q0 = 0, Q1 = 1

Design Strategies for Minimizing Clock Skew

Typical propagation delays for LS FFs: 13 ns Need substantial clock delay (on the order of 13 ns) for skew to be a problem in this relatively slow technology Nevertheless, the following are good design practices: distribute clock signals in general direction of data flows wire carrying the clock between two communicating components should be as short as possible for multiphase clocked systems, distribute all clocks in similar wire paths; this minimizes the possibility of overlap for the non-overlap clock generate, use the phase feedback signals from the furthest point in the circuit to which the clock is distributed; this guarantees that the phase is seen as low everywhere before it allows the next phase to go high
43
Choosing a Flipflop
R-S Clocked Latch:
used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types
J-K Flipflop: (historically popular, but now not used)

versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist
D Flipflop:
minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers
T Flipflops:
don't really exist, constructed from J-K FFs usually best choice for implementing counters
Preset and Clear inputs highly desirable!!

Registers
Collection of Flip-Flops with similar controls and logic
stored values somehow related share clocks, reset, and set lines similar logic at each stage
Examples
storage registers shift registers counters
45
Storage Register
+ \clr
Q3
DS
Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines Schematic Shape
D3
Q2
DS
171
12 CLK 13 CLR Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 9 10 7 6 2 3 1 15
D2
S R
Q1
D1 D0
D
11 5 4 14
D3 D2 D1 D0
S R
Q0
TTL 74171 Quad D-type FF with Clear (Small numbers represent pin #s on package)
clk
Kinds of Registers
Input/Output Variations Selective Load Capability Tri-state or Open Collector Outputs True and Complementary Outputs
377
11 1 18 17 14 13 8 7 4 3 CLK EN D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 19 16 15 12 9 6 5 2
374
11 18 17 14 13 8 7 4 3 CLK H QH G QG F QF E QE D QD C QC B QB A QA OE 1 19 16 15 12 9 6 5 2
74377 Octal D-type FFs with input enable
74374 Octal D-type FFs with output enable
EN enabled low and lo-to-hi clock transition to load new data into register
OE asserted low presents FF state to output pins; otherwise high impedence

47
A simple shift register
In In Clock D Q Q Q1 D Q Q Q2 D Q Q Q3 D Q Q Q4 t0 Out t1 t2 t3 t4 1 0 1 1 1 0 0 0
Q1 0 1 0 1 1 1 0 0
Q2 0 0 1 0 1 1 1 0
Q3 0 0 0 1 0 1 1 1
Q4 = Out 0 0 0 0 1 0 1 1
(a) Circuit
t5 t6 t7
(b) A sample sequence
48
Parallel-access shift register

Parallel output Q3 Q2 Q1 Q0
Q Q
Q Q
Q Q
Q Q
Serial input Shift/Load 2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)
Parallel input
Clock 49
Shift Register I/O

Serial vs. Parallel Inputs Serial Inputs: LSI, RSI Serial vs. Parallel Outputs Parallel Inputs: D, C, B, A Shift Direction: Left vs. Right Parallel Outputs: QD, QC, QB, QA Clear Signal 10 S1 Positive Edge Triggered Devices
9 S0 7 LSI 6 D 5 C 194 4 B 3 A 2 RSI 12 13 14 15
11 CLK 1 CLR 74194 4-bit Universal Shift Register
S1,S0 determine the shift function S1 = 1, S0 = 1: Load on rising clk edge synchronous load S1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0, S0 = 0: hold state Multiplexing logic on input to each FF!
Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications
Shift Register Application: Parallel to Serial Conversion

Sender Receiver
Parallel Inputs
10 S1 9 S0 7 LSI 6 D D7 5 C 194 D6 4 D5 D4 3B A 2 RSI Clock 11 CLK 1 CLR 10 S1 9 S0 7 LSI 6 D 5 C 194 4 3B A 2 RSI 11 CLK 1 CLR
12 13 14 15
10 S1 9 S0 7 LSI 6 D 5 C 194 4 3B A 2 RSI 11 CLK 1 CLR 10 S1 9 S0 7 LSI 6 D 5 C 194 4 3B A 2 RSI 11 CLK 1 CLR
12 D7 13 D6 14 D5 15 D4
Parallel Outputs
12D3 13D2 14D1 15D0
D3 D2 D1 D0
12 13 14 15
Serial transmission
Counters
Counters
Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... Binary vs. BCD vs. Gray Code Counters A counter is a "degenerate" finite state machine/sequential circuit A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output where the state is the only output
Types of counters Asynchronous vs. Synchronous Counters
52
Asynchronous counters
Ripple counter
1 Clock
State transitions are not sharp! Can lead to "spiked outputs" from combinational logic decoding the counter's state
Q Q
Q Q
Q Q
Q0
Q1
Q2
(a) Circuit
Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 6 7 0
A three-bit up-counter
(b) Timing diagram

53
Asynchronous counters, contd

1 Clock T Q Q T Q Q T Q Q
Q0
Q1
Q2
(a) Circuit
Clock Q0 Q1 Q2 Count 0 7 6 5 4 3 2 1 0
A three-bit down-counter (b) Timing diagram

Synchronous counter
Asynchronous counters
simple, but not very fast can build faster counters by clocking all FFs at the same time synchronous counter
Clock cycle Synchronous counters with T F/F 0 1 2 3 4 5 6 7 8 Q2 Q1 Q0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Q1 changes Q2 changes
T0=1 T1=Q0 T2=Q0Q1
55
A four-bit synchronous up-counter

1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2 T Q Q Q3
(a) Circuit
Clock Q0 Q1 Q2 Q3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
(b) Timing diagram

Enable and Clear capability
Enable Clock
Q Q
Q Q
Q Q
Q Q
Clear
57
A four-bit counter with D FFs

Enable D Q Q Q0
D Q Q
Q1
D Q Q
Q2
D Q Q Clock
Q3
Output carry
58
A counter with parallel-load capability

Enable D0 0 1 D Q Q Q0
D1
0 1
Q Q
Q1
D2
0 1
Q Q
Q2
D3
0 1
Q Q
Q3
Load Clock
Output carry
59
Catalog Counter
7 P 10 T 163 15 2 CLK RCO 6 5 4 3 9 1 D C B A LOAD CLR QD QC QB QA 11 12 13 14
Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D, C, B, A P, T Enable Inputs: both must be asserted to enable counting RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"
74163 Synchronous 4-Bit Upcounter 74161: similar in function, asynchronous load and reset
60
74163 Detailed Timing Diagram

CLR LOAD A B C D CLK P T QA QB QC QD RCO Clear 12 Load 13 14 15 Count 0 1 2 Inhibit
61
A modulo-6 counter with synchronous reset

1 0 0 0 Enable D0 D1 D2 Load Clock Clock Q0 Q1 Q2
(a) Circuit
Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1
(b) Timing diagram
62
A modulo-6 counter with asynchronous reset

1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2
(a) Circuit
Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1 2
(b) Timing diagram

Other types of counters

Two-digit BCD counters
Two modulo-10 counters, one for each digit Reset when the counter reaches 9
Ring counters
One bit is one while other bits are 0 one hot encoding
Johnson counter
1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000,
64
A two-digit BCD counter

1 0 0 0 0 Enable D0 D1 D2 D3 Load Clock Clock Clear 0 0 0 0 Enable D0 D1 D2 D3 Load Clock Q0 Q1 Q2 Q3
BCD 0
Q0 Q1 Q2 Q3
BCD 1
65
Ring Counter
Q0 Start Q1 Qn ? 1
Q Q
Q Q
Q Q
Clock
(a) An n -bit ring counter
Q0 Q1 Q2 Q3 y0 w1 y1 y2 y3 w0
2-to-4 decoder En
1 Q1 Q0
Clock
Clock
Two-bit up-counter Start Clear
(b) A four-bit ring counter
66
Johnson counter
Q0 Q1 Qn 1
Q Q
Q Q
Q Q
Reset Clock
67

Flip Flop and Register

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Flip Flop and Register

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Sequential Circuits Flip-Flops, Registers, and Counters

What will we learn?

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Circuits with feedback

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Control of an alarm system

the simplest case of a sequential circuit

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

A simple memory element

How to get a new value into the memory cell?

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

A controlled memory element

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

A memory element with NOR gates

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

A basic latch built with NOR gates

(b) Truth table t4 t5 t6 t7 t8 t9 t 10

? 0 1 ? 0 Time (c) Timing diagram

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

State Behavior of R-S Latch

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Theoretical R-S Latch State Diagram

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Observed R-S Latch Behavior

R-S Latch Analysis

hold 0 1 reset set not allowed

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Problems of R-S Latch

The slightest glitch on R or S could cause change in

Control when R and S inputs have effect on value stored

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Gated SR latch with NAND gates

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Problems of the Gated S/R Latches

When cascading level-sensitive Latches

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

How to stop changes from racing through chain?

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

How to eliminate the forbidden state?

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

How to eliminate the forbidden state? contd

J-K Latch J(t) K(t) Q(t)

hold 0 1 reset set toggle

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

J-K Latch: Race Condition

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Master/Slave J-K Flipflop

Sample inputs while clock high

Sample inputs while clock low

Master outputs Slave outputs

Correct Toggle Operation

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

(b) Timing diagram

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

(c) Graphical symbol

(b) Graphical symbol

2004Spring CS211 Digital Systems & Lab 2007 (jinsoo@cs.kaist.ac.kr)

Comparison of level-sensitive and edgetriggered D storage elements

Master-slave D flip-flop with Clear and Preset

Positive-edge-triggered D flip-flop with Clear and Preset

Q Preset Clock D Q Clear D Clear Q Q