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  • Generic Implementations of Elliptic Curve Cryptography Using Partial Reduction

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    Sanjiv Kumar Deepesh Mishra
    11 просмотров15 страниц
    This document describes the architecture of a processor that contains registers, a system bus (SBUS), data memory (DMEM), and arithmetic logic units such as a divider (DIV) and multiplier (MUL). It communicates with external memory over a data bus (DBUS) and contains control logic to perform arithmetic operations like addition and comparison on data from the SBUS and DMEM.

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    This document describes the architecture of a processor that contains registers, a system bus (SBUS), data memory (DMEM), and arithmetic logic units such as a divider (DIV) and multiplier (MUL). It communicates with external memory over a data bus (DBUS) and contains control logic to perform arithmetic operations like addition and comparison on data from the SBUS and DMEM.

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    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    11 просмотров15 страниц

    Generic Implementations of Elliptic Curve Cryptography Using Partial Reduction

    Загружено:

    Sanjiv Kumar Deepesh Mishra
    This document describes the architecture of a processor that contains registers, a system bus (SBUS), data memory (DMEM), and arithmetic logic units such as a divider (DIV) and multiplier (MUL). It communicates with external memory over a data bus (DBUS) and contains control logic to perform arithmetic operations like addition and comparison on data from the SBUS and DMEM.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 15

    SBUS

    Reg.file (R0..R7, RM,RC)

    256

    PCI

    DMEM

    DIV

    MUL

    ALU

    DBUS

    256

    SBUS n

    SBUS n

    d d

    n+d

    +
    n+d

    Z
    2n

    d [2n-1..d] 2n-d

    [2n-1..0] 2n

    en

    red163 red193 red233

    m (reduced) 2n (non-reduced)

    Z
    n DBUS

    SBUS +
    n n

    +
    n

    M 0 n 0

    /t B

    + /t V

    A
    m-1

    U
    m

    -1
    log2n

    -1
    log2n

    DBUS

    CA

    CB >

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