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ACTIVE-HDL


: ., . . ..



220201 .
ACTIVE-HDL VHDL.

, 2009

2009


...................................................................................................... 2
1.

Active-HDL ............................................................... 2

1.1.

............................................................................................. 2

1.2.

VHDL- .................................................................. 5

1.3.

............................................................................. 9

1.4.

..................................................... 12

1.5.

.......................................................... 15

2.

...................................... 20

2.1.

...................................................................................... 21

2.2.

.............................................................. 23

2.3.

ACTIVE-VHDL ......................... 25

3.

ACTIVE-HDL ........................................... 28

3.1.

........................................... 28

3.2.

............................................ 30

................................................................. 33


. VHDL.
,
VHDL.
VHDL- Active HDL Aldec. , , , .
www.aldec.com,
www.aldec.com.ua.
Active HDL VHDL, .
.
,
. . ().
Active HDL,
VHDL
.

1. ACTIVE-HDL
1.1.
Active-HDL
Windows. Getting Started ( ), . 1. , .
2

Create new workspace.


OK.
- More, Workspase/Design Explorer.

. ,
.

. 1. Getting Started

New Workspace (. 2),



(, F:\opitVHDL), opit1.

, -


. as bs, ps0,
ss ps1.
Active-HDL New Design Wizard,
. Create an ampty design,
3

, .
. Add files
, New Workspace (
F:\opit_hdl\opit1).
Syntesis tool Implementetion tool
none .

. 2. New Workspace

Active-HDL New Design Wizard,


.
Create an empty design,
, .
. Add files
, New Workspace (
F:\opit_hdl\opit1).
Synthesis tool Implementation tool none .
New Design Wizard .
. 4

New Design
Wizard. . Aktive-HDL
, . 3. . VHDL
Verilog (HDE), (FSM) (BDE).
HDE. ,
. 4. VHDL

. 3. design flow

. 4

1.2. VHDL-

, -

.
, (. 5).
. summf.
5

. 5 New Source File Wizard Name

(. 6).

. 6. New Source File Wizard Ports

New, (in
, out , inout buffer -

). . New .., .

.
. (as, bs, ps0)
(ss, ps1). ().
Array Index , 0 3 . , x[0], x[1], x[2], x[3].
. summf.vhd.

Design Browser, .
, ( ).
.
-- Title

: summf

-- File

: summf.vhd Generated : Sun Jan 6 12:33:05 2008

--{{
-- summf
summf
--

{entity {summf} architecture {summf}}


library IEEE;

--

use IEEE.STD_LOGIC_1164.all; -- ,
-- VHDL
entity summf is

-- summf

-- ( ),
--

(. 6)
7

port( as : in STD_LOGIC;
bs : in STD_LOGIC;
ps0 : in STD_LOGIC;
ss : out STD_LOGIC;
ps1 : out STD_LOGIC );
end summf;
-- }}
architecture summf of summf is -- summf summf
begin
--

end summf;
.
as bs, ps0. ss, ps1.
ss = as bs ps0 + as b ps0 + as bs ps0 + as bs ps0 =
= (as bs + as bs) ps0 + (as bs + as bs) ps0,
ps1 = as bs ps0 + as bs ps0 + as bs ps0 + as bs ps0 = (as bs + as bs) ps0 + as bs.

z = as bs + as bs .
ss = z ps0 + z ps0,

ps1 = z ps0 + as bs.

. ( ) .
. <=.
---------------------------------------------------------------------------------------------------- Title

: summf -- Design

--

: summ File

: summf.vhd

{entity {summf} architecture {summf}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity summf is

--
8

port( as, bs, ps0 : in STD_LOGIC; --


ss, ps1 : out STD_LOGIC);
end summf;
architecture summf of summf is
signal z: STD_LOGIC;

--
--

begin
z<=((not as ) and bs ) or ( as and (not bs));
ss<=(z and (not ps0)) or (not z and ps0); --
ps1<=(z and ps0) or (as and bs);
end summf;
. Compile

. -

VHDL- ,
Compile All

1.3.
.
( ) Waveform

. -


. Design Browser
Structure ( Design Browser). . 7

Name Waveform , ( ). . 8 . (as, bs, ps0) (ss, ps1) .

.
Stimulators,

. -

. 9.

. 8. Waveform


Waveform ( . 8 as). . 7. Design Browser

Signals Stimulators.

Type.
Formula.
, . ps0 ( Stimulators) 0 t=0 , 1 t=20 ,
=40 , .. 40
( 40 ).
: bs 80 , as 20 .

10

. 9 ()
Stimulators

Enter formula. : , , .
.
.
, 100
Run Until

. 10. . , . Value 54,8 , . .


. .

11

Clock ( )
. 50 .

. 10 (Clock B0), 20

(Clock B1) .. 1280 (Clock B7).

. () -

. Hotkey, 0, 1.
, 10 ,

. 10.

1.4.

Ative-HDL, . xor2, 2 and2 2 or2. 12

File New/Design.

Design Flow Manager

(),

summsh

.
. .

, . (),
. . 11 xor2.
.

(Wire) , (Bus).


.
1. ,

. 11. -

2. , .
3. , .
, .
4. , ( ).
,
( ).

13

General , View texts


. Properties . .
.
. 12 , summsh.bde.

. 12.

( ) HDL-.

. summsh.vhd .

---------------------------------------------------------------------------------------------------- File

: F:\opitVHDL\AllSum\summ\summ\compile\summsh.vhd

-- From

: F:\opitVHDL\AllSum\summ\summ\src\summsh.bde

--------------------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;

--

entity summsh is

-- summsh

port( as : in STD_LOGIC; -- ,
bs : in STD_LOGIC;
ps0 : in STD_LOGIC;
ps1 : out STD_LOGIC;
ss : out STD_LOGIC);
end summsh;
14

architecture summsh of summsh is

--

signal a_and_b, z, z_and_ps0 : STD_LOGIC;


begin

--

--

z <= bs xor as;


ss <= ps0 xor z;
a_and_b <= as and bs;
z_and_ps0 <= ps0 and z;
ps1 <= a_and_b or z_and_ps0;
end summsh;
.
summf (. 10).

1.5.
: summf.vhd
summsh.vhd. .
(0), (1) bb(0), bb(1),
p0, ss(0),
ss(1) p1.
aa(1:0),
. 13.

bb(1:0), ss(1:0). ACTIVE-VHDL


. 13.

. Design Browser

( File -

New/Design). (. 14).
Name summ2 ( ),
Block Diagram (-)
.
15

. 14.

(
).

. , aa, bb ss , .. .
. 15,
. . , )

( )
. 15. :
;

,
. . 15,
.
,
.

. -

( summ) summf.
16

. 16 .
.

, . 17

. 16.

. 17.

, .

summsh. . , : aa(0), aa(1),


bb(0), bb(1), ss(0), ss(1). . 18

.18.

VHDL-
,
.
17

VHDL- .
-- File

: f:\opitVHDL\AllSum\summ\summ\compile\summ2.vhd

library IEEE;

-- Active-HDL

use IEEE.std_logic_1164.all;
entity summ2 is
port(

--
--

p0 : in STD_LOGIC;
aa : in STD_LOGIC_VECTOR(1 downto 0);
bb : in STD_LOGIC_VECTOR(1 downto 0);
p1 : out STD_LOGIC;
ss : out STD_LOGIC_VECTOR(1 downto 0));
end summ2;
architecture summ2 of summ2 is -- summ2
--
component summf
port (

-- summf

as ,bs, ps0 : in STD_LOGIC;

ps1, ss : out STD_LOGIC);


end component;
signal ps1 : STD_LOGIC; --
--

ps1

begin
--
U1 : summf --
port map(
as => aa(0), bs => bb(0), ps0 => p0,
ps1 => ps1, ss => ss(0) );
U2 : summf --
port map(
as => aa(1), bs => bb(1), ps0 => ps1,
ps1 => p1,

ss => ss(1) );

end summ2;
18

Waveform,

aa, bb p0. Hotkey ( ).
aa bb - 00, 01, 10, 11, p0 0, 1. Signals
, Hotkeys
(. 19).

. 19.

. 20.

( 0,1,2,3). .
. ss.
.

. 20. summ2

19

2.
,
(11). . 21. ( s1, s2 s3)
(v1, v2, v3 v4).
. 1 - .
:
D

WD = 1

D;

CT = D

, -

CTD;

= 1 ,
1;
= 0

= 0000, 0.
1

.
.

s1

WD
WD

s1

WD CT0

s1

s3

CTM1

WD

s2

WD

s1

CT0

s3
s1

CTM1
-

WD CT0

s2
s3

. .
CTD
s2

CT0

. 21.

20

D- :

z1 = WD Q1 Q2 ,
d1 = WD PUSK CT 0 Q2 + CT 0 Q1 .

z 2 = WD PUSK CT 0 Q2 + CT 0 Q1,
d 2 = WD Q1,

d1 d2 , z1 z2 .

2.1.
VHDL.
--{entity {fgpi} architecture {fgpi}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fgpi is

--

fgpi

port( wd, pusk, ct0, q1, q2 : in STD_LOGIC;

--

d1, d2, z1, z2 : out STD_LOGIC);

--

end fgpi;
architecture fgpi of fgpi is
begin

--

--

z1<=wd and (not q1) and (not q2);


z2<=((not wd) and pusk and(not ct0) and (not q2)) or ((not ct0) and q1);
d1<=((not wd) and pusk and (not ct0) and (not q2))or ((not ct0) and q1);
d2<=wd and (not q1);
end fgpi;
8 D
r
(. 22). VHDL.
-- File

: TM8.vhd

--{entity {TM8} architecture {TM8}}


library IEEE;
21

4
5
12
13
9
1

d1
d2
d3
d4
c
r

q1
q2
q3
q4

2
3
7
6
10
11
15
14

. 22. TM8

use IEEE.STD_LOGIC_1164.all;
--

entity TM8 is
port( d1, d2, d3, d4, c, r : in STD_LOGIC;
q1, nq1, q2, nq2, q3, nq3, q4, nq4 : out STD_LOGIC);
end TM8;
--

( 8)

architecture TM8 of TM8 is


begin
process (d1, d2, d3, d4, c, r) --
-- ,
begin
-- r=1 (RESET)
if (r = '1') then q1<='0'; nq1<='1'; q2<='0'; nq2<='1';
q3<='0'; nq3<='1'; q4<='0'; nq4<='1';
elsif (c'event and c='1' and r='0')

-- -

--
then q1<=d1; nq1<= not d1; q2<=d2; nq2<= not d2;
q3<=d3; nq3<= not d3; q4<=d4; nq4<= not d4;
end if;
end process;
end TM8;
,
ACTIVE-HDL . 23. .

22

. 23.

VHDL-.

VHDL (Compile
(Waveform

) -

).

. 24. .
.

. 24.

2.2.
, . 7,
. 25. VHDL .
23

-- File

: ie7.vhd

--{entity {ie7} architecture {ie7}}


--
library IEEE;

15
1
10
9

-- 11
5
use IEEE.STD_LOGIC_1164.all;
4
14
--
use IEEE.STD_LOGIC_ARITH.all;

D CT16 Q
1
1
2
2
3
3
4
4
dw
ucu
wpu
ucd
wpd
urs

3
2
6
7
12
13

. 25. 7

use IEEE.STD_LOGIC_UNSIGNED.all;
-- (-)
entity ie7 is
port(
d1, d2, d3, d4, dw, ucu, ucd,urs: in STD_LOGIC;
q1, q2, q3, q4, wpu, wpd : out STD_LOGIC);
end ie7;
--
architecture ie7 of ie7 is
signal z : STD_LOGIC_VECTOR(0 to 3); --
begin
N: process (d1, d2, d3, d4, dw, ucu, ucd,urs)
begin
-- urs=1
if (urs='1') then z<=(others=>'0') ; wpu<='0'; wpd<='0';
-- D
elsif (urs='0' and dw='0') then z(0)<=d1; z(1)<=d2; z(2)<=d3; z(3)<=d4;
--
elsif (urs='0' and dw='1' and ucd='1' and ucu'event and ucu='1')
then if(z(0)='1' and z(1)='1' and z(2)='1' and z(3)='1') then wpu<='1'; end if;
z <= z + 1 ;
--
24

elsif (urs='0' and dw='1' and ucu='1' and ucd'event and ucd='1')
then if(z(0)='0' and z(1)='0' and z(2)='0' and z(3)='0') then wpd<='1'; end if;
z <= z - 1 ;
end if;
end process N;
q1<=z(0); q2<=z(1); q3<=z(2); q4<=z(3);
end ie7;
7 . 26.

. 26. 7

2.3. ACTIVE-VHDL
.
,
.
, , ,
.
,
. , .
25

,
.
:
(=D) (=-1). .
155- , ,
1557.
. 4-
( 1).

=0
4-.

( 1,
).
Active-VHDL
. 27. . W , (1), (0). 0 ,
4-. 3-.
(1),
0.
0000, .
, , imp.

26

. 27.

VHDL-
. . 28.
, (0101),
(0001), (1111) (0000). . . , .

5 ,
d1,d2,d3,d4 = 0101

1 .
0001

15
1111

. 28.

27

3. ACTIVE-HDL
(), , VHDL .
.

3.1.
-- File

: uagpi_mili.vhd -- Generated

library IEEE;

--

use IEEE.STD_LOGIC_1164.all;
-- ,
-- (
rs)
entity uagpi_mili is
port(
wd, pusk, ct0, c, rs : in STD_LOGIC;
dst, ctm1 : out STD_LOGIC);
end uagpi_mili;
--
architecture uagpi_mili of uagpi_mili is
type T_st is (s1,s2,s3); -- T_st,
--
signal st, next_st :T_st; -- T_st
-- st -
-- next_st -
begin
NS: process (st,wd, pusk, ct0, c, rs)
begin
28

if (rs='1') then -- :
-- 0, s1
dst<='0'; ctm1<='0'; st<=s1; next_st<=s1;
--
elsif ( c'event and c='1') then
case st is

-- VHDL

--

when s1=> -- s1
-- ,
--
if (wd='1') then next_st<=s2; dst<='1'; ctm1<='0';
elsif (wd='0' and pusk='0')
then next_st<=s1; dst<='0'; ctm1<='0';
elsif (wd='0' and pusk='1' and ct0='1')
then next_st<=s1; dst<='0'; ctm1<='0';
elsif (wd='0' and pusk='1' and ct0='0')
then next_st<=s3; dst<='0'; ctm1<='1';
end if;
-- s2

when s2=>
if (wd='1')

then next_st<=s2; dst<='0'; ctm1<='0';


elsif (wd='0')
then next_st<=s1; dst<='0'; ctm1<='0';
end if;
when s3=>

-- s3

if (ct0='0')
then next_st<=s3; dst<='0'; ctm1<='1';
elsif (ct0='1')
then next_st<=s1; dst<='0'; ctm1<='0';
29

end if;
end case;
st<=next_st;
end if;
end process NS;
end uagpi_mili;
. 29 , VHDL. . 24,
.

. 29.

3.2.
-- Title

: gpimr File

: gpimr.vhd

--{entity {gpimr} architecture {gpimr}}


library IEEE;

--

use IEEE.STD_LOGIC_1164.all;
entity uagpi_mura is

--

port( wd, pusk, ct0, c, rs : in STD_LOGIC;


dst, ctm1 : out STD_LOGIC);

--
--

end uagpi_mura;
architecture uagpi_mura of uagpi_mura is --
30

type T_st is (v1,v2,v3,v4);

-- ,
--

signal st, next_st :T_st;

-- st -

-- next_st ,
begin

-- -

NS: process (st,wd, pusk, ct0, c, rs)


begin

--

case st is

--
when v1=>

-- v1

if (wd='1') then next_st<=v2; --


v1
elsif (wd='0' and pusk='0')

then next_st<=v1;

elsif (wd='0' and pusk='1' and ct0='1') then next_st<=v1;


elsif (wd='0' and pusk='1' and ct0='0') then next_st<=v4;
end if;
when v2=>

-- v2

if (wd='1') then next_st<=v3;--


v2
elsif (wd='0') then next_st<=v1;
end if;
when v3=>

-- v3

if (wd='1')then next_st<=v3; --
v3
elsif (wd='0') then next_st<=v1;
end if;
when v4=>

-- v4

if (ct0='0') then next_st<=v4; --


v4
elsif (ct0='1') then next_st<=v1;
31

end if;
end case;
end process NS;

--

st<=v1 when rs='1' else -- v1 rs


-- rs -
next_st when c'event and c='1' else st; --
dst<='0' when st=v1 else

-- dst

'1' when st=v2 else


'0' when st=v3 else
'0' when st=v4;
ctm1<='0' when st=v1 else

-- ctm1

'0' when st=v2 else


'0' when st=v3 else
'1' when st=v4;
end uagpi_mura;
. 30 , VHDL. . 24,
.

. 30.

32


1.

. Altera HDL. . 2002. ISBN 5-93037-052-4 221 .

2.

. . VHDL:
. .: , 1992. 175 .

3.

.. ,
FPGA, 1
. 2004. N21. . 717.

4.

.. VHDL. . .: -, 2002. 224 .

5.

..
VHDL. StateCAD, ModelSim, LeonardoSpectrum. . : -, 2005.
384 .

6.

. WebPACK ISE Xilinx //


. 2001. N 6.

7.

. WebPACK ISE:
Xilinx. //
. 2001. N 7.

8.

. . // : XXI, 2007 . 410 .

9.

.., ... : . : , 2007 . 250 .

10. . ALTERA: , . . 2002. ISBN 5-94020-0331 576 .


11. :

. / .. . : - , 2002. 43.
33

ACTIVE-HDL

..
. .

-
29.08.2009 .
pdf
6090 1/8 1,46 .-. .
-
620002, , . , 19

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http://www.ustu.ru