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A B C D E 1 1 2 2 LA-1641 REV0.2 Schematic Document Intel Mobile
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B
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LA-1641 REV0.2 Schematic
Document
Intel Mobile P4 uFCBGA/uFCPGA Northwood Celeron
with Montara GML / ICH4-M / Integrated VGA
2002-11-20
3
3
4
4
Compal Electronics, Ltd.
Title
Cover P age
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Monday, November 25, 2002
Sheet
1
of
46
A
B
C
D
E

A

1

2

COMPAL CONFIDENTIAL

REV:0.3

CPU CLOCK Thermal Mobile P4 ICS950810 sensor Northwood Celeron PAGE 15 478 uFCPGA PAGE 4
CPU
CLOCK
Thermal
Mobile P4
ICS950810
sensor
Northwood Celeron
PAGE 15
478 uFCPGA
PAGE 4
PAGE 4, 5, 6
CHRONTEL 7011
DVO#C
TV-OUT Controller
DVO BUS
Montara GML
PAGE 14
LVDS&DAC Interface
DC/DC Interface
VGA 732 uFCBGA Embeded
MEMORY BUS
DDR DIMM X 2
CRT & LVDS
Connector
PAGE 38
PAGE 11
PAGE 13
PAGE 7,8,9,10
PSB
HUB Li nk
INTERNALIDE
PCI BUS
OZ-168
IDSEL: AD18
IDSEL: AD20
IDSEL: AD17
IDSEL: AD16
PAGE 25
MASTER 1
MASTER 2
MASTER 3
MASTER 3
PIRQC#, PIRQD#
SIRQ,(PIRQE#, PIRQF#)
PIRQB#
PIRQA#
(PIRQG#, PIRQH#)
PIRQA#, PIRQB#
(PIRQD)
INTERNALIDE
Secondary IDE
HDD/
Mini PCI
CD-ROM
Primary IDE
CARDBUS
LAN Controller
1394 Controller
Connect or
PAGE 26
ICH4-M
OZ6933
RTL8100BL
VIA 6307S
LPC
PAGE 24
PAGE 20
PAGE 22
PAGE 19
421 BGA
AC LINK
USB 2.0 Port X 4/
BlueTooth connector
PAGE 16,17,18
PAGE 29
MDC
PCMCIA
RJ45/RJ11
Connector
SOCKET
Connector
LPC
LPC
PAGE 27
PAGE 21
PAGE 23
POWER INTERFACE
B+
SD Reader
AUDIO
Audio AMP
Super I/O
EC/KBC
AC97 Codec
+CPU_CORE
Winbond
HARDWARE
W83L518D
LPC-47N227
PC87591
ALC202
TPA0232
+2.5VP
EQ
PAGE 33
PAGE 28
PAGE 34
PAGE 30
PAGE 31
PAGE 32
+1.5VALWP
+12VALWP
+5VALWP
+3VALWP
PowerGood Interface/
+1.25VSP
System Connector
+1.2VPP
+1.2VSP
BIOS/
PAGE 36, 37
PAGE 39, 40, 41, 42, 43, 44
Parallel PORT
Ext. I/O
PAGE 27
PAGE 35

4

41, 42, 43, 44 Parallel PORT Ext. I/O PAGE 27 PAGE 35 4 3 4 B

3

4

B

C

D

E

1

2

Parallel PORT Ext. I/O PAGE 27 PAGE 35 4 3 4 B C D E 1

3

Compal Electronics, Ltd.

Title

Cover P age

Size

Custom

Document Number

LA-1641

Rev

0.3

Date:

Monday, November 25, 2002

Sheet

2

of

46

A

B

C

D

E

A B C D E Voltage Rails SIGNAL STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V
A
B
C
D
E
Voltage Rails
SIGNAL
STATE
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
+VALW
+V
+VS
Clock
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
Power Plane
Description
S1
S3
S5
S1(Po wer On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
1 VIN
Adapter power supply (19V)
N/A
N/A
N/A
1
S3 (S uspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_VCC
Core voltage forCPU
ON
OFF
OFF
S4 (S uspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+1.2VP
1.2V switched power rail for CPU AGTLBus
ON
OFF
OFF
S 5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.2VS
1.2V switched power rail for Montara core
ON
OFF
OFF
+1.25VS
1.25V switched power ra il
ON
OFF
OFF
+1.5VS
AGP 4X
ON
OFF
OFF
+2.5V
2.5V power ra il
ON
ON
OFF
Board ID Table for AD channel
+2.5VS
2.5V switched power ra il
ON
OFF
OFF
+3VALW
3.3V always on power ra il
ON
ON
ON*
+3V
3.3V power ra il
ON
ON
OFF
Vcc
3.3V +/ - 5%
+3VS
3.3V switched power ra il
ON
OFF
OFF
Ra
100K +/ - 5%
+5VALW
5V always on power ra il
ON
ON
ON*
Board ID
Rb
V
AD_BID
min
V
AD_BID
typ
V AD_BID max
+5V
5V power rail
ON
ON
OFF
0
0
0 V
0 V
0 V
+5VS
5V switched power ra il
ON
OFF
OFF
1
8.2K +/ - 5%
0.216
V
0.250
V
0.289
V
+12VALW
12V always on power rail
ON
ON
ON*
2
18K +/- 5%
0.436
V
0.503
V
0.538
V
2 RTCVCC
RTC power
ON
ON
ON
3
33K +/- 5%
0.712
V
0.819
V
0.875
V
2
4
56K +/- 5%
1.036
V
1.185
V
1.264
V
5
100K +/ - 5%
1.453
V
1.650
V
1.759
V
Note : ON* means that this power plane is ON only with AC power available, other wise it is OFF.
6
200K +/ - 5%
1.935
V
2.200
V
2.341
V
External PCI Devices
7
NC
2.500
V
3.300
V
3.300
V
Devi ce
IDSE L#
REQ#/GNT#
Interrupts
Board ID
PCB Revision
0
0.1
CardBus
AD20
2
PIRQA/PIRQB(PIRQE/PIRQF)
1
0.2
LAN
AD17
3
PIRQB(PIRQD)
2
0.3
Mini-PCI
AD18
1/1
PIRQC/PIRQD(PIRQG/PIRQH)
3
0.4
1394
AD16
0
PIRQA
4
0.5
5
0.6
6
0.7
7
0.8
EC SM Bus1 address
EC SM Bus2 address
3
3
Device
Address
Device
Address
Sapporo Z to ZJ BOM modify list :
Smart Battery
0001
011X b
ADM1032
1001
110X b
1 . Remove R594
2 .Add R112
EEPROM(24C16/02)
1010
000X b
OZ168
0011
0100 b
(24C04)
1011 000Xb
Smart Battery
0001 011X b
Docking
0011
011X b
DOT Board
XXXX XXXXb
ICH4 SM Bus address
Device
Address
Clock Generator (
1101 001X
ICS-950810)
4
4
Compal Electronics, Ltd.
Title
Note List
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Friday, November 29, 2002
Sheet
3
of
46
A
B
C
D
E

1

2

1 2 3 A B C D E 4 +CPU_CORE U40A HA#[3 31] HD#[0 63] 7

3

A

B

C

D

E

4

+CPU_CORE U40A HA#[3 31] HD#[0 63] 7 HA#[3 31] HD#[0 HA#3 K2 B21 HD#0 A#3
+CPU_CORE
U40A
HA#[3 31]
HD#[0
63]
7
HA#[3 31]
HD#[0
HA#3
K2
B21
HD#0
A#3
D#0
HA#4
K4
B22
HD#1
A#4
D#1
HA#5
L6
A23
HD#2
K1
A#5
D#2
HA#6
A25
HD#3
A#6
D#3
HA#7
L3
C21
HD#4
D#4
HA#8
M6
A#7
D22
HD#5
A#8
D#5
HA#9
L2
B24
HD#6
A#9
D#6
HA#10
M3
C23
HD#7
M4
A#10
D#7
HA#11
C24
HD#8
A#11
D#8
HA#12
N1
B25
HD#9
A#12
HA#13
M1
D#9
G22
HD#10
A#13
D#10
HA#14
N2
H21
HD#11
A#14
D#11
HA#15
N4
C26
HD#12
HA#16
N5
A#15
D#12
D23
HD#13
A#16
D#13
HA#17
T1
J21
HD#14
R2
A#17
D#14
HA#18
D25
HD#15
A#18
D#15
HA#19
P3
H22
HD#16
A#19
D#16
HA#20
P4
E24
HD#17
R3
A#20
D#17
HA#21
G23
HD#18
A#21
D#18
HA#22
T2
F23
HD#19
U1
A#22
D#19
HA#23
F24
HD#20
A#23
D#20
HA#24
P6
E25
HD#21
A#24
D#21
HA#25
U3
F26
HD#22
A#25
D#22
HA#26
T4
D26
HD#23
A#26
D#23
HA#27
V2
L21
HD#24
R6
A#27
D#24
HA#28
G26
HD#25
A#28
D#25
HA#29
W1
H24
HD#26
A#29
D#26
HA#30
T5
Mobile
M21
HD#27
U4
A#30
D#27
HA#31
L22
HD#28
A#31
D#28
V3
J24
HD#29
W2
A#32
D#29
K23
HD#30
A#33
D#30
Y1
H25
HD#31
A#34
D#31
AB1
M23
HD#32
A#35
NorthWood
D#32
HREQ#[0 4]
N22
HD#33
7 HREQ#[0 4]
D#33
P21
HD#34
D#34
HREQ#0
J1
M24
HD#35
REQ#0
D#35
HREQ#1
K5
N23
HD#36
REQ#1
D#36
HREQ#2
J4
M26
HD#37
J3
REQ#2
D#37
HREQ#3
N26
HD#38
REQ#3
D#38
HREQ#4
H3
N25
HD#39
G1
REQ#4
D#39
R21
HD#40
7
H_ADS#
ADS#
D#40
P24
HD#41
D#41
R25
HD#42
AC1
D#42
R24
HD#43
+CPU_CORE
R91 Clo se to U37 pinM23
AP#0
D#43
V5
T26
HD#44
AA3
AP#1
D#44
T25
HD#45
BINIT#
D#45
R53
56_0402_5%
AC3
T22
HD#46
IERR#
D#46
T23
HD#47
D#47
R91
220_0402_5%
U26
HD#48
D#48
H6
U24
HD#49
7
H_BREQ0#
D2
BR0#
D#49
U23
HD#50
7
H_BPRI#
BPRI#
D#50
G2
V25
HD#51
7
H_BNR#
BNR#
D#51
G4
U21
HD#52
7
H_LOCK#
LOCK#
D#52
V22
HD#53
D#53
V24
HD#54
D#54
CLK_CPU_BCLK
AF22
W26
HD#55
15
CLK_CPU_BCLK
BCLK0
D#55
CLK_CPU_BCLK#
AF23
Y26
HD#56
15
CLK_CPU_BCLK#
BCLK1
D#56
W25
HD#57
D#57
Y23
HD#58
D#58
Y24
HD#59
F3
D#59
Y21
HD#60
7
H_HIT#
HIT#
D#60
E3
AA25
HD#61
7
H_HITM#
HITM#
D#61
E2
AA22
HD#62
7
H_DEFER#
DEFER#
D#62
AA24
HD#63
D#63
NorthWood
+CPU_CORE
A10
VCC_0
A12
VCC_1
H1
A14
H4
VSS_0
VCC_2
A16
VSS_1
VCC_3
H23
A18
VSS_2
VCC_4
H26
A20
A11
VSS_3
VCC_5
A8
VSS_4
VCC_6
A13
AA10
A15
VSS_5
VCC_7
AA12
VSS_6
VCC_8
A17
AA14
VSS_7
VCC_9
A19
AA16
A21
VSS_8
VCC_10
AA18
VSS_9
VCC_11
A24
AA8
A26
VSS_10
VCC_12
AB11
VSS_11
VCC_13
A3
AB13
VSS_12
VCC_14
A9
AB15
AA1
VSS_13
VCC_15
AB17
VSS_14
VCC_16
AA11
AB19
AA13
VSS_15
VCC_17
AB7
VSS_16
VCC_18
AA15
AB9
VSS_17
VCC_19
AA17
AC10
AA19
VSS_18
VCC_20
AC12
VSS_19
VCC_21
AA23
AC14
AA26
VSS_20
VCC_22
AC16
VSS_21
VCC_23
AA4
AC18
VSS_22
VCC_24
AA7
AC8
AA9
VSS_23
VCC_25
AD11
VSS_24
VCC_26
AB10
AD13
AB12
VSS_25
VCC_27
AD15
VSS_26
VCC_28
AB14
AD17
VSS_27
VCC_29
AB16
AD19
AB18
VSS_28
VCC_30
AD7
VSS_29
VCC_31
AB20
AD9
AB21
VSS_30
VCC_32
AE10
VSS_31
VCC_33
AB24
AE12
VSS_32
VCC_34
AB3
AE14
AB6
VSS_33
VCC_35
AE16
VSS_34
VCC_36
AB8
AE18
AC11
VSS_35
VCC_37
AE20
VSS_36
VCC_38
AC13
AE6
VSS_37
VCC_39
AC15
AE8
AC17
VSS_38
VCC_40
AF11
VSS_39
VCC_41
AC19
AF13
AC2
VSS_40
VCC_42
AF15
VSS_41
VCC_43
AC22
AF17
VSS_42
VCC_44
AC25
AF19
AC5
VSS_43
VCC_45
AF2
VSS_44
VCC_46
AC7
AF21
AC9
VSS_45
VCC_47
AF5
VSS_46
VCC_48
AD1
AF7
VSS_47
VCC_49
AD10
AF9
AD12
VSS_48
VCC_50
B11
VSS_49
VCC_51
AD14
B13
AD16
VSS_50
VCC_52
B15
VSS_51
VCC_53
AD18
B17
VSS_52
VCC_54
AD21
B19
AD23
VSS_53
VCC_55
B7
VSS_54
VCC_56
AD4
B9
AD8
VSS_55
VCC_57
C10
VSS_56
VCC_58
C12
VCC_59
C14
F13
VCC_61
C16
VCC_81
VCC_62
F15
C18
F17
VCC_82
VCC_63
C20
VCC_83
VCC_64
F19
C8
VCC_84
VCC_65
F9
D11
F11
VCC_85
VCC_66
D13
VCC_80
VCC_67
E8
D15
E20
VCC_79
VCC_68
D17
VCC_78
VCC_69
E18
D19
VCC_77
VCC_70
E16
D7
E14
VCC_76
VCC_71
D9
VCC_75
VCC_72
E12
E10
VCC_74
VCC_73
+3VS +3VS Thermal Sensor W=15mil ADM1032AR C503 0.1U_0402_16V4Z 5 H_THERMDA 5 H_THERMDC R377 R376
+3VS
+3VS
Thermal Sensor
W=15mil
ADM1032AR
C503
0.1U_0402_16V4Z
5
H_THERMDA
5
H_THERMDC
R377
R376
4.7K_0402_5%
4.7K_0402_5%
U38
C501
H_THERMDA
2
1
D+
VDD1
2200P_0402_25V7 K
H_THERMDC
3
6
D-
ALERT
8
4
25,34 EC_SMC2
SCLK
THERM
7
5
25,34 EC_SMD2
SDATA
GND
ADM1032AR_SOP-8
Address:1001_100X

63]

7

4

1

2

SDATA GND ADM1032AR_SOP-8 Address:1001_100X 63] 7 4 1 2 3 Compal Electronics, Ltd. Mobile P4-Celeron (1/

3

Compal Electronics, Ltd.

Mobile P4-Celeron (1/ 2)

Title

Size

Custom

Document Number

LA-1641

Rev

0.3

Date:

Thursday, November 28, 2002

Sheet

4

of

46

A

B

C

D

E

A B C D E +CPU_CORE R36 Layout note : 51.1_1%_0603 U40B 1. Place R381
A
B
C
D
E
+CPU_CORE
R36
Layout note :
51.1_1%_0603
U40B
1.
Place R381 and R382 within 0.5" of processor pin F20
2. Place decoupling cap 220PF near CPU.(Within 500mils)
1
1
3. GTLREF trace width 7 mils, and keep 10mils separated
H_RESET#
from other signals
+CPU_CORE
F1
J26
7
H_RS#0
G5
RS#0
DP#0
K25
7
H_RS#1
RS#1
DP#1
F4
K26
7
H_RS#2
AB2
RS#2
DP#2
+CPU_CORE
L25
R381
RSP#
DP#3
J6
7
H_TRDY#
49.9_0402_1%
TRDY#
2/3VCORE
AA21
+GTLREF
GTLREF0
R65
H_A20M#
C6
AA6
16
H_A20M#
A20M#
GTLREF1
H_FERR#
B6
F20
300_0402_5%
C506
C504
R382
16
H_FERR#
FERR#
GTLREF2
H_IGNNE#
B2
F6
16
H_IGNNE#
100_0402_1%
IGNNE#
GTLREF3
H_SMI#
B5
A22
220P_0402_25V8 K
1U_0603_10V6 K
16
H_SMI#
AB23
SMI#
NC1
H_PWRGD
A7
16
H_PWRGD
PWRGOOD
NC2
H_STPCLK#
Y4
+CPU_CORE
16 H_STPCLK#
STPCLK#
Place R65 near to U40 pinAB23
H_DPSLP#
AD25
8,16
H_DPSLP#
DPSLP#
H_INTR
D1
AD24 TESTTHI0_1
R56
56_0402_5%
16
H_INTR
LINT0
TESTHI0
H_NMI
E5
AA2
R59
56_0402_5%
16
H_NMI
W5
TESTHI1
56_0402_5%
16
H_INIT#
LINT1
AC21
R355
INIT#
TESTHI2
H_RESET#
AB25
AC20
R356
56_0402_5%
7 H_CPURST#
RESET#
TESTHI3
AC24
R58
56_0402_5%
R96
TESTHI4
AC23
R62
56_0402_5%
300_0402_5%
TESTHI5
H5
AA20
R354
56_0402_5%
7
H_DBSY#
H2
DBSY#
TESTHI6
AB22
R353
56_0402_5%
7
H_DRDY#
DRDY#
TESTHI7
+CPU_CORE
AD6
U6
TESTTHI8_10
R364
56_0402_5%
15
H_BSEL0
AD5
BSEL0
TESTHI8
W4
R359
56_0402_5%
15
H_BSEL1
BSEL1
TESTHI9
Y3
R66
56_0402_5%
Place R420 near to U12 pinW20
R420
Mobile
TESTHI10
A6
GHI#
GHI#
PM_CPUPERF#
17
56_0402_5%
H_THERMDA
B3
4
H_THERMDA
THERMDA
H_THERMDC
C4
H_DSTBN#[0 3]
2
4
H_THERMDC
THERMDC
H_DSTBN#[0
3]
7
2
E22
H_DSTBN#0
DSTBN#0
H_THERMTRIP#
A2
K22
H_DSTBN#1
THERMTRIP#
DSTBN#1
R22
H_DSTBN#2
NorthWood
DSTBN#2
W22
H_DSTBN#3
DSTBN#3
AC6
H_DSTBP#[0 3]
BPM#0
H_DSTBP#[0
3]
7
AB5
BPM#1
ITP_BPM0
AC4
F21
H_DSTBP#0
BPM#2
DSTBP#0
ITP_BPM1
Y6
J23
H_DSTBP#1
DSTBP#1
ITP_PRDY#
AA5
BPM#3
P23
H_DSTBP#2
BPM#4
DSTBP#2
ITP_PREQ#
AB4
W23
H_DSTBP#3
BPM#5
DSTBP#3
ITP_TCK
D4
L5
TCK
ADSTB#0
H_ADSTB#0
7
ITP_TDI
C1
R5
TDI
ADSTB#1
H_ADSTB#1
7
D5
TDO
+1.2VP
Murata
ITP_TMS
F7
H_DBI#[0 3]
TMS
H_DBI#[0
3]
7
LQG21F4R7N00
ITP_TRST#
E6
E21
H_DBI#0
TRST#
DBI#0
G25
H_DBI#1
L4
DBI#1
4.7UH_80mA_0805
P26
H_DBI#2
+CPU_CORE
DBI#2
1
2
+H_VCCA
AD20
V21
H_DBI#3
A5
VCCA
DBI#3
L3
4.7UH_80mA_0805
TP1
VCCSENSE
1
2
+H_VCCIOPLL
AE23
AE25
R95
VCCIOPLL
DBR#
56_0402_5%
AF25
NC7
+
C1
+
C433
AF3
C3
H_PROCHOT#
33UF_D2_16V
33UF_D2_16V
NC8
PROCHOT#
V6
MCERR#
AB26
H_CPUSLP#
SLP#
H_CPUSLP#
16
H_VSSA
AC26
ITP_CLK0
AD26
AD22
H_VSSA
ITP_CLK1
VSSA
CLK_CPU_ITP
A4
TP2
15
CLK_CPU_ITP
VSSSENSE
L24
3
COMP0
3
P1
COMP1
CLK_CPU_ITP#
AD2
15
CLK_CPU_ITP#
NC3
AD3
TP1 and TP2 must have test points
NC4
TP1
TP2
NorthWood
R87
R84
+1.2VP
R101
R98
51.1_1%_0603
@0_0402_5%
@0_0402_5%
51.1_1%_0603
C33
R84 R87 placed w ith in 0.5" of processor,
and at least 25m ils away from other signals
+5V
0.1U_0402_16V4Z
+CPU_CORE
+3VS
RP6
R590
CPU Voltag e ID
10K
***
1 8
ITP_TMS
2 7
ITP_TCK
34 EC_CPUPD#
3 6
ITP_TRST#
R591
4 5
ITP_TDI
470
R328
1K_0402_5%
1K_8P4R_0804_5%
1.5K_8P4R_0804_5%
Q60
2
3904
RP114
+CPU_CORE
4
CPU_VID0
45
4
CPU_VID1
45
Q61
2
2
1
H_THERMTRIP#
THERTRIP#
17
CPU_VID2
45
2
1
ITP_PREQ#
3904
R592
470
CPU_VID3
45
R85
200_0603
CPU_VID4
45
2
1
ITP_PRDY#
R80
200_0603
2
1
ITP_BPM0
R72
200_0603
Compal Electronics, Ltd.
2
1
ITP_BPM1
Title
R75
200_0603
Place pull up resistors near processor
Mobile P4-Celeron (2/ 2)
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Thursday, November 28, 2002
Sheet
5
of
46
A
B
C
D
E
1
2
12
12
1
2
COMP0
1
2
COMP1
AE11
F8
VSS_57
AE13
VSS_129
VSS_58
G21
AE15
VSS_130
VSS_59
G24
AE17
G3
VSS_131
VSS_60
AE19
VSS_132
VSS_61
G6
AE22
J2
VSS_133
VSS_62
AE24
VSS_134
VSS_63
J22
AE26
VSS_135
VSS_64
J25
AE7
3
1
12
J5
VSS_136
VSS_65
AE9
VSS_137
VSS_66
K21
AF1
K24
VSS_138
VSS_67
AF10
VSS_139
VSS_68
K3
AF12
VSS_140
VSS_69
K6
AF14
L1
VSS_141
VSS_70
AF16
VSS_142
VSS_71
L23
AF18
L26
VSS_143
VSS_72
AF20
VSS_144
VSS_73
3
1
12
L4
AF26
VSS_145
SKTOCC#
M2
AF6
M22
VSS_146
VSS_75
AF8
VSS_147
VSS_76
M25
B10
M5
VSS_148
VSS_77
B12
VSS_149
VSS_78
N21
B14
VSS_150
VSS_79
N24
B16
N3
VSS_151
VSS_80
B18
VSS_152
VSS_81
N6
B20
P2
VSS_153
VSS_82
B23
VSS_154
VSS_83
P22
B26
VSS_155
VSS_84
P25
B4
P5
VSS_156
VSS_85
B8
VSS_157
VSS_86
R1
C11
R23
VSS_158
VSS_87
C13
VSS_159
VSS_88
R26
C15
VSS_160
VSS_89
R4
C17
T21
VSS_161
VSS_90
C19
VSS_162
VSS_91
T24
C2
T3
VSS_163
VSS_92
C22
VSS_164
VSS_93
T6
C25
VSS_165
VSS_94
U2
C5
U22
VSS_166
VSS_95
C7
VSS_167
VSS_96
U25
C9
U5
VSS_168
VSS_97
D10
VSS_169
VSS_98
V1
D12
VSS_170
VSS_99
V23
D14
V26
VSS_171
VSS_100
D16
VSS_172
VSS_101
V4
D18
W21
VSS_173
VSS_102
D20
VSS_174
VSS_103
W24
D21
VSS_175
VSS_104
W3
D24
W6
VSS_176
VSS_105
D3
VSS_177
VSS_106
Y2
D6
Y22
VSS_178
VSS_107
D8
VSS_179
VSS_108
Y25
E1
VSS_180
VSS_109
Y5
E11
VSS_181
VSS_110
E13
VSS_111
E15
VSS_112
E17
VSS_113
E19
VSS_114
AE5
E23
AE4
VID0
VSS_115
E26
VID1
VSS_116
AE3
E4
AE2
VID2
VSS_117
E7
VID3
VSS_118
AE1
E9
VID4
VSS_119
F10
VSS_120
F12
VSS_121
AE21
F14
AF24
NC5
VSS_122
F16
NC6
VSS_123
F18
VSS_124
F2
VSS_125
F22
VSS_126
AF4
F25
VCCVID
VSS_127
F5
VSS_128
2 1
7 8
3
6
4
5
A B C D E Layout note : Layout note : Place close to CPU,
A
B
C
D
E
Layout note :
Layout note :
Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.
Place close to CPU power and
ground pin as possible
(<1inch)
1
1
Used ESR 25m ohm cap total ESR=2.5m ohm
Please place these cap in the socket cavity area
+CPU_CORE
+CPU_CORE
+
C132
+
C110
+
C92
+
C78
+
C60
220UF_D2_4V_25m
220UF_D2_4V_25m
220UF_D2_4V_25m
220UF_D2_4V_25m
220UF_D2_4V_25m
C71
C70
C69
C68
C67
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
+CPU_CORE
+CPU_CORE
+
C134
+
C113
+
C94
+
C81
+
C61
C130
C129
C128
C127
C126
220UF_D2_4V_25m
220UF_D2_4V_25m
220UF_D2_4V_25m
220UF_D2_4V_25m
220UF_D2_4V_25m
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
Please place these cap on the socket north side
+CPU_CORE
+CPU_CORE
C124
C109
C74
C73
C483
2
2
C44
C43
C42
C41
C40
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
+CPU_CORE
+CPU_CORE
C482
C500
C505
C481
C480
C52
C48
C35
C22
C15
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
0.22U_0603_16V7K_V1
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
+CPU_CORE
C34
C19
C12
C10
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
Please place these cap on the socket south side
+CPU_CORE
3
3
C180
C175
C165
C155
C154
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
+CPU_CORE
C161
C168
C138
C143
C150
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
+CPU_CORE
C148
C149
C141
C147
10U_1206_6.3V6M
10U_1206_6.3V6M
10U_1206_6.3V6 M
10U_1206_6.3V6 M
4
4
Compal Electronics, Ltd.
Title
CPU Decoupling
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Monday, November 25, 2002
Sheet
6
of
46
A
B
C
D
E
12
12
12
12
12
12
12
12
12
12
5 4 3 2 1 U37A 4 HA#[3 31] HD#[0 63] 4 Host data Ref.
5
4
3
2
1
U37A
4
HA#[3 31]
HD#[0
63]
4
Host data Ref. Voltage
Montara-GM(L)
HA#3
P23
K22
HD#0
T25
HA#3
HD#0
HA#4
H27
HD#1
+CPU_CORE
HA#4
HD#1
HA#5
T28
K25
HD#2
HA#5
HD#2
HA#6
R27
L24
HD#3
U23
HA#6
HD#3
HA#7
J27
HD#4
R57
HA7#
HD#4
HA#8
U24
G28
HD#5
49.9_0402_1%
1.Place R57 and R55 within 0.5" of U37 pinK21 J21 J17
2.Place C57 C62 C56 C63 in order from U37 to divider
3.HDVREF 10mil trace, 20mil space.
HA#8
HD#5
HA#9
R24
L27
HD#6
HA#9
HD#6
HA#10
U28
L23
HD#7
HA#10
HD#7
HA#11
V28
L25
HD#8
+HDVREF
D
U27
HA#11
HD#8
D
HA#12
J24
HD#9
HA#12
HD#9
HA#13
T27
H25
HD#10
R55
C63
C56
C62
C57
HA#14
V27
HA#13
HD#10
K23
HD#11
100_0402_1%
HA#14
HD#11
HA#15
U25
G27
HD#12
1U_0603_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
HA#15
HD#12
HA#16
V26
K26
HD#13
HA#17
Y24
HA#16
HD#13
J23
HD#14
HA#17
HD#14
HA#18
V25
H26
HD#15
HA#18
HD#15
HA#19
V23
F25
HD#16
HA#19
HD#16
HA#20
W25
F26
HD#17
HA#20
HD#17
HA#21
Y25
B27
HD#18
AA27
HA#21
HD#18
HA#22
H23
HD#19
HA#22
HD#19
HA#23
W24
E27
HD#20
HA#23
HD#20
HA#24
W23
G25
HD#21
HA#24
HD#21
HA#25
W27
F28
HD#22
HA#25
HD#22
Host address Ref. Voltage
HA#26
Y27
D27
HD#23
AA28
HA#26
HD#23
HA#27
G24
HD#24
HA#27
HD#24
HA#28
W28
C28
HD#25
HA#28
HD#25
HA#29
AB27
B26
HD#26
HA#29
HD#26
HA#30
Y26
G22
HD#27
+CPU_CORE
1.Place R86 and R83 within 0.5" of U37 pinY22
HA#30
HD#27
HA#31
AB28
C26
HD#28
HA#31
HD#28
E26
HD#29
HD#29
HREQ#0
R28
G23
HD#30
R86
HREQ#0
HD#30
HREQ#[0 4]
HREQ#1
P25
B28
HD#31
49.9_0402_1%
2.Place C105, C103 in order from U37 to divider
3.HAVREF 10mil trace, 20mil space.
4 HREQ#[0 4]
HREQ#1
HD#31
HREQ#2
R23
B21
HD#32
HREQ#2
HD#32
HREQ#3
R25
G21
HD#33
HREQ#3
HD#33
HREQ#4
T23
C24
HD#34
+HAVREF
HREQ#4
HOST
HD#34
T26
C23
HD#35
5
H_ADSTB#0
AA26
HADSTB#0
HD#35
D22
HD#36
R83
C103
C105
5
H_ADSTB#1
HADSTB#1
HD#36
C25
HD#37
100_0402_1%
HD#37
AD29
E24
HD#38
1U_0603_10V6K
0.1U_0402_16V4Z
15
CLK_MCH_BCLK#
AE29
HCLKN
HD#38
D24
HD#39
15
CLK_MCH_BCLK
HCLKP
HD#39
+HYSWING
K28
G20
HD#40
C
HYSWING
HD#40
C
+HXSWING
B18
E23
HD#41
HXSWING
HD#41
R54
27.4_0402_1%
+HYRCOMP
H28
B22
HD#42
HYRCOMP
HD#42
R35
27.4_0402_1%
+HXRCOMP
B20
B23
HD#43
HXRCOMP
HD#43
F23
HD#44
HD#44
+HDVREF
K21
F21
HD#45
J21
HVREF0
HD#45
C20
HD#46
HVREF1
HD#46
J17
C21
HD#47
HVREF2
HD#47
Host common clock Ref. Voltage
+HCCVREF
Y28
G18
HD#48
+HAVREF
Y22
HCCVREF
HD#48
E19
5
H_DSTBP#[0 3]
HD#49
HAVREF
HD#49
E20
HD#50
HD#50
H_DSTBN#0
J28
G17
HD#51
+CPU_CORE
HDSTBN#0
HD#51
H_DSTBN#1
C27
D20
HD#52
HDSTBN#1
HD#52
H_DSTBN#2
E22
F19
HD#53
D18
HDSTBN#2
HD#53
C19
5
H_DSTBN#[0 3]
H_DSTBN#3
HD#54
R88
HDSTBN#3
HD#54
H_DSTBP#0
K27
C17
HD#55
49.9_0402_1%
1.Place R88 and R89 within 0.5" of U37 pinY28
2.Place C102, C99 in order from U37 to divider
3.HCCVREF 10mil trace, 20mil space.
D26
HDSTBP#0
HD#55
H_DSTBP#1
F17
HD#56
HDSTBP#1
HD#56
H_DSTBP#2
E21
B19
HD#57
5 H_DBI#[0 3]
HDSTBP#2
HD#57
H_DSTBP#3
E18
G16
HD#58
+HCCVREF
J25
HDSTBP#3
HD#58
H_DBI#0
E16
HD#59
DINV0#
HD#59
H_DBI#1
E25
C16
HD#60
R89
C102
C99
B25
DINV1#
HD#60
H_DBI#2
E17
HD#61
100_0402_1%
DINV2#
HD#61
H_DBI#3
G19
D16
HD#62
1U_0603_10V6K
0.1U_0402_16V4Z
DINV3#
HD#62
C18
HD#63
HD#63
H_CPURST#
F15
5 H_CPURST#
CPURST#
HUB_PD[0 10]
HUB_PD0
U7
16 HUB_PD[0 10]
HI_0
HUB_PD1
U4
HI_1
HUB_PD2
U3
L28
HI_2
ADS#
H_ADS#
4
HUB_PD3
V3
M25
HI_3
HTRDY#
H_TRDY#
5
HUB_PD4
W2
N24
HI_4
H_DRDY#
5
W6
DRDY#
HUB_PD5
M28
HI_5
DEFER#
H_DEFER#
4
HUB_PD6
V6
N28
B
HI_6
HITM#
H_HITM# 4
HUB I/F REF VOLTAGE
B
HUB_PD7
W7
N27
H_HIT# 4
T3
HI_7
HIT#
HUB_PD8
P27
HI_8
HLOCK#
H_LOCK#
4
HUB_PD9
V5
M23
HI_9
BREQ0#
H_BREQ0# 4
HUB_PD10
V4
N25
HI_10
BNR#
H_BNR#
4
HUB_PSTRB
W3
P28
+1.5VS
16
HUB_PSTRB
PSTRBS
BPRI#
H_BPRI#
4
HUB_PSTRB#
V2
M26
16
HUB_PSTRB#
PSTRBF
DBSY#
H_DBSY#
5
HI_RCOMP
T2
N23
+1.2VS
HLRCOMP
RS#0
H_RS#0 5
R362
27.4_0402_1%
+HI_VSWING
U2
P26
W1
PSWING
RS#1
H_RS#1 5
+HI_VREF
M27
HI_REF
RS#2
H_RS#2 5
R363
80.6_0402_1%
Between divider and GMCH
MONTARA-GM(L)
+HI_VSWING
L a yout Note:
C496
1.Place R35 and R54 within 0.5" of U37 pinH28 B20
C488
R374
0.01U_0402_25V7K
0.1U_0402_16V4Z
51.1_0603_1%
2.Both HYRCOMP and HXRCOMP trace width are 18mil
and 25mils away from other signals
+HI_VREF
C499
R373
0.1U_0402_16V4Z
40.2_0603_1%
C498
HXSWING and HYSWING Ref. Voltage
0.01U_0402_25V7K
+CPU_CORE
+CPU_CORE
A
A
R319
301_0402_1%
1.Place R60 and R63 within 0.5" of U37 pinK28
2.Place R319 and R309 within 0.5" of U37 pinB18
3.+HYSWING, +HXSWING 10mil trace, 20mil space.
Place this schematic close to GMCH
R60
301_0402_1%
+HYSWING
+HXSWING
R63
C59
R309
C451
Compal Electronics, Ltd.
150_0402_1%
150_0402_1%
Title
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Montara-GML (HOST)
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Thursday, November 28, 2002
Sheet
7
of
46
5
4
3
2
1
HUB I/F
B 5 4 3 2 1 D C +1.5VS U37B Montara-GM(L) R347 1K_0402_1% R3 C9

B

5

4

3

2

1

D

C

+1.5VS U37B Montara-GM(L) R347 1K_0402_1% R3 C9 BLUE BLUE 13 R5 DVOBD0/(NC) D9 DVOBD1/(NC) BLUE#
+1.5VS
U37B
Montara-GM(L)
R347
1K_0402_1%
R3
C9
BLUE
BLUE
13
R5
DVOBD0/(NC)
D9
DVOBD1/(NC)
BLUE#
+GVREF
R6
C8
DVOBD2/(NC)
GREEN
GREEN
13
R4
D8
P6
DVOBD3/(NC)
GREEN#
A7
DVOBD4/(NC)
RED
RED
13
P5
A8
Close to Ball F1
DVOBD5/(NC)
RED#
R344
N5
H10
R14
39_0402_5%
DVOBD6/(NC)
HSYNC
HSYNC
13
1K_0402_1%
P2
J9
R13
39_0402_5%
DVOBD7/(NC)
VSYNC
VSYNC
13
C474
N2
E8
DVOBD8/(NC)
REFSET
+1.5VS
0.1U_0402_16V4Z
N3
B6
DVOBD9/(NC)
DDCACLK
DDC_CLK 13
M1
G9
M5
DVOBD10/(NC)
DDCADATA
DDC_DATA 13
DVOBD11/(NC)
R572
P3
R41
P4
DVOBCLK/(NC)
1K_0402_1%
G14
137_0402_1%
DVOBCLK#/(NC)
IYAM0
TXA0-
13
T6
E15
DVOBHSYNC/(NC)
IYAM1
TXA1-
13
T5
C15
DVOBVSYNC/(NC)
IYAM2
TXA2-
13
L2
C13
DVOBBLANK#/(NC)
IYAM3
100K_0402_5%
R64
M2
F14
DVOBFLDSTL/(NC)
IYAP0
TXA0+
13
E14
IYAP1
TXA1+
13
DVOBC_INTR#
G2
C14
CLK_VCH
DVOBCINTRB
IYAP2
TXA2+
13
DVOBC_CLKINT
M3
B13
14 DVOBC_CLKINT
DVOBCCLKINT
IYAP3
H12
R343
IYBM0
TXB0-
13
DVOC_CLK
J3
E12
@33_0402_5%
14
DVOC_CLK
DVOCCLK
TXB1-
13
DVOC_CLK#
J2
IYBM1
C12
14
DVOC_CLK#
DVOCCLK#
IYBM2
TXB2-
13
DVOC_HSYNC
K6
G11
14
DVOC_HSYNC
IYBM3
DVOC_VSYNC
L5
DVOCHSYNC
G12
14
DVOC_VSYNC
DVOCVSYNC
IYBP0
TXB0+
13
L3
E11
DVOCBLANK#
IYBP1
TXB1+
13
DVOBC_CLKINT
100K_0402_5%
R573
H5
C11
C473
DVOCFLDSTL
IYBP2
TXB2+
13
G10
@10P_0402_50V8K
IYBP3
D14
ICLKAM
TXACLK-
13
R67
MI2CCLK
K7
E13
14
MI2CCLK
MI2CCLK
ICLKAP
TXACLK+
13
@22_0402_5%
MI2CDATA
N6
E10
+3VS
14
MI2CDATA
MI2CDATA
ICLKBM
TXBCLK-
13
MDVICLK
N7
F10
M6
MDVICLK
ICLKBP
TXBCLK+
13
MDVIDATA
MDVIDATA
MDDCCLK
P7
B4
R26
2.2K_0402_5%
MDDCDATA
T7
MDDCCLK
DDCPCLK
C5
R25
2.2K_0402_5%
MDDCDATA
DDCPDATA
C66
@10P_0402_50V8K
G8
+3VS
DVOC_D0
K5
PANELBKLTCTL
F8
DVOCD0
PANELBKLTEN
ENABKL
13
DVOC_D1
K1
A5
ENVDD
13
DVOC_D2
K3
DVOCD1
PANELVDDEN
DVOCD2
DVOC_D3
K2
D12
R536
DVOCD3
LVREFH
DVOC_D4
J6
F12
10K_0402_5%
DVOCD4
LVREFL
DVOC_D5
J5
DVOCD5
R17
@8.2K_0402_5%
DVOC_D6
H2
B12
DVOCD6
LVBG
R18
@8.2K_0402_5%
DVOC_D7
H1
A10
R30
1.5K_0402_1%
DVOCD7
LIBG
R21
@8.2K_0402_5%
DVOC_D8
H3
DVOCD8
R22
@8.2K_0402_5%
DVOC_D9
H4
R19
@8.2K_0402_5%
DVOC_D10
H6
DVOCD9
DVOCD10
R20
@8.2K_0402_5%
DVOC_D11
G3
B7
DREFCLK
DVOCD11
DREFCLK
R16
@8.2K_0402_5%
B17
CLK_VCH
DREFSSCLK
CLK_VCH
15
R15
@8.2K_0402_5%
H9
LCLKCTLA
C6
LCLKCTLB
2
LCLKCTLB
R315
@330_0402_5%
ID0
E5
C675
ID1
F5
ADDID0
R314
@330_0402_5%
100P_0402_25V8 K
ADDID1
R311
@330_0402_5%
ID2
E3
AA22
1
ADDID2
DPWR#/(NC)
R310
@330_0402_5%
ID3
E2
Y23
ADDID3
DPSLP#
H_DPSLP#
5,16
R313
@330_0402_5%
ID4
G5
AD28
PCIRST#
ADDID4
RSTIN#
PCIRST#
14,16,19,20,21,22,24,26,28,33,34
R312
@330_0402_5%
ID5
F4
R316
@330_0402_5%
ID6
G6
ADDID5
J11
ADDID6
PWROK
SYS_PWROK
17,37
R317
330_0402_5%
ID7
F6
ADDID7
D6
R24
EXTTS0
+3VS
Address: 0x7F
330_0402_5%
R574
L7
AJ1
10K_0402_1%
DVODETECT
MCHDETECTVSS
DPMS_CLK
D5
F1
DPMS
+GVREF
GVREF
F7
17 AGP_BUSY#
AGPBUSY#
DVORCOMP
D1
B1
Y3
GRCOMP
NC0
AH1
1.5V level clock
66IN
NC1
A2
AA5
NC2
AJ2
DPMS_CLK
R322
732_0603_1%
RVSD0
NC3
R90
F2
A28
@33_0402_5%
RVSD1
NC4
R51
F3
AJ28
R318
B2
RVSD2
NC5
40.2_0603_1%
A29
RVSD3
NC6
B3
B29
C2
RVSD4
NC7
DVORCOMP should be 10mil width
and 20mil space
AH29
RVSD5
NC8
C3
AJ29
GST[1]
NC9
C115
@10P_0402_50V8K
D2
GST[0]
NC10
AJ4
604_0603_1%
D3
C4
AA9
RVSD8
NC11
D7
RVSD9
RVSD10
L4
RVSD11
1
2
12
DVO
CLKSMISCNC
DACLVDS
3
1
1
2

14 DVOC_TV_D[0 11]

DVOC_TV_D[0 11]
DVOC_TV_D[0 11]

RP115

DVOC_TV_D0 1 DVOC_D0 8 DVOC_TV_D1 2 DVOC_D1 7 DVOC_TV_D2 3 DVOC_D2 6 DVOC_TV_D3 4 DVOC_D3
DVOC_TV_D0
1 DVOC_D0
8
DVOC_TV_D1
2 DVOC_D1
7
DVOC_TV_D2
3 DVOC_D2
6
DVOC_TV_D3
4 DVOC_D3
5
22_8P4R_1206_5%

RP116

DVOC_TV_D4 1 DVOC_D4 8 DVOC_TV_D5 2 DVOC_D5 7 DVOC_TV_D6 3 DVOC_D6 6 DVOC_TV_D7 4 DVOC_D7
DVOC_TV_D4
1 DVOC_D4
8
DVOC_TV_D5
2 DVOC_D5
7
DVOC_TV_D6
3 DVOC_D6
6
DVOC_TV_D7
4 DVOC_D7
5
22_8P4R_1206_5%

RP117

DVOC_TV_D8 1 DVOC_D8 8 DVOC_TV_D9 2 DVOC_D9 7 DVOC_TV_D10 3 DVOC_D10 6 DVOC_TV_D11 4 DVOC_D11
DVOC_TV_D8
1 DVOC_D8
8
DVOC_TV_D9
2 DVOC_D9
7
DVOC_TV_D10
3 DVOC_D10
6
DVOC_TV_D11
4 DVOC_D11
5
22_8P4R_1206_5%
+1.5VS
+1.5V

I2C BUS PU LL UP

RP118 MDDCDATA 1 8 MDDCCLK 2 7 MDVICLK 3 6 MDVIDATA 4 5 8P4R-2.2K_0804 MI2CCLK
RP118
MDDCDATA
1 8
MDDCCLK
2 7
MDVICLK
3 6
MDVIDATA
4 5
8P4R-2.2K_0804
MI2CCLK
R61
2.2K_0402_5%
MI2CDATA
R70
2.2K_0402_5%

15 CLK_MCH_66M

2.2K_0402_5% MI2CDATA R70 2.2K_0402_5% 15 CLK_MCH_66M MONTARA-GM(L) B A D C +3VS U33A Q54 R538 2

MONTARA-GM(L)

B

A

D C +3VS U33A Q54 R538 2 2 1 PCIRST# 3904 74LVC14 0_0402_5% 147
D
C
+3VS
U33A
Q54
R538
2
2
1 PCIRST#
3904
74LVC14
0_0402_5%
147
+3VS C467 U33B 4 3 RTCCLK 74LVC14 147
+3VS
C467
U33B
4
3 RTCCLK
74LVC14
147

0.1U_0402_16V4Z

RTCCLK 17,20,21

A

Speard Spectrum Controller

Layout Note:

R327 1 2 @0_0402_5% 1.Place U54 cl ose to U3 2.CLK_MCH_48M 20mil space and to
R327 1
2
@0_0402_5%
1.Place U54 cl ose to U3
2.CLK_MCH_48M 20mil space and to other DREFCLK signal. 5m il Trace and keep
CLK_MCH_48M
+SVDD
+3VS
U32
1
2
R305
1K_0402_5%
1
2
1
5
R325
1
2
22_0402_1%
DREFCLK
X1/CLK
CLKOUT
R304
1K_0402_5%
7
2
+SVDD
FS1
X2
+SVDD
+3VS
8
4
1
2
L5
FS2
SS%
R329
1K_0402_5%
1
2
1
1
1
1
FCM2012C80_0805
W181
C441
C442
C38
C443
R336
0.1U_0402_10V6K
0.1U_0402_10V6K
4.7U_0805_6.3V6K
0.1U_0402_10V6K
2
2
2
2
1K_0402_5%
3
6
GND
VDD
1
2
15 CLK_MCH_48M CLK_MCH_48M R31 @33_0402_5% C17 @10P_0402_50V8K 1 2
15 CLK_MCH_48M
CLK_MCH_48M
R31
@33_0402_5%
C17
@10P_0402_50V8K
1
2

Compal Electronics, Ltd.

Title

Montara-GML (LVDS)

Size

Custom

Document Number

LA-1641

Rev

0.3

Date:

Thursday, November 28, 2002

Sheet

8

of

46

5

4

3

2

1

5 4 3 2 1 +1.2VS 1 1 + + C18 C46 C90 C98 C89
5
4
3
2
1
+1.2VS
1
1
+
+
C18
C46
C90
C98
C89
C54
150U_D2_6.3VM
150U_D2_6.3VM
C106
10U_1206_6.3V6 M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
U37D
+1.2VS
U37E
+CPU_CORE
C1
R17
One close to D29, one close to Y2
Close to VCCHL0~7
D
VSS91
D
G1
VSS0
U17
VSS1
VSS92
Montara-GM(L)
L1
AB17
J15
G15
U1
VSS2
VSS93
AC17
P13
VCC0
VTTLF0
H16
+1.2VS
VSS3
VSS94
VCC1
VTTLF1
AA1
F18
T13
H18
+1.2VS
VSS4
VSS95
VCC2
VTTLF2
AE1
J18
N14
J19
R2
VSS5
VSS96
AA18
R14
VCC3
VTTLF3
H20
VSS6
VSS97
VCC4
VTTLF4
AG3
AG18
U14
L21
C36
C104
C91
C100
AJ3
VSS7
VSS98
A19
P15
VCC5
VTTLF5
N21
C101
VSS8
VSS99
VCC6
VTTLF6
D4
D19
T15
R21
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_1206_6.3V6 M
0.1U_0402_16V7K
0.1U_0402_16V7K
VSS9
VSS100
VCC7
VTTLF7
G4
H19
AA15
U21
K4
VSS10
VSS101
AB19
N16
VCC8
VTTLF8
H22
VSS11
VSS102
VCC9
VTTLF9
N4
AE19
R16
M22
T4
VSS12
VSS103
F20
U16
VCC10
VTTLF10
P22
VSS13
VSS105
VCC11
VTTLF11
W4
J20
P17
T22
VSS14
VSS106
VCC12
VTTLF12
AA4
AA20
T17
V22
AC4
VSS15
VSS107
AC20
AA17
VCC13
VTTLF13
Y29
+2.5V
+1.5VS
+1.5VS_ALVDS
VSS16
VSS108
VCC14
VTTLF14
AE4
A21
AA19
K29
B5
VSS17
VSS109
D21
W21
VCC15
VTTLF15
F29
1
2
VSS18
VSS110
VCC16
VTTLF16
U5
H21
H14
AB29
L1
VSS19
VSS111
VCC17
VTTLF17
Y5
M21
+1.2VS
A26
C116
C117
C118
C119
C123
C120
L_0603
C449
C448
Y6
VSS20
VSS112
P21
VTTLF18
A20
VSS21
VSS113
VTTLF19
AG6
T21
V1
A18
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.01U_0402_16V7K
C7
VSS22
VSS114
V21
Y1
VCCHL0
VTTLF20
VSS23
VSS115
VCCHL1
E7
Y21
W5
A22
C24
0.1U_0402_16V7K
+2.5V
+2.5V
VSS24
VSS116
VCCHL2
VTTHF0
G7
AA21
U6
A24
C23
0.1U_0402_16V7K
J7
VSS25
VSS117
AB21
U8
VCCHL3
VTTHF1
H29
C55
0.1U_0402_16V7K
VSS26
VSS118
VCCHL4
VTTHF2
M7
AG21
W8
M29
C72
0.1U_0402_16V7K
R7
VSS27
VSS119
B24
V7
VCCHL5
VTTHF3
V29
C95
0.1U_0402_16V7K
C121
C122
C111
C112
C107
C108
100UF_10V_D2
100UF_10V_D2
VSS28
VSS120
VCCHL6
VTTHF4
AA7
F22
V9
VSS29
VSS121
VCCHL7
AE7
J22
AC1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C144
C513
AJ7
VSS30
VSS122
L22
D29
VCCSM0
AG1
VSS31
VSS123
H8
N22
+1.2VS_PLL
VCCAHPLL
VCCSM1
Y2
AB3
+2.5V
C
K8
VSS32
VSS124
VCCAGPLL
C
R22
VCCSM2
AF3
VSS33
VSS125
VCCSM3
P8
U22
A6
Y4
VSS34
VSS126
VCCADPLLA
VCCSM4
T8
W22
B16
AJ5
+1.5VS
+1.5VS_DVO
+CPU_CORE
V8
VSS35
VSS127
AE22
VCCADPLLB
VCCSM5
AA6
VSS36
VSS128
+1.5VS_DVO
VCCSM6
Y8
A23
AB6
1
2
1
1
AC8
VSS37
VSS129
D23
E1
VCCSM7
AF6
L38
VSS38
VSS130
VCCDVO_0
VCCSM8
E9
AA23
J1
Y7
L_0603
C58
C65
C476
+
C80
+
C53
C20
VSS39
VSS131
VCCDVO_1
VCCSM9
L9
AC23
N1
AA8
C479
150U_D2_6.3VM
150U_D2_6.3VM
C114
N9
VSS40
VSS132
AJ23
E4
VCCDVO_2
VCCSM10
AB8
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_1206_6.3V6M
10U_1206_6.3V6 M
0.1U_0402_16V7K
0.1U_0402_16V7K
VSS41
VSS133
VCCDVO_3
VCCSM11
R9
F24
J4
Y9
2
2
U9
VSS42
VSS134
H24
M4
VCCDVO_4
VCCSM12
AF9
VSS43
VSS135
VCCDVO_5
VCCSM13
W9
K24
E6
AJ9
VSS44
VSS136
VCCDVO_6
VCCSM14
AB9
M24
H7
AB10
AG9
VSS45
VSS137
P24
J8
VCCDVO_7
VCCSM15
AA11
VSS46
VSS138
VCCDVO_8
VCCSM16
C10
T24
L8
AB12
J10
VSS47
VSS139
V24
M8
VCCDVO_9
VCCSM17
AF12
VSS48
VSS140
VCCDVO_10
VCCSM18
AA10
AA24
N8
AA13
+1.5VS
+1.5VS_DAC
+2.5V
+2.5V_TXLVDS
VSS49
VSS141
VCCDVO_11
VCCSM19
AE10
AG24
R8
AJ13
D11
VSS50
VSS142
A25
K9
VCCDVO_12
VCCSM20
AB14
1
2
1
2
VSS51
VSS143
VCCDVO_13
VCCSM21
F11
D25
M9
AF15
L27
L28
H11
VSS52
VSS144
AA25
P9
VCCDVO_14
VCCSM22
AB16
L_0603
C21
C32
C8
L_0603
C37
C31
C30
C444
+
C7
VSS53
VSS145
VCCDVO_15
VCCSM23
AB11
AE25
AJ17
VSS54
VSS146
AC11
G26
+1.5VS_DAC
VCCSM24
AB18
0.1U_0402_16V7K
0.01U_0402_16V7K
@220UF_D2_4V_25m
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
22U_1206_16V4Z
47U_6.3V_M
AJ11
VSS55
VSS147
J26
A9
VCCSM25
AF18
VSS56
VSS148
VCCADAC0
VCCSM26
J12
L26
B9
AB20
AA12
VSS57
VSS149
N26
B8
VCCADAC1
VCCSM27
AF21
VSS58
VSS150
VSSADAC
VCCSM28
AG12
R26
AJ21
VSS59
VSS151
VCCSM29
A13
U26
+1.5VS_ALVDS
AB22
D13
VSS60
VSS152
W26
A11
VCCSM30
AF24
VSS61
VSS153
VCCALVDS
VCCSM31
F13
AB26
B11
AJ25
H13
VSS62
VSS154
A27
VSSALVDS
VCCSM32
AF27
VSS63
VSS155
F27
+1.5VS_DLVDS
VCCSM33
N13
AC29
B
VSS64
VSS156
VCCSM34
B
R13
AC27
G13
AF29
+1.2VS
+1.2VS_PLL
U13
VSS65
VSS157
AG27
B14
VCCDLVDS0
VCCSM35
AG29
FB1
VSS66
VSS158
VCCDLVDS1
VCCSM36
AB13
AJ27
J13
+1.5VS
+1.5VS_DLVDS
AE13
VSS67
VSS159
AC28
B15
VCCDLVDS2
0.1UH_10%
VSS68
VSS160
VCCDLVDS3
J14
AE28
C14
C450
1
2
VSS69
VSS161
P14
C29
+2.5V_TXLVDS
L7
T14
VSS70
VSS162
E29
F9
+2.5V_QSM
@220UF_D2_4V_25m
0.1U_0402_16V7K
L_0603
C29
C64
+
C76
VSS71
VSS163
VCCTXLVDS0
AA14
G29
B10
AJ6
AC14
VSS72
VSS164
J29
D10
VCCTXLVDS1
VCCQSM0
AJ8
FB2
0.1U_0402_16V7K
22U_1206_16V4Z
47U_6.3V_M
VSS73
VSS165
VCCTXLVDS2
VCCQSM1
D15
L29
A12
VSS74
VSS166
VCCTXLVDS3
H15
N29
+1.2VS_ASM
0.1UH_10%
N15
VSS75
VSS167
U29
+3VS_GPIO
AD1
C13
C25
VSS76
VSS168
VCCASM0
R15
W29
A3
AF1
U15
VSS77
VSS169
AA29
A4
VCCGPIO_0
VCCASM1
@220UF_D2_4V_25m
0.1U_0402_16V7K
VSS78
VSS170
VCCGPIO_1
AB15
AJ10
C26
VSS79
VSS171
AG15
AJ12
F16
VSS80
VSS172
AJ18
0.1U_0402_16V7K
MONTARA-GM(L)
VSS81
VSS173
J16
AJ20
P16
VSS82
VSS174
C22
VSS83
VSS176
T16
D28
VSS84
VSS177
AA16
E28
AE16
VSS85
VSS178
L6
VSS86
VSS179
A17
T9
D17
VSS87
VSS180
AJ26
+2.5V
+2.5V_QSM
VSS88
VSS181
H17
+3VS
+3VS_GPIO
+1.2VS
+1.2VS_ASM
VSS89
N17
1
2
VSS90
L11
R28
1
2
L_0603
C146
C145
0_0805_5%
L41
L_0603
C509
MONTARA-GM(L)
0.1U_0402_16V7K
4.7U_1206_10V7K
C16
C511
10U_1206_6.3V6M
0.1U_0402_16V7K
100UF_D_16V
A
A
Compal Electronics, Ltd.
Title
Montara-GML (POWER)
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Monday, November 25, 2002
Sheet
9
of
46
5
4
3
2
1
Montara-GM(L)
POWER
5 4 3 2 1 U37C RP16 4P2R_10 RP45 4P2R_10 RP24 4P2R_10 DDR_SMA10 1 4
5
4
3
2
1
U37C
RP16
4P2R_10
RP45
4P2R_10
RP24
4P2R_10
DDR_SMA10
1
4
DDR_F_SMA10
Montara-GM(L)
DDR_SDQ0
1
4
DDR_DQ0
DDR_SDQ4
1 DDR_DQ4
4
DDR_SBS1
2
3
DDR_F_SBS1
DDR_SMA0
AC18
AF2
DDR_SDQ0
DDR_SDQ1
2
3
DDR_DQ1
DDR_SDQ5
2 DDR_DQ5
3
SMA0
SDQ0
DDR_SMA1
AD14
AE3
DDR_SDQ1
AD13
SMA1
SDQ1
DDR_SMA2
AF4
DDR_SDQ2
RP27
4P2R_10
SMA2
SDQ2
DDR_SMA3
AD17
AH2
DDR_SDQ3
RP44
4P2R_10
RP23
4P2R_10
DDR_SMA9
1
4
DDR_F_SMA9
SMA3
SDQ3
DDR_SMA4
AD11
AD3
DDR_SDQ4
DDR_SDQ6
1
4
DDR_DQ6
DDR_SDQ3
1 DDR_DQ3
4
DDR_SMA8
2
3
DDR_F_SMA8
AC13
SMA4
SDQ4
DDR_SMA5
AE2
DDR_SDQ5
DDR_SDQ7
2
3
DDR_DQ7
DDR_SDQ2
2
3
DDR_DQ2
SMA5
SDQ5
DDR_SMA6
AD8
AG4
DDR_SDQ6
AD7
SMA6
SDQ6
DDR_SMA7
AH3
DDR_SDQ7
SMA7
SDQ7
DDR_SMA8
AC6
AD6
DDR_SDQ8
RP43
4P2R_10
RP22
4P2R_10
RP37
4P2R_10
SMA8
SDQ8
DDR_SMA9
AC5
AG5
DDR_SDQ9
DDR_SDQ12
1
4
DDR_DQ12
DDR_SDQ9
1 DDR_DQ9
4
DDR_SMA3
1
4
DDR_F_SMA3
D
SMA9
SDQ9
11,12 DDR_SMA3
DDR_F_SMA3
11
D
DDR_SMA10
AC19
AG7
DDR_SDQ10
DDR_SDQ15
2
3
DDR_DQ15
DDR_SDQ13
2 DDR_DQ13
3
DDR_SMA0
2
3
DDR_F_SMA0
SMA10
SDQ10
11,12 DDR_SMA0
DDR_F_SMA0
11
DDR_SMA11
AD5
AE8
DDR_SDQ11
SDQ11
DDR_SMA12
AB5
SMA11
AF5
DDR_SDQ12
SMA12
SDQ12
AH4
DDR_SDQ13
SDQ13
AF7
DDR_SDQ14
RP42
4P2R_10
RP21
4P2R_10
RP36
4P2R_10
SDQ14
AH6
DDR_SDQ15
DDR_SDQ14
1
4
DDR_DQ14
DDR_SDQ10
1
4
DDR_DQ10
DDR_SRAS#
1
4
DDR_F_SRAS#
SDQ15
11,12 DDR_SRAS#
DDR_F_SRAS#
11
DDR_SDQS0
AG2
AF8
DDR_SDQ16
DDR_SDQ11
2
3
DDR_DQ11
DDR_SDQ8
2
3
DDR_DQ8
DDR_SBS0
2
3
DDR_F_SBS0
SDQS0
MEMORY
AH5
SDQ16
DDR_SDQS1
AG8
DDR_SDQ17
SDQS1
SDQ17
DDR_SDQS2
AH8
AH9
DDR_SDQ18
SDQS2
SDQ18
DDR_SDQS3
AE12
AG10
DDR_SDQ19
RP26
4P2R_10
AH17
SDQS3
SDQ19
DDR_SDQS4
AH7
DDR_SDQ20
RP41
4P2R_10
RP20
4P2R_10
DDR_SMA12
1
4
DDR_F_SMA12
SDQS4
SDQ20
DDR_SDQS5
AE21
AD9
DDR_SDQ21
DDR_SDQ20
1
4
DDR_DQ20
DDR_SDQ17
1
4
DDR_DQ17
DDR_SMA11
2
3
DDR_F_SMA11
AH24
SDQS5
SDQ21
DDR_SDQS6
AF10
DDR_SDQ22
DDR_SDQ16
2
3
DDR_DQ16
DDR_SDQ18
2
3
DDR_DQ18
SDQS6
SDQ22
DDR_SDQS7
AH27
AE11
DDR_SDQ23
SDQS7
SDQ23
AD15
AH10
DDR_SDQ24
RP25
4P2R_10
SDQS8
SDQ24
AH11
DDR_SDQ25
DDR_SMA7
1
4
DDR_F_SMA7
SDQ25
AG13
DDR_SDQ26
RP40
4P2R_10
RP19
4P2R_10
DDR_SMA6
2
3
DDR_F_SMA6
DDR_SWE#
AD25
SDQ26
AF14
DDR_SDQ27
DDR_SDQ21
1
4
DDR_DQ21
DDR_SDQ19
1
4
DDR_DQ19
SWE#
SDQ27
DDR_SRAS#
AC21
AG11
DDR_SDQ28
DDR_SDQ23
2
3
DDR_DQ23
DDR_SDQ22
2 DDR_DQ22
3
SRAS#
SDQ28
DDR_SCAS#
AC24
AD12
DDR_SDQ29
SCAS#
SDQ29
AF13
DDR_SDQ30
RP15
4P2R_10
SDQ30
AH13
DDR_SDQ31
RP39
4P2R_10
RP18
4P2R_10
DDR_SCAS#
1
4
DDR_F_SCAS#
SDQ31
11,12 DDR_SCAS#
DDR_F_SCAS#
11
DDRCLK0
AB2
AH16
DDR_SDQ32
DDR_SDQ28
1
4
DDR_DQ28
DDR_SDQ25
1 DDR_DQ25
4
DDR_SWE#
2
3
DDR_F_SWE#
11
DDR_CLK0
SCMDCLK0
SDQ32
11,12 DDR_SWE#
DDR_F_SWE#
11
DDRCLK0#
AA2
AG17
DDR_SDQ33
DDR_SDQ26
2
3
DDR_DQ26
DDR_SDQ24
2 DDR_DQ24
3
11
DDR_CLK0#
SCMDCLK0#
SDQ33
DDRCLK1
AC26
AF19
DDR_SDQ34
11
DDR_CLK1
AB25
SCMDCLK1
SDQ34
DDRCLK1#
AE20
DDR_SDQ35
11
DDR_CLK1#
SCMDCLK1#
SDQ35
AC3
AD18
DDR_SDQ36
AD4
SCMDCLK2
SDQ36
AE18
DDR_SDQ37
RP38
4P2R_10
RP17
4P2R_10
SCMDCLK2#
SDQ37
DDRCLK3
AC2
AH18
DDR_SDQ38
DDR_SDQ27
1
4
DDR_DQ27
DDR_SDQ31
1 4
DDR_DQ31
11
DDR_CLK3
SCMDCLK3
SDQ38
DDRCLK3#
AD2
AG19
DDR_SDQ39
DDR_SDQ29
2
3
DDR_DQ29
DDR_SDQ30
2 3
DDR_DQ30
11
DDR_CLK3#
DDRCLK4
AB23
SCMDCLK3#
SDQ39
AH20
DDR_SDQ40
11
DDR_CLK4
SCMDCLK4
SDQ40
DDRCLK4#
AB24
AG20
DDR_SDQ41
DDR_DM[0
7]
C
11
DDR_CLK4#
DDR_DM[0
7]
11,12
C
AA3
SCMDCLK4#
SDQ41
AF22
DDR_SDQ42
SCMDCLK5
SDQ42
AB4
AH22
DDR_SDQ43
RP35
4P2R_10
RP14
4P2R_10
SCMDCLK5#
SDQ43
AF20
DDR_SDQ44
DDR_SDQ38
1
4
DDR_DQ38
DDR_SDQ32
1
4
DDR_DQ32
DDR_F_SBS[0 1]
SDQ44
DDR_F_SBS[0
1]
11
AH19
DDR_SDQ45
DDR_SDQ37
2
3
DDR_DQ37
DDR_SDQ33
2
3
DDR_DQ33
SDQ45
AC7
AH21
DDR_SDQ46
11,12 DDR_CKE0
AB7
SCKE0
SDQ46
AG22
DDR_SDQ47
DDR_DQS[0
7]
11,12 DDR_CKE1
SCKE1
SDQ47
DDR_DQS[0
7]
11,12
AC9
AE23
DDR_SDQ48
11,12 DDR_CKE2
SCKE2
SDQ48
AC10
AH23
DDR_SDQ49
RP34
4P2R_10
RP13
4P2R_10
11,12 DDR_CKE3
AD23
SCKE3
SDQ49
AE24
DDR_SDQ50
DDR_SDQ35
1
4
DDR_DQ35
DDR_SDQ36
1
4
DDR_DQ36
DDR_DQ[0
63]
11,12 DDR_SCS#0
SCS#0
SDQ50
DDR_DQ[0
63]
11,12
AD26
AH25
DDR_SDQ51
DDR_SDQ34
2
3
DDR_DQ34
DDR_SDQ39
2
3
DDR_DQ39
11,12 DDR_SCS#1
AC22
SCS#1
SDQ51
AG23
DDR_SDQ52
11,12 DDR_SCS#2
SCS#2
SDQ52
AC25
AF23
DDR_SDQ53
DDR_SMA[6 12]
11,12 DDR_SCS#3
SCS#3
SDQ53
DDR_SMA[6
12]
11,12
AF25
DDR_SDQ54
SDQ54
AG25
DDR_SDQ55
RP33
4P2R_10
RP12
4P2R_10
SDQ55
DDR_SBS0
AD22
AH26
DDR_SDQ56
DDR_SDQ40
1
4
DDR_DQ40
DDR_SDQ45
1
4
DDR_DQ45
DDR_F_SMA[6 12]
11,12 DDR_SBS0
AD20
SBA0#
SDQ56
DDR_F_SMA[6
12]
11
DDR_SBS1
AE26
DDR_SDQ57
DDR_SDQ46
2
3
DDR_DQ46
DDR_SDQ44
2
3
DDR_DQ44
11,12 DDR_SBS1
SBA1#
SDQ57
AG28
DDR_SDQ58
SDQ58
AF28
DDR_SDQ59
DDR_SMA[1 2]
SDQ59
DDR_SMA[1
2]
11,12
DDR_SDM0
AE5
AG26
DDR_SDQ60
SDM0
SDQ60
DDR_SDM1
AE6
AF26
DDR_SDQ61
RP32
4P2R_10
RP11
4P2R_10
AE9
SDM1
SDQ61
DDR_SDM2
AE27
DDR_SDQ62
DDR_SDQ41
1
4
DDR_DQ41
DDR_SDQ47
1 4
DDR_DQ47
DDR_SMA[4 5]
SDM2
SDQ62
DDR_SMA[4
5]
11,12
DDR_SDM3
AH12
AD27
DDR_SDQ63
DDR_SDQ42
2
3
DDR_DQ42
DDR_SDQ43
2 3
DDR_DQ43
SDM3
SDQ63
DDR_SDM4
AD19
SDM4
DDR_SDM5
AD21
DDR_SMA_B[1 2]
SDM5
DDR_SMA_B[1
2]
11,12
DDR_SDM6
AD24
SDM6
DDR_SDM7
AH28
AG14
RP31
4P2R_10
RP10
4P2R_10
SDM7
SDQ64
AH15
AE14
DDR_SDQ53
1
4
DDR_DQ53
DDR_SDQ49
1
4
DDR_DQ49
DDR_SMA_B[4 5]
SDM8
SDQ65
DDR_SMA_B[4
5]
11,12
AE17
DDR_SDQ55
2
3
DDR_DQ55
DDR_SDQ52
2
3
DDR_DQ52
SDQ66
AG16
SDQ67
Routed with Vias
next to ball.
DDR_SMA_B1 AD16
AH14
AC12
SMA_B1
SDQ68
DDR_SMA_B2
AE15
SMA_B2
SDQ69
DDR_SMA_B4 AF11
AF16
RP30
4P2R_10
RP9
4P2R_10
B
SMA_B4
SDQ70
B
DDR_SMA_B5 AD10
AF17
DDR_SDQ50
1
4
DDR_DQ50
DDR_SDQ51
1 4
DDR_DQ51
DDR_SDM0
R153
10_0402_5%
DDR_DM0
SMA_B5
SDQ71
DDR_SDQ54
2
3
DDR_DQ54
DDR_SDQ48
2 3
DDR_DQ48
RCVENOUT#
AC15
DDR_SDM1
R152
10_0402_5%
DDR_DM1
AC16
SRCVENOUT#
RCVENIN#
SRCVENIN#
DDR_SDM2
R151
10_0402_5%
DDR_DM2
+MRCOMP
AB1
AJ24
SMRCOMP
SMVREF0
+SDREF
RP29
4P2R_10
RP8
4P2R_10
DDR_SDM3
R150
10_0402_5%
DDR_DM3
+MVSWINGL
AJ22
DDR_SDQ57
1
4
DDR_DQ57
DDR_SDQ56
1 4
DDR_DQ56
SMVSWINGL
+MVSWINGH
AJ19
DDR_SDQ58
2
3
DDR_DQ58
DDR_SDQ60
2 3
DDR_DQ60
DDR_SDM4
R149
10_0402_5%
DDR_DM4
SMVSWINGH
DDR_SDM5
R148
10_0402_5%
DDR_DM5
MONTARA-GM(L)
C142
RP28
4P2R_10
RP7
4P2R_10
DDR_SDM6
R147
10_0402_5%
DDR_DM6
0.1U_0402_16V4Z
DDR_SDQ59
1
4
DDR_DQ59
DDR_SDQ61
1
4
DDR_DQ61
DDR_SDQ62
2
3
DDR_DQ62
DDR_SDQ63
2
3
DDR_DQ63
DDR_SDM7
R146
10_0402_5%
DDR_DM7
DDR REF & SWING VOLTAGE
DDR_SDQS0
R171
10_0402_5%
DDR_DQS0
+2.5V
+2.5V
+2.5V
DDR_SDQS1
R170
10_0402_5%
DDR_DQS1
DDR_SDQS2
R169
10_0402_5%
DDR_DQS2
R92
R97
R102
60.4_0402_1%
604_0603_1%
150_0402_1%
DDR_SDQS3
R168
10_0402_5%
DDR_DQS3
DDR_SDQS4
R167
10_0402_5%
DDR_DQS4
+MRCOMP
+MVSWINGL
+MVSWINGH
DDR_SDQS5
R166
10_0402_5%
DDR_DQS5
A
A
R93
R100
R107
DDR_SDQS6
R165
10_0402_5%
DDR_DQS6
60.4_0402_1%
150_0402_1%
604_0603_1%
C125
C139
C151
DDR_SDQS7
R164
10_0402_5%
DDR_DQS7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Electronics, Ltd.
Title
Montara-GML (DDR)
Size
Document Number
Rev
Custom
LA-1641
0.3
Date:
Thursday, November 28, 2002
Sheet
10
of
46
5
4
3
2
1
5 4 3 2 1 +2.5V +2.5V +2.5V +2.5V +SDREF_R +SDREF_R JP22 L18 JP23 L19
5
4
3
2
1
+2.5V
+2.5V
+2.5V
+2.5V
+SDREF_R
+SDREF_R
JP22
L18
JP23
L19
1
2
1
2
1
2
1
2
3
VREF
VREF
4
+SDREF
3
VREF
VREF
4
+SDREF
VSS
VSS
VSS
VSS
DDR_DQ0
5
6
DDR_DQ4
C208
MurataBLM21A601S_0805
DDR_DQ0
5
6
DDR_DQ4
C224
MurataBLM21A601S_0805
DQ0
DQ4
DQ0
DQ4
DDR_DQ1
7
8
DDR_DQ5
DDR_DQ1
7
8
DDR_DQ5
9
DQ1
DQ5
10
DQ1
DQ5
0.1U_0402_16V4Z
9
10
0.1U_0402_16V4Z
VDD
VDD
VDD
VDD
DDR_DQS0
11
12
DDR_DM0
DDR_DQS0
11
12
DDR_DM0
DQS0
DM0
DQS0
DM0
DDR_DQ6
13
14
DDR_DQ3
DDR_DQ6
13
14
DDR_DQ3
DQ2
DQ6
15
16
VSS
VSS
15
DQ2
DQ6
16
VSS
VSS
DDR_DQ7
17
18
DDR_DQ2
DDR_DQ7
17
18
DDR_DQ2
D
D
DDR_DQ12
19
DQ3
DQ7
20
DQ3
DQ7
DDR_DQ9
DDR_DQ12
19
20
DDR_DQ9
DDR_DQ[0
63]
DQ8
DQ12
DQ8
DQ12
DDR_DQ[0
63]
10,12
21
22
21
22
VDD
23
VDD
DDR_DQ15
24
DDR_DQ13
23
VDD
VDD
DDR_DQ15
24
DDR_DQ13
DQ9
DQ13
DQ9
DQ13
DDR_DQS1
25
26
DDR_DM1
DDR_DQS1
25
26
DDR_DM1
DQS1
DM1
DQS1
DM1
27
28
27
28
DDR_SMA[6 12]
VSS
VSS
VSS
VSS
DDR_SMA[6
12]
10,12
DDR_DQ14
29
30
DDR_DQ10
DDR_DQ14
29
30
DDR_DQ10
DQ10
DQ14
DQ10
DQ14
DDR_DQ11
31
32
DDR_DQ8
DDR_DQ11
31
32
DDR_DQ8
33
DQ11
DQ15
34
33
DQ11
DQ15
34
DDR_F_SMA[6 12]
VDD
VDD
VDD
VDD
DDR_F_SMA[6
12]
10
35
36
35
36
10 DDR_CLK0
CK0
VDD
10
DDR_CLK3
CK0
VDD
37
38
37
38
10 DDR_CLK0#
CK0#
VSS
10 DDR_CLK3#
39
40
CK0#
VSS
VSS
39
40
VSS
VSS
VSS
DDR_SMA[1 2]
DDR_SMA[1
2]
10,12
DDR_DQ20
41
42
DDR_DQ17
DDR_DQ20
41
42
DDR_DQ17
DQ16
DQ20
DQ16
DQ20
DDR_DQ16
43
44
DDR_DQ18
DDR_DQ16
43
44
DDR_DQ18
45
DQ17
DQ21
46
45
DQ17
DQ21
46
DDR_SMA[4 5]
VDD
VDD
VDD
VDD
DDR_SMA[4
5]
10,12
DDR_DQS2
47
48
DDR_DM2
DDR_DQS2
47
48
DDR_DM2
49
DQS2
DM2
DDR_DQ21
50
DDR_DQ19
DDR_DQ21
49
DQS2
DM2
50
DDR_DQ19
DQ18
DQ22
51
DQ18
DQ22
51
52
52
DDR_SMA_B[1 2]
VSS
VSS
VSS
VSS
DDR_SMA_B[1
2]
10,12
DDR_DQ23
53
54
DDR_DQ22
DDR_DQ23
53
54
DDR_DQ22
55
DQ19
DQ23
56
55
DQ19
DQ23
DDR_DQ28
DDR_DQ25
DDR_DQ28
56
DDR_DQ25
DDR_SMA_B[4 5]
DQ24
DQ28
DQ24
DQ28
DDR_SMA_B[4
5]
10,12
57
58
57
58
VDD
59
VDD
60
59
VDD
VDD
DDR_DQ26
DDR_DQ24
DDR_DQ26
60
DDR_DQ24
DQ25
DQ29
DQ25
DQ29
DDR_DQS3
61
62
DDR_DM3
DDR_DQS3
61
62
DDR_DM3
DDR_DQS[0
7]
DQS3
DM3
DQS3
DM3
DDR_DQS[0
7]
10,12
63
64
63
64
VSS
DDR_DQ27
65
VSS
66
VSS
VSS
DDR_DQ31
DDR_DQ27
65
66
DDR_DQ31
DQ26
DQ30
DQ26
DQ30
DDR_DQ29
67
68
DDR_DQ30
DDR_DQ29
67
68
DDR_DQ30
69
DQ27
DQ31
70
69
DQ27
DQ31
70
DDR_CKE[0 3]
VDD
VDD
VDD
VDD
DDR_CKE[0
3]
10,12
71
72
71
72
CB0
CB4
CB0
CB4
73
74
73
74
75
CB1
CB5
76
75
CB1
CB5
76
DDR_DM[0
7]
VSS
VSS
VSS
VSS
DDR_DM[0
7]
10,12
77
78
77
78
C
79
DQS8
DM8
C
80
79
DQS8
DM8
80
CB2
CB6
CB2
CB6
81
82
81
82
VDD
VDD
VDD
VDD
83
84
83
84
85
CB3
CB7
86
85
CB3
CB7
86
DU
DU/RESET#
DU
DU/RESET#
87
88
87
88
89
VSS
VSS
90
89
VSS
VSS
90
CK2
VSS
CK2
VSS
91
92
91
92
CK2#
VDD
CK2#
VDD
93
94
93
94
VDD
DDR_CKE1
95
VDD
96
DDR_CKE0
95
VDD
VDD
DDR_CKE3
96
DDR_CKE2
10,12 DDR_CKE1
CKE1
CKE0
DDR_CKE0
10,12
10,12 DDR_CKE3
CKE1
CKE0
DDR_CKE2
10,12
97
98
97
98
DU/BA2
DDR_F_SMA12
99
DU/A13
100
DDR_F_SMA11
DDR_SMA12
99
DU/A13
DU/BA2
100
DDR_SMA11
A12
A11
A12
A11
DDR_F_SMA9
101
102
DDR_F_SMA8
DDR_SMA9
101
102
DDR_SMA8
A9
A8
A9
A8
103
104
103
104
105
VSS
VSS
DDR_F_SMA7
106
VSS
VSS
DDR_F_SMA6
DDR_SMA7
105
106
DDR_SMA6
A7
A6
A7
A6
DDR_SMA5
107
108
DDR_SMA4
DDR_SMA_B5
107
108
DDR_SMA_B4
109
A5
A4
A5
A4
DDR_F_SMA3
110
DDR_SMA2
DDR_SMA3
109
110
DDR_SMA_B2
10
DDR_F_SMA3
A3
A2
10,12 DDR_SMA3
A3
A2
DDR_SMA1
111
112
DDR_F_SMA0
DDR_SMA_B1
111
112
DDR_SMA0
A1
A0
DDR_F_SMA0
10
A1
A0
DDR_SMA0
10,12
113
114
113
114
115
VDD
VDD
116
VDD
VDD
DDR_F_SMA10
DDR_F_SBS1
DDR_SMA10
115
116
DDR_SBS1
A10/AP
BA1
DDR_F_SBS1
10
A10/AP
BA1
DDR_SBS1
10,12
DDR_F_SBS0
117
118
DDR_F_SRAS#
DDR_SBS0
117
118
DDR_SRAS#
10
DDR_F_SBS0
BA0
RAS#
DDR_F_SRAS#
10
10,12 DDR_SBS0
119
120
119
BA0
RAS#
DDR_SRAS#
10,12
DDR_F_SWE#
DDR_F_SCAS#
DDR_SWE#
120
DDR_SCAS#
10
DDR_F_SWE#
WE#
CAS#
DDR_F_SCAS#
10
10,12 DDR_SWE#
WE#
CAS#
DDR_SCAS#
10,12
DDR_SCS#0
121
122
DDR_SCS#1
DDR_SCS#2
121
122
DDR_SCS#3
10,12
DDR_SCS#0
S0#
S1#
DDR_SCS#1 10,12
10,12 DDR_SCS#2
S0#
S1#
DDR_SCS#3 10,12
123
124
123
124
125
DU
DU
126
125
DU
DU
126
VSS
VSS
VSS
VSS
DDR_DQ38
127
128
DDR_DQ32
DDR_DQ38
127
128
DDR_DQ32
DQ32
DQ36
DQ32
DQ36
DDR_DQ37
129
130
DDR_DQ33
DDR_DQ37
129
130
DDR_DQ33
DQ33
DQ37
DQ33
DQ37
131
132
131
132
VDD
VDD
VDD
VDD
DDR_DQS4
133
134
DDR_DM4
DDR_DQS4
133
134
DDR_DM4
135
DQS4
DM4
136
DQS4
DM4
DDR_DQ35
DDR_DQ36
DDR_DQ35
135
136
DDR_DQ36
DQ34
DQ38
DQ34
DQ38
137
138
137
138
VSS
139
VSS
DDR_DQ34
140
VSS
VSS
DDR_DQ39
DDR_DQ34
139
140
DDR_DQ39
DQ35
DQ39
DQ35
DQ39
DDR_DQ40
141
142
DDR_DQ45
DDR_DQ40
141
142
DDR_DQ45
B
DQ40
DQ44
DQ40
DQ44
B
143
144
143
144
VDD
DDR_DQ46
145
VDD
146
DDR_DQ44
145
VDD
VDD
DDR_DQ46
146
DDR_DQ44
DQ41
DQ45
DQ41
DQ45
DDR_DQS5
147
148
DDR_DM5
DDR_DQS5
147
148
DDR_DM5
149
DQS5
DM5
150
149
DQS5
DM5
150
VSS
VSS
VSS
VSS
DDR_DQ41
151
152
DDR_DQ47
DDR_DQ41
151
152
DDR_DQ47
DQ42
DQ46
DQ42
DQ46
DDR_DQ42
153
154
DDR_DQ43
DDR_DQ42
153
154
DDR_DQ43