INTEGRATED CIRCUITS

INTEGRAED CIRCUITES (IC) MEANING THAT ALL THE COMPONENTS IN THIS CIRCUITS ARE FABRICATED ON THE SAME CHIP. ICs HAVE BECOME A VITAL PART OF MODERN ELECTRONICS CIRCUITS DESIGN. THEY ARE USED IN THE COMPUTER INDUDTRY ,AUTOMOBILE INDUSTRY, HOME APPLIANCES, COMMUNICATION AND CONTROL SYSTEMS. ICs ARE OF TWO BASIC TYPES : DIGITAL ICS LINEAR ICS

DIGITAL ICS

DIGITAL IC S ARE COMPLETE FUNCTIONING LOGIC NETWORK THAT EQUIVALENTS OF BASIC TRANSISTOR LOGIC CIRCUITS. THEY ARE USED TO FORM SUCH CIRCUITS AS GATE,COUNER,MUX, DEMUX, REGISTER,ETC. DIGITAL CIRCUITS CONCERNED WITH ONLY TWO LEVELS OF VOLTAGE HIGH AND LOW. DIGITAL CKTS ARE EASY TO DESIGN AND PRODUCE IN LARGE QUANTITIES AS LOW COST DEVICES.

LINEAR ICS
LINEAR ICS ARE EQUIVALENT OF DISCREAT TRANSISTER NETWORKS SUCH AS AMPLIFIER ,FILTER ,FREQUENCY MULTIPLIEAR AND MODULATORS. IT REQUIEARS EXTRA COMPONENTSFOR SATISFACTORY OPERATIONS. IN LINEAR CKTS THE OUTPUT OF ELECTRICAL SIGNALS VARY IN PROPORTION TO THE INPUT SIGNALS APPLIED. LINEAR CKTS ARE ALSO REFERRED TO AS ANALOG CIRCUITS.

GENERATION OF INTEGRATED CIRCUITS

TECHNOLOGY
INVENTON OF TRANSISTOR DISCREATE COMPONENTS SMALL SCALE INTEGRATION MEDIUM SCALE INTEGRATION LARGE SCALE INTEGRATION VERY LARGE SCALE INTEGRATION ULTRA LARGE SCALE INTEGRATION GIANT SCALE INTEGRATION NO. OF TRANSISTER PER CHIP 1 1 10 100-1000 1000-20,000 20,000-1,00,000 1,00,000-10,00,000 >10,00,000 YEAR 1947 1950 1961 1966 1971 1980 1990 2000

VLSI DESIGN

VLSI AN INTRODUCTION
VLSI Stands For Very Large Scale Integration VLSI IS A PROCESS OF INTEGRATION OF
MILLIONS OF TRANSISTOR IN A SINGLE CHIP .VLSI DESIGN INVOLVES ALL ASPECTS OF CREATING AN IC. USING VLSI WE CAN PACK MORE AND MORE LOGIC DEVICES INTO SMALLER AND SMALLER AREA

LANGUAGE USED IN VLSI

VLSI BASICALLY USE HDLS ie, HARDWARE DESCRIPTION LANGUAGE HDL IS A LANGUAGE FOR FORMAL DESCRIPTION OF ELECTRONIC CIRCUITS IT CAN DESCRIBE CIRCUITS OPERATION , ITS DESIGN AND TESTS TO VERIFY ITS OPERATION THEY CAN BE USED TO DESIGN ANYTHING FROM INDIVIDUAL FUNCTION MODULES TO LARGE MULTIPLE SYSTEMS

VARIOUS HDLs IN VLSI

VHDL- VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE DESCRIPTION LANGUAGE VERILOG- VERIFY LOGIC HARDWARE DESCRIPTION LANGUAGE ABEL- ADVANCE BOOLEAN EXPRESSION LANGUAGE

THE VHDL LANGUAGE

VHDL IS ONE OF THE MOST ACCEPTED AND WIDELY USED LANGUAGE FOR DESCRIBING DIGITAL SYSTEM . VHDL HAS BEEN APPROVED BY IEEE AS A STANDARD LANGUAGE FOR DESIGING HARDWARE. VHDL IS ABBRIVATION FOR Very High Speed Integrated Circuit HARDWARE DESCRIPTION LANGUAGE.

HISTORY OF VHDL
In 1987: STANDARD VERSION OF VHDL
IEEE Std 1076-1987 WAS LAUNCHED FOR INDUSTRIAL USE In 1993: REVISED IEEE Std-1076-1993 STANDARD WAS RELEASED, VHDL-93. In 2001: REVISED IEEE Std-1076-2001 STANDARD WAS RELEASED, VHDL-2001. In 2002: WORK ON VHDL -200X STARTED.

VHDL DESIGN CYCLE

DESIGN IDEA VHDL MODLE SIMULATION

SIMULATED WAVEFORMS

SYNTHESIZER CIRCUIT GENERATED CIRCUITED IMPLEMENTED

PROGRAM STRUCTURE
LIBRARY/PACKAGE ENTITY ARCHITECTURE

BASIC TERMINOLOGY/ DESIGN UNITS

(A) ENTITY DECLARATION (B) ARCHITECTURE BODY (C) CONFIGURATION DECLARATION (D) PACKAGE DECLARATION (E) PACKAGE BODY

ENTITY:

AN ENTITY IS THE MOST BASIC BUILDING BLOCK IN A DESIGN. A HARDWARE DESCRIPTION OF A DIGITAL SYSTEM IS CALLED AN ENTITY. AN ENTITY SPECIFIES THE EXTERNAL VIEW AND ONE OR MORE INTERNAL VIEWS.

ARCHITECTURE BODY:

THE ARCHITECTURE BODY CONTAINS THE INTERNAL DESCRIPTION OF THE ENTITY. THE ARCHTECTURE DESCRIBES THE FUNCTIONALITY & BEHAVIOUR OF THE ENTITY. AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY.

CONFIGURATION:

IT SPECIFIES THE BINDING OF ONE ARCHITECTURE BODY FROM THE MANY ARCHITECTURE BODIES. CONFIGURATION DECLARATION IS USED TO BIND ONE OF MANY ARCHITECTURE BODIES TO AN ENTITY. IT IS ALSO USED TO BIND COMPONENTS USED IN STRUCTURAL MODEL TO OTHER ENTITY ARCHITECTURE PAIR. AN ENTITY MAY HAVE ANY NUMBER OF DIFFERENT CONFIGURATION. A PACKAGE IS A COLLECTION OF COMMONLY USED DATA TYPES AND SUB PROGRAMS USED IN A DESIGN.

PACKAGE:

PACKAGE DECLARATION:

A PACKAGE DECLARATION ENCAPSULATES A SET OF RELATED DECLARATIONS SUCH AS DATA TYPES, COMPONENTS, SUB PROGRAM (PROCEDURE AND FUNCTIONS). THE DECLARATION INSIDE A PACKAGE CAN BE SHARED BY OTHER DESIGN UNITS BY USING A USE CLAUSE.

PACKKAGE BODY:

A PACKAGE BODY CONTAIN THE DEFINITIONS OF SUBPROGRAMS DECLARED IN A PACKAGE DECLARATION. NAME OF PACKAGE BODY SHOULD BE SAME AS PACKAGE DECLARATION.

NOTE: A HADRWARE DESCRIPTION OF DIGITAL SYSTEM i.e. AN ENTITY MUST HAVE AN ENTITY DECLARATION AND AT LEAST ONE ARECHITECTURE BODY.

ENTITY DECLARATION :

ENTITY DECLARATION DESCRIBES HOW AN ENTITY IS CONNECTED TO OUTSIDE WORLD. IT DESCRIBES THE EXTERNAL VIEW OF THE ENTITY. ENTITY DECLARATION SPECIFIES THE NAME OF ENTITY. IT ALSO SPECIFIES THE INPUT AND OUTPUT PORTS THROUGH WHICH ENTITY COMMUNICATES WITH THE EXTERNAL WORLD.

SYNTEX OF ENTITY DECLARATION : ENTITY entity-name IS PORT (port1: port1-type: port2: port2-type); END entity-name;

Ex.1 WRITE THE ENTITY DECLARATION FOR A 2 INPUT AND GATE. entity AND2 is port (a, b: in bit ; c : out bit); end AND2;

Ex. 2 WRITE THE ENTITY DECLARATION FOR A FULL ADDER. entity FullAdder is port (X, Y, Cin: in bit; -- Inputs Cout, Sum: out bit); -- Outputs end FullAdder;

FullAdde r

ARCHITECTURE :

IT SHOWS THE INSIDE VIEW OR WHAT ARE THE FUNCTIONS OPERATION ARE DONE AND WHICH TYPE OF THAT . AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY & DESCRIBES THE BEHAVIOUR OF THE ENTITY. INTERNAL DETAILS OF AN ENTITY ARE SPECIFIED BY AN ARCHITECTURE BODY BY USING ANY ONE OF THE FOLLOWING MODEL:

SYNTEX OF ARCHITECTURE: ARCHITECTURE arcitecture-name OF entityname IS .declare some signals here BEGIN .put some concurrent statement here END architecture-name;

AREHITECTURE BODY
BEHAVIORAL MODEL STRUCTURAL MODEL DATAFLOW MODEL

BEHAVIORAL MODEL:
THE BEHAVIORAL STYLE OF MODELING SPECIFIES THE BEHAVIORAL OF AN ENTITY AS A STATEMENTS THAT ARE EXECUTED SEQUENTIALLY IN THE SPECIFIED ORDER. ALL STATEMENTS WHICH ARE SPECIFIED INSIDE A PROCESS STATEMENT, DO NOT CLEARLY SPECIFIES THE STRUTURE OF THE ENTITY BUT MERELY ITS FUNCTIONALITY. A PROCESS STATEMENT IS A CONCURRENT STATEMENT THAT CAN APPEAR WITH IN AN ARCHITECTURE BODY.

EX.1 WRITE THE BEHAVIORAL MODEL DESCRIPTION OF AND GATE .

architecture AND-2-BEHAVIOR of AND-2 is begin process (A,B) begin C<=A and B; end process; end AND-2 BEHAVIOR;

EX.2 WRITE THE BEHAVIORAL MODEL DESCRIPTION OF EX-OR GATE .

architecture EX-OR-2-BEHAVIOR of EX-OR-2 is begin process (X,Y) begin Z<=X and Y; end process; end EX-OR-2 BEHAVIOR;

STRUCTURE ARCHITECTURE:
IN THE STRUCTRE STYLE OF MODELING AN ENTITY
IS DESCRIBED IN TERMS OF ITS COMPONENTS AND THEIR INTERCONNECTIONS. A STRUCTURE MODEL DOES NOT TELL ABOUT THE FUNCTIONALITY OF THE ENTITY . A STRUCTURE DESCRIPTION IS EASIEST TO BE SYNTHESIZED. THE ARCHITECTURE BODY IS COMPOSED OF TWO PARTS: 1.THE DECLARATION PART (BEFORE THE KEYWORD BEGIN) 2.THE STATEMENT PART (AFTER THE KEYWORD BEGIN). HALF ADDER IS SUCH TYPE OF STRUCTURE ARCHITECTURE.

EX.1 STRUCTURAL DESCRIPTION OF HALF ADDER.

architecture HALF-ADDER-STRUCTURE of HALF-ADDER is component AND2 port(IN1,IN2: in bit ; OUT1: out bit); end component; component XOR2 port(IN3,IN4: in bit ; OUT2 : out bit); end component; begin A1:AND2 port map (A,B, Sum); X1:XOR2 port map (A,B,Carry); end HALF-ADDER-STRUTURE;

DATAFLOW ARCHITECTURE:
IN THE DATAFLOW STYLE OF MODELING AN
ENTITY IS DESCRIBED IN TERMS OF DATA FLOW BY USING CONCURRENT SIGNAL ASSIGNMENT STATEMENTS. A DATAFLOW MODEL DOES NOT TELL ABOUT THE STRUCTURE OF THE ENTITY .

EX.1 DATAFLOW DESCRIPTION OF HALF ADDER. architecture HALF-ADDER-DATATFLOW of HALFADDER is begin SUM<=A xor B; CARRY<=A and B; end HALF-ADDER-DATAFLOW;

VHDL SOFTWARE USED

1.XILINX ISE 8.1 I 2.ALTERA 3.QUARTUS

OUTPUT WAVE FORM

OUTPUT WAVE FORM

OUTPUT WAVE FORM