Dell Xps m1210

A
COMPAL CONFIDENTIAL
1
MODEL NAME : HAL31(Discrete) & HAL30(UMA)

PCB NO : LA-3001P
COMPAL P/N : 45140031L11 (For Discrete)
45140031L01 (For UMA)
Bali (DIS&UMA) Schematics Document

uFCPGA Mobile Yonah
Intel Calistoga + ICH7M
2006-04-14
REV : 0.5 (DELL: X03)
@ : Nopop Component
1@ : UMA Used Only
2@ : Bali with descrete Used Only
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number
DA800004W0L
Description
PCB LA-3001P
REV0.4 MB
45140031L11 (For Discrete)

BOM NO: 45140031L01 (For UMA)
PCB P/N: DA800004W0L
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Cover Sheet
Size
Rev
0.4
LA-3001P
Date:
Document Number
Monday, April 17, 2006
Sheet
E
of
73
Compal confidential
Block Diagram
Model : Bali
FAN
Thermal
+FAN1_VOUT
GUARDIAN II
EMC4000
+3V_SUS
page 16
Pentium-M
Yonah-2M (Merom Support)
uFCPGA CPU
8X32M GDDR3 x2
PCI-E 16X
DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
400/533 / 667MHz
page 17,18
+0.9V_DDR_VTT
Calistoga
+1.8V_SUS
+1.8V_SUS
PCI BUS
+1.5V_RUN
page 20
SPDIF
+3V_RUN 33MHz
1466pin BGA
IDSEL:AD17
(PIRQC,D#,GNT#1,REQ#1)
+VCCP (1.05V)
For Integrity UMA Graphic
+3V_RUN
+2.5V_RUN
R5C832
+3V_RUN/ +1.5V_RUN 100MHz
+3V_SUS
On LCD Panel
Camera
+5V_RUN
+3V_LAN
page 26
2
+1.5V_RUN
100MHz
USB[4]
Mini Card 2
WLAN
Mini Card 1
WWAN
+3V_RUN
+1.5V_RUN page 29
+3V_RUN
+1.5V_RUN page 29
USB[5]
5 in 1 Card
Reader
48MHz
+3V_RUN
+3V_SUS
48MHz
Azalia I/F
S-ATA 0/2 ATA100
ATA100
ExpressCard CONN
+3V_RUN
+3V_SUS
+1.5V_RUN
SPI
USB Ports X2
USB[0]
USB[1]
USB Ports X2
+5V_SUS page 25
+5V_SUS page 25
IO/B
BC BUS
SMSC KBC
MEC5004
+RTC_CELL
+3.3V_ALW
IO/B
SPI
page 30
CD-ROM
Touch Pad
Int.KBD
page 34
+5V_MOD
page 34
S-HDD
M DC
+5V_HDD
IO/B
+3V_SUS
IO/B
IO/B
DC IN
page 50
HeadPhone &
MIC Jack
+3V_RUN
page 31
+VDD_CORE
IO/B
3
+3V_RUN
+VDDA
+3.3V_ALW
page 41
+5V_SUS
page 25
SMSC SIO
ECE5011
1.8V/0.9V
AMP & INT.

Speaker
Azalia Codec
STAC9220
+3V_RUN
33MHz
Bluetooth
+3V_RUN
IO/B
USB[3]
LPC BUS
USB[2]
page 27
+3V_RUN/ +1.5V_RUN 100MHz
page 21,22,23,24
Right
RJ45
page 29
PCI Express BUS
INTEL
ICH7-M
652pin BGA
+VCCP
USB[6]
USB[7]
1394
CONN
page 28
+1.5V_RUN
BCM4401KQL
page 28
DMI
Left
IDSEL:AD16
(PIRQC#,GNT#4,REQ#4)
page 10,11,12,13,14,15
PCI Express BUS
page6
1
Memory BUS
(DDR2) +1.8V_SUS
INTEL
page 44,45,46,47,48,49,50
TV CONN
+3V_RUN
page 7
H_D#(0..63)
System Bus
G72M
+1.22V_GFX_PCIE
+VCC_GFX_CORE
CK410M+
+VCCP
page 7,8,9
FSB 533/667 MHz
page 20
+INV_PWR_SRC
+LCDVDD page 19
+5VRUN
478pin
H_A#(3..31)
VGA CONN
LVDS CONN
Clock Generator
+VCCP (1.05V)
page 16
+VCC_CORE
+5VRUN
CPU ITP Port
On I/O daughter Card
page 37
Power Sequence
VCORE (IMVP-6)
1.5V/1.05V
page 40
page 42
CHARGER
3V/5V/15V
page 39
page 43
BATT IN
ST M25P80
+3V_SUS
page 30
page 33
page 38
Power On/Off
SW & LED
DC/DC Interface
page 37
page 35
RJ11
page 27

Title
Block Diagram
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
E
of
73
USB PORT#
PM TABLE
+5V_RUN
DESTINATION
JUSB1 (Ext Back Right Side)
Blue Tooth
EXPRESS CARD
CCD Camera
+3.3V_RUN
+2.5V_RUN
power
plane
+1.8V_RUN
+5V_ALW
+15V_SUS
+1.5V_RUN
+3.3V_ALW
+5V_SUS
+1.22V_GFX_PCIE
State
+3.3V_SRC
+0.9V_DDR_VTT
+3.3V_SUS
+VCC_GFX_CORE
+1.8V_SUS
+VCC_CORE
ICH7-M
+1.05V_VCCP
S0
ON
ON
ON
WWAN
S1
ON
ON
ON
JUSB2 (Ext Back Left Side)
S3
ON
ON
OFF
S5 S4/AC
ON
OFF
OFF
None
S5 S4/AC don't exist
OFF
OFF
OFF
None
None
None
None
SIO ECE5011
PCI TABLE
PCI DEVICE
IDSEL
REQ#/GNT#
PIRQ
LAN
AD16
REQ#3/GNT#3
IRQB
PCI EXPRESS
B
R5C832
AD17
REQ#2/GNT#2
IRQC
IRQD
DESTINATION
Lane 1
MINI CARD-1 WWAN
Lane 2
MINI CARD-2 WLAN
Lane 3
None
Lane 4
EXPRESS CARD
Title
Index and Config.

Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
of
73
ALWON
+5V_ALW
ADAPTER
ALWON
+3.3V_ALW
ENAB_3VLAN
+3.3V_LAN
AUX_EN
BATTERY
+3.3V_SRC
+PWR_SRC
SUS_ON
+3.3V_SUS
RUN_ON
+3.3V_RUN
GUARDIAN II
+2.5V_RUN
GFX_RUN_ON
MAX8632/
ISL88550
+VCC_GFX_CORE
(PU13)
+1.22V_GFX_PCIE
+VCC_CORE
+1.5V_RUN
+1.05V_VCCP
RUN_ON
SUSPWROK_5V
RUN_ON
+5V_SUS
MAX8632
(PU5)
ISL6227
(PU4)
RUN_ON
ADP3207
(PU7)
RUNPWROK
SUS_ON
Charger
+1.8V_SUS
+0.9V_DDR_VTT
SI4810
(Q28)
793475
(IO/B)
PL8 & PD8
+VDDA
+15V_SUS
RUN_ON
AUDIO_AVDD_ON
SI3456
(IO/B)
RUN_ON
SI3456
(IO/B)
MODC_EN#
HDDC_EN#
SI4800
(Q35)
+1.8V_RUN
+5V_HDD
+5V_MOD
+5V_RUN
L57
(Option)
Title
Power Rail
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
of
73
+3.3V_SUS
2.2K
ICH7-M
C22
ICH_SMBCLK
B22
ICH_SMBDATA
+3.3V_RUN
2.2K
2.2K
2.2K
2N7002
CLK_SCLK
16
2N7002
CLK_SDATA
17
+3.3V_SUS
8
32
30
32
CLK GEN.
SMBUS Address [D2]
30
+3.3V_ALW
Express Card
10K SMBUS Address [TBD]
10K
10
CLK_SMB
DAT_SMB
MINI WLAN Card
197
MINI WWAN Card
SMBUS Address [TBD]
SMBUS Address [TBD]
DIMMA
195
SMBUS Address [A0]
+3.3V_ALW
GUARDIAN II
197
SMBUS Address [2F]
DIMMB
195
C
SMBUS Address [A2]
+3.3V_ALW
8.2K
SIO
112
SBAT_SMBCLK
111
SBAT_SMBDAT
8.2K
6
+3.3V_ALW
LVDS connector Inverter
SMBUS Address [58]
+3.3V_ALW
8.2K
Macallan IV
B
PBAT_SMBCLK
PBAT_SMBDAT
8.2K
B
100
3
4
BATTERY
CONN
SMBUS Address [16]
10
CHARGER
SMBUS Address [12]
+3.3V_ALW
100
Title
SMBUS TOPOLOGY
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
of
73
CLK_CPU_ITP
2
R169
2
R174
1
CLK_MCH_BCLK
2
+3.3V_RUN
+CK_VDD_MAIN
R159
place Decoupling as closed physically possible to each VDD oins
G 2
3 S
L48
CLK_MCH_BCLK#
2
R163
1
2
CLK_CPU_BCLK
2
1
1
1
1
1
1
BLM21PG600SN1D_0805~D
ICH_SMBDATA 1
CLK_SDATA
C579
C554
C200
C575
C570
C574
R147
3
1
<23,29,36> ICH_SMBDATA
CLK_SDATA <17,18>
CLK_CPU_BCLK#
C530
2
Q51
R155
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
2
2
2
2
CLK_MCH_3GPLL
2N7002_SOT23~D
1
0.1U_0402_16V4Z~D 2
+CK_VDD_MAIN2
R208
L44
CLK_MCH_3GPLL#
1
+3.3V_RUN
R218
1
2
CLK_PCIE_SATA
1
1
1
1
C542
C541
C540
R221
CLK_PCIE_SATA#
1
ICH_SMBCLK
CLK_SCLK
R222
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
1
3
<23,29,36> ICH_SMBCLK
CLK_SCLK <17,18>
2
2
2
CLK_PCIE_ICH
1
Q50
R223
CLK_PCIE_ICH#
2N7002_SOT23~D
R470
1
2.2_0603_5%~D
R224
+CK_VDD_A
CLK_PCIE_MINI2
1
2
1
Placec these caps closed to CK410M
R164
+CK_VDD_A
+CK_VDD_48
+CK_VDD_REF
CLK_PCIE_MINI2#
1
R171
1
1
1
1
1
U15
CLK_PCIE_VGA
1
2@ R185
CLK_PCIE_VGA#
1
2
2
2
2
2
2@ R187
1 VDDSRC
7
CLKSEL2 CLKSEL1 CLKSEL0
VDDA
CLK_PCIE_MINI1
49 VDDSRC
1
R225
54 VDDSRC
8
GNDA
CLK_PCIE_MINI1#
65 VDDSRC
1
0
0
0
33.3
100
266
R226
H_STP_PCI#
CLK_PCIE_EXPCARD 1
H_STP_PCI# <23>
PCI_STOP# 25
R219
30 VDDPCI
1
0
0
33.3
100
133
H_STP_CPU#
CLK_PCIE_EXPCARD#1
36 VDDPCI
H_STP_CPU# <23>
CPU_STOP# 24
R220
MCH_DREFCLK
R455
12 VDDCPU
1
0
1
0
33.3
100
200
1_0603_5%~D
MCH_BCLK
CLK_MCH_BCLK
1@ R143
1
2
CLK_MCH_BCLK <10>
CPUT1 11
+CK_VDD_REF
MCH_DREFCLK#
C166
R158
33_0402_5%~D
18 VDDREF
1
2
1
MCH_BCLK#
CLK_MCH_BCLK#
1@
R151
1
2
1
2
1
1
0
33.3
100
166
CLK_MCH_BCLK# <10>
CPUC1 10
R162
33_0402_5%~D
DREF_SSCLK
1
2 +CK_VDD_48 40 VDD48
1
27P_0402_50V8J~D
X2
R132
1@ R156
2.2_0603_5%~D
CPU_BCLK
CLK_CPU_BCLK
DREF_SSCLK#
1
2
1
1
0
0
33.3
100
333
CLK_CPU_BCLK <7>
CPUT0 14
CLK_XTAL_IN
R146
33_0402_5%~D
1@ R160
20 XIN
Place crystal within
14.31818MHz_20P_1BX14318CC1A~D
C174
CPU_BCLK#
CLK_CPU_BCLK#
1
2
CLK_CPU_BCLK# <7>
500 mils of CK410M
CPUC0 13
27P_0402_50V8J~D
R154
33_0402_5%~D
1
1
0
33.3
100
100
CLK_XTAL_OUT
19 XOUT
1
2
1 R119
2
390_0402_5%~D
CPU_ITP
CLK_CPU_ITP
1
2
CLK_CPU_ITP <7>
CPUT_ITP/SRCT10 6
CLK_ICH_48M
R142 2
R168
33_0402_5%~D
1 33_0402_5%~D
1
1
0
33.3
100
400
<23> CLK_ICH_48M
FSA
CPU_ITP#
CLK_CPU_ITP#
41 USB_48MHz/FSLA
1
2
CLK_CPU_ITP# <7>
CPUC_ITP/SRCC10 5
CPU_MCH_BSEL0 R141 1
R173
33_0402_5%~D
2 8.2K_0402_5%~D
<8,10> CPU_MCH_BSEL0
CPU_MCH_BSEL1 45
1
1
1
Reserve
FSLB/TEST_MODE
PCIE_VGA
CLK_PCIE_VGA
3
1
2
CLK_PCIE_VGA <44>
SRCT9
R184
2@ 33_0402_5%~D
23 REF0/FSLC/TEST_SEL
2
1 FSC
R127
8.2K_0402_5%~D
PCIE_VGA#
CLK_PCIE_VGA#
1
2
Table : ICS954305AK
CLK_PCIE_VGA# <44>
SRCC9 2
R186
2@ 33_0402_5%~D
CLK_PCI_LOM
PCI_LOM
R122 2
34 PCICLK4/FCTSEL1
1 33_0402_5%~D
<26> CLK_PCI_LOM
CLKREQ9# 72
S
6.3V10UF 0805 X5R M H:0.85mm, wait CIS symbol.
CLK_CPU_ITP#
Change to ECJCV50J106M
2
G
R575
2.2K_0402_5%~D
2N7002
R589
2.2K_0402_5%~D
+3.3V_RUN
2
G
Place near each pin

W>40 mil
Place near CK410+
PCI
MHz
C543
0.047U_0402_16V4Z~D
SRC
MHz
C549
0.047U_0402_16V4Z~D
CPU
MHz
C552
4.7U_0603_6.3V6M~D
FSA
C569
0.047U_0402_16V4Z~D
FSB
C573
4.7U_0603_6.3V6M~D
FSC
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
2
49.9_0402_1%~D
CPU_BSEL
CPU_BSEL2(FSC) CPU_BSEL1(FSB)
<28> CLK_PCI_PCCARD
133
<30> CLK_PCI_5004
<23> CLK_ICH_14M
166
<10> MCH_DREFCLK
<10> MCH_DREFCLK#
<21> CLK_PCI_ICH
B
CLK_PCI_PCCARD R123 2
1 33_0402_5%~D
33
PCICLK3
SRCT8
70
MCH_3GPLL
PCI_PCCARD
32
PCICLK2
SRCC8
69
MCH_3GPLL#
PCICLK1
CLKREQ8#
71
SRCT7
66
SRCC7
67
R144 1
2 1@ 33_0402_5%~D DOT96
43
DOTT_96MHz/27MHz
CLKREQ7#
38
MCH_DREFCLK#
R152 1
2 1@ 33_0402_5%~D DOT96#
44
DOTC_96MHz/27MHz
SRCT6
63
PCIE_MINI1
CLK_PCI_ICH
R121 1
SRCC6
64
PCIE_MINI1#
R120 1
33_0402_5%~D PCI_ICH
37
ITP_EN/PCICLK_F0
39
Vtt_PwrGd#/PD
2 10K_0402_5%~D
CLK_ENABLE#
2 CLKIREF
475_0603_1%~D
XTALIN_CLK_GEN
Rb
16
2@ R456
DOT96
2
1
150_0402_5%~D
2@ R459
1
2
+3.3V_RUN
PIN43
PIN44
PIN47
PCI_LOM
UMA
Discrete
DOT96T
DOT96C
96/100M_T
SRCC5
61
CLKREQ5#
29
SRCT4
58
SRCC4
59
CLKREQ4#
57
SMBCLK
SMBDAT
SRCT3
55
GNDSRC
SRCC3
56
15
GNDCPU
CLKREQ3#
28
21
GNDREF
SRCT2
52
31
GNDPCI
SRCC2
53
35
GNDPCI
CLKREQ2#
26
42
GND48
SRCT1
50
68
GNDSRC
73
74
75
76
96/100M_C
60
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
1
R211
PCIE_SATA#
1
R212
SATA_CLKREQ#
R4721
PCIE_EXPCARD 1
R209
PCIE_EXPCARD#1
R210
CARD_CLK_REQ#
R124 1
PCIE_MINI2
1
R165
PCIE_MINI2#
1
R172
MINI2CLK_REQ#
R126 1
SRCC1
51
CLKREQ1#
46
LCD100/96/SRC0_T
47
DOT96_SSC
LCD100/96/SRC0_C
48
DOT96_SSC#
FSA
62
SRCT5
17
PIN48
10K_0402_5%~D
10K_0402_5%~D
R452
@ 10K_0402_5%~D
1@ 10K_0402_5%~D
27M_out
27M SSout
SRCT0
SRCC0
1
R157
1
R161
CLK_PCIE_MINI1 <29>
MINI1CLK_REQ# <29>
+3.3V_RUN
CLK_PCIE_ICH <23>
CLK_PCIE_ICH# <23>
Swap signals for

smooth routing
CLK_PCIE_SATA <22>
CLK_PCIE_SATA# <22>
2 10K_0402_5%~D
CLK_PCIE_EXPCARD
2
33_0402_5%~D
CLK_PCIE_EXPCARD#
2
33_0402_5%~D
2 10K_0402_5%~D
CLK_PCIE_MINI2
2
33_0402_5%~D
CLK_PCIE_MINI2#
2
33_0402_5%~D
SATA_CLKREQ# <23>
+3.3V_RUN
CLK_PCIE_EXPCARD <36>
CLK_PCIE_EXPCARD# <36>
CARD_CLK_REQ# <36>
+3.3V_RUN
CLK_PCIE_MINI2 <29>
CLK_PCIE_MINI2# <29>
MINI2CLK_REQ# <29>
+3.3V_RUN
2 10K_0402_5%~D
DREF_SSCLK
2
1@ 33_0402_5%~D
DREF_SSCLK#
2
1@ 33_0402_5%~D
DREF_SSCLK <10>
DREF_SSCLK# <10>
ICS954305DKLFT_MLF72~D

Title
Clock Generator
Size
Document Number
Rev
0.4
LA-3001P
Date:
CLK_MCH_3GPLL <10>
CLK_MCH_3GPLL# <10>
2 10K_0402_5%~D
CLK_PCIE_ICH
2
33_0402_5%~D
CLK_PCIE_ICH#
2
33_0402_5%~D
R444
Pop Ra,Rb,Rc, Rd for 27MHz output for G72

spectrum input
Routing trace length DOT96/DOT96# <50mil
CLKREQ6#
IREF
DOT96#
33_0402_5%~D
FCTSEL1
(PIN34)
CLK_PCIE_SATA
2
33_0402_5%~D
CLK_PCIE_SATA#
2
33_0402_5%~D
REF1
MCH_DREFCLK
<44> XTALSSIN_CLK_GEN
Rc
PCIE_SATA
22
CLK_SDATA
R451 2@
CLK_PCIE_MINI1# <29>
27
CLKREF
CLK_SCLK
R453
CLK_PCIE_MINI1
2
33_0402_5%~D
CLK_PCIE_MINI1#
2
33_0402_5%~D
PCI_SIO
1 33_0402_5%~D
Ra
+3.3V_RUN
1
R215
1
R216
MINI1CLK_REQ#
R473 1
PCIE_ICH
1
R213
PCIE_ICH#
1
R214
1 33_0402_5%~D
R128 2
1
R464
Pop R451 for 27MHz

output for G72
CLK_3GPLLREQ# <10>
+3.3V_RUN
R125 2
XTALIN_CLK_GEN
<44> XTALIN_CLK_GEN
2 10K_0402_5%~D
CLK_PCI_5004
<42> CLK_ENABLE#
Rd
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
CLK_ICH_14M
+3.3V_RUN
2@ R457
91_0402_5%~D
1
R207
1
R217
CLK_3GPLLREQ#
R204 1
Sheet
1
of
73
<10>
<10>
<10>
<10>
<10>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
<10> H_ADSTB#0
<10> H_ADSTB#1
<6> CLK_CPU_BCLK
<6> CLK_CPU_BCLK#
<10> H_RS#0
<10> H_RS#1
<10> H_RS#2
<10> H_TRDY#
<23,30> ITP_DBRESET#
<10> H_DBSY#
<22> H_DPSLP#
<22,42> H_DPRSTP#
<10> H_DPWR#
R431
@
1
2 TEST1
1K_0402_5%~D
<31> CPU_PROCHOT#
<22> H_PWRGOOD
<10,22> H_CPUSLP#
Stuff R427 for Yonah B0 and

forward.
R427
51_0402_5%~D
1
2
<16> H_THERMDA
C164
@ 2200P_0402_50V7K~D
K3
H2
K2
J3
L5
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
H_ADSTB#0
H_ADSTB#1
L2
V4
ADSTB0#
ADSTB1#
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRD Y#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
<16> H_THERMTRIP#
BCLK0
BCLK1
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
F3
F4
G3
G2
RS0#
RS1#
RS2#
TRDY#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
AD4
AD3
AD1
AC4
BPM0#
BPM1#
BPM2#
BPM3#
J26
M26
V23
AC20
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
H23
M24
W24
AD23
G22
N25
Y25
AE24
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
DATA GROUP
HOST CLK
CONTROL
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
MISC
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
Notes: Can be nopop on X00 board.
ITP_BPM#4
R253
22.6_0402_1%~D
H_RESET# 1
2
@
ITP_TDO
ITP_BPM#5
ITP_TCK
<6> CLK_CPU_ITP
<6> CLK_CPU_ITP#
R258
@ 22.6_0402_1%~D
CLK_CPU_ITP
CLK_CPU_ITP#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
29
JITP1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
No-stuff R253 & R258 for bits issue list: WI52082
@ MOLEX_52435-2891_28P~D
+1.05V_VCCP
Place near JITP
+3.3V_SUS
R246
150_0402_1%~D
ITP_DBRESET#
1
2
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
<10>
<10>
<10>
<10>
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
+1.05V_VCCP
R257
51_0402_5%~D
ITP_TDO
1
2
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
R252
51_0402_5%~D
H_RESET#
R281 39_0402_5%~D
ITP_TMS
1
2
R245
@
54.9_0402_1%~D
ITP_BPM#5
1
2
H_PW RGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
H_THERMDA
H_THERMDC
A24
A25
C7
THERMDA DIODE
THERMDC
THERMTRIP#
<16> H_THERMDC
ADDR GROUP
A22
A21
ITP_DBRESET# C20
H_DBSY#
E1
H_DPSLP#
B5
H_DPRSTP#
E5
H_DPWR#
D24
ITP_BPM#4
AC2
ITP_BPM#5
AC1
CPU_PROCHOT#D21
DINV0#
DINV1#
DINV2#
DINV3#
YONAH
GND6
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
C264
<10> H_LOCK#
<10> H_RESET#
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
+1.05V_VCCP
H_D#[0..63] <10>
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
0.1U_0402_16V4Z~D
56_0402_5%~D
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
0.1U_0402_16V4Z~D
<10> H_ADS#
<10> H_BNR#
<10> H_BPRI#
<10> H_BR0#
<10> H_DEFER#
<10> H_DRDY#
<10> H_HIT#
<10> H_HITM#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
C263
R419
+1.05V_VCCP
JCPU1A
<10> H_A#[3..31]
GND7
30
THERMAL
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
A6
A5
C4
B3
C6
B4
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
STPCLK#
SMI#
D5
A3
H_STPCLK#
H_SMI#
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
LEGACY CPU
R282
150_0402_5%~D
1
2
<22>
<22>
<22>
<22>
<22>
<22>
ITP_TDI
This shall place near CPU

R262
680_0402_5%~D
1
2
H_STPCLK# <22>
H_SMI# <22>
ITP_TRST#
R261 27.4_0402_1%~D
ITP_TCK
1
2
H_THERMTRIP#
TYCO_1-1674770-2_Yonah~D
H_THERMDA, H_THERMDC routing together with guard trace,

Trace width / Spacing = 10 / 10 mil
+1.05V_VCCP
2
+1.05V_VCCP
R264
56_0402_5%~D
1
2 H_THERMTRIP#
R35
75_0402_5%~D
1

CPU_PROCHOT#
Title
Yonah Processor(1/2)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
of
73
Length match within 25 mils

+VCC_CORE
JCPU1B
JCPU1C
+VCC_CORE
<42> VCCSENSE
<42> VSSSENSE
R293
2
B26
VCCA
K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
H_PSI#
AE6
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
+1.5V_RUN
VSSSENSE
100_0402_1%~D
Layout close CPU within 1"

Trace width/space=18mils/7mils
C173
10U_0805_4VAM~D
C167
0.01U_0402_16V7K~D
R283
2
VCCSENSE
VSSSENSE
VCCSENSE
100_0402_1%~D
AF7
AE7
+1.05V_VCCP
space with other is 50mil
<42> H_PSI#
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
133
166
<42>
<42>
<42>
<42>
<42>
<42>
<42>
VID0
VID1
VID2
VID3
VID4
VID5
VID6
V_CPU_GTLREF
AD26
CPU_MCH_BSEL0 B22
CPU_MCH_BSEL1 B23
CPU_MCH_BSEL2 C21
1
2
1
2
1
2
R328
R327
54.9_0402_1%~D
R435
27.4_0402_1%~D
R434
54.9_0402_1%~D
27.4_0402_1%~D
COMP0
COMP1
COMP2
COMP3
Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
+VCC_CORE
Layout Note:
B
COMP0,2 connect with Z0=27.4 ohm, make trace length shorter than 0.5".
COMP1,3 connect with Z0=55.5 ohm, make trace length shorter than 0.5".
E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
YONAH
POWER, GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
+1.05V_VCCP
R26
U26
U1
V1
YONAH
POWER, GROUNG, RESERVED SIGNALS AND NC
VCCSENSE
VSSSENSE
R428
V_CPU_GTLREF
1K_0402_1%~D
R429
A
2K_0402_1%~D
Layout close CPU PIN AD26
0.5 inch (max)

Title
Yonah Processor(2/2)
Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
of
73
Intel CRB schematic suggest to use X5R or better
+VCC_CORE
Place these inside

socket cavity on L8
(North side
Secondary)
1
C110
10U_0805_4VAM~D
1
C101
10U_0805_4VAM~D
1
C103
10U_0805_4VAM~D
1
C92
10U_0805_4VAM~D
1
C82
10U_0805_4VAM~D
1
C126
10U_0805_4VAM~D
1
C117
10U_0805_4VAM~D
1
C119
10U_0805_4VAM~D
1
C111
10U_0805_4VAM~D
C127
10U_0805_4VAM~D
+VCC_CORE
Place these inside

socket cavity on L8
(North side
Secondary)
1
C81
10U_0805_4VAM~D
1
C444
10U_0805_4VAM~D
1
C476
10U_0805_4VAM~D
1
C395
10U_0805_4VAM~D
1
C423
10U_0805_4VAM~D
1
C375
10U_0805_4VAM~D
1
C354
10U_0805_4VAM~D
1
C334
10U_0805_4VAM~D
1
C321
10U_0805_4VAM~D
C374
10U_0805_4VAM~D
+VCC_CORE
Place these inside

socket cavity on L8
(North side
Secondary)
1
C475
10U_0805_4VAM~D
1
C394
10U_0805_4VAM~D
1
C422
10U_0805_4VAM~D
1
C443
10U_0805_4VAM~D
1
C333
10U_0805_4VAM~D
C353
10U_0805_4VAM~D
+VCC_CORE
Place these inside

socket cavity on L8
(North side
Secondary)
1
C320
10U_0805_4VAM~D
1
C93
10U_0805_4VAM~D
1
C446
10U_0805_4VAM~D
1
C329
10U_0805_4VAM~D
1
C481
10U_0805_4VAM~D
C316
10U_0805_4VAM~D
10uF 0805 X6S -> 105 degree C
High Frequence Decoupling
Near VCORE regulator
6mOhm
PS CAP
+
2
6mOhm
PS CAP
1
+
2
6mOhm
PS CAP
1
+
2
6mOhm
PS CAP
C98
330U_D_2VM_R6~D
@
C108
330U_D_2VM_R6~D
@
C130
330U_D_2VM_R6~D
C88
330U_D_2VM_R6~D
South Side Secondary
C324
330U_D_2VM_R6~D
C125
330U_D_2VM_R6~D
+VCC_CORE
North Side Secondary
ESR <= 1.5m ohm

Capacitor > 1980uF
6mOhm
PS CAP
6mOhm
PS CAP
+1.05V_VCCP
1
C432
@ 330U_D2E_2.5VM_R9~D
+
2
C484
0.1U_0402_10V7K~D
C485
0.1U_0402_10V7K~D
C486
0.1U_0402_10V7K~D
C312
0.1U_0402_10V7K~D
C309
0.1U_0402_10V7K~D
C310
0.1U_0402_10V7K~D
Place these inside

socket cavity on L8
(North side
Secondary)
Title
CPU Bypass
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
of
73
UMA use 945GM A2 ( P/N: SA00000592L )

Discrete use 945PM A2 ( P/N: SA00000KD1L)
Description at page12
Note :
CFG3:17 has
internal pullup,
CFG18:19 has
internal pulldown
R81
B9
C13
H_ADSTB#0
H_ADSTB#1
HCLKN
HCLKP
AG1
AG2
CLK_MCH_BCLK#
CLK_MCH_BCLK
K4
T7
Y5
AC4
K3
T6
AA5
AC5
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
J7
W8
U3
AB10
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRD Y#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
HRS0#
HRS1#
HRS2#
B4
E6
D6
H_RS#0
H_RS#1
H_RS#2
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
<23>
<23>
<23>
<23>
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
<17>
<17>
<18>
<18>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
<17>
<17>
<18>
<18>
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
<17>
<17>
<18>
<18>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<17>
<17>
<18>
<18>
+1.8V_SUS
R436 1
1
R432
24.9_0402_1%~D
<21> PLTRST_MCH#
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
AY35
AR1
AW7
AW40
SM_CK0
SM_CK1
SM_CK2
SM_CK3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
AW35
AT1
AY7
AY40
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AU20
AT20
BA29
AY29
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
DDR_CS0_DIMMA# AW13
DDR_CS1_DIMMA# AW12
DDR_CS2_DIMMB# AY21
DDR_CS3_DIMMB# AW21
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SMRCOMPN
SMRCOMPP
AL20
AF10
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
AK1
AK41
PM_BMBUSY#
G28
PM_EXTTS#0
F25
PM_EXTTS#1_R
H26
THERMTRIP_MCH#
G6
ICH_PWRGD
AH33
PLTRST_MCH_R# AH34
MCH_ICH_SYNC#
K28
DPRSLPVR
AG33
AF33
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_MCH_3GPLL <6>
CLK_MCH_3GPLL# <6>
D_REF_CLKN
D_REF_CLKP
A27
A26
MCH_DREFCLK#
MCH_DREFCLK
MCH_DREFCLK# <6>
MCH_DREFCLK <6>
D_REF_SSCLKN
D_REF_SSCLKP
C40
D41
DREF_SSCLK#
DREF_SSCLK
CLK_REQ#
H32
CLK_3GPLLREQ#
G_CLKP
G_CLKN
BA13
BA12
AY20
AU21
AV9
AT9
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
SM_RCOMPN
SM_RCOMPP
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
SM_VREF0
SM_VREF1
PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
CFG5 <12>
CFG6 <12>
CFG7 <12>
CFG9 <12>
CFG10 <12>
CFG11 <12>
CFG12 <12>
CFG13 <12>
CFG16 <12>
CFG18 <12>
CFG19 <12>
CFG20 <12>
DREF_SSCLK# <6>
DREF_SSCLK <6>
CLK_3GPLLREQ# <6>
+1.5V_RUN
MCH_DREFCLK
1
R49
DREF_SSCLK
1
R337
MCH_DREFCLK# 1
R50
DREF_SSCLK#
1
R326
2
2@
2
2@
2
2@
2
2@
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
For Discrete Only
PM_EXTTS#1_R
R296
0_0402_5%~D
+3.3V_RUN
R300
DMITXP0
DMITXP1
DMITXP2
DMITXP3
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
V_DDR_MCH_REF
PM_EXTTS#0
10K_0402_5%~D
1
C704
PM_EXTTS#1_R 2
R297 @
1
10K_0402_5%~D
R313
THERMTRIP_MCH# 1
Place closed to U9 pinAK1,pinAK41
+1.05V_VCCP
75_0402_5%~D
221_0402_1%~D
AC37
AE41
AF37
AG41
CALISTOGA A0_FCBGA1466~D
<23,42> DPRSLPVR
R397
221_0402_1%~D
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
<16> THERMTRIP_MCH#
<23,33> ICH_PWRGD
2
1
R425
100_0402_1%~D
C509
100_0402_1%~D
H_VREF
DMITXN0
DMITXN1
DMITXN2
DMITXN3
M_ODT0
M_ODT1
M_ODT2
M_ODT3
<21> MCH_ICH_SYNC#
+1.05V_VCCP
R318
AE37
AF41
AG37
AH41
0.1U_0402_16V4Z~D
R365
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
M_ODT0
M_ODT1
M_ODT2
M_ODT3
0.1U_0402_16V4Z~D
Layout Note:
H_XRCOMP & H_YRCOMP / H_SWNG0 &
H_SWNG1 trace width and spacing is 10/20
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
<23> PM_BMBUSY#
<17> PM_EXTTS#0
<17,18,41> V_DDR_MCH_REF
+1.05V_VCCP
AC35
AE39
AF35
AG39
V_DDR_MCH_REF
+1.05V_VCCP
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
2 80.6_0402_1%~D
2
80.6_0402_1%~D
R395
24.9_0402_1%~D
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
CFG
<23>
<23>
<23>
<23>
AE35
AF39
AG35
AH39
CLK
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
M_OCDOCMP0
M_OCDOCMP1
<7>
<7>
<7>
<7>
H_RESET# <7>
H_ADS# <7>
H_TRDY# <7>
H_DPWR# <7>
H_DRDY# <7>
H_DEFER# <7>
H_HITM# <7>
H_HIT# <7>
H_LOCK# <7>
H_BR0# <7>
H_BNR# <7>
H_BPRI# <7>
H_DBSY# <7>
H_CPUSLP# <7,22>
<23>
<23>
<23>
<23>
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
CLK_MCH_BCLK# <6>
CLK_MCH_BCLK <6>
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
<17>
<17>
<18>
<18>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
<7>
<7>
<7>
<7>
<7>
<23>
<23>
<23>
<23>
NC
HOST
HADSTB#0
HADSTB#1
HDINV#0
HDINV#1
HDINV#2
HDINV#3
U9B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
J13
K13
E1
E2
Y1
U1
E4
W1
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
D8
G8
B8
F8
A8
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
PM
R383
54.9_0402_1%~D
R79
54.9_0402_1%~D
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DDR MUXING
+1.05V_VCCP
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
DMI
H_A#[3..31] <7>
U9A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
RESERVED
<7> H_D#[0..63]
H_SWNG0
H_SWNG1
1
2
2
C398
0.1U_0402_16V4Z~D
R396
100_0402_1%~D
C300
0.1U_0402_16V4Z~D
R330
100_0402_1%~D
R354
200_0402_1%~D
C326
0.1U_0402_16V4Z~D
Title
Calistoga(1 of 6)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
10
of
73
U9E
U9D
AU12
AV14
BA20
SA_BS0
SA_BS1
SA_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
DDR_A_D[0..63] <17>
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
<17> DDR_A_DM[0..7]
<17> DDR_A_DQS#[0..7]
<17> DDR_A_MA[0..13]
T2
T4
PAD~D
PAD~D
<17> DDR_A_CAS#
<17> DDR_A_RAS#
<17> DDR_A_WE#
DDR_A_CAS#
AY13
DDR_A_RAS#
AW14
DDR_A_WE#
AY14
SA_RCVENIN#
AK23
SA_RCVENOUT# AK24
DDR SYS MEMORY A
<17> DDR_A_DQS[0..7]
SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#
Add a test point
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D[0..63] <18>
<18> DDR_B_BS0
<18> DDR_B_BS1
<18> DDR_B_BS2
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AT24
AV23
AY28
SB_BS0
SB_BS1
SB_BS2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
AR24
AU23
AR27
AK16
AK18
SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#
<18> DDR_B_DM[0..7]
<18> DDR_B_DQS[0..7]
<18> DDR_B_DQS#[0..7]
<18> DDR_B_MA[0..13]
T3
T5
PAD~D
PAD~D
<18> DDR_B_CAS#
<18> DDR_B_RAS#
<18> DDR_B_WE#
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#
DDR SYS MEMORY B
<17> DDR_A_BS0
<17> DDR_A_BS1
<17> DDR_A_BS2
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
Add a test point
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
Title
Calistogo(2 of 6)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
11
of
73
Strap Pin Table
BIA_PWM
PANEL_BKEN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
ENVDD
<19> ENVDD
L_IBG
2
1
R290
1@ 1.5K_0402_1%~D
<19> BIA_PWM
<19> PANEL_BKEN
LVREF
LVREF for Alviso N.C

for Calistoga to GND
A32
A33
E26
E27
LA_CLK
LA_CLK#
LB_CLK
LB_CLK#
D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
TVDAC_A
TVDAC_B
TVDAC_C
TVIREF
J20
TV_IREF
TV_IRTN
B16
B18
B19
TV_IRTNA
TV_IRTNB
TV_IRTNC
J29
K30
TV_DCONSEL1
TV_DCONSEL0
G_CLK_DDC2
G_DAT_DDC2
C26
C25
DDCCLK
DDCDATA
VGA_VSYNC
VGA_HSYNC
VGA_BLU
CRT_RGB#
VGA_GRN
H23
G23
E23
D23
C22
B22
A21
B21
VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VGA_RED
<20> VGA_RED
LB_DATA#0
LB_DATA#1
LB_DATA#2
A16
C18
A19
1
2
<20> VGA_GRN
G30
D30
F29
CRT
<20> VGA_VSYNC
<20> VGA_HSYNC
<20> VGA_BLU
LB_DATA0
LB_DATA1
LB_DATA2
TV_CVBS_NB
TV_Y_NB
TV_C_NB
R360
R307
1@ 4.99K_0402_1%~D
1@ 150_0402_1%~D
R308
1@ 150_0402_1%~D
R305
1@ 150_0402_1%~D
Close to U9.J20
F30
D29
F28
TV
<20> TV_CVBS_NB
<20> TV_Y_NB
<20> TV_C_NB
LA_DATA#0
LA_DATA#1
LA_DATA#2
R366
B
Close to U9.J22
CRT_IREF
J22
CRT_IREF
1@ 255_0402_1%~D
Trace CRT_IREF should be at

least 25 mils away from any
other toggling signal.
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
PEG_MRX_GTX_P[0:15]
VGA_RED
2
1@ 150_0402_1%~D
VGA_GRN
2
1@ 150_0402_1%~D
VGA_BLU
2
1@ 150_0402_1%~D
PEG_MRX_GTX_P[0:15] <44>
PEG_MRX_GTX_N[0:15]
R271
2
2@ 0_0402_5%~D
TV_IRTN
1
2
R306
1
1@ 0_0402_5%~D
PEG_MRX_GTX_N[0:15] <44>
PEG_MTX_GRX_P[0:15]
PEG_MTX_GRX_P[0:15] <44>
2
R304
1
1@ 0_0402_5%~D
1
2
2@ 0_0402_5%~D
CRT_RGB#
1
R269
2
Low = Reverse Lane

High = Normal Operation
High = Reserved
00
01
10
11
Low = Disabled
High = Enabled
CFG19
(DMI Lane Reversal)
SDVO_CTRLDATA
Stuff AC Caps For Discrete

CFG20
(PCIE/SDVO select)
LDDC_CLK <19>
LDDC_DATA <19>
@2.2K_0402_5%~D
<10> CFG11
R310 1
2 @ 2.2K_0402_5%~D
<10> CFG12
R277 1
2 @ 2.2K_0402_5%~D
<10> CFG13
R312 1
2 @ 2.2K_0402_5%~D
<10> CFG16
R275 1
2 @ 2.2K_0402_5%~D
CFG[3:17] have internal pullup
= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation (Default)
CFG16
(VCC Select)
Low = Calistoga
(FSB Dynamic ODT)

CFG18
Low = Reserved
High = Mobility
R276
<10> CFG10
+3.3V_RUN
<10> CFG18
<10> CFG19
<10> CFG20
Low = 1.05V (Default)
High = 1.5V
R57
2 @ 1K_0402_5%~D
R55
2 @ 1K_0402_5%~D
R56
2 @ 1K_0402_5%~D
C
CFG[18:19] have internal pulldown
Low = Normal
Operation (Default):
Lane number in Order
Resistors Stuff Table
High = Reverse Lane

Low = No SDVO Device Present
(Default)
High = SDVO Device Present
R290,R305,R307,R308,R360
,R366,R301,R302,R303,R294
,R295,R292,R306,R304,R38
,R39,298,R299,
UMA
Low = Only PCIE or SDVO is

operational. (Default)
High = PCIE/SDVO are

operating simu.
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
C58
2 0.1U_0402_16V4Z~D 2@
2@ C61 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
C63
2 0.1U_0402_16V4Z~D 2@
2@ C65 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2
C68
2 0.1U_0402_16V4Z~D 2@
2@ C71 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
C74
2 0.1U_0402_16V4Z~D 2@
2@ C79 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4
C80
2 0.1U_0402_16V4Z~D 2@
2@ C84 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
C87
2 0.1U_0402_16V4Z~D 2@
2@ C90 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
C91
2 0.1U_0402_16V4Z~D 2@
2@ C94 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
C96
2 0.1U_0402_16V4Z~D 2@
2@ C105 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
C106 1
2 0.1U_0402_16V4Z~D 2@
2@ C107 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
C109 1
2 0.1U_0402_16V4Z~D 2@
2@ C113 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
R271,R272,R273,R270,R53,
R358,R345,R266,R267,R268,
R371,R269
Discrete
+3.3V_RUN
R299
R298
1@ 2.2K_0402_5%~D
1@ 2.2K_0402_5%~D
G_CLK_DDC2
1 CLK_DDC2
Q18
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10
C112 1
2 0.1U_0402_16V4Z~D 2@
2@ C116 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11
C120 1
2 0.1U_0402_16V4Z~D 2@
2@ C124 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12
C123 1
2 0.1U_0402_16V4Z~D 2@
2@ C129 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13
C134 1
2 0.1U_0402_16V4Z~D 2@
2@ C137 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14
C136 1
2 0.1U_0402_16V4Z~D 2@
2@ C140 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15
C142 1
2 0.1U_0402_16V4Z~D 2@
2@ C147 1
2 0.1U_0402_16V4Z~D
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
CLK_DDC2 <20>
1@ BSS138_SOT23~D
+3.3V_RUN
G_DAT_DDC2
Q19
1
DAT_DDC2
DAT_DDC2 <20>
1
2@
1
2@
1
2@
1
2@
High = Mobile CPU
VGA_BLU
0_0402_5%~D
VGA_GRN
0_0402_5%~D
VGA_RED
0_0402_5%~D
CRT_IREF
0_0402_5%~D
2
R266
2
R267
2
R268
2
R371
2 @ 2.2K_0402_5%~D
TV_CVBS_NB
0_0402_5%~D
TV_Y_NB
0_0402_5%~D
TV_C_NB
0_0402_5%~D
TVIREF
0_0402_5%~D
VGA_VSYNC
0_0402_5%~D
VGA_HSYNC
0_0402_5%~D
CFG[13:12]
<10> CFG9
Low = DT/Transportable CPU
LVREF
1
1@ 0_0402_5%~D
1
2@
1
2@
1
2@
1
2@
1
2@
1
2@
1@ 2.2K_0402_5%~D
2
R292
2
R272
2
R273
2
R270
2
R53
2
R358
2
R345
PEG_MTX_GRX_N[0:15] <44>
+3.3V_RUN
R38
LCTLA_CLK
2
1@ 10K_0402_5%~D
LCTLB_DATA
2
1@ 10K_0402_5%~D
CFG11
2 @ 2.2K_0402_5%~D
R311 1
+1.05V_VCCP
R39
1@ 2.2K_0402_5%~D
1
R294
1
R295
CFG10
R329 1
PEG_MTX_GRX_N[0:15]
+1.5V_RUN
+3.3V_RUN
CFG9
+1.5V_RUN
1
R303
1
R302
1
R301
CFG7
<10> CFG7
High = Calistoga
LCD_ACLK+_NB
LCD_ACLK-_NB
C37
B35
A37
LVDS
<19> LCD_ACLK+_NB
<19> LCD_ACLK-_NB
LCD_A0-_NB
LCD_A1-_NB
LCD_A2-_NB
LA_DATA0
LA_DATA1
LA_DATA2
D40
D38
Low = Moby Dick
<19> LCD_A0-_NB
<19> LCD_A1-_NB
<19> LCD_A2-_NB
B37
B34
A36
EXP_COMPI
EXP_COMPO
CFG6
<10> CFG6
<19> LCD_A0+_NB
<19> LCD_A1+_NB
<19> LCD_A2+_NB
LCD_A0+_NB
LCD_A1+_NB
LCD_A2+_NB
SDVOCTRL_DATA
SDVOCTRL_CLK
PCI-EXPRESS GRAPHICS
H27
H28
+1.5V_RUN_PCIE
R353
24.9_0402_1%~D
PEGCOMP 1
2
@2.2K_0402_5%~D
U9C
2 @ 2.2K_0402_5%~D
R309
SDVO_CTRLDATA have internal pull down
High = DMI x 4
R274 1
<10> CFG5
Low = DMI x 2
CFG5
1@ BSS138_SOT23~D
A
NOTE:
1@ is for UMA Implemetation.
2@ is for Discrete Implementation.
Title
Calistoga(3 of 6)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
12
of
73
VCC _SYNC
U9H
VCC_SYNC
Cg
C36
Ch
2
R54
+1.5V_RUN_QTVDAC
Ck
2+1.5VRUN_QTVDAC
1
2@ 0_0402_5%~D
+1.5V_RUN
L7
BLM18PG181SN1_0603~D
1
2
100mA
+1.5V_RUN_HPLL
45mA Max.
C460
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+1.5V_RUN_DPLLA
1
2@ 0_0402_5%~D
C488
22U_0805_6.3VAM~D
+1.5V_RUN_DPLLB
+1.5V_RUN
+1.5V_RUN
L26
2
1
10U_CK2125 100M-T_20%_0805~D
L6
La
1
C279
0.1U_0402_16V4Z~D
R421
R409
L39
1
2 +3GPLL_R 2
1+3V_GPLL 1
2
0.5_0805_1%~D
0_0805_5%~D
1
40mA Max.
2
1
10U_CK2125 100M-T_20%_0805~D
1
C15
1@ 470U_D2_2.5VM_R15~D
C285
0.1U_0402_16V4Z~D
C514
0.1U_0402_16V4Z~D
C474
C450
22U_0805_6.3VAM~D
close pin A38
1@ 0_0402_5%~D
1 VCCD_LVDS
2
R36
+1.5V_RUN
L40
2
1
BLM11A121S_0603~D
45mA Max.
2
1
BLM11A121S_0603~D
1
R37
2
La, Lb use 0_0805_5% resistor

for Int. VGA as Travis.
+1.5V_RUN
C448
R546
+3.3V_TV_DAC
+1.5V_RUN_MPLL
40mA Max.
Ce, Cf, Cg, Ch, Cj, Ck,

Cl replace by 0 ohm
0805 resistor
+1.5V_RUN
L38
C10
1
2@ 0_0402_5%~D
2
3
C23
1@ 0.1U_0402_16V4Z~D
+3VRUN_ATV
2
R23
For Power measurement.

No need for RTS board
Lb
C311
1@ 470U_D2_2.5VM_R15~D
Note : C15,C311 stuff for UMA

No Stuff for Ext. VGA.
A
1@ 10_0603_5%~D
1@ 10U_0805_4VAM~D
1VCCD_TVDAC
VCCA_LVDS
close pin B30/C30/A30
10U_0805_4VAM~D
1@ 10_0603_5%~D
1@ 0_0402_5%~D
1 VCCA_TVDACC
1@ C296
0.1U_0402_16V4Z~D
+3.3V_RUN
1
R20
2
1
1
1@ 22n_0805_25V
C483
D17
1
2@ 0_0402_5%~D
+3VRUN_TVDACC
0.022U_0402_16V7K~D
R378
1+2.5V_CRT_DAC 1
2
R46
1@ 0_0603_5%~D
+3VRUN_ATVBG
1@ C7
0.1U_0402_16V4Z~D
R28
+1.5V_RUN
+1.5V_RUN
Note : Ca~Cd No stuff for Ext. VGA.

Stuff for Int. VGA.
+1.5V_RUN_3GPLL
+2.5V_RUN
Cl
+1.5V_RUN_QTVDAC
C447
0.1U_0402_16V4Z~D
+1.05V_VCCP
D12
VCCTX_LVDS
1@ 0_0402_5%~D
1 VCCA_TVDACB
C8
1@ 0.1U_0402_16V4Z~D
+1.5V_RUN
Cd
C9
1@ 0.1U_0402_16V4Z~D
Cc
R41
2
C32
0.1U_0402_16V4Z~D
1
2@ 0_0402_5%~D
Cf
C21
+3.3V_RUN
2
3
C18
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
+3.3V_RUN
200mA
1@ R323
0_0402_5%~D
1VCCD_TV_DAC 2
1@ 0_0402_5%~D
1 VCCA_TVDACA
2
R30
C31
A23
B23
B25
Ce
L5
1@ BLM18PG181SN1_0603~D
1
2
C271 1@
22n_0805_25V
C19
D21 VCCD_TVDAC
H19
+1.5V_RUN_QTVDAC
R25
2
1@ C39
VCCD_LVDS
A28
B28
C28
+1.5V_RUN
1
2@ 0_0402_5%~D
2
3
1@ 22n_0805_25V
+1.5V_RUN
2
R24
+3V_TVDAC
+3VRUN_TVDACB
1@ C25
close pin D21
+1.5V_RUN
1@ 0_0402_5%~D
1 VCCA_TVBG
1@ 22n_0805_25V
+3VRUN_TVDACC
AH1
AH2
R29
2
22n_0805_25V
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
+1.5V_RUN
1
2@ 0_0402_5%~D
C307
Place the caps

close to pins
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
Connect the GND plane of pin G20

with decoupling cap of C296 pin2
GND via.
C40
1@ 0.01U_0402_16V7K~D
+1.5V_RUN
+3VRUN_TVDACB
C41
1@ 0.1U_0402_16V4Z~D
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
+1.5V_RUN
1@ 0_0402_5%~D
1 VCCA_LVDS
2
R48
0.022U_0402_16V7K~D
VCCHV0
VCCHV1
VCCHV2
+3VRUN_TVDACA
C270 1@
VCCD_TVDAC
VCCDQ_TVDAC
+1.5V_RUN
0.022U_0402_16V7K~D
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
+3VRUN_ATVBG
R47
2
1@ C14
VCCD_HMPLL0
VCCD_HMPLL1
+2.5V_RUN
Route VSSACRTDAC gnd from GMCH to

decoupling cap ground lead and then
connect to the gnd plane.
E19 VCCA_TVDACAPlace Bottom

F19
C20 VCCA_TVDACB
D20
E20 VCCA_TVDACC
F20
+2.5V_RUN
1@ 22n_0805_25V
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
1 +2.5V_CRTDAC
2@ 0_0402_5%~D
0.022U_0402_16V7K~D
VCCA_TVBG
VSSA_TVBG
+1.5V_RUN_MPLL
0.022U_0402_16V7K~D
AF2
H20 VCCA_TVBG R344 0_0402_5%~D

G20 VSSA_TVBG
2
1
Cb
C273 1@
VCCA_MPLL
Ca
+3V_TVDAC
+3VRUN_TVDACA
+1.05V_VCCP
CRTDAC: Route caps within

250mil of Alviso. Route FB
within 3" of Calistoga
0.1U_0402_16V4Z~D
VCCA_LVDS
1
2
L10 1@ BLM18PG181SN1_0603~D
C290
1@ 0.1U_0402_16V4Z~D
C289
A38
B39
+1.5V_RUN_DPLLA
+1.5V_RUN_DPLLB
+1.5V_RUN_HPLL
C274
1@ 4.7U_0603_6.3V6M~D
C434
0.47U_0402_10V4Z~D
0.22U_0402_10V4Z~D
C348
0.22U_0402_10V4Z~D
VCCA_LVDS
VSSA_LVDS
1
2@ 0_0402_5%~D
0.1U_0402_16V4Z~D
+1.5V_RUN
2
R51
0_0805_5%~D
Route +2.5V_RUN from GMCH pinG41 to

decoupling cap (C314)<200mil to the edge.
+2.5V_CRT_DAC
1@ 0_0402_5%~D
1 VCCTX_LVDS
2
R60
C43
1@ 0.01U_0402_16V7K~D
B26
C39
AF1
Cj
1@ C59
MCH_D2
MCH_AB1
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
0.1U_0402_16V4Z~D
Place the C348

close to M3
+2.5V_CRTDAC
E21
F21
G21
C30
10U_0805_4VAM~D
P O W E R
2
+1.5V_RUN_3GPLL
+2.5V_RUN
C42
0.1U_0402_16V4Z~D
C278
0.47U_0402_10V4Z~D
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2
C33
1@ 10U_0805_4VAM~D
MCH_A6
AC33
G41
H41
1+1.5VRUN_PCIE 1
R52
2
C314
R99
L13
W=30 mils
1@ C51
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
+1.5V_RUN_PCIE
0.022U_0402_16V7K~D
C47
C332
2.2U_0603_6.3V6K~D
C438
4.7U_0603_6.3V6M~D
AB41
AJ41
L41
N41
R41
V41
Y41
+2.5V_RUN
1@ 0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
C304
+2.5V_RUN
For Power measurement.

No need for RTS board
+2.5V_RUN
1
Should be placed on top
C131
10U_0805_4VAM~D
C367
220U_D2_4VM_R45~D
B30 VCCTX_LVDS
C30
A30
C115
10U_0805_4VAM~D
CRB 270uF
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
C83
220U_D2_4VM_R45~D
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76
H22
1@ 22n_0805_25V
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
1@ R361
0_0402_5%~D
2
1
2
1
2@
R374
0_0402_5%~D
+1.05V_VCCP
Should be placed in cavity

1@ MMBD4148_SOT23~D
CRT DAC Voltge Follower Circuit - 700mV
1@ MMBD4148_SOT23~D
TV DAC Voltge Follower Circuit - 700mV
Title
Calistoga(4 of 6)
Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
13
of
73
+1.05V_VCCP
+1.8V_SUS
U9G
+1.05V_VCCP
P O W E R
C184
C490
0.1U_0402_16V4Z~D
C525
0.47U_0402_10V4Z~D
C489
0.47U_0402_10V4Z~D
Place near U9.BA15
C186
Place near U9.BA23
C185
10U_0805_4VAM~D
10U_0805_4VAM~D
C528
0.47U_0402_10V4Z~D
0.1U_0402_16V4Z~D
VCCSM_LF2
VCCSM_LF1
C497
0.47U_0402_10V4Z~D
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
C531
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
+1.8V_SUS
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16
C533
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107
+1.05V_VCCP
C500
CRB 270uF
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
0.47U_0402_10V4Z~D
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
0.1U_0402_16V4Z~D
+
2
C568
220U_D2_4VM_R45~D
Place near U9.AT41 & AM41
0.47U_0402_10V4Z~D
P O W E R
VCCSM_LF4
VCCSM_LF5
C496
C548
220U_D2_4VM_R45~D
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
0.1U_0402_16V4Z~D
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99
C526
0.47U_0402_10V4Z~D
C337
1U_0603_10V4Z~D
C338
0.22U_0402_10V4Z~D
C405
10U_0805_4VAM~D
C345
10U_0805_4VAM~D
C413
0.22U_0402_10V4Z~D
C440
0.22U_0402_10V4Z~D
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
C515
0.47U_0402_10V4Z~D
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
+1.5V_RUN
U9F
Place near U9.AV1 & AJ1

A
Title
Calistoga(5 of 6)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
14
of
73
U9I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
P O W E R
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
U9J
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
P O W E R
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
Title
Calistoga(6 of 6)
Size
Rev
0.4
LA-3001
Date:
Document Number
Sheet
1
15
of
73
+3.3V_SUS
1
3
Place thermal resistor near the SODIMM For discrete design
R260
8.2K_0402_5%~D
SYMBOL(SOT23-NEW)
2
2222
+1.05V_VCCP
THERMATRIP1#
+5V_SUS
R255
C
2.2K_0402_5%~D
1
2
2
B
Q14 E
PMBT3904_SOT23~D
FAN1 Control and Tachometer
+3.3V_RUN
+5V_SUS
1
R19
2@
2.21K_0603_1%~D
R18
2@
10K_0402_5%~D
+3.3V_SUS
VCP1
10K_0402_5%~D
8.2K_0402_5%~D
R317
C233
JFAN1
22U_1206_10V4Z~D
@ RB751V_SOD323~D
@1000P_0402_50V7K~D
+1.05V_VCCP
MOLEX_53398-0371~D
2
5V_CAL_SIO# <31>
G
2N7002_SOT23~D
2@Q7
Dell COE schematic suggest populate

for discrete down design
C12
2@
2200P_0402_50V7K~D
THERMATRIP2#
R278
C
2.2K_0402_5%~D
1
2
2
B
Q20 E
PMBT3904_SOT23~D
1
D10
1
2
3
1 C235
1
2
3
C234
@ 1000P_0402_50V7K~D
+FAN1_VOUT
FAN1_TACH <30>
0.1U_0402_16V4Z~D
<7> H_THERMTRIP#
R113
R133 2@
10KB_0603_1%_TSM1A103F34D3R~D
C262
C267
0.1U_0402_16V4Z~D
<10> THERMTRIP_MCH#
May need to place thermal resistor underneath WWAN Mini Card stuff
this thermistor circuit for additional sensor in Discrete Down Designs
H_THERMDA/H_THERMDC
routing together. Trace
width / Spacing = 10 / 10 mil
Place C252 as close to the

Guardian pins as possible
+5V_SUS
+5V_SUS
R440
10KB_0603_1%_TSM1A103F34D3R~D
<7> H_THERMDA
C252
2200P_0402_50V7K~D
<7> H_THERMDC
1
1
R21
2.21K_0603_1%~D
Vset=(Tp-70/21)
<44> THERMTRIP_VGA#
C247
THERMTRIP1#
15
THERMTRIP2#
30
4
INTRUDER#
22
LDO_SET
24
LDO_OUT
LDO_OUT
25
27
LDO_IN
LDO_IN
26
28
VDD_5V
FAN_OUT
33
FAN_DAC
VGA_THERMDN_R
2
1
1@ R608 0_0402_5%~D
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
Thermal
EMC4000_C_QFN40~D
1 C255
2200P_0402_50V7K~D
SMBUS ADDRESS : 2F
VGA_THERMDP_R
2
1
1@ R609 0_0402_5%~D
<35> SNIFFER_GREEN#
<35> SNIFFER_YELLOW#
2@
For Discrete: Stuff R259,R249 and no stuff Q13,C253

For UMA: Stuff Q13 and no stuff R259,R249
<45> VGA_THERMDN
<45> VGA_THERMDP
R259
2
2200P_0402_50V7K~D
C100
@ 2200P_0402_50V7K~D
ACAV_IN <30,43>
1
10K_0402_5%~D
+RTC_CELL
C11
C17
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
C261
Voltage margining circuit for LDO output.For

Vmargin, stuff R280=31.6K and R279=1K for production
R251
1
R280 @
31.6K_0402_1%~D
@
LDO_SET
+2.5V_RUN
THERM_STP# <39>
2
@ R285
+5V_RUN

THERMTRIP_SIO <31>
+2.5V_RUN
C257
Place near the bottom SODIMM For UMA design
LDO_SET
+3V_LDOIN
10
11
19
20
32
41
Q3
PMBT3904_SOT23~D
10K_0402_5%~D
DP3
DN3
C251
R250
1
2
THERMTRIP_SIO
THERM_STP#
R279
+FAN1_VOUT
+3.3V_ALW
1K_0603_5%~D
VSET
HW_LOCK#
VSS
Place under CPU
REM_DIODE1_N
REM_DIODE1_P
36
37
DN1
DP1
10U_0805_10V4Z~D
2200P_0402_50V7K~D
2
Q13 1@
PMBT3904_SOT23~D
2
THERMTRIP3#
39
29
9
1
2
VGA_THERMDN_R/VGA_THERMDN,
To cut the stub trace
VGA_THERMDP_R/VGA_THERMDP routing for discrete M/B
together. Trace width / Spacing = 10 / 10 mil
1
16
2.5V_RUN_PWRGD <33>
REM_DIODE1_N, REM_DIODE1_P routing together.

Trace width / Spacing = 10 / 10 mil
POWER_SW#
14
R256

C250
2200P_0402_50V7K~D
R247
118K_0402_1%~D
1K_0402_5%~D
332K_0402_1%~D
2
+3V_PWROK#
THERMATRIP2#
R242
0.1U_0402_16V4Z~D
+RTC_PWR3V
THERMATRIP1#
THERMTRIP_VGA#
2
8.2K_0402_5%~D
1
R321
+3.3V_SUS
31
+3V_SUS
VSUS_PWRGD
LDO_POK
VCP1
VCP2
5V_CAL_SIO2# <31>
C259
1U_0603_10V4Z~D
+3.3V_RUN
0.27_1210_5%~D
C260 @
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 VGA_THERMDN_R
2@ 0_0402_5%~D
R249
2
1 VGA_THERMDP_R
0_0402_5%~D

Title
Thermal sensor and Fan

Size
Document Number
Rev
0.3
LA-3001P
Date:
<30,35> POWER_SW#
13
2
1K_0402_5%~D
38
3
40
2
G
1
R316
<33> ICH_PWRGD#
VCP
VCP
C16
2200P_0402_50V7K~D
0.1U_0402_16V4Z~D
DP2
DN2
C269
2N7002_SOT23~D S
Q24
+RTC_CELL
ATF_INT# <30>
<23,33> SUSPWROK
ATF_INT#
17
ATF_INT#
LDO_SHDN#_ADDR
+3VSUS_THRM
12
21
1
2
R315
1K_0402_5%~D
18
SMDATA
SMBCLK
23
2
7.5K_0402_5%~D
35
34
1
R284
+3.3V_SUS
7
8
0.1U_0402_16V4Z~D
DAT_SMB
CLK_SMB
<30> DAT_SMB
<30> CLK_SMB
U16
R320
49.9_0603_1%~D
1
2
1
C268
+3.3V_SUS
@ C253
R22
10K_0402_5%~D
Sheet
1
16
of
73
+1.8V_SUS
+1.8V_SUS
V_DDR_MCH_REF
<11> DDR_A_DQS#[0..7]
V_DDR_MCH_REF <10,18,41>
JDIMA1
DDR_A_DQS#1
DDR_A_DQS1
C214
C215
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C217
2.2U_0603_6.3V6K~D
C223
2.2U_0603_6.3V6K~D
C224
2.2U_0603_6.3V6K~D
DDR_A_D10
DDR_A_D11
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
C216
0.1U_0402_16V4Z~D
C213
0.1U_0402_16V4Z~D
C222
0.1U_0402_16V4Z~D
C221
0.1U_0402_16V4Z~D
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
<10> DDR_CKE0_DIMMA
<11> DDR_A_BS2
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<11> DDR_A_BS0
<11> DDR_A_WE#
+0.9V_DDR_VTT
<11> DDR_A_CAS#
<10> DDR_CS1_DIMMA#
<10> M_ODT1
C231
0.1U_0402_16V4Z~D
C230
0.1U_0402_16V4Z~D
C229
0.1U_0402_16V4Z~D
C226
0.1U_0402_16V4Z~D
C227
0.1U_0402_16V4Z~D
C228
0.1U_0402_16V4Z~D
C211
0.1U_0402_16V4Z~D
C210
0.1U_0402_16V4Z~D
C209
0.1U_0402_16V4Z~D
C208
0.1U_0402_16V4Z~D
C207
0.1U_0402_16V4Z~D
C206
0.1U_0402_16V4Z~D
C205
0.1U_0402_16V4Z~D
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_CKE0_DIMMA
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
+0.9V_DDR_VTT
RP6
DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
1
2
3
4
RP10
8
7
6
5
1
2
3
4
8
7
6
5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_CKE1_DIMMA
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
56_1206_8P4R_5%~D 56_1206_8P4R_5%~D
RP7
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
1
2
3
4
1
2
3
4
8
7
6
5
DDR_A_D56
DDR_A_D57
Layout Note:
Place these resistor
closely JDIMA1,all
trace length<750 mil
RP8
8
7
6
5
DDR_A_MA13
M_ODT0
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_DM7
DDR_A_D58
DDR_A_D59
56_1206_8P4R_5%~D 56_1206_8P4R_5%~D
RP5
1
R228
2 DDR_CKE0_DIMMA
56_0402_5%~D
Layout Note:
closely JDIMA1,all
trace length
Max=1.3"
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
FOX_AS0A426-MARL-7F~D
DIMMA
REVERSE
Place DIMM-A on Top
(MH=6.5mm)
DDR_A_D20
DDR_A_D21
PM_EXTTS#0_R <18>
R231
1
DDR_A_DM2
PM_EXTTS#0 <10>
0_0402_5%~D
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <10>
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0 <10>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Title
DDRII-SODIMM SLOT-A
Size
Document Number
Rev
0.4
LA-3001P
Date:
R229
2 DDR_A_BS2
56_0402_5%~D
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_A_D14
DDR_A_D15
R230
1
R227
M_CLK_DDR0
M_CLK_DDR#0
10K_0402_5%~D
56_1206_8P4R_5%~D56_1206_8P4R_5%~D
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
DDR_A_DM1
10K_0402_5%~D
DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
C212
8
7
6
5
C218
1
2
3
4
2.2U_0603_6.3V6K~D
RP9
8
7
6
5
CLK_SDATA
CLK_SCLK
0.1U_0402_16V4Z~D
M_ODT1
1
DDR_CS1_DIMMA# 2
DDR_A_CAS#
3
DDR_A_WE#
4
<6,18> CLK_SDATA
<6,18> CLK_SCLK
+3.3V_RUN
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_A_D12
DDR_A_D13
DDR_A_D8
DDR_A_D9
+1.8V_SUS
DDR_A_D6
DDR_A_D7
DDR_A_D2
DDR_A_D3
DDR_A_DM0
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D4
DDR_A_D5
C220
<11> DDR_A_MA[0..13]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C219
Layout Note:
Place near JDIMA1
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z~D
DDR_A_D0
DDR_A_D1
<11> DDR_A_DM[0..7]
<11> DDR_A_DQS[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
2.2U_0603_6.3V6K~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<11> DDR_A_D[0..63]
Sheet
1
17
of
73
+1.8V_SUS
+1.8V_SUS
V_DDR_MCH_REF
<11> DDR_B_DQS#[0..7]
JDIMB1
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
C603
C600
2.2U_0603_6.3V6K~D
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
<10> DDR_CKE2_DIMMB
<11> DDR_B_BS2
+0.9V_DDR_VTT
<11> DDR_B_CAS#
<10> DDR_CS3_DIMMB#
<10> M_ODT3
C637
0.1U_0402_16V4Z~D
C638
0.1U_0402_16V4Z~D
C639
0.1U_0402_16V4Z~D
C640
0.1U_0402_16V4Z~D
C641
0.1U_0402_16V4Z~D
C642
0.1U_0402_16V4Z~D
C643
0.1U_0402_16V4Z~D
C582
0.1U_0402_16V4Z~D
C583
0.1U_0402_16V4Z~D
C584
0.1U_0402_16V4Z~D
C585
0.1U_0402_16V4Z~D
C586
0.1U_0402_16V4Z~D
C587
0.1U_0402_16V4Z~D
DDR_B_BS2
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<11> DDR_B_BS0
<11> DDR_B_WE#
DDR_CKE2_DIMMB
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D16
DDR_B_D17
C604
0.1U_0402_16V4Z~D
C601
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
C602
2.2U_0603_6.3V6K~D
C625
0.1U_0402_16V4Z~D
C630
0.1U_0402_16V4Z~D
C624
2.2U_0603_6.3V6K~D
C629
2.2U_0603_6.3V6K~D
DDR_B_D10
DDR_B_D11
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
+0.9V_DDR_VTT
RP22
M_ODT3
1
DDR_CS3_DIMMB# 2
DDR_B_CAS#
3
DDR_B_WE#
4
RP19
8
7
6
5
1
2
3
4
8
7
6
5
DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
56_1206_8P4R_5%~D 56_1206_8P4R_5%~D
RP21
DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3
1
2
3
4
1
2
3
4
8
7
6
5
DDR_B_D56
DDR_B_D57
Layout Note:
closely JDIMB1,all
trace length<750 mil
RP18
8
7
6
5
DDR_B_BS1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4
DDR_B_DM7
DDR_B_D58
DDR_B_D59
56_1206_8P4R_5%~D 56_1206_8P4R_5%~D
RP17
DDR_B_MA6
DDR_B_MA7
DDR_B_MA11
DDR_CKE3_DIMMB
56_1206_8P4R_5%~D56_1206_8P4R_5%~D
1
R542
2 DDR_B_BS2
56_0402_5%~D
1
R541
2 DDR_CKE2_DIMMB
56_0402_5%~D
Layout Note:
closely JDIMB1,all
trace length
Max=1.3"
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_B_D12
DDR_B_D13
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
PM_EXTTS#0_R <17>
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <10>
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2
DDR_B_MA13
M_ODT2 <10>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 <10>
M_CLK_DDR#2 <10>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3.3V_RUN
R510
2
10K_0402_5%~D
R506
10K_0402_5%~D
Title
DDRII-SODIMM SLOT-B
Size
Document Number
Rev
0.4
LA-3001P
Date:
M_CLK_DDR3
M_CLK_DDR#3
DIMMB
STANDARD
Place DIMM-B on Bottom
(5.2mm)
DDR_B_DM1
FOX_AS0A426-M2SN-7F~D
C626
8
7
6
5
C621
1
2
3
4
2.2U_0603_6.3V6K~D
8
7
6
5
0.1U_0402_16V4Z~D
1
2
3
4
CLK_SDATA
CLK_SCLK
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
DDR_B_D7
DDR_B_D6
RP20
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
<6,17> CLK_SDATA
<6,17> CLK_SCLK
+3.3V_RUN
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_B_DM0
+1.8V_SUS
DDR_B_D3
DDR_B_D2
C622
DDR_B_D1
DDR_B_D4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C628
DDR_B_DQS#0
DDR_B_DQS0
Layout Note:
Place near JDIMB1
<11> DDR_B_MA[0..13]
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z~D
DDR_B_D5
DDR_B_D0
<11> DDR_B_DM[0..7]
<11> DDR_B_DQS[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
2.2U_0603_6.3V6K~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
<11> DDR_B_D[0..63]
Sheet
1
18
of
73
Overlap on D26 for pop option

+5V_RUN
LCD Power
+3.3V_RUN
+LCDVDD
+15V_SUS
@ R652
R288
1
1
2
Q17
I
G
Q15
DTC124EKA_SC59~D
LCD_A0LCD_A0+
+3.3V_RUN
+LCDVDD
+LCDVDD
0.1U_0402_16V4Z~D
C29
FPBACK_EN
1
R63
R639 1@
2
1
0_0402_5%~D
BACKLITEON
SBAT_SMBCLK
SBAT_SMBDAT
<31> FPBACK_EN
0.1U_0402_16V4Z~D
BIA_PWM_R
@ R40
1
2
0_0402_5%~D
2
0_0402_5%~D
PANEL_BKEN_R
BIA_PWM_EC
BIA_PWM_EC <30>
C258
R59
100K_0402_5%~D
SBAT_SMBCLK <30>
SBAT_SMBDAT <30>
1
+GFX_PWR_SRC
+5V_ALW
Stuff R63 for M'07 Inverter
C34
Change from 12/08 Dell GG list as

least COE schematic
LCD_TST <23>
LCD_TST
Populate R610 For Platform Without

DPST Support. No STUFF for
Discrete DPST Support Due to Back
Up Plan.
R610
Change population for discrete
10K_0402_5%~D
board as dell request, bits
2@
issue p/n:DF51426
+3.3V_RUN
LDDC_CLK_R
LDDC_DATA_R
0.1U_0603_50V4Z~D
2
G
O
ENVDD_EN
BIA_PWM for M'07 Inverter
LCD_A1LCD_A1+
C38
1 2
3
2
G
Q12
2N7002_SOT23~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C265
0_0603_5%~D
2
1
100K_0402_5%~D
LCD_A2LCD_A2+
470_0402_5%~D
1
R287
2N7002_SOT23~D
10U_1206_16V4Z~D
R289
100K_0402_5%~D
@ R646
2
100K_0402_5%~D
1
R286
20 mil
C256
LCD_ACLKLCD_ACLK+
IPEX_20330-044E-01F~D
Q21
1
SI3456DV-T1-E3_TSOP6~D
C275
G
0_0402_5%~D
USBP4+ <23>
USBP4- <23>
+CMOS_VDD
+LCDVDD
D26
6
5
2
1
1
<36>
<36>
<36>
<36>
C28
INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1
0.1U_0402_16V4Z~D
45
46
47
48
49
50
51
52
53
54
55
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TXUCLKUTTXUCLKUT+
GND1
TXUOUT2TXUOUT2+
GND2
TXUOUT1TXUOUT1+
GND3
TXUOUT0TXUOUT0+
GND4
TXLCLKOUTTXLCLKOUT+
GND5
TXLOUT2TXLOUT2+
MGND1
GND6
MGND2
TXLOUT1MGND3
TXLOUT1+
MGND4
GND7
MGND5
TXLOUT0MGND6
TXLOUT0+
MGND7
GND8
MGND8 PANEL_I2C_CLK
MGND9 PANEL_I2C_DAT
MGND10
GND9
MGND11
VEDID
GND10
LCDVDD1
LCDVDD2
PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC
GND11
FPBACK
GND12
PBAT_SMBCLK
PBAT_SMBDAT
GND13
+5V_ALWF
LAMP_START
GND14
+3.3V_RUN
+15V_SUS
JLVDS1
0.1U_0402_16V4Z~D
Dual layout for Q16
Q16
FDS4435_NL_SO8~D
+PWR_SRC
Overlap on Q16 for pop option
40mil
2
4
6
5
2
1
+GFX_PWR_SRC
C266
0.1U_0603_50V4Z~D
PWR_SRC_ON
Please put the resistors close to connector side
+GFX_PWR_SRC
1
R243
100K_0402_5%~D
1
Q64
SI3457DV-T1_TSOP6~D
8
7
6
5
1
2
3
+PWR_SRC
C254
1000P_0402_50V7K~D
40mil
PWR_SRC_ON
1@ RP14
1
2
3
4
1@ RP16
8
7
6
5
LCD_ACLKLCD_ACLK+
LCD_A2LCD_A2+
<12> LDDC_CLK
<12> LDDC_DATA
<12> BIA_PWM
<12> PANEL_BKEN
1
2
3
4
0_1206_8P4R_5%~D
1
2
3
4
8
7
6
5
LDDC_CLK_R
LDDC_DATA_R
BIA_PWM_R
PANEL_BKEN_R
SI3457DV : P CHANNAL
<30,32,33,39,40,41,50> RUN_ON
FDS4435: P CHANNAL
0_1206_8P4R_5%~D
2@ RP3
<45> LCD_ACLK-_VGA
<45> LCD_ACLK+_VGA
<45> LCD_A2-_VGA
<45> LCD_A2+_VGA
2
G
<12> LCD_ACLK-_NB
<12> LCD_ACLK+_NB
<12> LCD_A2-_NB
<12> LCD_A2+_NB
Q11
3 2N7002W-7-F_SOT323~D
R244
1
2
1
100K_0402_5%~D
For Discrete: Populting RP3,RP4,RP15,R248

For UMA: Populting RP14,RP13,RP16,R254
0_1206_8P4R_5%~D
8
7
6
5
<44> LDDC_CLK_VGA
<44> LDDC_DATA_VGA
<44> BIA_PWM_VGA
<44> PANEL_BKEN_VGA
0_1206_8P4R_5%~D
4
3
2
1
5
6
7
8
2@ RP15
1@ RP13
<12> LCD_A1-_NB
<12> LCD_A1+_NB
<12> LCD_A0-_NB
<12> LCD_A0+_NB
1
2
3
4
8
7
6
5
LCD_A1LCD_A1+
LCD_A0LCD_A0+
<12> ENVDD
<44> ENVDD_VGA
1
R254
2
R248
2 ENVDD_EN
1@
0_0402_5%~D
1
2@
0_0402_5%~D
0_1206_8P4R_5%~D
2@ RP4
A
<45> LCD_A1-_VGA
<45> LCD_A1+_VGA
<45> LCD_A0-_VGA
<45> LCD_A0+_VGA
1
2
3
4
8
7
6
5
0_1206_8P4R_5%~D
Title
LVDS Conn
Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
19
of
73
L32
0.47UH_CIL10NR47KNC_10%_0603~D
1
2
D7
@ DA204U_SOT323~D
SP_DIF_D
Place All Of These CAPS, INDUCTORS

and DIODE CLamp for < 200mils.
+5V_RUN
+3.3V_RUN
C426
1
SP_DIF_C
Place C709 near

JSVID1 pin 5
D1
D2
D3
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D
0.1U_0402_16V4Z~D
110_0603_1%~D
U19
SN74AHCT1G125GW_SC70-5~D
0.01U_0402_16V7K~D
2@ R90
2
1
SP_DIFB
220_0603_1%~D
R596
R400
SP_DIF 2
YPRPB_DET# <44>
0_0402_5%~D
R88
0_0402_5%~D
1@
C709
2
2
R91
Change as 11/22 Dell GG list
10K_0402_5%~D
C416
L29,L32,L34 change to Murata 560NH +-10% LQM18NNR56K00(SHI0156BK8L), wait CIS symbol.
Pop 75 ohm resistor for Discrete M/B
Pop 150 ohm resistor for UMA

+3.3V_RUN
POPULATE R90 WHEN COMPONENT VIDEO IS ENABLED.

3
R367, R379, R384,

R234, R236, R239
FOX_MH11777-BUR6-7F~D
SPDIF
<36> SPDIF
2
4
6
7
5
3
1
8
9
SVIDEO_Y
0.1U_0402_16V4Z~D
C379
82P_0402_50V8J~D
C381
C707
8.2P_0402_50V8J~D
D6
@ DA204U_SOT323~D
JSVID1
82P_0402_50V8J~D
L34
0.47UH_CIL10NR47KNC_10%_0603~D
1
2
TV_Y
D5
@ DA204U_SOT323~D
SVIDEO_C
SVIDEO_CVBS
C349
C706
8.2P_0402_50V8J~D
+3.3V_RUN
82P_0402_50V8J~D
82P_0402_50V8J~D
C351
R379
150_0402_1%~D
2
1
C325
C705
8.2P_0402_50V8J~D
CLOSE TO JSVID1
TV_CVBS
R384
150_0402_1%~D
2
1
82P_0402_50V8J~D
82P_0402_50V8J~D
C331
R367
150_0402_1%~D
2
1
TV_C
L29
0.47UH_CIL10NR47KNC_10%_0603~D
1
2
OE#
+5V_RUN
L16
BLM18BB600SN1D_0603~D
1
2
L17
1
2
L18
1
2
1
2
R236
150_0402_1%~D
2
1
R234
150_0402_1%~D
2
1
R239
150_0402_1%~D
2
1
2
1
1
2
2
1
2
1
+5V_SYNC
P
2
39_0402_5%~D
VSYNC_L
A
G
VSYNC
R15
39_0402_5%~D
1
OE#
HSYNC_L
U1
Y
R611
4
HSYNC_R
1
R612
1
HSYNC
OE#
1
R11
L3
BLM11A121S_0603~D
HSYNC_L2 1
2
2 VSYNC_L2 1
2
0_0402_5%~D
L4
BLM11A121S_0603~D
U2
Y
C3
0_0402_5%~D
VSYNC_R
5
6
7
8
0.1U_0402_16V4Z~D
2@ RP2
R1
2 VSYNC
1@
0_0402_5%~D
1
2@
0_0402_5%~D
0_1206_8P4R_5%~D
4
3
2
1
10K_0402_5%~D
1
R61
2
R62
0_1206_8P4R_5%~D
RP1 1@
<44> RED_VGA
<44> GRN_VGA
<44> BLU_VGA
<44> HSYNC_VGA
C246
0.01U_0402_16V7K~D
2 CLK_DDC2_R
1@
0_0402_5%~D
1
2@
0_0402_5%~D
16
17
C1
1
R13
2
R12
JVGA_VS
M_ID2#
FOX_DZ11A91-ND209-9F~D
C2
<44> VSYNC_VGA
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
JVGA_HS
B
R8
<12> VGA_VSYNC
NC_M_SEN#
R
22P_0402_50V8J~D
RED
GREEN
BLUE
HSYNC
R10
1K_0402_5%~D
1
2
22P_0402_50V8J~D
8
7
6
5
C244
<12> CLK_DDC2
@ 1K_0402_5%~D
<44> DAT_DDC2_VGA
<44> CLK_DDC2_VGA
1
2
3
4
@ 10P_0402_50V8J~D
8
7
6
5
1
R2
2
R3
2 DAT_DDC2_R
1@
0_0402_5%~D
1
2@
0_0402_5%~D
R9
<12> DAT_DDC2
0_1206_8P4R_5%~D
<12> VGA_RED
<12> VGA_GRN
<12> VGA_BLU
<12> VGA_HSYNC
@ 1K_0402_5%~D
DAT_DDC2_R
CLK_DDC2_R
2@ RP11
1
2
3
4
C242
D25
0_1206_8P4R_5%~D
<44> TV_Y_VGA
<44> TV_CVBS_VGA
<44> TV_C_VGA
R14
+5V_RUN
R4
TV_C
TV_CVBS
TV_Y
2.2K_0402_5%~D
2.2K_0402_5%~D
8
7
6
5
1@ RP12
1
2
3
4
+CRT_VCC
Please put the resistor close to connector side
<12> TV_C_NB
<12> TV_CVBS_NB
<12> TV_Y_NB
@ 10P_0402_50V8J~D
C240
1
C245
@ 10P_0402_50V8J~D
@ 22P_0402_50V8J~D
C243
@ 22P_0402_50V8J~D
C241
@ 22P_0402_50V8J~D
NOTE:
1@ is for UMA Implemetation.
2@ is for Discrete Implementation.
+CRT_VCC
R633 0_1206_5%~D
BLUE
GREEN
+3.3V_SUS
D11
RED
Title
Interval LVDS, TV_OUT and CRT connector

Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
20
of
73
+3.3V_RUN
PCI_REQ0#
2
8.2K_0402_5%~D
PCI_REQ1#
2
8.2K_0402_5%~D
PCI_REQ2#
2
8.2K_0402_5%~D
PCI_REQ3#
2
8.2K_0402_5%~D
PCI_REQ4#
2
8.2K_0402_5%~D
PCI_REQ5#
2
8.2K_0402_5%~D
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C26
A9
B19
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
<28>
<28>
<26>
<26>
+3.3V_SUS
U24A
74VHC08MTCX_NL_TSSOP14~D
PCI_PCIRST#
IN1
IN2
PCI_RST#_L
R521
IN1
IN2
CLK_PCI_ICH <6>
ICH_PME# <31>
PCIRST_PCCARD# <28>
33_0402_5%~D
+3.3V_SUS
PCI_PLTRST#
PCIRST_LOM# <26>
33_0402_5%~D
PCI_DEVSEL# <26,28>
PCI_PERR# <26,28>
PCI_SERR# <26,28>
PCI_STOP# <26,28>
PCI_TRDY# <26,28>
PCI_FRAME# <26,28>
OUT
7
PCI_IRDY# <26,28>
PCI_PAR <26,28>
R514
<26,28>
<26,28>
<26,28>
<26,28>
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
C605
0.1U_0402_16V4Z~D
14
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
U24B
14
1
R195
1
R188
1
R179
1
R177
1
R194
1
R196
B15
C12
D12
C15
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
R525
ICH_GPIO2_PIRQE#
2
8.2K_0402_5%~D
ICH_GPIO3_PIRQF#
2
8.2K_0402_5%~D
ICH_GPIO4_PIRQG#
2
8.2K_0402_5%~D
ICH_GPIO5_PIRQH#
2
8.2K_0402_5%~D
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PCI_REQ1#
OUT
PLTRST1#_L
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
<26> PCI_PIRQB#
<28> PCI_PIRQC#
<28> PCI_PIRQD#
A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9
PIRQA#
PIRQB#
PIRQC#
PIRQD#
I/F
GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#
MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
G8
F7
F8
G7
R526
AE9
AG8
AH8
F21
AH20
MCH_ICH_SYNC#
IN1
IN2
U24C
R495
OUT
PLTRST2#_L
R494
2
12
IN2
PLTRST_EXP# <36>
U24D
14
IN1
33_0402_5%~D
+3.3V_SUS
13
PLTRST_EC# <30>
33_0402_5%~D
MCH_ICH_SYNC# <10>
ICH7M A0_BGA652~D
PLTRST_ICH# <23>
33_0402_5%~D
+3.3V_SUS
10
PLTRST_MCH# <10>
33_0402_5%~D
Interrupt
14
1
R192
1
R189
1
R193
1
R191
PCI_REQ0#
PCI_PIRQA#
2
8.2K_0402_5%~D
PCI_PIRQB#
2
8.2K_0402_5%~D
PCI_PIRQC#
2
8.2K_0402_5%~D
PCI_PIRQD#
2
8.2K_0402_5%~D
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
OUT
R504
PLTRST3#_L
11
PLTRST3# <29>
33_0402_5%~D
1
R198
1
R183
1
R199
1
R197
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#
PCI
+3.3V_RUN
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
PCI_PLOCK#
2
8.2K_0402_5%~D
PCI _IRDY#
2
8.2K_0402_5%~D
PCI_SERR#
2
8.2K_0402_5%~D
PCI_PERR#
2
8.2K_0402_5%~D
U25B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
1
R190
1
R200
1
R181
1
R182
<26,28> PCI_AD[0..31]
PCI_DEVSEL#
2
8.2K_0402_5%~D
PCI_STOP#
2
8.2K_0402_5%~D
PCI_TRDY#
2
8.2K_0402_5%~D
PCI_FRAME#
2
8.2K_0402_5%~D
1
R180
1
R175
1
R178
1
R176
PCI_GNT5#
PCI_GNT4#
@ C138
1
2
0.1U_0402_16V4Z~D
Rb
R552
R535
1K_0402_5%~D
@ 1K_0402_5%~D
Ra
+COINCELL
R95
1K_0402_5%~D
ICH Boot BIOS select
R544
GNT4#
Rb
10_0402_5%~D
CLK_ICH_TERM 1
GNT5#
Ra
1
2
+COINCELL 1
2
CLK_PCI_ICH
COINCELL_R 2
+3.3V_RTC_LDO
JCOIN1
+COINCELL
Place closely pin U10.A9
D8
BAT54C-7-F_SOT23~D
MOLEX_53398-0290~D
LPC
11
unstuff
unstuff
PCI
10
unstuff
stuff
+RTC_CELL
SPI
01
stuff
C632
unstuff
8.2P_0402_50V8J~D
C148
1U_0603_10V4Z~D
Title
ICH7(1/4)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
21
of
73
C690
12P_0402_50V8J~D
2
1
1
3
R582
1
2
20K_0402_5%~D
+RTC_CELL
INTRUDER#
2ICH_INTVRMEN
332K_0402_1%~D
10K_0402_5%~D
R625
<36> ICH_AZ_MDC_RST#
<36> ICH_AZ_CODEC_SDIN0
<36> ICH_AZ_MDC_SDIN1
0_0402_5%~D
D
SATA_ACT#
Q58
SATA_ACT#_R
SATA_ACT#_R <35>
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
C692
U5
V4
T5
LAN_RXD0
LAN_RXD1
LAN_RXD2
1U_0603_10V4Z~D
U7
V6
V7
1
R549
<36> ICH_AZ_MDC_SDOUT
ICH_AZ_SDOUT_R
2
33_0402_5%~D
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LDRQ0#
LDRQ1# / GPIO23
AC3
AA5
LPC_LDRQ0#
LPC_LDRQ1#
LFRAME#
AB3
LPC_LFRAME#
A20GATE
A20M#
AE22
AH28
SIO_A20GATE
H_A20M#
CPUSLP#
AG27
H_CPUSLP_R#
TP1 / DPRSTP#
TP2 / DPSLP#
AF24
AH25
H_DPRSTP_R#
T2
T3
T1
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
SATA_ACT#
AG24
H_PW RGOOD
AG22
AG21
AF22
AF25
H_IGNNE#
RCIN#
AG23
SIO_RCIN#
SMI#
NMI
AF23
AH24
H_SMI#
H_NMI
STPCLK#
AH22
H_STPCLK#
THERMTRIP#
AF26
THRMTRIP_ICH#
DA0
DA1
DA2
AH17
AE17
AF17
IDE_DA0
IDE_DA1
IDE_DA2
DCS1#
DCS3#
AE16
AD16
ACZ_SDOUT
<36> SATA_RX2<36> SATA_RX2+
<6> CLK_PCIE_SATA#
<6> CLK_PCIE_SATA
+3.3V_RUN
1
R536
R534
2
SATALED#
AF3
AE3
AG2
AH2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA_RX2SATA_RX2+
SATA_ITX_DRX_N2
SATA_ITX_DRX_P2
AF7
AE7
AG6
AH6
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
CLK_PCIE_SATA#
CLK_PCIE_SATA
AF1
AE1
SATA_CLKN
SATA_CLKP
2
24.9_0402_1%~D
AH10
AG10
SATARBIASN
SATARBIASP
AG16
AH16
AF16
AH15
AF15
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
Within 500 mils
IDE_IRQ
8.2K_0402_5%~D
<36>
<36>
<36>
<36>
<36>
IDE_ DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
2
R502
2
R522
IGNNE#
INIT3_3V#
INIT#
INTR
SATA
SATA_RX0SATA_RX0+
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
NOTE: SNIFFER_LED_OFF# is
Push-Pull from the MEC5004
AF18
LPC_LFRAME# <30>
AG26
FERR#
IDE
<30>
<30>
<30>
<30>
SIO_A20GATE <30>
H_A20M# <7>
GPIO49 / CPUPWRGD
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
H_DPSLP#
H_FERR#
LAN_TXD0
LAN_TXD1
LAN_TXD2
R5
T4
AA6
AB5
AC4
Y6
BSS138W-7-F_SOT323~D
<30,35> SNIFFER_LED_OFF#
INTVRMEN
INTRUDER#
LAN_RSTSYNC
U1
R6
LAD0
LAD1
LAD2
LAD3
AC-97/AZALIA
@
1
W4
Y5
LAN_CLK
C698
27P_0402_50V8J~D
R590
2
1
33_0402_5%~D
ICH_AZ_BITCLK_R
1
2
ICH_AZ_SYNC_R
1
2
R537
33_0402_5%~D
ICH_AZ_RST_R#
1
2
R547
33_0402_5%~D
ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1
<36> ICH_AZ_MDC_BITCLK
<36> ICH_AZ_MDC_SYNC
RTCRST#
V3
SATA_ACT#
AA3
U3
R530
2
RTXC1
RTCX2
W1
Y1
Y2
W3
CMOS_CLR1 SHORT PADS~D
+3.3V_RUN
AB1
AB2
LAN
ICH_RTCX2
2
0_0402_5%~D
ICH_RTCRST#
1
R583
INTRUDER#
U25A
R592
1
R591
1M_0402_5%~D
10M_0402_5%~D
RTC
C701
12P_0402_50V8J~D
2
1
LPC
Y5
32.768K_12.5PF_Q13MC30610003~D
R595
ICH_RTCX1
Package
9.6X4.06 mm
+RTC_CELL
D
CPU
H_CPUSLP#
1
@ 0_0402_5%~D
H_DPRSTP#
1
0_0402_5%~D
H_CPUSLP# <7,10>
H_DPRSTP# <7,42>
H_DPRSTP# daisy
ICH7-M --> Yonah --> IMVP6(ADP3207)
H_DPSLP# <7>
H_FERR# <7>
H_PWRGOOD <7>
H_IGNNE# <7>
H_INIT#
H_INTR
+3.3V_RUN
H_INIT# <7>
H_INTR <7>
R491
IDE_DCS1#
IDE_DCS3#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
DDREQ
AE15
IDE_DDREQ
+1.05V_VCCP
R492
SIO_RCIN#
H_STPCLK# <7>
1
R515
10K_0402_5%~D
H_SMI# <7>
H_NMI <7>
10K_0402_5%~D
2
56_0402_5%~D
1
IDE_DA0 <36>
IDE_DA1 <36>
IDE_DA2 <36>
IDE_DCS1# <36>
IDE_DCS3# <36>
IDE_DD[0..15]
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
SIO_A20GATE
SIO_RCIN# <30>
+1.05V_VCCP
C609
@0.1U_0402_16V4Z~D
R503
H_FERR#
56_0402_5%~D
IDE_DD[0..15] <36>
IDE_DDREQ <36>
ICH7M A0_BGA652~D
Close to ICH7
<36> ICH_AZ_CODEC_SDOUT
1
R550
2 ICH_AZ_SDOUT_R
33_0402_5%~D
<36> ICH_AZ_CODEC_SYNC
1
R538
2 ICH_AZ_SYNC_R
33_0402_5%~D
1
R548
2 ICH_AZ_RST_R#
33_0402_5%~D
Place near ICH7 side.
<36> ICH_AZ_CODEC_RST#
C703
A
27P_0402_50V8J~D
<36> SATA_TX0+
<36> SATA_TX2-
R594
1
<36> ICH_AZ_CODEC_BITCLK
<36> SATA_TX0-
ICH_AZ_BITCLK_R
<36> SATA_TX2+
2
1
C680 3900P_0402_50V7K~D
2
1
C683 3900P_0402_50V7K~D
SATA_ITX_DRX_N0
2
1
@ C661 3900P_0402_50V7K~D
2
1
@ C659 3900P_0402_50V7K~D
SATA_ITX_DRX_N2
SATA_ITX_DRX_P0
SATA_ITX_DRX_P2
33_0402_5%~D
A
Title
ICH7(2/4)
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
22
of
73
+3.3V_RUN
+3.3V_SUS
1
2
2.2K_0402_5%~D
2 I CH_RI#
8.2K_0402_5%~D
SPKR
1
R496
+3.3V_SUS
R488
@
10_0402_5%~D
<36> SPKR
ITP_DBRESET#
1
R485
2 LAMP_STAT#
10K_0402_5%~D
PM_BMBUSY#
<10> PM_BMBUSY#
AB18
SMBALERT#
+3.3V_SUS
IDE_RST_MOD
<36> IDE_RST_MOD
1
R483
2 SIO_EXT_SMI#
10K_0402_5%~D
1
R484
2 SIO_EXT_SCI#
10K_0402_5%~D
1
R493
<26,28,30> CLKRUN#
<25> BT_RADIO_DIS#
1
R524
1
R531
2 ICH_BATLOW#
8.2K_0402_5%~D
1
R532
2 ICH_PCIE_WAKE#
680_0402_5%~D
GPIO26
B21
E23
GPIO27
GPIO28
CLKRUN#
AG18
GPIO32 / CLKRUN#
BT_RADIO_DIS#
AC19
U2
GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#
IMVP_PWRGD
<33,42> IMVP_PWRGD
2 SMBALERT#
10K_0402_5%~D
GPIO18 / STPPCI#
GPIO20 / STPCPU#
A21
ICH_PCIE_WAKE#
F20
IRQ_SERIRQ
AH21
SIO_THRM#
AF20
<31> ICH_PCIE_WAKE#
<28,30> IRQ_SERIRQ
<30> SIO_THRM#
2 LINKALERT#
10K_0402_5%~D
AC1
B2
CLK_ICH_14M
CLK_ICH_48M
SUSCLK
C20
ICH_SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
B24
D23
F22
SIO_SLP_S3#
PWROK
AA4
ICH_PWRGD
AD22
VRMPWRGD
GPIO
GPIO6
GPIO7
GPIO8
<30> SIO_EXT_SMI#
GPIO16 / DPRSLPVR
TP0 / BATLOW#
AC22
DPRSLPVR
ICH_BATLOW#
SIO_SLP_S5# <30>
ICH_PWRGD <10,33>
DPRSLPVR <10,42>
PWRBTN#
C23
SIO_PWRBTN#
LAN_RST#
C19
PLTRST_ICH#
RSMRST#
Y4
SUSPWROK
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
SATACLKREQ#/GPIO35
GPIO38
GPIO39
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
SUSPWROK <16,33>
R523
<29> PCIE_TX1+
<29> PCIE_RX2<29> PCIE_RX2+
<29> PCIE_TX2-
C590 1
2 0.1U_0402_16V4Z~D
C589 1
2 0.1U_0402_16V4Z~D
C591 1
2 0.1U_0402_16V4Z~D
C592 1
2 0.1U_0402_16V4Z~D
PCIE_RX1F26
PCIE_RX1+
F25
PCIE_ITX_WWANRX_N1 E28
PCIE_ITX_WWANRX_P1 E27
PCIE_RX2PCIE_RX2+
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
2 0.1U_0402_16V4Z~D
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
R586
47_0402_5%~D
1
2
2
1
R642
47_0402_5%~D
1
2
R560 47_0402_5%~D
<25> USB_OC0_1#
+3.3V_SUS
RP23
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC2#
A
4
3
2
1
5
6
7
8
<25> USB_OC6_7#
10K_1206_8P4R_5%~D
USB_OC0_1#
1
R588
2
10K_0402_5%~D
USB_OC6_7#
1
R570
2
10K_0402_5%~D
10K_0402_5%~D
R562
2
<30> ICH_EC_SPI_DO
<30> ICH_EC_SPI_DIN
ICH_EC_SPI_CLK
+3.3V_SUS
USB_OC0_1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6_7#
PERn1
PERp1
PETn1
PETp1
H26
H25
G28
G27
PERn2
PERp2
PETn2
PETp2
K26
K25
J28
J27
PERn3
PERp3
PETn3
PETp3
M26
M25
L28
L27
PERn4
PERp4
PETn4
PETp4
P26
P25
N28
N27
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
PERn6
PERp6
PETn6
PETp6
R2
P6
P1
SPI_CLK
SPI_CS#
SPI_ARB
P5
P2
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31
SPI
<30> ICH_EC_SPI_CLK
<30> SPI_CS#
+3.3V_SUS
10K_0402_5%~D
+3.3V_SUS
R585
C593 1
<36> PCIE_TX4+
PCIE_RX4PCIE_RX4+
PCIE_ITX_EPRX_N4
PCIE_ITX_EPRX_P4
2 0.1U_0402_16V4Z~D
C588 1
R561

<36> PCIE_TX4-
Express Card--->
10K_0402_5%~D
CLK_ICH_48M
R539
1
R584
10_0402_5%~D
HDDC_EN# <31,36>
MODC_EN# <31,36>
4.7P_0402_50V8C~D
WWAN_RADIO_DIS# <29>
Bits issue DF49798
USB
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V26
V25
U28
U27
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y26
Y25
W28
W27
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA28
AA27
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD25
AD24
AC28
AC27
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
DMI_CLKN
DMI_CLKP
AE28
AE27
CLK_PCIE_ICH#
CLK_PCIE_ICH
C25
D25
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBRBIAS#
USBRBIAS
D2
D1
USBRBIAS
DMI_ZCOMP
DMI_IRCOMP
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
<10>
<10>
<10>
<10>
Within 500 mils
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
R505 24.9_0402_1%~D
1
2
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
<25>
<25>
<25>
<25>
<25>
<25>
<36>
<36>
<19>
<19>
<29>
<29>
<25>
<25>
<25>
<25>
+1.5V_RUN
----->Right Port
----->Right Port
----->Blue Tooth
----->Express Card
----->CCD Camera
----->WWAN
----->Left Port
----->Left Port
R587 22.6_0402_1%~D
1
2
Within 500 mils
ICH7M A0_BGA652~D
Title
ICH7(3/4)
Size
Document Number
Rev
0.4
LA-3001P
Date:
C700
U25D
PCI-EXPRESS
<29> PCIE_TX2+
100K_0402_5%~D
Place closely pin ICH7.B2
R644
DIRECT MEDIA INTERFACE
Mini Card 2-(WLAN) -->
10K_0402_5%~D
SATA_CLKREQ#
SATA_CLKREQ# <6>
PLTRST_DELAY#
PLTRST_DELAY# <44>
WWAN_RADIO_DIS#
10K_0402_5%~D
DPRSLPVR
@ 4.7P_0402_50V8C~D
SIO_EXT_SCI# <30>
@R635 0_0402_5%~D
HDDC_EN#
1
2
MODC_EN#
1
2
GPIO24 @R636 0_0402_5%~D
(PCI Express Wake Event)

<29> PCIE_TX1-
C702
R554
1
PLTRST_ICH# <21>
SIO_EXT_SCI#
PLTRST_DELAY#
Mini Card 1-(WWAN) -->
SIO_PWRBTN# <30>
ICH7M A0_BGA652~D
close to SB (ICH7-M)
@ 10_0402_5%~D
SIO_SLP_S3# <30>
SIO_SLP_S5#
C21
R593
CLK_ICH_14M <6>
CLK_ICH_48M <6>
10K_0402_5%~D
WAKE#
SERIRQ
THRM#
R600 0_0402_5%~D
1
2 SIO_EXT_WAKE_R# AC21
LAMP_STAT#
AC18
SIO_EXT_SMI#
E21
<30> SIO_EXT_WAKE#
CLK14
CLK48
GPIO11 / SMBALERT#
AC20
AF21
LCD_TST
<19> LCD_TST
GPIO0 / BM_BUSY#
B23
H_STP_PCI#
H_STP_CPU#
<6> H_STP_PCI#
<6> H_STP_CPU#
No Stuff for M'07
SPKR
SUS_STAT#
SYS_RST#
GPIO
2 WWAN_RADIO_DIS#
10K_0402_5%~D
RI#
A19
A27
A22
SYS
<7,30> ITP_DBRESET#
1
R487
A28
CLK_ICH_14M
1
BT_RADIO_DIS#
2
10K_0402_5%~D
Place closely pin ICH7.AC1
AF19
AH18
AH19
AE19
1
R486
GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP
2
8.2K_0402_5%~D
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
SATA
GPIO
CLKRUN#
1
R477
C22
B22
A26
B25
A25
Clocks
U25C
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
POWER MGT
10K_0402_5%~D
1
IRQ_SERIRQ
2
10K_0402_5%~D
R528
2.2K_0402_5%~D
SMB
1
R476
1
R511
R512
10K_0402_5%~D
R527
2
SIO_THRM#
2
8.2K_0402_5%~D @
R529
1
R475
8.2K_0402_5%~D
+3.3V_SUS
+3.3V_RUN
Sheet
1
23
of
73
+1.05V_VCCP
U25E
U25F
C596
D16
RB751V_SOD323~D
ICH_V5REF_RUN
100_0402_5%~D
D18
C658
0.1U_0402_16V4Z~D
C595
0.1U_0402_16V4Z~D
+1.5V_DMIPLL
L50
BLM11A601S_0603~D
+1.5V_DMIPLL
1
2
+1.5V_RUN
R499
2+1.5V_DMIPLL_L
+1.5V_RUN
C673
+1.5V_RUN
0.1U_0402_16V4Z~D
R563
0.5_0805_1%~D
+VCCSATAPLL
+VCCSATAPLL
+3.3V_RUN
C679
C677
0.1U_0402_16V4Z~D
10U_0805_4VAM~D
L53
10U_LB2012T100MR_20%_0805~D
2+VCCSATAPLL_L 1
2
C633
0.1U_0402_16V4Z~D
+1.5V_RUN
C644
1U_0603_10V4Z~D
+3.3V_SUS
C694
0.1U_0402_16V4Z~D
+1.5V_RUN
0.1U_0402_16V4Z~D
AG28
VccDMIPLL
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
AD2
VccSATAPLL
AH11
Vcc3_3[2]
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
E3
VccSus3_3[19]
C1
VccUSBPLL
AA2
Y7
C693
+3.3V_SUS
C687
Vcc3_3[1]
V5
V1
W2
W7
VccSus1_05/VccLAN1_05[1]
VccRTC
W5
VccSus3_3[1]
P7
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
A24
C24
D19
D22
G19
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
Vcc1_5_A[19]
Vcc1_5_A[20]
AB17
AC17
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
T7
F17
G17
Vcc1_5_A[24]
Vcc1_5_A[25]
AB8
AC8
C616
C28
G20
VccSus1_05[2]
VccSus1_05[3]
A1
H6
H7
J6
J7
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
0.1U_0402_16V4Z~D
+RTC_CELL
+3.3V_SUS
C689
0.1U_0402_16V4Z~D
C611
C699
0.1U_0402_16V4Z~D
C615
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_SUS
C696
0.1U_0402_16V4Z~D
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
K7
VccSus1_05[1]
C688
0.1U_0402_16V4Z~D
+3.3V_RUN
C695
0.1U_0402_16V4Z~D
B27
C580
C599
10U_0805_4VAM~D
0.01U_0402_16V7K~D
0.5_0805_1%~D
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
+3.3V_RUN
C623
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
0.1U_0402_16V4Z~D
C678
+3.3V_RUN
ICH_V5REF_SUS
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
0.1U_0402_16V4Z~D
C618
RB751V_SOD323~D
AE23
AE26
AH26
+1.05V_VCCP
+3.3V_SUS
0.1U_0402_16V4Z~D
10_0402_5%~D
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
+3.3V_RUN
C606
R557
R7
0.1U_0402_16V4Z~D
C598
+3.3V_SUS
VccSus3_3/VccSusHDA
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
Vcc3_3 / VccHDA
U6
C607
+5V_SUS
C617
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
1
1
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
C597
R533
0.1U_0402_16V4Z~D
+3.3V_RUN
C594
2
+5V_RUN
0.1U_0402_16V4Z~D
C581
220U_D2_4VM_R45~D
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
V5REF_Sus
330U_D2E_2.5VM_R9~D
+1.5VRUN_L
1
2
V5REF[2]
F6
C614
C612
L49
AD17
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
C613
ICH_V5REF_SUS
V5REF[1]
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
0.1U_0402_16V4Z~D
+1.5VRUN_L
+1.5V_RUN
D
G10
1U_0603_10V4Z~D
ICH_V5REF_RUN
C635
0.1U_0402_16V4Z~D
+1.5V_RUN
C697
0.1U_0402_16V4Z~D
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
ICH7M A0_BGA652~D
ICH7M A0_BGA652~D
0.1U_0402_16V4Z~D
Title
ICH7(4/4)
Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
24
of
73
USB PORT#
+USB_R_PWR
10U_1206_16V4Z~D
@
C27
0.1U_0402_16V4Z~D
C35
1
JUSB1
2
U7
1
2
3
4
USB_BACK_EN#
<31> USB_BACK_EN#
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
USB_OC0_1#
8
7
6
5
USB_OC0_1# <23>
TPS2062DR_SO8~D
C22
0.1U_0402_16V4Z~D
+5V_SUS
C13
150U_D_6.3VM_R55~D
C77
0.1U_0402_16V4Z~D
C73
150U_D_6.3VM_R55~D
+USB_R_PWR
1
+
2
USBP0_DUSBP0_D+
A1
A2
A3
A4
A_VCC
A_DA_D+
A_GND
USBP1_DUSBP1_D+
B1
B2
B3
B4
B_VCC
B_DB_D+
B_GND
9
10
11
12
G1
G2
G3
G4
FOX_UB1112H-8Z4-HT~D
DESTINATION
Blue Tooth
EXPRESS CARD
CCD Camera
ECE5011 HUB
No Stuff
<23> USBP0+
@ L27
DLW21SN900SQ2_0805~D
1 1
2 2
USBP0_D+
<23> USBP0-
USBP0_D-
<23> USBP1+
@ L28
1 1
2 2
USBP1_D+
<23> USBP1-
USBP1_D-
R3460_0402_5%~D
2
1
R3590_0402_5%~D
2
1
R3520_0402_5%~D
2
1
R3630_0402_5%~D
2
1
Place U5, U6 as close as USB connector.

+USB_R_PWR
U6
USBP0_D+
USBP1_D-
D1+
D2+
GND
VCC
D1-
D2-
IP4220CZ6_SO6~D
+USB_L_PWR
@
C277
0.1U_0402_16V4Z~D
C272
2
B
10U_1206_16V4Z~D
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USB_OC6_7#
USB_OC6_7# <23>
C26
0.1U_0402_16V4Z~D
+
2
C64
150U_D_6.3VM_R55~D
<31> USB_SIDE_EN#
USB_SIDE_EN#
TPS2062DR_SO8~D
C48
0.1U_0402_16V4Z~D
U17
1
2
3
4
C37
150U_D_6.3VM_R55~D
+USB_L_PWR
+5V_SUS
U5
1
+
2
USBP6_D+
1
JUSB2
2
USBP6_DUSBP6_D+
A1
A2
A3
A4
A_VCC
A_DA_D+
A_GND
USBP7_DUSBP7_D+
B1
B2
B3
B4
B_VCC
B_DB_D+
B_GND
9
10
11
12
G1
G2
G3
G4
USBP7_D-
USBP0_D+USB_L_PWR
D1+
D2+
GND
VCC
D1-
D2-
USBP7_D+
USBP6_D-
IP4220CZ6_SO6~D
FOX_UB1112H-8Z4-HT~D
+3.3V_RUN
B
No Stuff
<23> USBP6+
@ L19
1 1
2 2
USBP6_D+
<23> USBP6-
USBP6_D-
USBP1_D+
C5
<23> USBP7+
@ L24
1 1
2 2
USBP7_D+
<23> USBP7-
USBP7_D-
0.1U_0402_16V4Z~D
2
JBT1
R3190_0402_5%~D
2
1
R3310_0402_5%~D
2
1
R3140_0402_5%~D
2
1
R3240_0402_5%~D
2
1
1
2
3
4
5
6
7
8
9
10
<29,35> BT_ACTIVE
<29> COEX2_WLAN_ACTIVE
<23> BT_RADIO_DIS#
<29> COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
BT_RADIO_DIS#
COEX1_BT_ACTIVE
COEX3
33P_0402_50V8J~D
C4
@ 100P_0402_50V8J~D
C6
Place near JBT.
R17
10K_0402_5%~D
2
1
<23> USBP2<23> USBP2+
1
2
3
4
5 GND
6 GND
7
8
9
10
11
12
JST_BM10B-SRSS-TB1(LF)(SN)~D
Title
USB 2.0 PORT

Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
25
of
73
Current Consumption: Max 1.5A
+3.3V_SRC
Q5
+3.3V_LAN
+3.3V_SUS
SI3456DV-T1-E3_TSOP6~D
S
6
5
2
1
L14
R112
4
1
2
0_0805_5%~D
@
2
+1.8V_LOM
+3.3V_LAN
+1.8V_LOM
R68
R67
R65
R66
1
1
1
1
2
2
2
2
49.9_0603_1%~D
49.9_0603_1%~D
49.9_0603_1%~D
49.9_0603_1%~D
C46
C44
2
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
Place close to LAN chip (U10)
+3.3V_LAN
+3.3V_LAN
<32> ENAB_3VLAN
LAN_TX+
LAN_TXLAN_RX+
LAN_RX-
R65-68 should be rated at least 1/16W
+3.3V_LAN
SPROM_DOUT
C85
1000P_0402_50V7K~D
None
1Kb
10K Pullup
SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DIN
98
95
101
99
EXT_POR_L
89
JTAG_TDO
JTAG_TCK
JTAG_TDI
JTAG_TRST_L
JTAG_TMS
83
80
82
73
81
LOM_LOW_PWR# <31>
Place R381,C352,C493
close to pin69
1
2
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
+3.3V_LAN
Replace with BLM11A601S if needed to meet

noise guideline for EPHY_BIAS_AVDD pin
B
R381
0_0603_5%~D
C76
0.1U_0402_16V4Z~D
C143
0.1U_0402_16V4Z~D
C139
0.1U_0402_16V4Z~D
C69
0.1U_0402_16V4Z~D
C67
4.7U_0805_10V4Z~D
Place C66,C78 close to pin64
Place close
to pin 57
EPHY_PLLVDD
C66
2
R114
33_0402_5%~D
2.2U_0805_10V6K~D
place Decoupling as closed physically possible to each power pins

1
C78
1000P_0402_50V7K~D
C171
22P_0402_50V8J~D

Title
BROADCOM 4401L LAN

Size
Document Number
Rev
0.4
LA-3001P
Date:
+1.8V_LOM
BCM4401KQL_LQFP128~D
CLK_PCI_LOM
EPHY_BIAS_AVDD
1
Place closely pin 118
SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DI
C133
0.1U_0402_16V4Z~D
C99
27P_0402_50V8J~D
C97
27P_0402_50V8J~D
+3.3V_LAN
1K_0402_5%~D
25MHZ_20PF_1BG25000CK1A~D
1
2
XTAL_AVDD
XTAL_AVSS
114
25
56
VESD1
VESD2
VESD3
91
92
96
97
REG_AVDD1
REG_AVDD2
REG_VOUT1
REG_VOUT2
106
79
94
VDDIO0
VDDIO1
VDDIO2
115
125
19
30
40
52
7
VDDBUS1
VDDBUS2
VDDBUS3
VDDBUS4
VDDBUS5
VDDBUS6
VDDBUS7
112
17
44
VDDCORE1
VDDCORE2
VDDCORE3
65
68
90
93
12
46
111
100
84
2
24
74
13
47
120
35
105
1
2
EECLK_PXE
EEDATA_PXE
U12:ORG NC is 16x64.
+3.3V_LAN
R412
VAUX_AVAIL
C118
0.1U_0402_16V4Z~D
2 XO
XTAL_IN
XTAL_OUT
87
85
86
C86
0.1U_0402_16V4Z~D
PCI_CLKRUN_L
67
66
806_0402_1%~D
R92
Y2
XI
22
VAUX_AVAIL
GPIO0
GPIO1
8
7
6
5
AT93C46-10SU-2.7_SO8~D
LAN_TX+ <27>
LAN_TX- <27>
LAN_RX+ <27>
LAN_RX- <27>
104
103
108
102
109
110
107
NC0
NC2
NC3
NC4
NC5
NC6
NC7
VCC
NC
ORG
GND
C155
0.1U_0402_16V4Z~D
<23,28,30> CLKRUN#
1.27K_0402_1%~D
LAN_TX+
LAN_TXLAN_RX+
LAN_RX-
CS
SK
DI
DO
C156
0.1U_0402_16V4Z~D
100_0402_5%~D
62
61
59
60
1
2
3
4
C144
0.1U_0402_16V4Z~D
LAN_AD16
EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN
1 R387
U12
SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DI
C122
0.1U_0402_16V4Z~D
71
72
88
1
2
BLM11A601S_0603~D
C70
4.7U_0805_10V4Z~D
EPHY_VREF
EPHY_RDAC
EPHY_TESTMODE
EPHY_PLLVDD
+1.8V_LOM
C75
0.1U_0402_16V4Z~D
PCI_AD16
64
63
+3.3V_LAN
L11
C121
0.1U_0402_16V4Z~D
R101
EPHY_PLLVDD
EPHY_PLLGND
+1.8V_LOM
EPHY_BIAS_AVDD
C493
0.1U_0402_16V4Z~D
PCI_RST_L
PCI_CLK
PCI_GNT_L
PCI_REQ_L
PCI_PME_L
PCI_IDSEL
69
70
C160
0.1U_0402_16V4Z~D
117
118
119
121
113
5
EPHY_BIAS_AVDD
EPHY_BIAS_AVSS
C162
0.1U_0402_16V4Z~D
<21> PCIRST_LOM#
<6> CLK_PCI_LOM
<21> PCI_GNT3#
<21> PCI_REQ3#
<28,31> SYS_PME#
58
57
C352
0.1U_0402_16V4Z~D
PCI_CBE3_L
PCI_CBE2_L
PCI_CBE1_L
PCI_CBE0_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_DEVSEL_L
PCI_STOP_L
PCI_PERR_L
PCI_SERR_L
PCI_PAR
PCI_INT_L
BCM 4401KQL
EPHY_AGND
EPHY_AVDD
LINK_LED10# <27>
LINK_LED100# <27>
ACTLED# <27>
C72
0.1U_0402_16V4Z~D
4
18
32
43
20
21
23
26
27
28
29
31
116
Broadcom
75
76
77
78
10K Pullup
C128
0.1U_0402_16V4Z~D
<21,28> PCI_C_BE3#
<21,28> PCI_C_BE2#
<21,28> PCI_C_BE1#
<21,28> PCI_C_BE0#
<21,28> PCI_FRAME#
<21,28> PCI_IRDY#
<21,28> PCI_TRDY#
<21,28> PCI_DEVSEL#
<21,28> PCI_STOP#
<21,28> PCI_PERR#
<21,28> PCI_SERR#
<21,28> PCI_PAR
<21> PCI_PIRQB#
PCI_AD[0..31]
<21,28> PCI_AD[0..31]
LED0_L
LED1_L
LED2_L
LED3_L
None
None
16Kb
C152
4.7U_0805_10V4Z~D
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
LINK_LED10#
LINK_LED100#
ACTLED#
R402
10K_0402_5%~D
122
123
124
126
127
128
1
3
6
8
9
10
11
14
15
16
33
34
36
37
38
39
41
42
45
48
49
50
51
53
54
55
R399
10K_0402_5%~D
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
R389
10K_0402_5%~D
U10
None
+3.3V_LAN
4Kb
SPROM_CLK
Sheet
1
26
of
73
+3.3V_LAN
JW IRE1
1 1
2 2
+3.3V_LAN
JLOM1
RJ_TIP
R J_RING
13
YELLOW
14
COMMON0
11
TRD1P
12
TRCT1
LAN_TX-
10
TRD1N
LAN_RX+
TRD2P
TRCT2
TRD2N
NC
NC
NC
NC
NC
NC
MOLEX_53398-0290~D
C
<26> LAN_TX+
Layout Note:Place close to the J_RJ1
<26> LAN_TX<26> LAN_RX+
RJ_TIP
R J_RING
J_RJ1
RJ_TIP_1
1
RJ_RING_1 2
@
C238
300P_1808_3KV8K~D
C236
300P_1808_3KV8K~D
L2
FBM-L11-160808-301LMA20T_2P~D
1
2
1
2
L1
FBM-L11-160808-301LMA20T_2P~D
@
LAN_TX+
3
4
<26> LAN_RX-
1
2
LAN_RX-
GND1
GND2
TYCO_1566598-1~D
ACTLED#
R5
LINK_LED10# R7
LINK_LED100# R6
<26> ACTLED#
<26> LINK_LED10#
<26> LINK_LED100#
1
1
1
1CT:1CT
TRP1P
TRP1N
1CT:1CT
TRP2P
TRP2N
NC
NC
16
COMMON1
17
15
GREEN
ORANGE
NC
NC
2 X 75 OHMS
2 150_0402_5%~D
2 150_0402_5%~D
2 150_0402_5%~D
1000pF 2KV
B
TYCO_1368458-1~D
18
19
C237 0.01U_0402_16V7K~D
C239 0.01U_0402_16V7K~D
SHIELD0
SHIELD1
Title
Magnetic & RJ45

Size
Date:
Document Number
Rev
0.4
LA-3001
Sheet
1
27
of
73
+3.3V_R5C832
U21
1
2
MDIO04
SDPWR0
MDIO05
SDPWR1
MDIO06
SDLED#
XDPWR
MMCPWR
MSWR
MMCLED#
MSLED#
XDWP#
XDLED#
MDIO07
SDEXTCK
MDIO08
SDCCMD
MMCCMD
MSBS
XDWE#
MDIO09
SDCCLK
MMCCLK
MSCCLK
XDRE#
MDIO10
SDCDAT0
MMCDAT
MSCDAT0
XDCDAT0
MDIO11
SDCDAT1
MSCDAT1
XDCDAT1
MDIO12
SDCDAT2
MSCDAT2
XDCDAT2
MDIO13
SDCDAT3
MSCDAT3
XDCDAT3
MSEXTCK
MDIO14
XDCDAT4
MDIO15
XDCDAT5
BLM21A601SPT_0805~D
MDIO16
XDCDAT6
MDIO17
XDCDAT7
MDIO18
XDCLE
MDIO19
XDALE
Function set pin define

UDIO3
UDIO4
MSEN
XDEN
Pull-up
Pull-up
Pull-up
Pull-up
Function
Enable
SD,XD,MS,MMC Card
Solve MS Duo Adaptor short problem

Layout Note: Place close to R5C832
and Shield GND
Layout Note: Place close to R5C832

R5C832XI
R5C832XO
@ R500
1
2
0_0402_5%~D
24.576MHz_16P_1BG24576CKIA~D
SDDATA2_MSDATA2_XDD2
1 R130
2 R5C832XO
680_0402_5%~D
+3.3V_RUN_CARD
22P_0402_50V8J~D
Q38
3 2N7002_SOT23~D
1
2
R519
@ 0_0805_5%~D
R96 1
R103 1
SI2303BDS-T1-E3_SOT23-3~D
B
100K_0402_5%~D
2 10K_0402_5%~D
2 100K_0402_5%~D
SDCD#_XDCD0#
XD_CDSW#
S Q37
2N7002_SOT23~D
XD_CDSW#
2
G
Q9
Place close to J5IN1

+3.3V_RUN_CARD
UDIO4
UDIO5
R5C832_TQFP128~D
Q8
+3.3V_RUN_XD
+15V_SUS R509
1
2
+3.3V_R5C832
SDDATA2
C172
1
2
X1
R508
0_0402_5%~D
@
MS_INS# 2
G
2N7002_SOT23~D
4
13
22
28
54
62
63
68
118
122
22P_0402_50V8J~D
SDDATA1
Q35
3 2N7002_SOT23~D
UDIO4
UDIO5
R5C832XI
IRQ_SERIRQ <23,30>
C163
1
2
2
G
72
60
56
65
59
57
C182
IRQ_SERIRQ
0.01U_0402_16V7K~D 1
96
101
100
@ R498
1
2
0_0402_5%~D
2
G
XDR/B#
SDWP#
1
2
Add test point
XDCE#
MDIO03
NC
XDCD1#
MSCD#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L47
1
XD Card
XDCD0#
AGND
AGND
AGND
AGND
AGND
+3.3V_R5C832
MMCCD#
HWSPND#
TEST
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDRE#
XDD4
XDD5
XDD6
XDD7
XDCLE
XDALE
+3V_RUN_PHY
1
SDCD#
MS Card
MS Pro Card
MDIO02
1000P_0402_50V7K~D
UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
TPB0+ <29>
TPB0- <29>
MMC Card
MDIO01
0.47U_0402_10V4Z~D
INTA#
INTB#
TPA0+ <29>
TPA0- <29>
C178
0.1U_0402_16V4Z~D
FIL0
REXT
VREF
TPBIAS0 <29>
SD Card
C459
0.47U_0402_10V4Z~D
94
95
C179
0.01U_0402_16V7K~D
XI
XO
C550
0.01U_0402_16V7K~D
58
55
R170
1
C177
10U_0805_6.3V6M~D
MSEN
XDEN
+3.3V_RUN
0_0805_5%~D
C522
0.01U_0402_16V7K~D
97
SDCD#_XDCD0#
MSCD#_XDCD1
XD_CE#
SDWP#_XDRB#
CARD_EN
XDWP#
TP_SD/MMC/MS/XD_LED#
CLK_PCI_PCCARD
C551
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
C135
R97
111
107
103
102
99
TPB0+
TPB0-
10U_0805_6.3V6M~D
105
104
C449
0.01U_0402_16V7K~D
10K_0402_5%~D
100K_0402_5%~D
R100
+3.3V_R5C832
69
66
TPBP0
TPBN0
C503
0.01U_0402_16V7K~D
@ 0_0402_5%~D
109
108
+3.3V_R5C832
Media I/F
MDIO00
+VCC_ROUT
C181
<21> PCI_PIRQD#
<21> PCI_PIRQC#
R102 1
<31> CB_HWSPND#
TPAP0
TPAN0
TPA0+
TPA0-
10K_0402_1%~D
115
116
TPBIAS0
C180
0.01U_0402_16V7K~D
2 @ 0_0402_5%~D
TPBIAS0
113
C482
0.01U_0402_16V7K~D
R98
98
106
110
112
C513
0.01U_0402_16V7K~D
<26,31> SYS_PME#
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
C562
<23,26,30> CLKRUN#
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#
+3V_RUN_PHY
R140
0.01U_0402_16V7K~D
R139 1
121
PCIRST_PCCARD# 119
BUS_GRST#
71
117
70
2 0_0402_5%~D
CLK_PCI_PCCARD
<21> PCIRST_PCCARD#
REQ#
GNT#
86
R458
124
123
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
67
C527
PCI_REQ2#
PCI_GNT2#
<21> PCI_REQ2#
<21> PCI_GNT2#
33
23
25
24
29
26
8
30
31
+3.3V_R5C832
10P_0402_50V8J~D
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_AD17
1
2
100_0402_5%~D
R109
<21,26> PCI_PERR#
<21,26> PCI_SERR#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
10_0402_5%~D
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI _IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_IDSEL
PCI_PERR#
PCI_SERR#
<21,26>
<21,26>
<21,26>
<21,26>
<21,26>
<21,26>
No pop R98 to fix

current leakage issue
from ZRS M/B
<6>
7
21
35
45
16
34
64
114
120
10U_0805_6.3V6M~D
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
+VCC_ROUT
C149
0.01U_0402_16V7K~D
<21,26>
<21,26>
<21,26>
<21,26>
VCC_3V
VCC_MD3V
61
C153
0.1U_0402_16V4Z~D
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
+3.3V_R5C832
C141
0.01U_0402_16V7K~D
C150
1U_0603_10V4Z~D
@ 0_0402_5%~D
VCC_RIN
10
20
27
32
41
128
10U_0805_6.3V6M~D
BUS_GRST#
R5C832
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
C157
0.01U_0402_16V7K~D
R108
<31> CBUS_GRST#
100K_0402_5%~D
R105
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C145
+3.3V_R5C832
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
C146
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
<21,26> PCI_AD[0..31]
SD,MMC,MS,MS PRO,XD muti-function pin define
32
35
39
+3.3V_R5C832
SDCD#_XDCD0#
1
SDCLK_MSCLK_XDRE#
0_0402_5%~D
MSCD#_XDCD1
D15
R565
2
D9
MSCD#_XDCD1
SD3_VSS
SD6_VSS
SD_GND
+3.3V_R5C832
2
SDCLK
SDCMD_MSBS_XDWE#
SDCD#_XDCD0#
SDWP#_XDRB#
MS Card
Interface
SD Card
Interface
34
31
40
41
33
U13
5
MS_INS#
CARD_EN
@ R507
2
RB751V_SOD323~D
D14
2
1
0_0402_5%~D
XD_CDSW#
IN
ON/OFF#
OUT
GND
N.C
1
2
3
G5240B1T1U_SOT23-5~D
RB751V_SOD323~D

Title
MOLEX_48000-3002~D
5 IN 1 CardReader CONN.
R5C832 and 5 IN 1
Size
Document Number
Rev
0.4
LA-3001P
Date:
RB751V_SOD323~D
+3.3V_RUN_CARD
+3.3V_R5C832
C169
1U_0603_10V4Z~D
SD5_CLK
SD2_CMD
SD_SW
SD_SW/WP
SD4_VDD
C151
SDDATA1
SDDATA2
0.1U_0402_16V4Z~D
36
37
38
30
R150
10K_0402_5%~D
GND0
GND1
GND2
SD7_DAT0
SD8_DAT1
SD9_DAT2
SD1_CD/DAT3
R149
10K_0402_5%~D
42
43
44
R545
SDDATA3_MSDATA3_XDD3 0_0402_5%~D
MSCLK
1
2 SDCLK_MSCLK_XDRE#
SDCMD_MSBS_XDWE#
MS_INS#
R559
150K_0402_5%~D
XD0_GND
XD9_GND
23
22
24
26
27
21
25
28
20
29
0.01U_0402_16V7K~D
XD18_VCC
1
10
MS4_DATA0
MS3_DATA1
MS5_DATA2
MS7_DATA3
MS8_SCLK
MS2_BS
MS6_INS
MS9_VCC
MS1_VSS
MS10_VSS
C645
0.01U_0402_16V7K~D
C608
2.2U_0805_10V6K~D
19
4 IN 1 CONN
C620
+3.3V_RUN_XD
XD1_CD
XD2_R/B#
XD3_RE#
XD4_CE#
XD5_CLE
XD6_ALE
XD7_WE#
XD8_WP#
XD10_D0
XD11_D1
XD12_D2
XD13_D3
XD14_D4
XD15_D5
XD16_D6
XD17_D7
xD Card
Interface
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
C619
0.01U_0402_16V7K~D
J5IN1
XD_SW#
SDWP#_XDRB#
SDCLK_MSCLK_XDRE#
XD_CE#
XDCLE
XDALE
SDCMD_MSBS_XDWE#
XDWP#
XDD4
XDD5
XDD6
XDD7
XD_SW#
+3.3V_RUN_CARD
Sheet
1
28
of
73
Mini Wireless LAN Card
Mini Wireless WAN Card

+3.3V_RUN
JMINI1
<31,36> PCIE_WAKE#
+3.3V_RUN
<6> CLK_PCIE_MINI2#
<6> CLK_PCIE_MINI2
<30> HOST_DEBUG_RX
<30> 8051TX
PCIE_RX2PCIE_RX2+
PLTRST3# <21>
ICH_SMBCLK <6,23,36>
ICH_SMBDATA <6,23,36>
8051RX <30>
LED_WLAN#
LED_WLAN# <35>
R325 1
2 0_0402_5%~D BT_ACTIVE <25,35>
@ +1.5V_RUN
+
2
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
ICH_SMBCLK
ICH_SMBDATA
<23> USBP5+
USBP5+
USBP5_D+
L15 @
R167 1
2 0_0402_5%~D
R166 1
2 0_0402_5%~D
1
1
+
2
ICH_SMBCLK <6,23,36>
ICH_SMBDATA <6,23,36>
USBP5_DUSBP5_D+
T1
PAD~D
+1.5V_RUN
+3.3V_LAN
1
JCLIP1
1
1
2
3
4
C281
0.1U_0402_16V4Z~D
USBP5_D-
WWAN_RADIO_DIS# <23>
PLTRST3# <21>
+3.3V_LAN
C53
33P_0402_50V8J~D
UIM_DATA <35>
UIM_CLK <35>
UIM_RESET <35>
UIM_VPP <35>
WWAN_RADIO_DIS#
PLTRST3#
TYCO_1775838-1~D
C282
33P_0402_50V8J~D
C553
+SIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
+3.3V_RUN
WLAN_RADIO_OFF#
1
2
3
4
MOLEX_48099-5200~D
JCLIP2
RB751V_SOD323~D
Suport for WoW

prevents backdrive when WoW is enabled.
USBP5-
D22
2
<23> USBP5-
Close to JMINI1 Conn.

1
C249
0.047U_0402_16V4Z~D
1
1
330U_V_6.3VM_R25M~D
+3.3V_RUN
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
TYCO_1775838-1~D
<31> WLAN_RADIO_DIS#
PCIE_TX1PCIE_TX1+
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C283
33P_0402_50V8J~D
54
PCIE_RX1PCIE_RX1+
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C280
0.047U_0402_16V4Z~D
GND2
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
C195
33P_0402_50V8J~D
GND1
MINI1CLK_REQ#
+3.3V_LAN
ICH_SMBCLK
ICH_SMBDATA
C187
53
<23> PCIE_TX1<23> PCIE_TX1+
Close to JMINI1 Conn.
C194
33P_0402_50V8J~D
WLAN_RADIO_OFF#
PLTRST3#
C193
33P_0402_50V8J~D

HOST_DEBUG_TX <30>
0.047U_0402_16V4Z~D
C191
0.1U_0402_16V4Z~D
C248
4.7U_0603_6.3V6M~D
C201
C188
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
+3.3V_LAN
C190
33P_0402_50V8J~D
+3.3V_RUN
<6> CLK_PCIE_MINI1#
<6> CLK_PCIE_MINI1
C198
330U_V_6.3VM_R25M~D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
<6> MINI1CLK_REQ#
C199
0.047U_0402_16V4Z~D
PCIE_TX2PCIE_TX2+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C189
0.047U_0402_16V4Z~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C544
0.047U_0402_16V4Z~D
<31,36> PCIE_WAKE#
<25> COEX2_WLAN_ACTIVE
<25> COEX1_BT_ACTIVE
<6> MINI2CLK_REQ#
JMINI2
C192
0.1U_0402_16V4Z~D
R241
0_0402_5%~D
PCIE_WAKE#
COEX2_WLAN_ACTIVE
1
2
COEX1_BT_ACTIVE 1
2
MINI2CLK_REQ#
R240
0_0402_5%~D
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
PCIE_WAKE#
1
2
3
4
@ R628
0_0402_5%~D
1
2
1
2
3
4
MOLEX_48099-5200~D
Layout Note: Place close to R5C832 Chip
Layout Note: Place close to 1394 Connector
R391
0_0402_5%~D
1
2
TPBIAS0
1
2
1
2
L35
@
R393
0_0402_5%~D
2
1
2
TPA_0J1394
4
3
2
1
R4030_0402_5%~D
2
1
TPA+
TPATPB+
TPB-
GND
GND
GND
GND
5
6
7
8
TYCO_2-1775815-2~D
TPB_0+
L36
1
DLW21SN121SQ2L_4P~D
R4010_0402_5%~D
2
1
TPB_0-
R468
5.11K_0603_1%~D
2
270P_0402_50V7K~D
C571
TPA_0+
R460
56.2_0603_1%~D
R461
56.2_0603_1%~D
TPA0+
TPA0TPB0+
TPB0-
0.33U_0603_10V7K~D
C567
0.01U_0402_16V7K~D
R462
C572
TPA0+
TPA0TPB0+
TPB0-
56.2_0603_1%~D
<28>
<28>
<28>
<28>
R463
56.2_0603_1%~D
DLW21SN121SQ2L_4P~D
<28> TPBIAS0
Title
MINI CARD & 1394 Connector

Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
29
of
73
5V tolerant pins
+3.3V_SUS
21
44
65
83
116
Use Low ESR cap<2 ohms
8
7
6
5
2
1
2
1
2
2
Q65
@ MMBT3906_SOT23~D
1
D
VR_CAP
@ 0_0402_5%~D
Flash write protect bottom 4K

of internal bootblock flash
Q66
@ 2N7002_SOT23~D
3
2
G
R651
1
R650
FWP#
1
C711
@ 4.7U_0603_6.3V6M~D
1
2
R649
2
SFPI_EN
1
1
R647
@ 10K_0402_5%~D
D27
+3.3V_ALW
@
MEC5004_VTQFP128~D
Low = write protected

STUFF for Development
NO STUFF for Production
+3.3V_ALW
+3.3V_ALW
RESET_OUT# <33>
2
0_0402_5%~D
+3.3V_ALW
1=Flash Recovery Enabled

0=Flash Recovery Disabled
around circuit for EMC5004 Rev.C version
@ 100K_0402_5%~D

Title
EMC5004
Size
Document Number
Rev
0.4
LA-3001P
Date:
1
2
VCC
HOLD#
C
D
M25P80-VMW6TP_SO8~D
VCC_PLL
101
104
VSS_PLL
VR_CAP
22
VSS
VSS
VSS
VSS
VSS
AGND
26
51
74
88
113
125
2
RUNPWROK <31,33,42> Work
S#
Q
W#
VSS
200 MIL SO8
RUNPWROK
VR_CAP
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO
100K_0402_5%~D
2
10_0402_5%~D
VCC
HOLD#
SCLK
SI
R410 @
3
2
2
EC_32KHZ <31>
49
1
2
3
4
@ 10K_0402_5%~D
CS#
SO
WP#
GND
8
7
6
5
U23
@ RB751V_SOD323~D
LID_CL# <35>
R516
10K_0402_5%~D
@
1K_0402_5%~D
1
BIA_PWM_EC <19>
EC_32KHZ
1
2
2
BIA_PWM_EC
117
C610
1
2
0.1U_0402_16V4Z~D
R405
FWP#
73
ALWON
POWER_SW# <16,35>
+3.3V_SUS
1K_0402_5%~D
84
0.1U_0402_16V4Z~D
POWER_SW#
R153
nFWP
GPIOA3/WINDMON
C508
1
R117
1
150 MIL SO8
PS_ID_DISABLE# <37>
SIO_EXT_SMI# <23>
BAT2_LED# <35>
BAT1_LED# <35>
L41
BLM11A121S_0603~D
1
2
To SW/B
MX25L8005MI-15G_SOP8~D
ATF_INT# <16>
RESET_OUT#
INSTANT_POWER_SW# <35>
Flash ROM
SIO_EXT_SMI#
BAT2_LED#
BAT1_LED#
TEST_PIN
R518
47_0402_5%~D
1.5mm SMT~D
11
115
114
1
R627
1
2
3
4
Bits issue list: WI52662
ATF_INT#
53
52
72
U22
SPI_CS#
EC_FLASH_SPI_DIN
3
2
1
SFPI_EN
PS_ID_DISABLE#
nRESET_OUT/OUT6
+3.3V_SUS
JDEBG2
3
2
1
@ 100K_0402_5%~D
For power 15V

charge bump circuit
1
2
3
GPIO83/32KHZ_OUT
XOSEL
PS_ID <37>
INSTANT_POWER_SW#
10K_0402_5%~D
R145
123
SIO_EXT_SCI# <23>
R648
C477
0.047U_0402_16V4Z~D
CAP_LED#
CAP_LED# <35>
SCRL_LED#
SCRL_LED# <35>
NUM_LED#
NUM_LED# <35>
2SPI_CS#
0_0402_5%~D SPI_CS# <23>
XTAL1
XTAL2
R406
LID_CL#
91
90
89
4
C175
4.7U_0603_6.3V6M~D
R411
100K_0402_5%~D
LID_CL_SIO#
SGPIO40
SGPIO41
SGPIO42
SGPIO43
BC Bus
L43
BLM11A121S_0603~D
+3.3V_ALW
KB_XOSEL
R110
C183
22P_0402_50V8J~D
122
124
10K_0402_5%~D
R131
32.768K_12.5PF_Q13MC30610003~D
VCC1
VCC1
VCC1
VCC1
VCC1
121
VCC0
1
2
32K_XTAL1
32K_XTAL2
SIO_EXT_SCI#
RUN_ON_D
PS_ID
VGA_IDENTIFY
LID_CL_SIO#
DEBUG_ENABLE#
HOST_DEBUG_TX
HOST_DEBUG_RX
PWRGD
0_0402_5%~D
Y4
BC_CLK
BC_DAT
BC_INT
BREATH_LED <35>
10K_0402_5%~D
100K_0402_5%~D
C170
22P_0402_50V8J~D
1
2
87
86
85
BREATH_LED
MAIN_PWR_SW#
1@
BC_CLK
BC_DAT
BC_INT#
Rb
EC_PWM3_188Khz <39>
70
71
OUT7/nSMI
nPWR_LED
nBAT_LED
VGA_IDENTIFY
R115
1
+RTC_CELL
2@
Ra
FAN1_TACH <16>
SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX
GPIO96/TOUT1
+3.3V_ALW
SNIFFER_LED_OFF# <22,35>
66
55
54
69
68
67
SGPIO35
SGPIO36 (SFPI_EN)
SGPIO37
0 = UMA (Pop Rb)
<31> BC_CLK
<31> BC_DAT
<31> BC_INT#
AUX_EN <32,39>
SUS_ON <32,33,39>
RUN_ON <19,32,33,39,40,41,50>
ITP_DBRESET# <7,23>
SBAT_SMBDAT <19>
SBAT_SMBCLK <19>
DAT_SMB <16>
CLK_SMB <16>
SIO_SLP_S5# <23>
SIO_SLP_S3# <23>
SIO_RCIN# <22>
SIO_EXT_WAKE# <23>
FAN1_TACH
1
R643
1 = Discrete Gfx (Pop Ra)
AUX_EN
SUS_ON
RUN_ON
ITP_DBRESET#
SBAT_SMBDAT
SBAT_SMBCLK
DAT_SMB
CLK_SMB
SIO_SLP_S5#
SIO_SLP_S3#
SIO_RCIN#
SIO_EXT_WAKE#
FLCS0
FLCS1
EC_PWM3_188Khz
PBAT_SMBCLK <38,43>
PBAT_SMBDAT <38,43>
C168
109
110
48
47
46
45
1U_0603_10V4Z~D
SIO_PWRBTN#
OUT2/PWM3
OUT9/PWM2
OUT11/PWM1
OUT10/PWM0
PBAT_SMBCLK
PBAT_SMBDAT
INSTANT_ON_SW#
R118
FLCLK
FLDATAIN
FLDATAOUT
SNIFFER_LED_OFF#
C158
1U_0603_10V4Z~D
100K_0402_5%~D
103
106
108
43
42
41
SNIFFER_PWR_SW# <35>
1
ACAV_IN <16,43>
C161
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DIN
EC_FLASH_SPI_DO
HSTCLK
HSTDATAIN
HSTDATAOUT
GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1
R116
102
105
107
AB1B_CLK
AB1B_DATA
AB1A_CLK
AB1A_DATA
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK
8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100
R111
10K_0402_5%~D
1
2SNIFFER_PWR_SW#
ALWON <39>
R517
<23> SIO_PWRBTN#
ICH_EC_SPI_CLK
ICH_EC_SPI_DIN
ICH_EC_SPI_DO
120
119
126
127
128
118
10K_0402_5%~D
LRESET#
PCICLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
SER_IRQ
ALWON
SNIFFER_SW#
INSTANT_ON_SW#
MAIN_PWR_SW#
ACAV_IN
ALWON
POWER_ SW_IN2#
POWER_ SW_IN1#
POWER_ SW_IN0#
ACAV_IN
BGPO0
nEC_SCI/SPDIN2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO31/TIN1/SPCLK1
Host/8051
<23> ICH_EC_SPI_CLK
<23> ICH_EC_SPI_DIN
<23> ICH_EC_SPI_DO
57
58
59
60
61
62
63
64
56
R417
PLTRST_EC#
CLK_PCI_5004
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ
PLTRST_EC#
CLK_PCI_5004
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ
SBAT_SMBDAT
2
10K_0402_5%~D
2
10K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
+RTC_CELL
PWR SW
LPC Interface
<21>
<6>
<22>
<22>
<22>
<22>
<22>
<23,26,28>
<23,28>
@ MOLEX_53398-0571~D
PBAT_SMBCLK
SBAT_SMBCLK
100K_0402_5%~D
DEBUG_ENABLE#
2
0_0402_5%~D
PBAT_SMBDAT
HOST_DEBUG_TX <29>
HOST_DEBUG_RX <29>
R454
100K_0402_5%~D
R418
8051RX
8051TX
HOST_DEBUG_TX
HOST_DEBUG_RX
1U_0603_10V4Z~D
GPIO94/IMCLK
GPIO95/IMDAT
KCLK
KDAT
EMCLK
EMDAT
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX
1
10K_0402_5%~D
100K_0402_5%~D
75
76
77
78
79
80
81
82
CLK_TP_SIO
DAT_TP_SIO
<34> CLK_TP_SIO
<34> DAT_TP_SIO
+RTC_CELL
2
R426
100K_0402_5%~D
G2 5
G1 4
3
2
1
5
4
3
2
1
1 R203
R202
10K_0402_5%~D
JDBG1
7
6
R201
10K_0402_5%~D
+3.3V_ALW
C455
SGPIO34/A20M
OUT5/KBRST
SIO_A20GATE
SIO_THRM#
<22> SIO_A20GATE
<23> SIO_THRM#
0.1U_0402_16V4Z~D
92
50
C457
KSI7/GPIO19
KSI6/GPIO17
KSI5/GPIO10
KSI4/GPIO9
KSI3/GPIO8
KSI2/GPIO7
KSI1/GPIO6
KSI0/SGPIO30
0.1U_0402_16V4Z~D
33
34
35
36
37
38
39
40
0.1U_0402_16V4Z~D
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
C176
KSO17/GPIOA1
KSO16/GPIOA0
GPIO5/KSO15
GPIO4/KSO14
KSO13/GPIO18
KSO12/OUT8
KSO11/GPIOC7
KSO10/GPIOC6
KSO9/GPIOC5
KSO8/GPIOC4
KSO7/GPIO3
KSO6/GPIO2
KSO5/GPIO1
KSO4/GPIO0
KSO3/GPIOC3
KSO2/GPIOC2
KSO1/GPIOC1
KSO0/GPIOC0
C519
12
13
14
15
16
17
18
19
20
23
24
25
27
28
29
30
31
32
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
C506
+3.3V_ALW
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
Keyboard and Mouse Interface
22_0402_5%~D
R422
8051RX
8051TX
<29> 8051RX
<29> 8051TX
U20
<34> KSI[0..7]
10U_0805_6.3V6M~D
C523
Place closely pin 58
ATF_INT#
<34> KSO[0..17]
1
R135
1
R134
1
R137
1
R136
1
R104
1
R106
CLK_SMB
VCC0
C524
0.1U_0402_16V4Z~D
DAT_SMB
R441
1
0_0402_5%~D
CLK_PCI_5004
+3.3V_ALW
+3.3V_ALW
+RTC_CELL
IMCLK,IMDAT,EMCLK,EMDAT,
KCLK,KDAT,8051RX,8051TX
GPIO43,GPIO35~37
Sheet
1
30
of
73
+3.3V_ALW
+3.3V_RUN
IMVP6_PROCHOT#
100K_0402_5%~D
MDC_RST_DIS#
ADAPT_OC
EXPRCRD_STBY#
<36> MDC_RST_DIS#
<43> ADAPT_OC
<36> EXPRCRD_STBY#
NB_MUTE
<36> NB_MUTE
<37> AC_OFF
IMVP6_PROCHOT#
5V_CAL_SIO#
<42> IMVP6_PROCHOT#
<16> 5V_CAL_SIO#
5V_CAL_SIO2#
<16> 5V_CAL_SIO2#
X00 Modify 9/14
LOM_LOW_PWR#
AUDIO_AVDD_ON
BEEP
ADAPT_TRIP_SEL
<26> LOM_LOW_PWR#
<36> AUDIO_AVDD_ON
<36> BEEP
<43> ADAPT_TRIP_SEL
SC_DET#
<36> SC_DET#
2
1
HDDC_EN#
MODC_EN#
100K_0402_5%~D
R641
100K_0402_5%~D
R640
+3.3V_ALW
<23> ICH_PCIE_WAKE#
<21> ICH_PME#
<16> THERMTRIP_SIO
<28> CBUS_GRST#
<36> CPPE#
<19> FPBACK_EN
<28> CB_HWSPND#
<7> CPU_PROCHOT#
<23,36> HDDC_EN#
<23,36> MODC_EN#
2 10K_0402_5%~D
USB_SIDE_EN#
USB_BACK_EN#
DBAY_MODPRES#
<25> USB_SIDE_EN#
<25> USB_BACK_EN#
GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N
32
33
GPIOH[6]
GPIOH[7]
ATEST
126
REG_EN
123
122
ECE5011_XTAL1
ECE5011_XTAL2
NC
46
KHz_32
96
EC_32KHZ
PWRGD
RUNPWROK
105
WLAN_RADIO_DIS#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
GPIOF[3]
GPIOF[2]
GPIOF[1]
GPIOF[0]
C330
0.1U_0402_16V4Z~D
1
1
1
C408
C409
4.7U_0805_6.3V6K~D
C371
0.1U_0402_16V4Z~D
C363
C89
C95
2 4.7U_0805_6.3V6K~D
2 4.7U_0805_6.3V6K~D
2 0.1U_0402_16V4Z~D
C60
4.7U_0805_6.3V6K~D
R404
10K_0402_5%~D
1
2
+3.3V_ALW
C
@ C102
33P_0402_50V8J~D
1
2
EC_32KHZ <30>
RUNPWROK <30,33,42>
WLAN_RADIO_DIS# <29>
ECE5011_XTAL2 1
R93
2
0_0402_5%~D
@
Y3
24MHZ_20PF_1BX24000BK1A~D
C114
33P_0402_50V8J~D
1
2
@
GPIOH[2]
GPIOH[3]
115
116
117
118
Route RBIAS and its

return to pin 128 very
short.
XTAL1/CLKIN
XTAL2
OUT65
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
CIRTX
CIRRX
35
VDDA18PLL
VDD18
CAP_LDO
RBIAS
ECE5011_XTAL1
63
28
29
30
31
113
114
C360
0.1U_0402_16V4Z~D
GPIOD[1]/CIRTX
GPIOD[2]/CIRRX
TEST_PIN
C335
0.1U_0402_16V4Z~D
34
42
43
57
85
108
119
61
62
GPIO
125
124
120
86
127
54
52
49
47
41
56
37
44
39
64
55
53
50
48
38
45
40
11
17
23
36
51
72
87
121
128
5V tolerant pins
GPIOB[7:0],GPIOC[7:0]
GPIOD[1:0],GPIOE[7:0]
ECE5011_VTQFP128~D
R42
10K_0402_5%~D
1
2
R43
10K_0402_5%~D
1
2
R44
10K_0402_5%~D
1
2
R45
10K_0402_5%~D
1
2
+3.3V_ALW
BID3 BID2 BID1 BID0 REV
0
0
0
0
0
@
BID0
R31
10K_0402_5%~D
BID1
R32
10K_0402_5%~D
BID2
R33 @ 1
10K_0402_5%~D
BID3
R34
10K_0402_5%~D
GPIOB[0]
GPIOB[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]
GPIOD[0]
GPIOC[1]
GPIOC[0]
GPIOB[7]
GPIOB[6]
GPIOB[5]
GPIOB[4]
GPIOB[3]
GPIOB[2]
ICH_PCIE_WAKE#
88
ICH_PME#
89
THERMTRIP_SIO
90
CBUS_GRST#
91
CPPE#
92
FPBACK_EN
93
CB_HWSPND#
94
CPU_PROCHOT#
95
R637 0_0402_5%~D
HDDC_EN# 1
106
2
MODC_EN# 1
107
2
R638 0_0402_5%~D
BID3
109
BID2
110
BID1
111
BID0
112
R86 1
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
VDDA33PLL
VDDA18PLL
VDD18
CAP_LDO
RBIAS
R94
1M_0402_5%~D
SBAT_ALARM#
PBAT_ALARM#
<38> PBAT_ALARM#
GPIOE[0]
GPIOE[1]
GPIOE[2]
GPIOE[3]
GPIOE[4]
GPIOE[5]
GPIOE[6]
GPIOE[7]
R398
12K_0402_1%~D
R70
1
1
2
3
4
5
84
83
6
TOUCH_PAD_LED#
LOW_LIGHT
CAM_IMG_CAPTURE#
MIC_SWITCH
<34> TOUCH_PAD_LED#
<34> LOW_LIGHT
<35> CAM_IMG_CAPTURE#
<36> MIC_SWITCH
9
10
13
12
15
16
19
18
21
22
+3.3V_ALW
L33
1
2
M_LED_A
SW_LED
<34> M_LED_A
<35> SW_LED
USB
4.7U_0805_6.3V6K~D
SNIFFER_WIRELESS_ON/OFF#
BC_INT#
BC_DAT
BC_CLK
<35> SNIFFER_WIRELESS_ON/OFF#
<30> BC_INT#
<30> BC_DAT
<30> BC_CLK
USBDP0
USBDN0
USBDP1
USBDN1
USBDP2
USBDN2
USBDP3
USBDN3
USBDP4
USBDN4
VDDA33
2 SYS_PME#
10K_0402_5%~D
GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT
BC_DAT
BC_CLK
8
14
20
R84
24
25
26
27
58
59
60
ECE5011
VDDA33
VDDA33
VDDA33
+3.3V_ALW
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
C453
0.1U_0402_16V4Z~D
<38> PBAT_PRES#
<29,36> PCIE_WAKE#
<26,28> SYS_PME#
97
98
99
100
101
102
103
104
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
PCIE_WAKE#
SYS_PME#
DOCK_SIO_ALERT#
PBAT_PRES#
C454
0.1U_0402_16V4Z~D
U18
C456
0.1U_0402_16V4Z~D
PCIE_WAKE#
2
10K_0402_5%~D
2 DOCK_SIO_ALERT#
10K_0402_5%~D
PBAT_ALARM#
2
10K_0402_5%~D
SBAT_ALARM#
2
10K_0402_5%~D
DBAY_MODPRES#
2
10K_0402_5%~D
1
R362
1
R372
1
R351
1
R356
1
R375
C62
0.1U_0402_16V4Z~D
+3.3V_ALW
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
M00
X00
X01
X02
X03
Title
HUB/ECE5011
Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
31
of
73
+3VRUN Source
R58 @
30_0805_5%
1
R447 @
30_0805_5%
2
Z4008
Z4007
Z4006
Q39 @
2
2N7002_SOT23~D
G
S
Q44 @
2
2N7002_SOT23~D G
Q25 @
2N7002_SOT23~D
Q2 @
2
2N7002_SOT23~D G
2
G
3
200K_0402_5%~D
R567 @
30_0805_5%
3.3VRUN Turn ON Delay:

Populate RC Componant
R631
CPU VR Requirements: 5VRUN

need to be > 1.5Vlevel, before
3.3VRUN canbe Switched ON.
C708
470P_0402_50V7K~D
Reserve for discharge path
R564 @
30_0805_5%
R597
30_0805_5%
Z4011
D
Q42 @
2
2N7002_SOT23~D
G
2
G
S
Z4009
Z4010
R467
20K_0402_5%~D
Q47 @
2N7002_SOT23~D
SUS_ON_5V#
Q52
2N7002_SOT23~D
S
+1.8VRUN Source
2@ D24
C159
10U_0805_10V4Z~D
2@
MMBD4148_SOT23~D
+1.8V_RUN
1
Q4
2@
SI4800DY-T1-E3_SO8~D
1
2
3
R138
20K_0402_5%~D
2@
2
2
+1.8V_SUS
8
7
6
5
2
G
3
Maximum Rds for Q45, Q26,Q4

should 15mohm
1
R558 @
30_0805_5%
1
1
+2.5V_RUN
+1.8V_SUS
+0.9V_DDR_VTT
+5V_RUN
1
2
3
Q46
2N7002_SOT23~D
8
7
6
5
C547
10U_0805_10V4Z~D
+5VRUN Source
Q26
SI4810DY_SO8~D
1 C685
Q49
2N7002_SOT23~D
2
G
2
G
<19,30,33,39,40,41,50> RUN_ON
4700P_0402_25V7K~D
RUN_ON_5V#
RUN_ENABLE
+5V_SUS
R569
100K_0402_5%~D
R572
100K_0402_5%~D
R540 @
30_0805_5%
<39> RUN_ENABLE
+5V_ALW
+1.5V_RUN
100K_0402_5%~D
R568
20K_0402_5%~D
RUN_ON_5V#
+1.8V_RUN
Updated as COE A06
+15V_SUS
+3.3V_RUN
GFX_RUN_ON <50>
2@
2
Z4005
4
D23
MMBD4148_SOT23~D
+5V_RUN
R632
1
+3.3V_RUN
1
2
3
Q45
SI4810DY_SO8~D
8
7
6
5
+3.3V_SRC
C663
10U_0805_10V4Z~D
Run Planes Enable
2 R107
2@
200K_0402_5%~D
2
For G72 GDDR3 Power

+3.3V_LAN power enable signal
C154
0.047U_0402_16V4Z~D
2@
+3.3V_SUS Source
SUS_ON 2
G
Q41
2N7002_SOT23~D
2
S
1
1
R553
20K_0402_5%~D
2
2
Q40
2N7002_SOT23~D
3
<30,33,39> SUS_ON
1
1
R520
470K_0402_5%~D
SUS_ON_5V#2
G
+3.3V_SUS
1
2
3
1
2
Q36
2N7002_SOT23~D
SUS_ENABLE
2
1
ENAB_3VLAN <26>
ENAB_3VLAN
2
1
Q34
2N7002_SOT23~D
R501
2
G
200K_0402_5%~D
<30,39> AUX_EN
AUX_EN
R555
100K_0402_5%~D
2
G
Q43
SI4810DY_SO8~D
8
7
6
5
R513
100K_0402_5%~D
R497
100K_0402_5%~D
+3.3V_SRC
R556
100K_0402_5%~D
+PWR_SRC
+5V_ALW
C660
10U_0805_10V4Z~D
+15V_SUS
+PWR_SRC
Title
POWER CONTROL
Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
32
of
73
+3.3V_RUN
+3.3V_SUS
C686
1
R573
20K_0402_5%~D
+3.3V_SUS
C691
IN1
IN2
U26A
+3.3V_SUS
OUT
14
4
5
+3.3V_ALW
+3.3V_SUS
+3.3V_SUS
R571
10K_0402_5%~D
<30,32,39> SUS_ON
14
For Discrete Graphic Core VR

Not stuff R576 & R577 if
page50 PR159 & PR160 are
populated.
Q48
2
B
E
1
2
5V_3V_1.8V_RUN_PWRGD
IN2
2
1
RESET_OUT#
14
IN1
OUT
ICH_PWRGD
Q61 2@
2
B
3
Q60 2@
2N7002_SOT23~D
PMBT3904_SOT23~D
Change for Dell GG list request 12/13.
Q10
2N7002_SOT23~D
2
G
ICH_PWRGD# <16>
1
2
1
1
R232
100K_0402_5%~D
10
C710
<30> RESET_OUT#
IMVP_PWRGD
0.1U_0402_10V7K~D
2@
2
G
1
+3.3V_SUS
B
R471 2@
100K_0402_5%~D
<23,42> IMVP_PWRGD
SUSPWROK <16,23>
+1.8V_SUS
1.8V_ON
ICH_PWRGD#
SUSPWROK
Or use N-FET (SOT23) 2N7002,RHU002N06,2N7000
R129
10K_0402_5%~D
2@
11
IN2
PMBT3904_SOT23~D
+1.8V_RUN
U26C
OUT
7
74LVC3G14DC_VSSOP8~D
U26D
IN1
Y
4
C684
<50> GFX_CORE_PWRGD
0.1U_0402_10V7K~D
<50> GFX_PCIE_PWRGD
12
13
5
U27C
P
3
+3.3V_SUS
RUNPWROK <30,31,42>
R574
100K_0402_5%~D
<41> +0.9V_DDR_PWRGD
<10,23> ICH_PWRGD
RUNPWROK
IN2
SUSPWROK_1P8V
<40> 1.05V_RUN_PWRGD
OUT
<41> SUSPWROK_1P8V
<40> 1.5V_RUN_PWRGD
IN1
<16> 2.5V_RUN_PWRGD
U26B
RUN_ON
<19,30,32,39,40,41,50> RUN_ON
14
0.1U_0402_16V4Z~D
8
4
U27B
P
6
1
R576
0_0402_5%~D
1
R577
0_0402_5%~D
0_0402_5%~D
R581
2
1
R578
0_0402_5%~D
R579
0_0402_5%~D
0_0402_5%~D
R580
2
0.01U_0402_25V7K~D
C681
+3.3V_SUS
U27A
5V_3V_1.8V_RUN_PWRGD
0.1U_0402_16V4Z~D
Title
POWER SEQUENCE
Size
Rev
0.4
LA-3001P
Date:
Document Number
Sheet
1
33
of
73
Add a 10K pull-up to +5V_RUN from bits issue list: WI52078

+5V_RUN
CLK_TP_SIO
JTP1
L51
BLM11A601S_0603~D
1
2
TP_DATA
<31> M_LED_A
<31> TOUCH_PAD_LED#
<31> LOW_LIGHT
TP_CLK
+5V_RUN
LED Control
Status
LOW_LIGHT
TOUCH_PAD_LED#
1
3
5
7
9
11
13
15
17
19
1
3
5
7
9
11
13
15
17
19
21
GND1
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
GND2
22
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
+5V_RUN
1
JST_BM20B-SRDS-G-TFC(LF)(SN)~D
Signals
0.1U_0402_16V4Z~D
C225
TP_DATA
TP_CLK
C232
0.1U_0402_16V4Z~D
C634
KSO17
M_LED_A
TOUCH_PAD_LED#
LOW_LIGHT
10P_0402_50V8J~D
1
2
L52
BLM11A601S_0603~D
C627
T/P & Media CONN.

TOUCH_PAD_LED#
10P_0402_50V8J~D
C636
10P_0402_50V8J~D
10P_0402_50V8J~D
C631
R645
10K_0402_5%~D
1
1
2
2
<30> CLK_TP_SIO
DAT_TP_SIO
R551
R543
<30> DAT_TP_SIO
4.7K_0402_5%~D
4.7K_0402_5%~D
+5V_RUN
Description
OFF
LOW
High bright for Touch PAD LED
HIGH
Low bright for Media LED/Touch PAD LED
High bright for Media LED
M_LED_A
JKYBD1
<30> KSI[0..7]
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
B
<30> KSO[0..17]
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
30
29
28
27
26
GND
GND
31
32
NC
NC
33
34
JAE_FK2S030W12~D
100P_0402_50V8J~D
C656
100P_0402_50V8J~D
C647
100P_0402_50V8J~D
C667
100P_0402_50V8J~D
C668
100P_0402_50V8J~D
C648
100P_0402_50V8J~D
C669
100P_0402_50V8J~D
C649
100P_0402_50V8J~D
C664
100P_0402_50V8J~D
C650
100P_0402_50V8J~D
C665
100P_0402_50V8J~D
C651
100P_0402_50V8J~D
C670
100P_0402_50V8J~D
C652
100P_0402_50V8J~D
C671
100P_0402_50V8J~D
C672
100P_0402_50V8J~D
C654
100P_0402_50V8J~D
C655
100P_0402_50V8J~D
C653
100P_0402_50V8J~D
C676
100P_0402_50V8J~D
C674
100P_0402_50V8J~D
C675
100P_0402_50V8J~D
C662
100P_0402_50V8J~D
C657
100P_0402_50V8J~D
C666
100P_0402_50V8J~D
C646
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
5
Title
INT KB/Touch Pad/Media CONN

Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
34
of
73
+3.3V_SUS
POWER Button CONN.
+3.3V_RUN
Q33
INSTANT_POWER_SW#
CAM_IMG_CAPTURE#
POWER_SW_R#
SATA_ACT#_R
LID_CL#
+SIM_PWR
UIM_VPP
+3.3V_SW_RUN
INSTANT_POWER_SW# <30>
SW_LED <31>
CAM_IMG_CAPTURE# <31>
<16> SNIFFER_YELLOW#
POWER_SW#
1 R237
2
+3.3V_ALW 100_0402_5%~D
SATA_ACT#_R <22>
LID_CL# <30>
SNIFFER_YELLOW#
R465
100K_0402_5%~D
DDTA114EUA-7-F_SOT323~D
POWER_SW# <16,30>
+3.3V_SUS
+SIM_PWR
UIM_VPP <29>
<16> SNIFFER_GREEN#
R626
1
SNIFFER_GREEN#
R479
220_0402_5%~D
1
2
MMBT3906WT1G_SC70-3~D
Q59
B
1
1
2
R478
220_0402_5%~D
Updated as COE A06
FD1
SNI FFER_Y
D13
3 Y
1
2
G
12-22AUYSYGC/530-A2/TR8_G/Y~D
SNIFFER_G
+3.3V_RUN
FD25
+3.3V_RUN
+3.3V_SW_RUN
FD2
1
FD15
1
FD16
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
SNIFFER_LED_OFF#
<29> LED_WLAN#
LED_WLAN#
S
1
FD13
FD4
1
FD5
1
Q1
Q63
2N7002_SOT23~D
2
G
PCB Fiducial Mark (FIDUCIAL)
Q62
FD17
Q29
Fiducial Mark
1
BT_ACTIVE_R
SNIFFER_LED_OFF#
1BS008-13130-042-7F_4P~D
10K_0402_5%~D
<22,30> SNIFFER_LED_OFF#
SNIFFER_PWR_SW#
<30> SNIFFER_PWR_SW#
TYCO_1775876-1~D
<25,29> BT_ACTIVE
JSNIFF1
<31> SNIFFER_WIRELESS_ON/OFF#
off
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
Reverse
UIM_DATA
UIM_CLK
UIM_RESET
<29> UIM_DATA
<29> UIM_CLK
<29> UIM_RESET
1
3
5
7
9
11
13
15
17
19
21
23
1
3
5
7
9
11
13
15
17
19
21
23
BT_ACTIVE_R
LED_WLAN
BREATH_LED
CAP_LED#
NUM_LED#
SCRL_LED#
BAT1_LED#
BAT2_LED#
<30> BREATH_LED
<30> CAP_LED#
<30> NUM_LED#
<30> SCRL_LED#
<30> BAT1_LED#
<30> BAT2_LED#
JSW1
R_LED_WLAN 1
FD3
R16
220_0402_5%~D
2
LED_WLAN
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D

FD11
1
FD8
1
FD9
1
FD7
1
Screw

FD14
1
FD12
1
FD10
1
FD6
H1
H_C276D110
H2
H_C276D110
H4
H3
H5
H_C217D118 H_O276X236D157X118 H_C276D110
H8
H6
H_C276D110 H_C315D102x91
H9
C315D91
FD26
FD24
1
FD23
1
FD21
1

FD18
1
FD19
1
FD22
1
FD20
1
VGA stand-Off
H10
H_C236D110
H11
H12
H13
H_C276D110 H_C315D102x91H_C315D102x91
H15
H_C315D110
H16
H_C276D110
H17
H_C276D110
H18
H19
H_C276D110 H_C276D110
H7
H_C217D43
H14
H_C217D43
B
PCB Fiducial Mark (SMD40M80)
5
Title
SW LED/B & ME & spare parts

Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
35
of
73
JIO1
CD-ROM IDE BUS
<23> IDE_RST_MOD
IDE_DD11
IDE_DD10
IDE_DD7
IDE_DD5
IDE_DD6
IDE_DD4
IDE_DD1
IDE_DD8
IDE_DD3
IDE_DD9
IDE_DD0
IDE_DD15
IDE_DD2
IDE_DD12
EXPRESS CARD

<23> USBP3<23> USBP3+
SATA HDD

<22> SATA_TX0<22> SATA_TX0+

<22> SATA_TX2<22> SATA_TX2+
<29,31> PCIE_WAKE#
<6> CARD_CLK_REQ#
<31> CPPE#
<21> PLTRST_EXP#
<31> EXPRCRD_STBY#
<23,31> HDDC_EN#
<31> SC_DET#
+3.3V_RUN
+3.3V_SUS
+5V_SUS
+5V_RUN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
GND
4
6
8
10
12
14
16
18
20
22
GND
26
28
30
32
34
36
38
40
42
44
46
GND
50
52
54
56
58
60
62
64
66
68
70
GND
74
76
78
80
82
84
86
88
90
92
94
GND
98
100
102
104
106
108
110
112
114
116
118
GND
GND
3
5
7
9
11
13
15
17
19
21
GND
25
27
29
31
33
35
37
39
41
43
45
GND
49
51
53
55
57
59
61
63
65
67
69
GND
73
75
77
79
81
83
85
87
89
91
93
GND
97
99
101
103
105
107
109
111
113
115
117
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
IDE_DD13
IDE_DD14
IDE_DDREQ <22>
IDE_DIOR# <22>
IDE_DCS3# <22>
IDE_DCS1# <22>
IDE_DIOW# <22>
IDE_DDACK# <22>
IDE_IRQ <22>
IDE_DIORDY <22>
IDE_DA2 <22>
IDE_DA1 <22>
IDE_DA0 <22>
CLK_PCIE_EXPCARD# <6>
CLK_PCIE_EXPCARD <6>
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
<19>
<19>
<19>
<19>
MODC_EN# <23,31>
MDC_RST_DIS# <31>
ICH_AZ_MDC_SDOUT <22>
ICH_AZ_MDC_SDIN1 <22>
ICH_AZ_MDC_RST# <22>
ICH_AZ_MDC_SYNC <22>
ICH_AZ_MDC_BITCLK <22>
ICH_AZ_CODEC_SDIN0 <22>
ICH_AZ_CODEC_RST# <22>
SPEAKER
MDC
C
AC 97
ICH_AZ_CODEC_SYNC <22>
ICH_AZ_CODEC_SDOUT <22>
ICH_AZ_CODEC_BITCLK <22>
SPDIF <20>
NB_MUTE <31>
MIC_SWITCH <31>
BEEP <31>
SPKR <23>
+1.5V_RUN
AUDIO_AVDD_ON <31>
+3.3V_RUN
+5V_SUS
+15V_SUS
FOX_QT00120A-1120-9F~D
B
shielding
IDE_DD[0..15]
IDE_DD[0..15] <22>
Title
I/O BOARD DOCKING

Size
Date:
Document Number
Rev
0.4
LA-3001P
Sheet
1
36
of
73
PS_ID Detector
D
+5V_ALW
PR1
2.21K_0402_1%~D
1
2
PR3
33_0402_5%~D
1
2
+3.3V_RTC_LDO
PS_ID
PS_ID <30>
PU1
IN
NC
MIC5235-3.3BM5_SOT23-5~D
PS_ID_DISABLE# <30>
EN
PC2
1U_0805_25V4Z~D
2
1
PR5
10K_0402_1%~D
2
1
PD2
DA204U_SOT323~D
2
G
PR4
100K_0402_1%~D
1
2
OUT
PR6
@ 100_0402_5%~D
1
2
PD3
SM24_SOT23
+5V_ALW
+5V_ALW
PC1
2.2U_0603_6.3V6K
2
1
3.3V RTC Power
+PWR_SRC
GND
DOCK_PSID
PQ1
FDV301N_SOT23
PR2
0_0402_5%~D
1
2
PD1
DA204U_SOT323~D
+3.3V_ALW
PR7
15K_0402_1%~D
1
2
C
B
PQ2
PMBT3904_SOT23~D
+DC_IN Source
PQ3
FDS6679Z_SO8~D
1
2
3
+DC_IN
PL1
BLM11B102S 0603~D
DOCK_PSID
2
1
PWR_ID
+DC_IN_SS
PL2
FBM-L11-453215-900LMAT_1812~D
1
2
8
7
6
5
PJP22
1
PQ_G
PAD-OPEN 4x4m
PL3
FBM-L11-453215-900LMAT_1812~D
-D CIN_JACK 1
2
PC7
10U_1206_25V6M~D
DC-_2
+ DCIN_JACK
PR9
10K_0603_5%
2
1
PC6
0.1U_0603_25V7K~D
2
1
GND_1
DC-_1
PC5
0.1U_0603_25V7K~D
2
1
DC+_2
PC4
0.01U_0402_25V7K~D
2
1
GND_2
DC+_1
PAD-OPEN 4x4m
PR10
47K_0402_5%~D
2
1
GND_3
MH1
MH2
PC3
0.47U_0805_25V7k
1
2
GND_4
PC8
0.01U_0402_25V7K~D
2
1
PR8
240K_0402_5%~D
2
1
PJP21
PJDC1
FOX_JPD113D-509-TR~D
Low_PWR 1
THE POINT
3
@ PR180
240K_0402_5%~D
NOTE: "THE POINT LOCATED

AT PS MODULE
@
PQ37
SI2301BDS_SOT23~D
<31> AC_OFF
2
@
GPIO Input from EC
PQ36
DTC115EUA_SC70
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
+DCIN
Size
Document Number
Date:
Rev
X02
Bali
Sheet
1
37
of
73
+3.3V_ALW
ESD Diodes
6
+3.3V_ALW
+VCHGR
PL5
FBM-L11-453215-900LMAT_1812~D
1
2
Z4304
Z4305
Z4306
PR14
100_0402_5%~D
1
2
PR15
100_0402_5%~D
1
2
PBAT_SMBCLK <30,43>
PBAT_SMBDAT <30,43>
PBAT_ALARM# <31>
PC194
0.1U_0402_25V4K~D
2
1
Z4307
@
C
PR13
100_0402_5%~D
1
2
PC9
0.1U_0603_25V7K~D
2
1
PR12
100_0402_5%~D
1
2
PC193
2200P_0402_25V7K
2
1
PC10
2200P_0402_50V7K~D
2
1
+PBATT
PJBAT1
SUYIN_200028MR009G502ZL~D
BATT1+ 1
BATT2+ 2
SMB_CLK 3
SMB_DAT 4
BATT_PRES# 5
SYSPRES# 6
BATT_VOLT 7
10 GND
BATT1- 8
11 GND
BATT2- 9
5
4
PD7
@ DA204U_SOT323~D
PR11
10K_0402_1%~D
2
1
PD6
@ DA204U_SOT323~D
1
PD5
@ DA204U_SOT323~D
1
PD4
@ DA204U_SOT323~D
1
Battery Connector
+PBATT
3
2
1
PBAT_PRES# <31>
SUYIN_200028MR009G502ZL
TOP view
Title
Battery Conn
5
Size
Document Number
Date:
Rev
X02
Bali
Sheet
1
38
of
73
Reference COE system power Rev A 04
5 Volt +/-5%
design current: 4.1A
peak current: 5.8A
Min OCP:
5.9A
25
LDO3
PR188
0_0603_5%~D
MAX8734AEEI+_QSOP28~D
GNDA_SYS
GNDA_SYS
+3.3V_SRC
PR40
1K_0402_1%~D
1
2
PAD-OPEN 4x4m
<30> ALWON
<16> THERM_STP#
PR41
0_0402_5%~D
PR35
0_0402_5%~D
2
1
PR33
0_0402_5%~D
2
1
PR34
0_0402_5%~D
2
1
PD19
BAT54S-2-GP
3
1 1
PC185
1U_0603_25V6K
2
MMBZ5245B_SOT23~D
PD17
2
2
PC180
2.2U_1206_25V7M~D
2
PR30
100K_0402_5%~D
2
1
PR31
0_0402_5%~D
2
1
PR39
0_0402_5%~D
2
1
5
IN1
IN2
@
PU15
@
PR207
120_0402_5%~D
PR29
97.6K_0603_1%
1
2
1
2
PR28
84.5K_0402_1%
1
2
PR210
7.5K_0402_5%~D
SN74LVC1G08_SC70-5~D
2
THERM_STP# <16>
G
PQ9
RHU002N06_SOT323
B
GNDA_SYS
+VCC_MAX8734
RUN_ON
PC181
2.2U_1206_25V7M~D
PR179
0_0805_5%~D
C
2
B
PD16
EC11FS2_SOD106~D
2
1
PC17
10U_1206_25V6M~D
PC16
0.1U_0603_25V7K~D
2
1
5
6
7
8
1U_0603_25V6K
PD18
PC187
PC184 BAT54S-2-GP
2
1
1U_0603_25V6K
3
2
1 1
2
2
1
@
<19,30,32,33,40,41,50>
Enable Skip Mode
+5VSUSP OCP
Ton=1/200k * Vo/Vin=1.316us
Toff=1/200k - 1.316us = 3.684us
DeltaI=5V/4.7uH * 3.684us = 3.92A
Iimit=(VILM*0.1)/Rds(on)+1/2 DeltaI
VILM=2*102/(102+84.5)=1.094V *0.1=109.4mV
IC 7% tolerance (min 101.7mV)(Typ 109.4mV)(max 117mV)
Iimit=(VILM)/Rds(on)+1/2 Delta I
Iimit Min=101.7mV/(20mOhm*1.4)+1/2 Delta I=5.86A
Iimit Typ=109.4mV/(16mOhm*1.4)+1/2 Delta I=6.8A
Iimit Max=117mV/(16mohm*1.4)+1/2 Delta I=7.2A
GNDA_SYS
@
<30> EC_PWM3_188Khz
PR38
0_0402_5%~D
2
1
SUSPWROK_5V <41>
PJP3
1
+
2
MAX8734_TON
+5V_SUS
PAD-OPEN 4x4m
+3.3V_SRCP
MAX8734_PRO#
PR37
100K_0402_1%~D
1
2
MAX8734_ILIM3
PR36
102K_0402_1%
1
2
1
+5V_SUSP
PR26
100K_0402_1%~D
1
2
PR32
240K_0402_5%~D
1
2
PJP2
MAX1999_SKIP#
6
5
2
1
PAD-OPEN 4x4m
GNDA_SYS
MAX8734_ILIM5
PR27
2K_0402_1%~D
1
2
PC31
1000P_0402_50V7K~D
2
1
D
+15V_SUSP
+15V_SUS
GNDA_SYS
+VCC_MAX8734
+3.3V_RTC_LDO
PJP18
MAX8734_REF
+3.3V_SRCP
+3.3V_ALW
L-S Rds-on= 16~20m ohm
GNDA_SYS
PU14
TC7SH32FU_SSOP5~D
<30,32,33> SUS_ON
+3.3V_ALW
PC29
1U_0603_10V6K~D
5
1
G
PC174
0.1U_0603_25V7K~D
O
I0
RUN_ENABLE <32>
2
MAX8734_SHDN#
PC30
10U_1206_10V4Z
2
1
3
2
<30,32> AUX_EN
I1
<30,32,33> SUS_ON
FDC655BN_NL_SSOT-6~D
PQ6
SI4800BDY-T1_SO8~D
MAX8734_ILIM5
MAX8734_ILIM3
MAX8734_REF
MAX8734_TON
ON3
ON5
FB3
3
4
12
MAX8734_ON3
MAX8734_ON5
PL23
1
+5V_ALW
11
5
8
13
23
2
MAX8734_FB3
L-S Rds-on (max)

=5.9~7.25m ohms
OUT3
4.7u_SIQHB1250-4R7PF_10A_20%
0_0402_5%~D
ILIM5
ILIM3
REF
TON
GND
PGOOD
22
DL3
MAX8734_DL
MAX8734_FB5
MAX8734_PRO#
PR205
24
MAX8734_DL3
+5V_SUSP
MAX8734_DL5
21
1
9
10
PR209
0_0402_5%~D
@
0_0402_5%~D PR206
2
1
19
OUT5
N.C.
FB5
PRO
+5V_SUSP
PC183
150U_D2E_6.3VM_R18
DL5
LX3
PC27
150U_D2E_6.3VM_R18
DH3
27
PC28
0.1U_0402_10V7K~D
2
1
26
MAX8734_LX3
PR22
0_0603_5%~D
1
2
MAX8734_DH3
PL8
4.7U_STQB1250-4722PF-7A
PR24
0_0402_5%~D
1
2
BST3
+5V_SUSP
LX5
MAX8734_LX5
MAX8734_DH5
15
16
PR178
10K_0805_5%~D
14
DH5
3
2
1
BST5
SHDN
5
6
7
8
LDO5
VCC
GNDA_SYS
PQ39
PC19
1U_0603_10V6K~D
2
1
V+
28
Output Caps ESR

= 25// 25=12.5 m ohms
+3.3V_SRC
PC23
0.1U_0603_25V7K~D
1
2
1
2
3
8
7
6
5
PR21
0_0603_5%~D
2
SKIP
PR20
0_0603_5%~D
1
2
1
2
3
17
PC24
0.1U_0603_25V7K~D
2
1
PQ7
FDS6676AS_SO8~D
PR23
0_0402_5%~D
1
2
PC26
0.1U_0402_10V7K~D
2
1
PC25
150U_D2E_6.3VM_R18
PC182
150U_D2E_6.3VM_R18
PL7
2.0UH+-20%_HMP1340-2R0PF-12A~D
1
2
PR19
0_0603_5%~D
1
2
18
MMBT2222ALT1G_SOT23
PQ40
1
3
3
2
1
S
S
S
+3.3V_SRCP
MAX8734_BST5B
PR177
0_0805_5%~D
+15VS_L 1
2
Place these CAPs

close to FETs
PQ8
SI4810BDY_SO8~D
MAX8734_BST3B
PU2
MAX8734_V+ 20
GNDA_SYS
PC20
4.7U_1206_10V7K~D
2
1
GNDA_SYS
@
4
PD8
RB717F_SOT323~D
2
1
3
PR18
47_0603_5%~D
+VCC_MAX8734 2
1
PC18
1U_0603_10V6K~D
2
1
D
D
D
D
8
7
6
5
PQ5
HAT2198R-EL-E_SO8~D
PC15
2200P_0402_50V7K~D
2
1
PR17
10_1206_5%~D
1
2
+5V_ALW
Place these CAPs

close to FETs
3.3 Volt +/-5%

design current: 7A
Max current: 9.9A
Min OCP: 11.5A
+VCC_MAX8734
PC22
0.1U_0603_25V7K~D
2
1
PR16
0_1206_5%~D
1
2
PC21
4.7U_1206_25V6K~D
2
1
PC14
2200P_0402_50V7K~D
2
1
PC13
0.1U_0603_25V7K~D
2
1
PC12
10U_1206_25V6M~D
PJP1
PAD-OPEN 4x4m
1
2
Unpop 15V charger bump
+15V_SUSP
+DCD C_PWR_SRC
PC11
10U_1206_25V6M~D
+PWR_SRC
PC186
1U_0603_25V6K
DC +3V/ +5V/ +15V

PL6
FBM-L11-453215-900LMAT_1812~D
1
2
PC190
0.47U_0603_10V7K~D
MAX8734 Current Limit Characteristics

min
typ
max
Tolerance
VLIM=0.5V 40mV 50mV 60mV
20%
VLIM=1.0V 93mV 100m 107mV
7%
+3.3VSRC OCP
Ton=1/300k * Vo/Vin=0.578us
Toff=1/300k - 0.578us = 2.752us
DeltaI=3.3V/2uH * 2.752us = 4.54A
VILM=2*100/(100+97.6)=1.01V *0.1=101mV
IC 7% tolerance (min 94mV)(Typ 101mV)(max 108mV)
Iimit Min=94mV/(7.25mOhm*1.4)+1/2 Delta I=11.5A
Iimit Typ=101mV/(5.9mOhm*1.4)+1/2 Delta I=14A
Iimit Max=108mV/(5.9mohm*1.4)+1/2 Delta I=15.3A
Title
5
+3.3V/+5V
Size
Document Number
Date:
Rev
X02
Bali
Sheet
1
39
of
73
Reference COE 1.05/1.5V ISL6227 Rev A04
+1.5VRUNP / +VCCP_1P05VP
PJP6
PAD-OPEN 4x4m
1
2
+VCCP_1P05VP
PJP7
PAD-OPEN 4x4m
1
2
16
PG2/REF
ISL6227_OCSET1
SOFT1
12
ISL6227_SOFT1
PG1
15
GND
ISL6227CA-T_SSOP28~D
PR59
1K_0402_1%~D
1
2
GNDA_DC2
+1.5V_RUN
+1.05V_VCCP
PC40
10U_1206_25V6M~D
PC39
10U_1206_25V6M~D
PC38
0.1U_0603_25V7K~D
2
1
5
6
7
8
@
L-S Rds-on
=9m~11.5m ohms
ISL6227_VSEN1
1
+
2
1
+
2
Output Caps ESR

= 9//9mohms=4.5m ohm
Use PR49 and PR55

for voltage margining
GNDA_DC2
PR52=0, PR60 Nopop, PWM/ HYS

PR52 Nopop, PR60=0, froce PWM
GNDA_DC2 GNDA_DC2
1.5V_RUN_PWRGD <33>
RUN_ON <19,30,32,33,39,41,50>
Layut notes:
Place PC43 need very close Pin1 of PU4, and Pin28 of PU4.
Place PR63 need very close Pin1 of PU4.
Minimize loop including PQ10, PQ13, PL10, PC49, PC52.
Minimize loop including PQ11, PQ12, PL11, PC47, PC48, PC51.
Route GNDA_DC2 using 25mil trace width.
Minimize GNDA_DC2 trace length.
Place PC46, PR48 and PR54 near Pin19 of PU4.
Place PR61 and PR53 near Pin20 of PU4.
Place PC50, PR49 and PR55 near Pin10 of PU4.
Place PR52 and PR60 near Pin9 of PU4.
Place PR56, PC54, PR57, PC53 near Pin 18, 17, 11, 12 of PU5.
Place PR46, PR47 near Pin7, 22 of PU4.
Place PR44, PC44 near Pin23, 25 of PU4.
Place PR45, PC45 near Pin6, 4 of PU4.
Route 1.05V Boot and 1.5V Boot using 25mil trace width and minimze length.
Need large copper fill areas to PQ10, PQ11, PQ12 and PQ13 for thermal inprovment.
Minize length of 1.5V phase node and 1.05V phase node.
PC33, PC34,PC35 and PC36 need close Pin5, 6, 7, 8 of PQ10.
PC37, PC38, PC39 and PC40 need close Pin5, 6, 7, 8 of PQ11.
Route +1.5V_1P05VP_PWRSRC using 50 mil trace width and minimize length.
"Route VSEN1 and VSEN2 away from the inductor and switch node.
Sense Vout directly at the output bulk capacitor"
PC48
330U_D2E_2.5VM_R9~D
ISL6227_EN1
11
PC47
330U_D2E_2.5VM_R9~D
PC51
10U_0805_6.3V5K~D
2
1
EN1
OCSET1
PR49
5.11K_0402_1%~D
2
1
3
10
9
PR52
0_0402_5%~D
1
2
SOFT2
PGND1
VSEN1
VOUT1
1.05V_RUN_PWRGD <33>
GNDA_DC2
PR63
GND
0_0603_5%~D
2
1 GNDA_DC2
GNDA_DC2
4
Title
B
PR60
0_0402_5%~D
1
2
17
ISL6227_LGATE1
PR47
1.87K_0402_1%
ISL6227_ISEN1 1
2
PR55
30.1K_0603_1%~D
2
1
PC54
0.01U_0402_25V7K~D
1
2
PC192
0.47U_0603_16V7K
1
2
OCSET2
PL11
1.5uH_SIL104-1R5F_10A_30%~D
1
2
PC50
0.01U_0402_25V7K~D
2
1
EN2
ISEN1
+VCCP_1P05VP
PR50
1K_0603_1%~D
1
2
21
LGATE1
3
2
1
PGND2
VSEN2
VOUT2
ISL6227_PHASE1
1.05 Volt +/-5%

Thermal Design Current: 5.7A
Maximum current: 8.1A
OCP min: 8.8A, Max 19.1A
3
2
1
26
19
20
ISL6227_UGATE1
PQ11
FDS8880_SO8~D
ISEN2
5
6
7
8
LGATE2
22
PHASE1
PQ12
FDS6670AS_SO8~D
27
UGATE1
PR57
124K_0402_1%~D
1
2
PHASE2
ISL6227_BOOT1
PC53
0.01U_0402_25V7K~D
1
2
UGATE2
25
BOOT1
PC37
2200P_0402_50V7K~D
2
1
PC42
0.01U_0402_25V7K~D
2
1
PR45
0_0603_5%~D
2
1
PC41
1U_0603_10V6K~D
2
1
24
GNDA_DC2GNDA_DC2 GNDA_DC2
2
PD21
PJP8
PAD-OPEN 4x4m
1
2
BOOT2
13
14
PC178
1000P_0402_50V7K~D
2
1
PC179
1000P_0402_50V7K~D
2
1
PR61
0_0402_5%~D
2
PJP5
PAD-OPEN 4x4m
1
2
+1.5V_RUNP
23
DDR
VIN
COE A04: Unpop PD21, PC192 for sequencing requirements
GNDA_DC2
PR56
124K_0402_1%~D
1
2
ISL6227_SOFT2
L-S Rds-on= 9m~11.5m ohm
<19,30,32,33,39,41,50> RUN_ON
VCC
ISL6227_OCSET2 18
Use PR48 and PR54

for voltage margining
PR43
10_0805_5%~D
1
2
ISL6227_EN2
28
ISL6227CA-T
8
7
6
5
PQ13
FDS6670AS_SO8~D
ISL6227_LGATE2
PR46
1.43K_0402_1%~D
1
2ISL6227_ISEN2
ISL6227_VSEN2
PR53=0, PR61 Nopop, PWM/ HYS

PR53 Nopop, PR61=0, froce PWM
PC43
2.2U_0805_10V6K~D
2
1
ISL6227_UGATE2
GNDA_DC2
3
PC188
2.2U_0805_10V6K~D
2
1
PR44
0_0603_5%~D
2
1
ISL6227_BOOT2
1
2
3
PR54
28.7K_0603_1%~D
2
1
Output Caps ESR

= 9mohms
PU4
GNDA_DC2
ISL6227_PHASE2
PR51
1K_0603_1%~D
1
2
PR48
19.6K_0402_1%~D
2
1
PC46
330P_0402_50V7K~D
2
1
PR53
0_0402_5%~D
1
2
PC49
330U_D2E_2.5VM_R9~D
PC52
10U_0805_6.3V5K~D
2
1
PL10
3.8UH_SIL1045K-3R8_8A
1
2
1
2
3
+1.5V_RUNP
PC44
0.1U_0603_25V7K~D
1
2
8
7
6
5
PQ10
FDS8880_SO8~D
ISL6227_VCC
1.5 Volt +/-5%

Maximum current: 6.7A
OCP min: 7.4A, max 14.4A
Place these CAPs

close to FETs
PC45
0.1U_0603_25V7K~D
1
2
+5V_SUS
Place these CAPs

close to FETs
ISL6227_BOOT1B
3
PR42
0_0402_5%~D
1
2
PR58
1K_0402_1%~D
2
1
ISL6227_BOOT2B
PD9
BAT54A-7-F_SOT23~L
PC36
2200P_0402_50V7K~D
2
1
PC35
0.1U_0603_25V7K~D
2
1
PC33
10U_1206_25V6M~D
PJP4
PAD-OPEN 4x4m
1
2
PC34
10U_1206_25V6M~D
+PWR_SRC
PL9
FBM-L11-453215-900LMAT_1812~D
+1.5V_1P05VP_PWRSRC
1
2
+1.5VRUNP /+VCCP_1P05VP
Size
Document Number
Date:
Rev
X02
Bali
Sheet
D
40
of
73
Reference Coe Rev. A05
+1.8VSUSP/ +0.9V_DDR_VTT
DDR2 Termination
PL12
FBM-L11-453215-900LMAT_1812~D
+D DR_PWR_SRC
1
2
+5V_ALW +5V_SUS
PR64
10_1206_5%~D
2
1
26
28
DH
POK1
POK2
+0.9V_DDR_PWRGD <33>
27
SUSPWROK_5V <39>
SUSPWROK_1P8V <33>
FB
8
7
6
5
14
PGND2
11
TON
VTT
12
Ton =Ref, f= 450KHz
@ PR170
0_0402_5%~D
2
1
GND
24
PC74
1000P_0402_50V7K~D
2
1
8 SS
SKIP
ILIM
REF
PR75
100K_0402_1%~D
1
2
MAX8632_ILIM
PR78
84.5K_0402_1%
2
1
VTTR
10
PR171
0_0402_5%~D
2
GNDA_DDR
+1.8V_SUSP
0.9 Volt
Design current 0.7A
Peak current 1A
GNDA_DDR
VTTS
PR202
0_0603_5%~D
2
1
PC73
0.22U_0603_10V7M~D
2
1
PR77
17.4K_0402_1%~D
2
1
L-S Rds-on
=3.7(Typ)~4.8 (max) ohms
MAX8632_REF
+1.8V_SUSP
PR72
20_0603_1%~D
MAX8632_REFIN
2
1
Ton open, f= 300KHz
25
MAX8632_FB
PR74
0_0402_5%~D
2
1
<19,30,32,33,39,40,50>
PC72
10U_0805_6.3V5K~D
15
REFIN
MAX8632ETI+_TQFN28~D
RUN_ON
PC64
10U_0805_6.3V5K~D
VOUT
MAX8632_STBY
PC71
10U_0805_6.3V5K~D
16
13
PC70
10U_0805_6.3V5K~D
PGND1
VTTI
PC69
0.1U_0402_10V7K~D
2
1
23
STBY
PC68
0.1U_0402_10V7K~D
2
1
DL
PC75
1U_0603_10V6K~D
2
1
LX
21
MAX8632_AVDD
Output Caps ESR

= 15mohms/ each
SHDN
GND
19
MAX8632_DL
1
2
3
PQ15
IRF7832_SO8~D
3
+
PR73
27.4K_0603_1%~D
2
1
PC65
0.1U_0402_10V7K~D
2
1
PC63
330U_D2E_2.5VM~D
PC62
330U_D2E_2.5VM~D
17
5
29
MAX8632_LX
MAX8632_DL
PC60
1U_0603_10V6K~D
2
1
MAX8632_AVDD
MAX8632_OVP
TP0
VIN
duplicate pull up resistors on Page 33

R573 +3.3V_RUN for power good signal
of +0.9V_DDR_PWRGD, Unpop PR68 from M00.
1
2
3
18
BST
PR68
100K_0402_1%~D
1
2
20
GNDA_DDR
AVDD
2
1_0603_5%~D
22
PR69
1
OVP/ UVP
VDD
PU5
PC61
0.1U_0805_50V7M~D
2
1
MAX8632_DH
PL13
1.5U+-20%_HMP1340-1R5PF-15A
2
1
+3.3V_SUS
+DDR_PWR_SRC
PQ14
IRF7821_SO8~D
+1.8V_SUSP
SUSPWROK_5V
PR67
100K_0402_1%~D
1
2
PR184
0_0603_5%~D
1
2
PR66
@ 0_0402_5%~D
2
1
8
7
6
5
1.8 Volt +/-5%

Design Current: 10.2A
Peak Current: 14.5A
OCP min 15.7A
PR65
0_0402_5%~D
2
1
PR185
0_0603_5%~D
1
2
Place these CAPs

close to FETs
PC59
4.7U_1206_10V7K~D
2
1
PD10
RB751V-40_SOD323~D
PC58
2200P_0402_50V7K~D
2
1
PC55
10U_1206_25V6M~D
PJP9
PAD-OPEN 4x4m
1
2
PC57
0.1U_0603_25V7K~D
2
1
PC56
10U_1206_25V6M~D
+PWR_SRC
+0.9V_DDR_VTTP
1
0.9 Volt
VTTR current limit: +-32mA typ
GNDA_DDR
GNDA_DDR
GNDA_DDR
GNDA_DDR
PJP12
PAD-OPEN 4x4m
1
2
+1.8V_SUSP
PJP13
PAD-OPEN 4x4m
1
2
+1.8VSUS OCP
+1.8V_SUS
Toff=1/450k (1-1.8/19) = 2.22us

DeltaI=1.8V/1.5uH * 2.22us = 2.66A
VILM=2*100/(100+84.5)=1.08V *0.1=108mV
IC 10% tolerance (min 97.2mV)(Typ 108mV)(max 118.8mV)
Iimit Min=97.2mV/(4.8mOhm*1.4)+1/2 Delta I=15.7A
(10A,320mils ,Via NO.=20)
PJP14
A
+0.9V_DDR_VTTP
2
PAD-OPEN 4x4m
+0.9V_DDR_VTT
(2A,200mils ,Via NO.=4)
Title
5
+1.8VSUSP/ +0.9V_DDR_VT
Size
Document Number
Date:
Rev
X02
Bali
Sheet
1
41
of
73
IMVP-6 solution
-For Merom: 3-phase: Thermal Design Current 35A / Iccmax 44A
-For Yonah: 3-phase: Thermal Design Current 28.8A / Iccmax 36A
Reference COE Vcore Rev A 03

H
+PWR_SRC
PR80
7.32K_0603_1%
2
1
CROWBAR
VCC
VCC
SW2
DPRSLP
SW3
21
G
S
PR104
10_0402_1%~D
1
2
PC76
220U_CE-AX_25V_M ~D
PC82
10U_1210_25V6M~D
2
1
PC81
10U_1210_25V6M~D
2
1
CROWBAR
VCC
DRVH
SW
GND
DRVL
PC105
2200P_0402_50V7K~D
2
1
PQ21
D
S
AD3419_DRVL3
G
S
+PWR_SRC
PR124
93.1K_0603_1%
2
1
IRF7821_SO8~D
3
1
AD3419_SW3
ADP3419JRM_MSOP-10
DRVLSD#
AD3419_DRVH3
SD#
+VCC_CORE
PR118
10_0402_1%~D
1
2
B
PC111
1500P_0402_50V7K~D
PL17
0.45U_MPC1040LR45_27A_20%~D
10
PQ22
PR123
93.1K_0603_1%
2
1
BST
PR120
93.1K_0603_1%
2
1
IN
PC109
0.33U_0603_10V7K
2
1
PR116
0_0603_5%~D
1
2
PR115
147K_0402_1%~D
PU9
PR117
CPU _PWR_SRC
PD13
RB751V-40_SOD323~D
AD3419_BST3
2
1
PC112
1000P_0402_50V7K~D
2
1
Rdson_typ
4.8mohms
PC103
4.7U_0805_10V6K
2
1
PH2
220K_0402_5%_TH11-4H104FT
2
1
PR113
71.5K_0402_1%
1
2
PC102
1800P_0402_50V7K
2
1
PC101
470P_0603_50V8J~D
2
1
+5V_RUN
0_0402_5%~D
PC80
0.1U_0805_25V7K~D
2
1
PQ16
20
19
Place PH2 close to

output inductor of phase 1.
PC100
470P_0603_50V8J~D
2
1
18
ADP3207_CSSUM
17
16
ADP3207_CSREF
ADP3207_RAMPADJ 15
1
2
PR114 280K_0603_1%
1
PC79
2200P_0402_50V7K~D
2
1
3
D
IRF7821_SO8~D
D
AD3419_DRVL2
GND
CSCOMP
CSSUM
CSREF
LLSET
RAMPADJ
RT
14
2
154K_0603_1%
PR111 1
13
12
PR110
2
NOTE: ( Connection VCORE output Cap GND)

De-populate PR245 and PR246 when CPU is present
+VCC_CORE
PR119
100_0603_5%~D
1
2
@
PR122
100_0603_5%~D
1
2
56.2K_0402_1%
1
11
1000P_0402_50V7K~D
PC104
2
1
VSSSENSE <8>
@
PC110
1000P_0402_50V7K~D
2
1
160K_0603_1%
1
2
PR109
1
2
NOTE:PR111 is reversed for loop

gain measurement purpose
VCCSENSE <8>
RRPM
ILIMIT
VRPM
2
<10,23> DPRSLPVR
PR112
0_0603_5%~D
ADP3419JRM_MSOP-10
+VCC_CORE
PL16
0.45U_MPC1040LR45_27A_20%~D
AD3419_SW2
PC108
10U_1210_25V6M~D
2
1
STSET
22
PC107
10U_1210_25V6M~D
2
1
23
GND
DRVL
PC106
0.1U_0805_25V7K~D
2
1
SW1
SS
0_0402_5%~D
1
0_0402_5%~D
1
0_0402_5%~D
1
PC92
10U_1210_25V6M~D
2
1
24
PC91
10U_1210_25V6M~D
2
1
CROWBAR
ADP3207_PWM3
PR103
2
PR105
2
PR106
2
PWM3
AD3419_DRVH2
PC90
0.1U_0805_25V7K~D
2
1
PC89
2200P_0402_50V7K~D
2
1
ADP3207_PWM2
SW
PC99
1500P_0402_50V7K~D
DRVLSD#
10
9
ADP3207_PWM1
PWM2
PR85
10_0402_1%~D
1
2
PQ19
26
BST
DRVH
PQ20
PWM1
COMP
PR181
499_0402_1%
PC78
0.33U_0603_10V7K
2
1
S
SD#
FB
10
1
IN
ADP3207_#OD
ADP3207_#DCM
27
IRF7821_SO8~D
28
OD
DCM
PU8
PC87
0.33U_0603_10V7K
2
1
ADP3207_VRTT
PC98
470P_0402_50V7K
2
1
PC97
0.012U_0402_16V7K~D
2
1
PC86
4.7U_0805_10V6K
2
1
VRTT
29
25
1
30
ADP3207_TTSENSE
32
31
PSI
VCC
33
DPRSTP
35
34
VID6
VID5
36
ADP3207JCP-RL_LFCSP-40
CPU _PWR_SRC
FBRTN
PD12
RB751V-40_SOD323~D
AD3419_BST2
2
1
+VCC_CORE
Rdson_typ
4.8mohms
+5V_RUN
CLKEN
FDS7088SN3_SO8~D
PGDELAY
TTSENSE
PC94
150P_0402_50V8J
2
1
PR101
PC96
PC95
1.65K_0402_1% 220P_0402_50V8K
18P_0402_50V8K
2
1
1
2 1
2
PR102
28.7K_0603_1%~D
PWRGD
3
4
@
PQ18
2N7002_SOT23~D
2
G
EN
PR100
0_0603_5%~D
1
2
1
PC93
4700P_0402_25V7K
1
2
AD3419_DRVL1
1
PR930_0402_5%~D
1
PR940_0402_5%~D
2
1
PR950_0402_5%~D
2
1
PR960_0402_5%~D
2
1
PR970_0402_5%~D
2
37
38
PC88
1000P_0402_50V7K~D
1
2
ADP3419JRM_MSOP-10
IMVP6_PROCHOT# <31>
VID4
VID3
PU7
VID2
PR99
0_0402_5%~D
2
1
<30,31,33> RUNPWROK
VID0
<6> CLK_ENABLE#
40
<23,33> IMVP_PWRGD
39
0_0402_5%~D
1
2
1
2
PR92
0_0402_5%~D
1
2
PR98
0_0402_5%~D
VID1
1
2
PR90
1.91K_0603_1%~D
PR89
1.91K_0603_1%~D
2
1
<8> VID0
PR91
FDS7088SN3_SO8~D
PR88
0_0402_5%~D
2
1
DRVL
AD3419_SW1
@
<8> H_PSI#
<7,22> H_DPRSTP#
<8> VID6
<8> VID5
<8> VID4
<8> VID3
<8> VID2
<8> VID1
8
7
FDS7088SN3_SO8~D
NOTE:Populate PR86 and de-pop PR88 for 3 phase,

De-POP PR86 and populate PR88 for 2 phase.
0_0402_5%~D
+3.3V_RUN
SW
GND
+
2
PL15
0.45U_MPC1040LR45_27A_20%~D
ADP3207_VCC
PR86
AD3419_DRVH1
DRVLSD#
10
9
BST
DRVH
PC85
1500P_0402_50V7K~D
SD#
PQ17
IN
+1.05V_VCCP
PU6
CPU _PWR_SRC
PR83
10_0603_5%
PR81
0_0603_5%~D
1
2
PC77
4.7U_0805_10V6K
2
1
<30,31,33> RUNPWROK
PH1
100K_0603_5%_TH11-4H104FT
2
1
2
+5V_RUN
PC84
1U_0805_25V4Z~D
PC83
0.01U_0402_25V7K~D
2
1
PD11
RB751V-40_SOD323~D
AD3419_BST1
2
1
+5V_RUN
@
PR82
0_0402_5%~D
Thermistor PH1 should be placed

close to the hot spot of the VR
PL14
FBM-L18-453215-900LMA90T_1812~D
A

Title
+VCORE
Size
Document Number
Date:
Rev
X02
Bali
8
42
Sheet
1
of
73
Reference COE charger Rev A 11
+DC_IN discharge path
Smart Charger
+PWR_SRC
PJP19
PAD-OPEN 4x4m
1
2
D
PQ27 @
RHU002N06_SOT323
S
CCV
MAX8731_CCI
CCI
MAX8731_CCS
CCS
27 MAX8731_CSSN
DLO
REF
DAC
12
PGND
CSIP
PC191
3300P_0402_50V7K
PC175
220P_0402_50V7K~D
17
15
FBSB
16
GND
MAX8731_TQFN28~D
@
2
1
PR208
1K_0603_5%
2
1
PC119
10U_1206_25V6M~D
2+VCHGR_L
1
19
18
CSIN
+VCHGR
PL20
MAX8731_SW
20
FBSA
PC118
10U_1206_25V6M~D
PR139
0.01_2512_1%~D
4
3
PC117
0.1U_0805_50V7M~D
2
1
Place these CAPs

close to FETs
8.2U_HMU1356-8R2_5.8A_20%~D
3
2
1
PC131
1U_0603_10V6K~D
2
1
PC130
0.01U_0402_25V7K~D
2
1
PC129
0.01U_0402_25V7K~D
2
1
PC133
0.01U_0402_25V7K~D
2
1
GNDA_CHGR
PC132
0.1U_0402_10V7K~D
2
1
PR143
10K_0402_1%~D
2
1
0_0603_5%~D
2
1 GNDA_CHGR
PC134
0.1U_0402_10V7K~D
2
1MAX8731_DAC
MAX8731_REF
PR142
GND
LX
PC127
10U_1206_25V6M~D
IINP
PC126
10U_1206_25V6M~D
MAX8731_CCV
PD20
PC125
10U_1206_25V6M~D
MAX8731_IINP
24 MAX8731_DHI
PR174
23 1
2
1_0603_1%~D
PR140
4.7K_0402_5%~D
2
1
<30,38> PBAT_SMBDAT
DHI
GNDA_CHGR
BATSEL
PC123
1U_0603_10V6K~D
1
2
PC124
0.1U_0805_50V7M~D
2
1
14
21 MAX8731_LDO
100_0402_5%~D
PR199
GNDA_CHGR
LDO
PC116
2200P_0402_50V7K~D
2
1
SDA
PQ31
SI4810BDY_SO8~D
SCL
25
3
2
1
10
BST
5
6
7
8
VDD
GNDA_CHGR
PQ30
SI4800BDY-T1_SO8~D
ACOK
11
PC115
1U_0603_10V6K~D
1
2
PR138
33_0603_1%~D
1
2
13
MAX8731_VCC
PR136
0_0603_5%~D
1
2MAX8731_BSTB
PD14
RB751V-40_SOD323~D
2
1
MAX8731_ACOK
26
PC121
0.1U_0603_25V7K~D
2
1
ACIN
VCC
PC122
0.1U_0402_10V7K~D
2
1
<30,38> PBAT_SMBCLK
MAX8731_ACIN
+5V_ALW
GNDA_CHGR
DCIN
<16,30> ACAV_IN
PR137
0_0402_5%~D
1
2
PU10
22
+DC_IN_SS
+5V_ALW
PC189
0.01U_0603_25V
2
1
PC120
0.01U_0402_25V7K~D
2
1
PC114
1U_0805_25V4Z~D
2
1
@
PR173
0_0402_5%~D
CSSN
PR135
49.9K_0402_1%~D
2
1
PR172
0_0402_5%~D
PR133
PR134
15.8K_0402_1%~D
10K_0402_1%~D
ACAV_IN
2
1
1
2MAX8731_LDO
GND
+DC_IN
GNDA_CHGR
MAX8731_ACSNS
PR132
365K_0402_1%~D
1
2
C
PR130
100K_0402_1%~D
2
1
28 MAX8731_CSSP
PR129
10K_0402_1%~D
2
1
<16,30> ACAV_IN
CSSP
2
G
+VCHGR
8
7
6
5
PR127
470K_0402_5%~D
2
1
PC177
0.1U_0805_50V7M~D
2
1
PQ23
SI4835BDY-T1-E3 _SO8~D
1
2
3
PQ28
RHU002N06_SOT323
2
G
D
N657586
PR126
10K_0402_1%~D
1 2
1
PC113
10U_1206_25V6M~D
+DC_IN_SS
1
2
3
PL19
FBM-L11-453215-900LMAT_1812~D
1
2
5
6
7
8
8
7
6
5
CHRG_IN
PR125
0.01_2512_1%~D
PC176
2200P_0402_50V7K~D
2
1
PQ26
SI4835BDY_SO8~D
MAX8731_CSIP
MAX8731_CSIN
+VCHGR
GNDA_CHGR
GNDA_CHGR
PC142
100P_0402_50V8K
2
1
+5V_ALW
4.32M
301K 56.2K
27.4K
90
4.43
976K
49.9K
9.31K 38.3K
13.3K
N/A
PQ32
2N7002_SOT23~D
2
G
+5V_ALW
5
IN+
IN-
O
4
PC143
0.01U_0402_25V8K
2
1
PR144 PR147 PR149 PR150 PR201
3.17
Layout Notes:
Minimize loop including PQ30,PL20,PR139,PC124,PC125,PC126,PC127.
Place PC117,PC118,PC119 very close PQ30 pins 5,6,7,8.
Place PC175 near Pin23.
Place PC189 near Pin15.
IN+
PU12A
LM393DR_SO8~D
1
PC140
100P_0402_50V8K
2
1
IN-
PC137
10P_0402_50V8J~D
2
1
4
4
PC139
100P_0402_50V8K
2
1
<31> ADAPT_TRIP_SEL
PC141
0.01U_0402_25V8K
2
1
@ PR201
38.3K_0402_1%~D
PR150
PR149
27.4K_0402_1%
56.2K_0402_1%
2
1 2
1
PC138
0.01U_0402_25V8K
2
1
Trip current (A)
65
ADAPT_OC <31>
Adapter (W)
+3.3V_ALW
PR146
100K_0402_5%~D
2
1
PR147
301K_0402_1%
2
1
PR144
4.32M_0402_1%
1
2
PR148
0_0402_5%~D
1
2
PR145
100K_0402_1%~D
2
1
+5V_ALW
MAX8731_REF
The charger UL design for UMA 65W adapter.

Discrete 90w adapter need change;
PR144 to 976K.
PR147 to 49.9K.
PR149 to 13.3K.
PR150 to 9.31K.
PR201 to 38.3K
7
PU12B
LM393DR_SO8~D
A
Title
3
Charger
Size
Document Number
Date:
Rev
X02
Bali
Sheet
1
43
of
73
U8A
1 C327
C336
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
2@ 2
2@
1 C344
C355
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
2@ 2
2@
1 C357
C362
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
2@ 2
2@
1 C368
C382
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
2@ 2
2@
1 C388
C397
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
2@ 2
2@
1 C400
C414
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
2@ 2
2@
1 C417
C431
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
2@ 2
2@
1 C433
C445
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
2@ 2
2@
1 C452
C464
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
2@ 2
2@
1 C467
C480
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
2@ 2
2@
1 C487
C494
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
2@ 2
2@
1 C495
C505
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
AD5
AD6
AE6
AE7
AD7
AC7
AE9
AE10
AD10
AC10
AE12
AE13
AD13
AC13
AC15
AD15
AE15
AE16
AC18
AD18
AE18
AE19
AC21
AD21
AE21
AE22
AD22
AD23
AF25
AE25
AE24
AD24
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
CLK_PCIE_VGA
AE3
CLK_PCIE_VGA#
AE4
2@
PLTRST_DELAY#
R630
AC6
1
2
0_0402_5%~D
1
2
2@ R76
0_0402_5%~D
<6> CLK_PCIE_VGA
<6> CLK_PCIE_VGA#
<23> PLTRST_DELAY#
<6> XTALIN_CLK_GEN
IN
GND
XTALIN_R
1
2
@ R77
0_0402_5%~D
27MHz_16PF_6P27000126~D
XTALOUT
<6> XTALSSIN_CLK_GEN
XTALSSIN_R
2@ R74
1
2
0_0402_5%~D
PEX_RST_N
AD4
AC4
AE1
AD2
AD1
U9
AD3
DACA_VREF
AB4
R87
I2CB_SDA
HSYNC_VGA
VSYNC_VGA
RED_VGA
BLU_VGA
GRN_VGA
2@ R69
1
2
DACAVREF
1
C57
TV_C_VGA
TV_CVBS_VGA
TV_Y_VGA
DACB_VREF
E7
DACBVREF
2
2.2K_0402_5%~D 2@
2
2.2K_0402_5%~D 2@
NVIDIA Johnson's recommend

from 0715 mail
HSYNC_VGA <20>
VSYNC_VGA <20>
RED_VGA <20>
BLU_VGA <20>
GRN_VGA <20>
124_0402_1%~D
<---CRT
C
2
0.01U_0402_16V7K~D 2@
TV_C_VGA <20>
TV_CVBS_VGA <20>
TV_Y_VGA <20>
DACB_RSET
1
C319 2@ 1
VGADDCCLK
VGADDCDAT
I2CB_SCL
I2CB_SDA
LDDC_CLK_VGA
LDDC_DATA_VGA
D10
E10
F9
F10
E9
D8
C7
B7
1
R348
DEVID3 <49>
2@ R78
1
2
10K_0402_5%~D
DACB_HSYNC
DACB_VSYNC
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_IDUMP
DACB_RSET
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA
I2CB_SCL
RAM_CFG2 <49>
RAM_CFG3 <49>
DEVID3
E6
F5
F4
D5
E4
L9
D6
IFPAB_VPROBE
IFPCD_VPROBE
2
2@ R357 124_0402_1%~D
2 0.01U_0402_16V7K~D
<---CRT
<---DVI
<---LVDS
LDDC_CLK_VGA <19>
LDDC_DATA_VGA <19>
N6
M5
B
XTALIN
XTALOUT
XTALOUTBUFF
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
AE27
AD27
AE26
AD26
AD25
D7
C1
XTALSSIN
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
AF13
AF14
2@ G72-N-A1_BGA533~D
2@
R614
10K_0402_5%~D
10K_0402_5%~D
Stuff R74,R76 and No stuff

R75,R77 for clock Gen 27MHz
PEX_REFCLK
PEX_REFCLK_N
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_IDUMP
DACA_RSET
@
R75
1
2
0_0402_5%~D
2 18P_0402_50V8J~D
J4
RAM_CFG2
RAM_CFG3
@
R615
10K_0402_5%~D
<49> XTALSSIN
C54 @
C2
XTALOUTBUFF C3
<49> XTALOUTBUFF
B1
MIOB_VREF
R83
DEVID2 <49>
DEVID0 <49>
DEVID1 <49>
R424
10K_0402_5%~D
2@
R613
2@
+3.3V_RUN
+3.3V_RUN
R370 2@
470K_0402_5%~D
2
G
XTALIN
R2
K2
K3
LDDC_DATA_VGA
<20> CLK_DDC2_VGA
CLK_DDC2_VGA 1
D
@
1 18P_0402_50V8J~D
Y1
@
GND
OUT 3
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT_N
DEVID2
DEVID0
DEVID1
C55
2
B
G4
F1
G1
F2
R85
RAM_CFG0 <49>
RAM_CFG1 <49>
2
2.2K_0402_5%~D 2@
2
2.2K_0402_5%~D 2@
2@ 2
2@
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CTL3
RAM_CFG0
RAM_CFG1
R376 2@
470K_0402_5%~D
VGADDCCLK
<20> DAT_DDC2_VGA
DAT_DDC2_VGA
Q22
2@
2N7002W-7-F_SOT323~D
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3
2
G
1 C322
C328
+3.3V_RUN
LDDC_CLK_VGA
3
S
2@ 2
2@
YPRPB_DET# <20>
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
THERMTRIP_VGA# <16>
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
1 C308
C318
YPRPB_DET#
R634
0_0402_5%~D
1 C302
C313
2@ 2
2@
THERMTRIP_VGA#
2@ 2
2@
GPIO1_SW_VREF <45,48>
BIA_PWM_VGA <19>
ENVDD_VGA <19>
PANEL_BKEN_VGA <19>
GFX_CORE_CNTRL <50>
PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
@ R629
0_0402_5%~D
1
2
1 C291
C298
DVO / GPIO
2@ 2
2@
GPIO1_SW_VREF
BIA_PWM_VGA
ENVDD_VGA
PANEL_BKEN_VGA
GFX_CORE_CNTRL
PEG_MRX_GTX_P0
0.1U_0402_10V7K~D
PEG_MRX_GTX_N0
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N1
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P2
0.1U_0402_10V7K~D
PEG_MRX_GTX_N2
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P3
0.1U_0402_10V7K~D
PEG_MRX_GTX_N3
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P4
0.1U_0402_10V7K~D
PEG_MRX_GTX_N4
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P5
0.1U_0402_10V7K~D
PEG_MRX_GTX_N5
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P6
0.1U_0402_10V7K~D
PEG_MRX_GTX_N6
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P7
0.1U_0402_10V7K~D
PEG_MRX_GTX_N7
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P8
0.1U_0402_10V7K~D
PEG_MRX_GTX_N8
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P9
0.1U_0402_10V7K~D
PEG_MRX_GTX_N9
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_P10 0.1U_0402_10V7K~D
PEG_MRX_GTX_N10
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N11
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N12
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N13
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N14
2
1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N15
2
1
0.1U_0402_10V7K~D
A9
D9
A10
B10
C10
C12
B12
A12
A13
B13
B15
A15
B16
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
DACs
PEG_MRX_GTX_N[0:15]
<12> PEG_MRX_GTX_N[0:15]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
I2C
PEG_MRX_GTX_P[0:15]
<12> PEG_MRX_GTX_P[0:15]
Part 1 of 5
TEST
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
PCI EXPRESS
PEG_MTX_GRX_N[0:15]
<12> PEG_MTX_GRX_N[0:15]
AF1
AG2
AG3
AG4
AF4
AF5
AG6
AG7
AF7
AF8
AG9
AG10
AF10
AF11
AG12
AG13
AG15
AG16
AF16
AF17
AG18
AG19
AF19
AF20
AG21
AG22
AF22
AF23
AG24
AG25
AG26
AF27
CLK
PEG_MTX_GRX_P[0:15]
<12> PEG_MTX_GRX_P[0:15]
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
VGADDCDAT
Q23 2@
2N7002W-7-F_SOT323~D
Title
NVG72 PCIE,GPIO,CLK
Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
44
of
73
FBAD[0:63]
U8C
DQMA#[0:7] <48>
U8B
FBAA4
FBARAS#
FBAA5
FBA_BA1
FBBA2
FBBA4
FBBA3
FBACS1#
FBACS0#
FBAA11
FBACAS#
FBAWE#
FBA_BA0
FBBA5
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
D21
F22
F20
A21
V27
W22
V22
V24
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
A22
E22
F21
B21
V26
W23
V23
W27
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
B22
D22
E21
C21
V25
W24
U24
W26
DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7
R343 2@
1K_0402_5%~D
2
1
FBACS1# <48>
FBACS0# <48>
FBACAS# <48>
FBAWE# <48>
FBA_BA0 <48>
FBA_RST# <48>
R438 2@
10K_0402_5%~D
IFPC_TXC
IFPC_TXC_N
IFPC_TXD0
IFPC_TXD0_N
IFPC_TXD1
IFPC_TXD1_N
IFPC_TXD2
IFPC_TXD2_N
J3
IFPCD_RSET
3GIO_ADR_0 <49>
3GIO_ADR_1
3GIO_ADR_2
3GIO_ADR_1 <49>
3GIO_ADR_2 <49>
MIO_A_HSYNC
C4
MIOA_HSYNC
NC_0
NC_1
NC_2
NC_3
D12
E12
F12
C13
R349
+3.3V_RUN
2@
BUFRST_N
A6
STEREO
F7
SWAPRDY
THERMDN
THERMDP
A7
C9
B9
VGA_THERMDN, VGA_THERMDP routing

together. Trace width / Spacing = 10 / 10 mil
VGA_THERMDN
VGA_THERMDN <16>
@ C346
2200P_0402_50V7K~D
ROM_SCLK
ROM_SI
ROM_SO
ROMCS_N
SERIAL
D2
F3
D3
D1
VGA_THERMDP
VGA_THERMDP <16>
Place cap close to U28(G72)
2@ G72-N-A1_BGA533~D
C
VREF=VDDQ x Rb(Ra+Rb)
VREF=1.26V=0.7 x VDDQ
+1.8V_RUN
2@
R601 @
909_0402_1%~D
C396
2@
GPU_SW_VREF
1
<44,48> GPIO1_SW_VREF
2@ G72-N-A1_BGA533~D
1.18K_0402_1%~D
Ra
2@ R388
2
1
10mil
CLKA0 <48>
CLKA0# <48>
CLKA1 <48>
CLKA1# <48>
0.022U_0402_16V7K~D
10mil
1
FBA_VREF
IFPAB_RSET
3GIO_ADR_0
2@
R355
2@
CLKA0
CLKA0#
CLKA1
CLKA1#
U6
V1
W1
T1
R1
T3
T2
V2
V3
PEX_PLL_EN_TERM100 <49>
SUB_VENDOR <49>
FBA_CKE <48>
A16
L24
K23
M22
N22
M23
M24
K22
FBA_BA1 <48>
R394
FB_VREF
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_REFCLK
FBA_REFCLK_N
FBA_DEBUG
FBA_RST#
FBAA7
FBAA10
FBA_CKE
FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1
FBARAS# <48>
1K_0402_5%~D
2
1
G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24
PEX_PLL_EN_TERM100
SUB_VENDOR
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
Part 2 of 5
A2
B3
A3
D4
A4
B4
B6
P4
C6
G5
V4
511_0402_1%~D
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
MEMORY INTERFACE
A26
C24
B24
A24
C22
A25
B25
D23
G22
J23
E24
F23
J24
F24
G23
H24
D16
E16
D17
F18
E19
E18
D20
D19
A18
B18
A19
B19
D18
C19
C16
C18
N26
N25
R25
R26
R27
T25
T27
T26
AB23
Y24
AB24
AB22
AC24
AC22
AA23
AA22
T24
T23
R24
R23
R22
T22
N23
P24
AA24
AA27
AA26
AB25
AB26
AB27
AA25
W25
MIO_A_D0
MIO_A_D1
MIO_A_D2
MIO_A_D3
MIO_A_D4
MIO_A_D5
MIO_A_D6
MIO_A_D7
MIO_A_D8
MIO_A_D9
MIO_A_D10
Part 3 of 5
10K_0402_5%~D
2
1
DQSA_RN[0:7] <48>
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
R89
10K_0402_5%~D
2
1
DQSA_RN[0:7]
DQSA_WP[0:7] <48>
T4
U4
N4
N5
R5
R4
T5
T6
R6
P6
W5
W6
W3
W2
AA2
AA3
AB1
AA1
AB3
AB2
NC
DQSA_WP[0:7]
LCD_ACLK+_VGA
LCD_ACLK-_VGA
LCD_A0+_VGA
LCD_A0-_VGA
LCD_A1+_VGA
LCD_A1-_VGA
LCD_A2+_VGA
LCD_A2-_VGA
LCD_ACLK+_VGA
LCD_ACLK-_VGA
LCD_A0+_VGA
LCD_A0-_VGA
LCD_A1+_VGA
LCD_A1-_VGA
LCD_A2+_VGA
LCD_A2-_VGA
GENERAL
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
FBBA[2:5] <48>
LVDS/TMDS
FBAA[0:11] <48>
FBBA[2:5]
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBAD[0:63] <48>
FBAA[0:11]
DQMA#[0:7]
Rb
Q55
@
2N7002_SOT23~D
2
G
Calibration
Stuff for G74
GDDR3
FB_CALx_PD_VDDQ
60
FB_CALx_PU_GND
40
FB_CALx_TERM_GND
60
VREF RATIO
0.7xFBVDDQ
Title
NVG72 Memory Interface,LVDS

Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
45
of
73
+1.22V_GFX_PCIE
C342
2@
C389
2@
E15
F15
F16
J17
J18
L19
N19
R19
U19
W19
2@ 2
2@ 2
4700P_0402_25V7K~D
C471
2@ 2
4700P_0402_25V7K~D
C468
2@ 2
0.022U_0402_16V7K~D
C399
2@ 2
0.022U_0402_16V7K~D
C470
2@ 2
0.022U_0402_16V7K~D
C472
2@ 2
0.022U_0402_16V7K~D
C473
0.1U_0402_10V7K~D
C463
2@ 2
0.1U_0402_10V7K~D
C462
4.7U_0603_6.3V6M~D
C501
2@ 2
C350
2@
2@ 2
2@ 2
4700P_0402_25V7K~D
C425
2@ 2
4700P_0402_25V7K~D
C415
2@ 2
0.022U_0402_16V7K~D
C437
2@ 2
0.022U_0402_16V7K~D
C439
2@ 2
0.1U_0402_10V7K~D
C435
0.1U_0402_10V7K~D
C469
2@ 2
0.1U_0402_10V7K~D
C436
0.1U_0402_10V7K~D
C461
2@ 2
F17
F19
J19
J22
L22
M19
P22
T19
U22
Y22
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
2@
F6
G6
J6
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
W4
Y4
L4
IFPAB_PLLVDD
V5
40mA
IFPCD_PLLVDD
M4
40mA
C376
0.1U_0402_10V7K~D
2@
2@
DACA_VDD
DACB_VDD
IFPAB_IOVDD
R338
2
2@
10K_0402_5%~D
R73
1
AE2
F8
DACA_VDD 70mA
DACB_VDD 140mA
H4
PLLVDD
D13
FBA_PLLAVDD
FBA_PLLVDD
D14
FBCAL_PD_VDDQ
D15
CLAMP
D11
2@
2@
FBCAL_PD_VDDQ
2
2@
10K_0402_5%~D
2@ R390
1
2
2@
2@
2
2
2@
L22 2@
BLM11A121S_0603~D
1
2
2@
C52
0.1U_0402_10V7K~D
2@
+2.5V_RUN
This is NC for G72. It was

there to support NVxx
+1.8V_RUN
60.4_0402_1%~D
+3.3V_RUN
G72-N-A1_BGA533~D
L20 2@
BLM11A121S_0603~D
2
1
1
DACA_VDD
C305
2@
G72_PLLVDD
C347
2@
2@
2
C288
2@
C306
2@
DACB_VDD
2@
2@
2
C50
4.7U_0603_6.3V6M~D
C286
10U_0805_10V4Z~D
C276
10U_0805_10V4Z~D
L21 2@
1
2
+1.8V_RUN
BLM11A121S_0603~D
1
IFPAB_PLLVDD
FBA_PLLAVDD
PLLVDD
C56
4.7U_0603_6.3V6M~D
C45
4.7U_0603_6.3V6M~D
C410
0.1U_0402_10V7K~D
C429
0.1U_0402_10V7K~D
C359
0.1U_0402_10V7K~D
C391
0.1U_0402_10V7K~D
C428
0.1U_0402_10V7K~D
+3.3V_RUN
1
MIO_A_VDDQ_0
MIO_A_VDDQ_1
MIO_A_VDDQ_2
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
C343 2@
0.1U_0402_10V7K~D
2@
2
2@ L25
2
1
BLM11A121S_0603~D
0.1U_0402_10V7K~D
C427
2@ 2
MIOBCAL_PD_VDDQ
C301
2
4.7U_0603_6.3V6M~D
+1.22V_GFX_PCIE
L30 2@
BLM11A121S_0603~D
2
1
0.1U_0402_10V7K~D
2@ 2
4.7U_0603_6.3V6M~D
C504
+1.8V_RUN
J5
+3.3V_RUN
1
+1.8V_RUN
1
K5
K6
L6
470P_0402_50V7K~D
C412
2@
180mA
20mA
Y6
AA5
+1.22V_GFX_PCIE
L9 2@
2
1
C287
2@
470P_0402_50V7K~D
PEX_PLLAVDD
2.2U_0603_6.3V6K~D
C392
2@
F13
F14
J12
J13
J15
J16
2.2U_0603_6.3V6K~D
4700P_0402_25V7K~D
C377
2@
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C390
2@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C356
2@
0.1U_0402_10V7K~D
1U_0603_10V6K~D
+3.3V_RUN
VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
2@
1
C49
C341
1U_0603_10V6K~D 0.01U_0402_16V7K~D
W9
W10
W11
W12
C411
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
2@
1
4700P_0402_25V7K~D
C370
0.022U_0402_16V7K~D
2200P_0402_50V7K~D
0.1U_0402_10V7K~D
C401
2@
2@
1
2@
4700P_0402_25V7K~D
2@
1
0.01U_0402_16V7K~D
C420
2@
C387
2@
2@
1
2 2@
2@
C340
2@
1
2@
C303
4700P_0402_25V7K~D
C403
2@
C386
2@
2@
1
C295
4.7U_0603_6.3V6M~D
2 2@
C323
4700P_0402_25V7K~D
C366
2@
G72_PLLVDD
2
2@
1
C297
470P_0402_50V7K~D
C372
2@
C418
2@
2@
C293
4.7U_0603_6.3V6M~D
C385
2@
C364
2@
W17
W18
AB10
AB11
AB14
AB15
AB20
AB21
AA4
AB5
AB6
AB7
AB8
AB9
AB12
AB13
AB16
AB17
AB18
AB19
AC9
AC11
AC12
AC16
AC17
AC19
AC20
C317
470P_0402_50V7K~D
C373
2@
0.1U_0402_16V4Z~D
FBA_PLLAVDD
1000P_0402_50V7K~D
C369
2@
C516
2@
0.1U_0402_10V7K~D
4.7U_0603_6.3V6M~D
L31 2@
BLM11A121S_0603~D
1
2
C402
2@
VDD_0
PEX_IOVDD_0
Part 4 of 5
VDD_1
PEX_IOVDD_1
VDD_2
PEX_IOVDD_2
VDD_3
PEX_IOVDD_3
VDD_4
PEX_IOVDD_4
VDD_5
PEX_IOVDD_5
VDD_6
PEX_IOVDD_6
VDD_7
PEX_IOVDD_7
VDD_8
PEX_IOVDDQ_0
VDD_9
PEX_IOVDDQ_1
VDD_10
PEX_IOVDDQ_2
VDD_11
PEX_IOVDDQ_3
VDD_12
PEX_IOVDDQ_4
VDD_13
PEX_IOVDDQ_5
VDD_14
PEX_IOVDDQ_6
NV_PLLAVDD
PEX_IOVDDQ_7
VDD_16
PEX_IOVDDQ_8
VDD_17
PEX_IOVDDQ_9
VDD_18
PEX_IOVDDQ_10
VDD_19
PEX_IOVDDQ_11
VDD_20
PEX_IOVDDQ_12
VDD_21
PEX_IOVDDQ_13
VDD_22
PEX_IOVDDQ_14
VDD_23
PEX_IOVDDQ_15
VDD_24
PEX_IOVDDQ_16
VDD_25
PEX_IOVDDQ_17
VDD_26
PEX_IOVDDQ_18
VDD_27
VDD_28
PEX_PLLAVDD
VDD_29
PEX_PLLDVDD
VDD_30
VDD_31
VDD_32
MIOB_VDDQ_0
VDD_33
MIOB_VDDQ_1
VDD_34
MIOB_VDDQ_2
VDD_35
MIOBCAL_PD_VDDQ
POWER
+1.22V_GFX_PCIE
0.022U_0402_16V7K~D
10U_0805_4VAM~D
For PLAVDD
C419
2@
C383
2@
0.1U_0402_10V7K~D
C442
2@
220P_0402_50V7K~D
0.022U_0402_16V7K~D
C365
2@
0.1U_0402_10V7K~D
0.022U_0402_16V7K~D 2200P_0402_50V7K~D
C299
2@
C358
2@
0.1U_0402_10V7K~D
C292
2@
0.1U_0402_10V7K~D
C315
2@
40mA
10U_0805_4VAM~D
L23 2@
BLM11A121S_0603~D
C284
2@
0.1U_0402_10V7K~D
10U_0805_4VAM~D
PLLVDD
470P_0402_50V7K~D
4700P_0402_25V7K~D
+2.5V_RUN
J9
J10
J11
L12
L13
L15
L16
M9
M11
M12
M13
M14
M15
M16
M17
N9
N11
N17
R9
R11
R17
T9
T11
T12
T13
T14
T15
T16
T17
U12
U13
U15
U16
W13
W15
W16
C458
0.1U_0402_10V7K~D
U8D
2.2U_0603_6.3V6K~D
C339
0.1U_0402_10V7K~D
+VCC_GFX_CORE
For PLVDD
C361
0.1U_0402_10V7K~D
1808mA
C294
2@
Title
NVG72 PWR
Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
46
of
73
U8E
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
U17
U23
U26
V9
V19
W14
Y2
Y5
Y23
Y26
AC2
AC8
AC14
AC23
AC26
AD8
AD9
AD11
AD12
AD14
AD16
AD17
AD19
AD20
AC5
AF2
AF3
AF6
AF9
AF12
AF15
AF18
AF21
AF24
AF26
MIOBCAL_PU_GND
PEX_PLLGND
PLLGND
V6
M6
M3
AA6
H5
FBA_PLLGND
C15
FBCAL_PU_GND
FBCAL_TERM_GND
E13
H22
1
IFPAB_PLLGND
IFPCD_PLLGND
R602 2@
40.2_0402_1%~D
2
2@G72-N-A1_BGA533~D
R386 2@
40.2_0402_1%~D
2
Part 5 of 5
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND
B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E14
E17
E20
E23
E26
F11
H2
H6
H23
H26
J14
K9
K19
L2
L5
L11
L14
L17
L23
L26
N12
N13
N14
N15
N16
P2
P5
P9
P11
P12
P13
P14
P15
P16
P17
P19
P23
P26
R12
R13
R14
R15
R16
U2
U5
U11
U14
Title
NVG72 GND
Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
47
of
73
VSSA
VSSA
CLKA0
CLKA0#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A3
A10
G1
G12
L1
L12
V3
V10
2@
2
2@
2
100P_0402_50V8J~D
2@
2
470P_0402_50V7K~D
C196
0.01U_0402_16V7K~D
C576
2@
2
1000P_0402_50V7K~D
C546
2@
2
0.01U_0402_16V7K~D
C545
2@
2
0.1U_0402_10V7K~D
C197
2@
2
0.1U_0402_10V7K~D
C537
2@
2
0.1U_0402_10V7K~D
C577
2@
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBACS1#
FBACS0#
FBA_CKE
FBACAS#
H3
F4
H9
F9
RAS#
CAS#
WE#
CS#
FBAWE#
CLKA1
CLKA1#
H4
J11
J10
CKE
CK
CK#
0.1U_0402_10V7K~D
C538
2@
1.18K_0402_1%~D
2@ R450
2
1
C203
0.1U_0402_10V7K~D
For Mirror config
A4
A9
DQSA_RN4
DQSA_RN6
DQSA_RN5
DQSA_RN7
D3
D10
P10
P3
RDQS0
RDQS1
RDQS2
RDQS3
A2
A11
F1
F12
M1
M12
V2
V11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V4
V9
H10
SEN
RESET
RFM
J1
J12
VSSA
VSSA
+1.8V_RUN
FBA_RST#
FBARAS#
2@
2@
ZQ
MF
2@
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
VDDA
VDDA
K1
K12
FBBA4
FBBA3
FBBA5
FBAA2
FBAA3
Swap data group for trace

length fine tune
+1.8V_RUN
+1.8V_RUN
FBA_VDDA2
FBA_VDDA3
2@ L42 BLM18PG181SN1_0603~D
2
1
2
1
2@ L46 BLM18PG181SN1_0603~D
Change to 220ohm/100MHz
K4J55323QG-BC14_FBGA136~D
CLKA1
CLKA1#
Place close to U14
FBAD[0:63]
FBAA[0:11]
FBBA[2:5]
DQSA_WP[0:7]
2@
2
2@ C561
1
2@ C529
1
0.047U_0402_16V4Z~D
2
0.047U_0402_16V4Z~D
2
DQMA#[0:7]
2@
2
2@
2
2@
2
2@
2
2@
2
2@
2
2@
2
2@
2
FBAD[0:63] <45>
FBAA[0:11] <45>
FBBA[2:5] <45>
DQSA_WP[0:7] <45>
DQSA_RN[0:7] <45>
DQMA#[0:7] <45>
0.01U_0402_16V7K~D
2@
2
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C565
2@
2
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C557
C536
2@
2
0.1U_0402_10V7K~D
C535
2@
2
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C556
C202
C560
2@
2
470P_0402_50V7K~D
C564
2@
2
2@
2
0.1U_0402_10V7K~D
C204
2@
2
2@
2
470P_0402_50V7K~D
C563
2@
2
2@
2
0.1U_0402_10V7K~D
C534
2@
2
2@
2
470P_0402_50V7K~D
C555
2@
2
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C559
C578
2@
2
0.01U_0402_16V7K~D
2@
2
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C566
C165
2@
2
2@
2
DQSA_RN[0:7]
Place below decoupling caps close U14 VDDQ Pins
C558
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C502
2@
2
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C421
C430
0.1U_0402_10V7K~D
C393
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C465
C404
470P_0402_50V7K~D
C507
2@
2
0.1U_0402_10V7K~D
C407
2@
2
470P_0402_50V7K~D
C406
2@
2
0.1U_0402_10V7K~D
C498
2@
2
470P_0402_50V7K~D
C511
2@
2
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C499
C512
C521
C424
0.047U_0402_16V4Z~D
2
0.047U_0402_16V4Z~D
2
+1.8V_RUN
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C466
C520
2@
2
VREF
VREF
RFU1
RFU2
FBBA2
Place below decoupling caps close U14 VDD Pins

4.7U_0603_6.3V6M~D
C539
2@
2
Place below decoupling caps close U11 VDDQ Pins
FBA_VDDA0
FBA_VDDA1
2@ L37 BLM18PG181SN1_0603~D
2
1
2
1
2@ L12 BLM18PG181SN1_0603~D
<45> CLKA1
<45> CLKA1#
C532
2@
2
100P_0402_50V8J~D
2@
2
470P_0402_50V7K~D
C517
2@
2
1000P_0402_50V7K~D
C492
2@
2
0.01U_0402_16V7K~D
C510
0.01U_0402_16V7K~D
C384
2@
2
0.1U_0402_10V7K~D
C380
2@
2
0.1U_0402_10V7K~D
C491
0.1U_0402_10V7K~D
C441
C378
2@
2
+1.8V_RUN
H1
H12
J2
J3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD54
FBAD55
FBAD52
FBAD53
FBAD49
FBAD50
FBAD48
FBAD51
FBAD42
FBAD41
FBAD46
FBAD44
FBAD45
FBAD40
FBAD43
FBAD47
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
+1.8V_RUN
4.7U_0603_6.3V6M~D
C518
+1.8V_RUN
2@ C132
1
2@ C451
1
+1.8V_RUN
10mil FBA_VREF1
10mil FBA_VREF3
+1.8V_RUN
K4J55323QG-BC14_FBGA136~D
Place close to U11
WDQS0
WDQS1
WDQS2
WDQS3
R148 2@
240_0603_5%~D
Change to 220ohm/100MHz
2@
D2
D11
P11
P2
+1.8V_RUN
1
2
2@
Place below decoupling caps close U11 VDD Pins
2@
2
K1
K12
DQSA_WP4
DQSA_WP6
DQSA_WP5
DQSA_WP7
FBAA5
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
J12
VDDA
VDDA
+1.8V_RUN
FBAA4
A3
A10
G1
G12
L1
L12
V3
V10
SEN
RESET
RFM
DM0
DM1
DM2
DM3
V4
V9
H10
FBA_RST#
FBACS1#
E3
E10
N10
N3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A2
A11
F1
F12
M1
M12
V2
V11
RDQS0
RDQS1
RDQS2
RDQS3
ZQ
MF
D3
D10
P10
P3
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
DQMA#4
DQMA#6
DQMA#5
DQMA#7
60.4_0402_1%~D
A4
A9
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Rb
Stuff for G74
Ra
2@
CKE
CK
CK#
@ R606
909_0402_1%~D
VREF_SW_A2
1
2
Rb
H4
J11
J10
FBA_CKE
CLKA0
CLKA0#
2@
S
2N7002_SOT23~D
RAS#
CAS#
WE#
CS#
2
G
2@ R206
2
1
H3
F4
H9
F9
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
Ra
R480
FBARAS#
FBACAS#
FBAWE#
FBACS0#
+1.8V_RUN
R382
VREF
VREF
RFU1
RFU2
@ R604
909_0402_1%~D
VREF_SW_A2
1
2
Q57
D
+1.8V_RUN
R481
60.4_0402_1%~D
H1
H12
J2
J3
10K_0402_5%~D
WDQS0
WDQS1
WDQS2
WDQS3
For Mirror config
<45> FBA_RST#
<45> FBACS1#
60.4_0402_1%~D
<45> CLKA0
<45> CLKA0#
R407
60.4_0402_1%~D
R408
240_0603_5%~D
R430
+1.8V_RUN
FBARAS#
FBACAS#
FBAWE#
FBACS0#
<45> FBA_CKE
2@
2@
D2
D11
P11
P2
2@
1.18K_0402_1%~D
<45>
<45>
<45>
<45>
C479
2@
Stuff for G74
2@
DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
+1.8V_RUN
C478
2@
0.1U_0402_10V7K~D
2
2@ R413
2
1
1.18K_0402_1%~D
1
2
1.18K_0402_1%~D
2@ R415
2
1
DM0
DM1
DM2
DM3
10mil FBA_VREF0
10mil FBA_VREF2
0.1U_0402_10V7K~D
1
3
Rb
E3
E10
N10
N3
FBBA4
FBBA5
FBAA6
FBAA9
FBAA0
FBAA1
FBBA2
FBAA11
FBAA10
FBBA3
FBAA8
FBAA7
FBA_BA1
FBA_BA0
511_0402_1%~D
R416
@ R605
Ra
909_0402_1%~D
VREF_SW_A1
1
2
Rb
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
R205
511_0402_1%~D
2@
S
2N7002_SOT23~D
<45> FBA_BA0
<45> FBA_BA1
Ra
VREF=1.26V=0.7 x VDDQ
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
R449
2
G
R420
@ R603
909_0402_1%~D
VREF_SW_A1
1
2
Q56
D
+1.8V_RUN
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
511_0402_1%~D
2@
511_0402_1%~D
+1.8V_RUN
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
D
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
U14
VREF=VDDQ x Rb(Ra+Rb)
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
U11
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
+1.8V_RUN
2@ R442
1
2
121_0402_1%~D
2@ R433
1
2
121_0402_1%~D
2@ R446
1
2
121_0402_1%~D
2@ R443
1
2
121_0402_1%~D
2@ R439
1
2
121_0402_1%~D
2@ R445
1
2
121_0402_1%~D
2@ R437
1
2
121_0402_1%~D
2@ R448
1
2
121_0402_1%~D
Title
NVG72 External DDR

Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
48
of
73
G72MV STRAPS
STRAPS
PIN
DESCRIPTION
Value
<45>
<44>
<44>
<44>
<44>
R340
2K_0402_5%~D
2
1
R347
2K_0402_5%~D
2
1
R336
2K_0402_5%~D
2
1
R82
2K_0402_5%~D
2
1
2@
R322
2K_0402_5%~D
2
1
R339
2K_0402_5%~D
2
1
R364
2K_0402_5%~D
2
1
2@
R373
2K_0402_5%~D
2
1
2@
R333
10K_0402_5%~D
2
1
@
RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
SUB_VENDOR
3GIO_ADR_0
3GIO_ADR_1
3GIO_ADR_2
<44> RAM_CFG0
<44> RAM_CFG1
<44> RAM_CFG2
<44> RAM_CFG3
<45> SUB_VENDOR
<45> 3GIO_ADR_0
<45> 3GIO_ADR_1
<45> 3GIO_ADR_2
R64
10K_0402_5%~D
2
1
R334
10K_0402_5%~D
2
1
R341
10K_0402_5%~D
2
1
+3.3V_RUN
2@
MIOBD10
MIOB_VSYNC
Parallel=00, SERIAL AT25F=01 DEFAULT,

Serial SST45VF=10, LPC=11
01
SUB_VENDOR
MIOAD1
VBIOS on card (pull high)

VBIOS with system BIOS (pull down)
PEX_PLL_TERM
MIOAD0
ROM_TYPE[1:0]
0
0001
8Mx32 DDR monolithic (64bit)

300MHz, 1.8V
8Mx32 DDR monolithic (32bit)
1001
300MHz, 1.8V
PEX_PLL_EN_TERM100
DEVID3
DEVID2
DEVID1
DEVID0
PEX_PLL_EN_TERM100
DEVID3
DEVID2
DEVID1
DEVID0
For GDDR1
0010
8Mx32 DDR (Samsung K4D55323QF-GC)

300MHz, 1.8V
MIOBD0
4Mx32 DDR generic (64bit)
0100
MIOBD1
1.8V I/O
MIOBD8
R80
10K_0402_5%~D
2
1
2@
R350
2K_0402_5%~D
2
1
R332
10K_0402_5%~D
2
1
R71
10K_0402_5%~D
2
1
2@
R335
10K_0402_5%~D
2
1
R342
10K_0402_5%~D
2
1
RAM_CFG[3:0]
2@
MIOBD9
1100
4Mx32 DDR generic (32bit)

1.8V I/O
2@
Infineon 8Mx32
0101
500MHz, 1.8V
Hynix 8Mx32
For GDDR3
0111
500MHz, 1.8V
G72xx
Samsung 8Mx32
0110
DEVID3 DEVID2 DEVID1 DEVID0

1
G72M
G72MV
8
7
6
5
2 @
C20
+3.3V_RUN
P1819GF-08SR_SO8~D
Internal pull up
U3.Pin3
C24
10U_0805_10V4Z~D
XIN/CLKIN XOUT
VSS
VDD
D_C
PD#
ModOUT REFCLK
L8 @
BLM11A121S_0603~D
1
2
+3VL
R27
10K_0402_5%~D
1
R26
R72
0_0402_5%~D
2
1
<44> XTALSSIN
1
2
3
4
U3
<44> XTALOUTBUFF
10K_0402_5%~D
2
1
+3.3V_RUN
0.1U_0402_10V7K~D
G72GLM
500MHz, 1.8V
-1.75% (DOWN)
0.875% (CENTER)
*
A
Title
NVG72 Strapping
Size
Document Number
Date:
Rev
0.4
LA-3001P
Sheet
1
49
of
73
Graphics Power reference COE Rev A08

Graphics Power for HAL31 Discrete only.
GNDA_GFX
2
S
S
S
3
2
1
1
2
PC152
330U_D2E_2.5VM_R9~D
PC151
330U_D2E_2.5VM_R9~D
output voltage adjustable network
1
1
PR167
2
10K_0402_5%~D
2
PR168
10K_0402_5%~D
PJP20
1
2
1
@ PC162
100P_0402_50V8J~D
GNDA_GFX
PQ35
BSS138W-7-F_SOT323~D
2
G
3
<44> GFX_CORE_CNTRL
1
GFX_CORE_CNTRL
0_0402_5%~D
PC163
0.01U_0402_16V7K~D
+3.3V_RUN
GNDA_GFX
PR166
2
GNDA_GFX
PR169
100K_0402_5%~D
PC161
22U_0805_6.3V6M~D
+
2
PR164
178K_0402_1%
PC160
22U_0805_6.3V6M~D
1U_0603_10V6K~D
+
2
GNDA_GFX
PR162
1.21K_0402_1%
PC159
2
1
PR165
4.99K_0402_1%~D
PC158
0.01U_0402_16V7K~D
1
PR163
100K_0402_5%~D
PC148
2200P_0402_50V7K~D
5
6
7
8
D
D
D
D
PD15
CMDSH_SOD323~D
PC157
10U_0805_10V4Z~D
+1.22V_GFX_PCIEP
PC147
0.1U_0603_50V4Z~D
PC149
2.2U_0603_6.3V6K~D
L-S Rds-on
=(Typ) 5.9m ~(max) 7.25m ohm
+1.8V_SUS
PR158
24.9K_0402_1%~D
<33> GFX_PCIE_PWRGD
2
GFX_REF
<33> GFX_CORE_PWRGD
+VCC_GFX_COREP
3
2
1
VTTI
REFIN
14
13
15
PR161
57.6K_0402_1%~D
16
FB
+VCC_GFX_CORE +-2%
Maximum current: 8A
OCP min: 12A
OUT
STBY#
PQ34
FDS6676AS_SO8~D
POK2
PAD-OPEN 43X79
PL22
0.88UH_MPC1040LR88_17A_20%~D
1
2
PC155
1000P_0402_50V7K~D
1
2
PR160
100K_0402_5%~D
PC150
0.22U_0603_10V7K~D
2
1
2
1_0603_5%~D
5
6
7
8
17
Populated PR159, PR160

if Page 33 R576, R577 are Unpop.
De-pop PD15 for ISL88550

1
2
25
24
GND
26
AVDD
SKIP#
28
27
18
VIN
EPAD
PQ33
FDS6612A~D
PR155
1
UGATE
MAX8632/ISL88550
PL21
FBMA-L11-453215-900LMA60T_1812~D
1
2
+PWR_SRC
PJP17
PR182
69.8K_0402_1%~D
19
PC153
0.1U_0402_10V7K~D
PHASE
POK1
29
GNDA_GFX
PR159
1
2
100K_0402_5%~D
20
ILIM
PC156
0.047U_0402_16V4Z~D
8 SS
+3.3V_RUN
21
BOOT
2
GNDA_GFX
LGATE
VTT
PR157
332K_0402_1%~D
REF
12
PC154
0.22U_0402_10V4Z~D
C
PR156
2
249K_0402_1%
PGND2
1
1
OVP/UVP
VTTR
GFX_REF
11
GFX_+5V_RUN
NC
@ PR153
0_0402_5%~D
2 1 TON
10
+VCC_GFX_COREP
SHDNA#
@ PR154
0_0402_5%~D
1
2
VTTS
PR152
61.9K_0402_1%~D
PU13
GNDA_GFX
22
<32> GFX_RUN_ON
"Del PR204 100k"

HW has same R632 100k (Page 32) between +3.3V_RUN to PU13 Pin_27
VDD
PGND1
PC144
@ PR203
0_0402_5%~D
2
<19,30,32,33,39,40,41> RUN_ON
+GPU_PWR_SRC
1U_0603_10V6K~D
23
GFX_+5V_RUN
PC146
10U_1206_25V6M~D
PR151
10_0805_5%~D
1
2
PC145
10U_1206_25V6M~D
+5V_SUS
GNDA_GFX
PAD-OPEN 43X118
PJP15
+VCC_GFX_COREP
GNDA_GFX
2
+VCC_GFX_CORE
PAD-OPEN 43X118
PJP16
+1.22V_GFX_PCIEP
+1.22V_GFX_PCIE
PAD-OPEN 43X79
A
Title
PWR_NVG72 +VDD_CORE
Size
Document Number
Date:
Rev
X02
LA-3001P
Sheet
1
50
of
73
Version Change List ( P. I. R. List )

Item Page#
D
Title
Date
ALL
H/W
9/14
31
H/W
31
Request Owner
Issue
Description
Solution
Description
Bill
Revision change to X00(0.2)
9/14
Bill
H/W
9/14
Bill
19
H/W
9/20
Bill
20
H/W
9/20
Bill
32
H/W
9/23
Reden
CoE update. ( CRT, LVDS, SVIDEO and DVI

Interfaces_A06)
CoE update. ( CRT, LVDS, SVIDEO and DVI
Interfaces_A06)
CoE update. ( M07 SYSTEM POWER
SEQUENCE_A03)
23
H/W
9/28
Reden
ALL
H/W
9/28
14
H/W
10
22
11
Rev.
Modify Done.
0.2
Update Board ID to 0001 for X00
Stuff R42 and no-stuff R31
0.2
CoE update. ( EC_A05)
Add GPIO USB_CAM_EN# and ADAPT_TRIP_SEL
0.2
Delete U28, R607. Add R610.
0.2
Update Populattion Note for the RGB and TV out Filter.
0.2
Change R58,R540,R567,R447,R558,R564,R597 to 30_0805_5%
0.2
Update the ICH7 USB bus connection
Add connection of USB4+/- for CCD, USB2+/- for Blue tooth
0.2
Reden
Change Connector for ME request
Update J1394, JTP1, JBT1, JLVDS1 connector
0.2
9/30
Reden
Update the note for MCH power
Remove the placement note for C489,C525 as COE schematic
0.2
H/W
9/30
Scott
22
H/W
9/30
12
23
H/W
13
23
H/W
Modify OK
0.2
Scott
Pull-up on SATA_ACT# (R530) should be

populated
Capacitor on THRMTRIP_ICH# (C609) can be
de-populated
Modify OK
0.2
9/30
Scott
Rename net LCM_SMB_CLK to ICH_SMLINK0
Modify OK
0.2
9/30
Scott
Rename net LCM_SMB_DAT to ICH_SMLINK1
Modify OK
0.2
Modify OK
0.2
Delete R233, R235, R238, Add R611, R612 (39 Ohm). And move L3 & L4
before caps C1 & C2.
0.2
14
29
H/W
9/30
Can remove R489 and R490. Leave pins 3 and

B.McFarland 5 as NC on JMINI1. See A06 Ref Schem.
15
20
H/W
9/30
John Lerma
16
20
H/W
9/30
John Lerma
17
33
H/W
9/30
John Lerma
18
23
H/W
9/30
Reden
19
47
H/W
9/30
Reden
20
20
H/W
10/04
Reden
Please check the latest reference

schematics. Delete 75 ohm resistors on
RED, GREEN, & BLUE. Add 39 ohms series
resistors to ouputs of U1 & U2. Move L3 &
L4 before caps C1 & C2.
Please check the latest reference
schematics. Delete 75 ohm resistors on
TV_C, TV_CVBS, & TV_Y. Filter circuit
values have been changes and a cap in
parallel with each inductor has been
added.
Add diode for power leakage in power
sequence circuit
No stuff R485 (10k pull high) for
M'07 inverter
Change pull down resistor value to follow
COW schematic
Change S-video filter bead same as COE
schematic
Remove R368, R380, R385.
0.2
Change R129,R482,R466 to 100K,and change Q6,Q30,Q27 to 2N3906,and

change R471,R474,R469 to 4.7K.
0.2
Modify OK
0.2
Change R602,R386 to 37.4_0402_1%
0.2
Change L29,L32,L34 to 0.47UH_CIL10NR47KNC_10%_0603
0.2
Title
5
Changed-List History 1
Size
Document Number
Date:
Rev
0.3
LA-3001P
Sheet
1
51
of
73

Item Page#
D
Title
Date
Request Owner
Issue Description
Solution Description
Modify ok.
0.2
Modify ok.
0.2
29
H/W
10/05
John
Swap CLKREQ signal between WWAN and WLAN
27
H/W
10/05
John
Change C236,C238 from 1000p to 300p
Rev.
Connecting JMINI2 pins 16 - HOST_DEBUG_TX, 17 - HOST_DEBUG_RX, 19 - 8051_TX,

0.2
& 42 - 8051_RX.
29
H/W
10/05
John
32
H/W
10/05
John
44
H/W
10/05
John
49
H/W
10/05
John
20
H/W
10/05
John
44
H/W
10/05
John
31
H/W
10/06
Reden
Remove C682 and replace C685 with 4700pF

as COE schematic
Add signal THERMTRIP_VGA# to G72 pin B13
from Guardian II
Change R341, R334, R64, & R333 from 2K to
10K
Change Caps C331,C325,C351,C349,C381,& C379
from 82pF to 47pF and add C705~C707
Add 10K pull-down resistor to G72 pins C3,
C1, & D7
Add signal U18 pin5 (GPIOE4) connect
to TP connector for LED.
10
44
H/W
11/02
John
Add 150ohm terminal resistor on GFx side.
11
22
H/W
11/02
Reden
Add SNIFFER LED Disable Circuit as

COE schematic
Add Q58,R625
0.3
12
30
H/W
11/02
Reden
Added 0 ohm to EC5004 test pin
Modify ok.
0.3
13
29
H/W
11/02
Reden
14
35
H/W
11/02
Reden
15
44
H/W
11/02
Reden
16
20
H/W
11/17
Reden
17
44
H/W
11/17
Reden
18
44
H/W
11/17
Reden
33
H/W
11/18
Reden
Added circuit to support WoW from S3/S4.

Modify
Blocking diode and bypass resistor as COE
Added a circuit (Transistor and Resistors) to
keep BT LED off when the SNIFFER is turned onModify
Change pull up resistor same as COE graphic
Change
schematic.
Change VCC_CRT Diode D11 to RB500 (rate
Modify
Io=100mA).
Add series resistor on signal of
Modify
PLTRST_DELAY#.
Add series resistor on signal of
Modify
THERMTRIP_VGA#.
Change Q6,Q27,Q30 to MMBT3906, and delete
D19~D21(RB751V_SOD323~D) same as COE
Modify
schematic.
32
H/W
11/18
Reden
Added 3VRUN Delay RC CKT, to Fix IMVP_PWRGD

Glitch issue and add 1.8 VRUN Delay RC CKT,
to meet GFX Power Sequence Requirement
24
32
H/W
11/18
Reden
25
32
H/W
11/21
Reden
26
20
H/W
11/23
John
19
Add debug signals to WLAN connector
Modify ok.
0.2
Modify ok.
0.2
Modify ok.
0.2
Modify ok.
0.2
Modify ok.
0.2
Modify ok.
0.2
Add 150ohm of R619~R624
0.3
ok.
0.3
ok.
0.3
R370,R376 from 4.7K to 470K.
0.3
ok.
0.3
ok.
0.3
ok.
0.3
0.3
ok.
20
21
0.3
Modify ok.
23
Added Diode Bleed off for 3VRUN and 1.8VRUN

for GFX Power Down Sequence adjustment.
Change the GFX_RUN_ON connection to VR turn
on pin as COE A06 version schematic.
Change U19 connection from EC to GND as
GG list request.
Modify ok.
0.3
Modify ok.
0.3
A
0.3
Modify ok.
Title
5
Size
Document Number
Date:
Rev
0.3
LA-3001P
Sheet
1
52
of
73

Item Page#
D
John
Change JTP1 pin 19 from +5V_ALW to +5V_RUN

as Dell GG list
Place a 0 ohm 1206 place holder between
D11 pin 1 and JCRT1 pin 9
Change WWAN USB source from EC to ICH7M/USB5
and remove WWLAN USB signal from EC.
Add connection for signal of YPRPB_DET# to
G72 pin A15 through a series resistor.
12/01
John
Change R615 to no-pop
H/W
12/02
John
34
H/W
11/23
John
20
H/W
11/23
John
29
H/W
11/23
John
44
H/W
11/24
44
H/W
Rev.
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
H/W
12/06
Reden
Add connection to EC for signal

HDDC_EN# and MODC_EN#
Change R456 to 150, R457 to 91 for internal
spectrum clock.
20
H/W
12/07
John
Add a diode for U1,U2 power pin.
Modify ok.
0.3
20
H/W
12/07
John
Add a cap 0.1uf for JSVID1 pin5
Modify ok.
0.3
10
28
H/W
12/07
John
Change u13 to G5240B1T1U
Modify ok.
0.3
11
30
H/W
12/07
John
Add connection for pin73 for LVDS BIA_PWM

through resistor
Modify ok.
0.3
12
20
H/W
12/08
John
Remove the C104 form dell COE team request.
Modify ok.
0.3
13
6/44/49
H/W
12/12
Reden
Modify ok.
0.3
14
31
H/W
12/12
John
Modify ok.
0.3
H/W
12/13
John
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.3
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
23/31
16
33
H/W
12/13
John
17
35
H/W
12/14
Reden
18
H/W
12/14
Reden
19
31
H/W
12/15
Reden
Remove external spectrum and swap populated

resistor for internal CLK GEN.
Add pull up resistors to +3.3V_ALW for signals
of HDDC_EN#,MDDC_EN#
Add damping series resistors (47ohm) for
signal SPI_CS# on EC and ICH7
Removed 3V/5V power good sequence circuit and
change +1.8V_RUN PWRGD circuit.
Swap the Sniffer LED (D13) pin define,
Pin3=>Yellow, Pin2=>Green.
Change CPU VCORE area caps , 22uF->10uF and
replace 330uF poly with 6m ohm x 4pcs.
Change pull up resistors of HDDC_EN#,MDDC_EN#
from 10k to 100K for leakage issue.
20
49
H/W
12/15
Reden
Change Device ID from 0111 to 1000 for G72M
15
Date
Title
Request Owner
Issue Description
23/30
21
32
H/W
2006/2/07
Reden
23
13
H/W
2006/2/07
Reden
24
24
H/W
2006/2/07
Reden
25
20
H/W
2006/2/08
Reden
Change C154 from 0.01uf to 0.047uf to match

G72 VDD_CORE&1.8V power up sequence
Change L6/L26 TDK to 2nd and use Taiyo for
main source
Change L53 TDK to 2nd and use Taiyo for main
source
Change TV filter caps valus as dell's suggest
1. Change C331,C351,C381,C325,C349,C378 from
47pf to 82pf
2. Change C705,C706,C707 from 22pf to 8.2pf
Title
5
Size
Document Number
Date:
Rev
0.3
LA-3001P
Sheet
1
53
of
73

Item Page#
D
Date
35
H/W
02/17
Reden
35
H/W
02/17
Reden
19
H/W
02/21
Reden
To add logic circuit to control 3.3V_RUN for

power switch board.
Add pull down resistor (10K) for signal
PLTRST_DELAY# to fix leakage issue
Add SI3457DV P channel mos to dual-stuff for
+GFX_PWR_SRC
31
H/W
02/21
Reden
Change board ID to X02 (0011)
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
Modify ok.
0.4
19
H/W
02/21
Reden
20
H/W
02/21
Reden
23
H/W
02/22
Reden
Stuff R485 for Bits issue WI52653
Modify ok.
0.4
16
H/W
02/22
Reden
Change thermal setpoint from 85 degrees to 88

degrees, change R242 from 147K ohm to 322K ohm
1% and R247 from 41.2K ohm to 118K ohm 1%.
Modify ok.
0.4
12
19
H/W
02/28
Reden
Add R652 overlap on D26 for CMOS power pop

option
Modify ok.
0.4
13
31
H/W
04/03
Reden
Change board ID to X03 (0100)
Modify ok.
0.5
14
16
H/W
04/11
Reden
Switch Q7,Q24 Pin S,D connection
Modify ok.
0.5
19
22,23,34
H/W
02/21
Reden
H/W
02/21
Reden
10
11
Rev.
Add voltage drop diode for CMOS power

(+5V_RUN), and remove D'05 buffer.
populate the 48MHz/bit_clk/keyboard signal
termination for EMI issue
Change population option for BACKLITEON,stuff
R610 for DSC and stuff R639 for UMA.
Change R611,R612 resister to 0 for signal
quality.
Title
Request Owner
Issue Description
15
H/W
Modify ok.
0.5
16
H/W
Modify ok.
0.5
17
H/W
Modify ok.
0.5
18
H/W
Modify ok.
0.5
19
H/W
Modify ok.
0.5
20
H/W
Modify ok.
0.5
21
H/W
Modify ok.
0.5
23
H/W
Modify ok.
0.5
24
H/W
Modify ok.
0.5
25
H/W
Modify ok.
0.5
26
H/W
Title
5
Size
Document Number
Date:
Rev
0.3
LA-3001P
Sheet
1
54
of
73
Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
Title
Date
Request
Owner
Issue Description
Rev.
P39
P40
+3.3VALW
+1.5V / +1.05V OCP
X00
0926/2005
Dell
Dell request to change PC30 from 4.7U_1206 to 10U_1206
PC30 change to 10U_1206_10V
0926/2005
Dell
+1.5V OCP min = 7.4A, +1.05V OCP min = 9.3A
1.) +1.5V OCP:

PR56 change to 124K, PR46 change to 1.43K
X00
2.) +1.05V OCP:
PR57 change to 124K, PR47 change to 1.87K
P41
+1.8V_SUS
0926/2005
Dell
Contact the FB pin of the controller to the

AVDD pin via zero ohm resister
Add PR202 0 ohm 0603 between FB pin with AVDD pin of PU5 MAX8632
X00
P39
+15V_SUS
0926/2005
Compal
Follows
Unpop PR179 10K_0805
X00
P50
+VCC_GFX
0926/2005
Compal
Improve +1.22V_GFX_PCIEP pin7 STBY# and

pin5 POK1 pull high resister of PU13 MAX8632.
Depop PR159, PR160 100K_0402
X00
P40
+1.5V / +1.05V
1004/2005
Dell
Improve better phase margin
PC46 change to 330pf/0402/50v
P41
+1.8V_SUSP OCP
1004/2005
Dell
Improve 1.8V_SUSP OCP
PR78 change to 84.5K
X00
COE +15V reference schematics
X00
P39
+3.3VALW
1004/2005
Dell
Dell request to populate PC11 at the input to the 3V requlator
Populate PC11 10uf/1206/25V
X00
P50
+VCC_GFX
1007/2005
Dell
Dell request to Change PR167 pin 1 contact to +3.3V_RUN
PR167 pin1 contact to +3.3V_RUN
X00
1007/2005
Dell
MAX8632 Just connect pin 24

directly to the exposed pad
P50
+VCC_GFX
P41
+1.8V_SUSP
12
P41
+1.8V_SUSP
1007/2005
Dell
13
P43
Charger
1007/2005
P41
+1.8V_SUSP
1107/2005
10
without using zero ohm resistor .
DEL PR186 and PR79
X00
Dell request to populate PR74.

( PU5 MAX8632 f from 300K change to 450khz)
Add PR74
X00
Dell
Dell request to change PR174 to 1_0603.
PR174 from 1_0805 change to 1_0603(refer to COE Rev A09)
X00
Dell
Dell Coe DDR Rev A05 request to del PR70
DEL PR70
Change PR69 from 0 ohm to 1 ohm.
X01
14
15
16
P43
Charger
1107/2005
Dell
1.
2.
3.
4.
5.
6.
7.
Dell Coe Cgarger Rev A07 requested
Change PR174 from 0_0805 to 1_0603.

Add PC175 220P_0402
Del PR200, Add PR199 100_0402, PC189 0.01U_0603 PU10 Pin 15 & Pin16 shorted.
Add PR144 4.3M 0402.
Del PR201.
Change PR149 from 59K to 56.2K 0402
Change PR150 from 33.2K to 27.4K 0402.
X01
A
Title
Power-Changed-List History
Size
Date:
Document Number
Rev
X01
Bali
Sheet
1
55
of
73
Version Change List ( P. I. R. List ) for

Power Circuit
Request Owner
Item Page#
Title
Date
Issue
Description
17
P50
+VDD_CORE
1108/2005
Dell
18
P50
+VDD_CORE
1108/2005
Dell
19
P37
+DC_IN
1202/2005
Dell
Add solder jumper pads in parallel with PL2 & PL3.
20
P43
Charger
1120/2005
Dell
21
P42
+VCC_CORE
1120/2005
P37
P38
P39
P40
P41
P42
P43
P50
EMI Bead
23
P39
24
P42
22
Dell COE Graphics Power reference A07 requested
Follow Coe ref De-pop PR203.

Del PR204, H/W has same R632 100k on Page 32 between +3.3V_RUN to PU13 Pin_27.
1.
2.
3.
4.
5.
6.
7.
Solution
Description
PR155 to 1 ohm.
Rev.
Change
Change PR161 from 69.8K to 57.6K.
Change PR164 from 118K to 178K.
Change PR166 from 301 to 0 ohm.
Change PR162 from 1.1K to 1.21K
All +5V_RUN change to +5V_SUS.
All +3V_RUN change to +3V_SUS.
X01
Del PR203
Del PR204
X01
Add PJP21, PJP22
X01
Dell COE Charger reference A09 requested
De pop PC189
Add PC191
X01
Compal
Improve VCC-CORE OCP to 55A.

( original design X00 PR109 191K OCP point 45A only.)
Change PR109 to 160K
X01
Change PL2, PL5, PL6, PL9, PL12, PL14, PL19, PL21 footprint to L_1812-S for 2nd source
X01
1122/2005
Compal
Change Footprint 'L_1812' to "L-1812-S"
3.3VSRC
1124/2005
Dell
+VCC_CORE
1130/2005
Compal
for 2nd source
X01
Nopop PQ39 since this will not be needed once the EC HUB is removed.
Unpop PQ39
Tokin inductor 0.45uH/27A rusted on surface after storage test.
change PL15, PL16, PL17 to Panasonic
X01
ETQP4LR45XFC (0.45uH 10% Lead Free)
X01
25
P50
+VDD_CORE
1201/2005
Dell
Improve +3.3V_RUN leakage at S3 mode
1. Change PR167 Pin_1 net name from +3.3V_SUS change to +3.3V_RUN

2. Change PR159, PR160 Pin_1 net name from +3.3V_SUS change to +3.3V_RUN
26
P43
Charger
1201/2005
Dell
CoE Charger Ref A10 request: Deeply discharged battery problem.
Add PR208, PD20
X01
27
P50
+VDD_CORE
1202/2005
Dell
Change PR167 to 4.7K to fix stair step issue seen on signal.
Change PR167 to 4.7K
X01
28
P40
+1.5V_RUN
1202/2005
Dell
Add PC192 0.1uF cap to pin 21 of PU4 for power-up sequencing.

Also add PD20 diode in parallel with PR59 for power-down sequencing.
Add PC192, PD21
X01
29
P37
DC_IN
1206/2005
Dell
ChangePR9 from 4.7K to 10K.

The exising 4.7K exceeds power dissipation rating of 0603 size at 20V.
Change PR9 from 4.7K to 10K
X01
P43
Charger
1206/2005
Dell
Unpop PQ27, PR126
Unpop PQ27, PR126
+15VP
1206/2005
Dell
Add a PR209 150 ohm between PD19 Pin_3 and PD18 Pin_2
to prevent +15V_SUSP short cause PD18 damage.
Add PR209 150 ohm
30
X01
P44
31
A
X01
A
Title
Size
Date:
Document Number
Rev
X01
Bali
Sheet
1
56
of
73
Version Change List ( P. I. R.

List ) for Power Circuit Request Owner
Item Page#
32
33
P49
P38
P40
Title
+VDD_CORE
Battery Conn
+1.5VRUNP/+VCCP_1P05VP
Date
Issue
Description
1207/2005
Dell
Dell require to update.
1212/2005
Dell
Change PC98
Solution
Description
from 680PF to 390PF
Rev.
D
X01
1.Add 2200pF_0402 and 0.1uF_0402 unpop Cap at PJBAT1 pin 5 to GND.
2.Change PC192 from 0.1U to 0.47 uF.
3.Pop PC48.
X01
Unpop all 15v charge pump components
34
P39
+15V_CHAGRE PUMP
0215/2006
Dell
1.PU15 AND Gate change to SN74LVC1G08 (+-32mA)

2.Iccrease cap value PC190 at the AND gate Vcc from 0.1uf to 0.47uf.
3. Change PR209 to 0 ohm
(There are already 100k resister for protection against excessive short current.)
4. Add new PR210 7.5k in series with AND Gate input to PWM path from U20.
5. Change out gate resister PR207 from 300 ohm to 120 ohm.
X02
35
P42
+VCC_CORE
0223/2006
Compal
36
P39
+5V_SUSP
0215/2006
Compal
37
P40
+1.5V_RUNP
0215/2006
Dell
+VCC_CORE
0407/2006
Dell
38
Acoustic noise concern
Populate PC76 220uF AL Cap
Power components PL8 interfere with log low
Power components PL10 interfere with log low (pad short risk)
X02
PL8 from 4.7u_STQB125A-4722PF 8A (5.7mm) change to STQB1250-4722APF 7A (5mm).
PL10 change to SIL1045K-3R8-R 8A
Acoustic noise concern
PC98 from 390pf change to 470pf
Dell require to depoplation.
Depop PR119 and PR122
X02
X02
X02
39
P42
+VCC_CORE
0412/2006
Dell
Title
Size
Date:
Document Number
Rev
X01
Bali
Sheet
1
57
of
73

Dell Xps m1210

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A

MODEL NAME : HAL31(Discrete) & HAL30(UMA)

Bali (DIS&UMA) Schematics Document

45140031L11 (For Discrete)

PCB P/N: DA800004W0L

Compal Electronics, Inc.

For Integrity UMA Graphic

+3V_RUN/ +1.5V_RUN 100MHz

AMP & INT.

+3V_RUN/ +1.5V_RUN 100MHz

PCI Express BUS

PCI Express BUS

FSB 533/667 MHz

CPU ITP Port

On I/O daughter Card

Compal Electronics, Inc.

JUSB1 (Ext Back Right Side)

JUSB1 (Ext Back Right Side)

JUSB2 (Ext Back Left Side)

JUSB2 (Ext Back Left Side)

S5 S4/AC don't exist

MINI CARD-1 WWAN

MINI CARD-2 WLAN

Index and Config.

PL8 & PD8

SMBUS Address [D2]

MINI WLAN Card

MINI WWAN Card

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [A0]

SMBUS Address [2F]

SMBUS Address [A2]

LVDS connector Inverter

SMBUS Address [58]

SMBUS Address [16]

SMBUS Address [12]

6.3V10UF 0805 X5R M H:0.85mm, wait CIS symbol.

Place near each pin

Swap signals for

Compal Electronics, Inc.

Pop Ra,Rb,Rc, Rd for 27MHz output for G72

Pop R451 for 27MHz

Monday, April 17, 2006

Stuff R427 for Yonah B0 and

Notes: Can be nopop on X00 board.

No-stuff R253 & R258 for bits issue list: WI52082

Place near JITP

This shall place near CPU

H_THERMDA, H_THERMDC routing together with guard trace,

Compal Electronics, Inc.

Length match within 25 mils

Layout close CPU within 1"

space with other is 50mil

Resistor placed within

POWER, GROUNG, RESERVED SIGNALS AND NC

Compal Electronics, Inc.

0.5 inch (max)

Intel CRB schematic suggest to use X5R or better

Place these inside

Place these inside

Place these inside

Place these inside

10uF 0805 X6S -> 105 degree C