Index: No No Title Title Title No Title No

5 4 3 2 1
D D
INDEX
Page Page Page Page
TITLE TITLE TITLE TITLE
No No No No
01 INDEX 21 TRANSCEIVER 41 HAUL TRANSCEIVER_4 61 DDR2 SDRAM
02 BLOCK DIAGRAM 22 SOURCE TERMINATION 42 HAUL TRANSCEIVER_5 62 DDR2 SDRAM
03 MINI_PCI_CONNECTOR 23 DESTINATION TERMINATION 43 HAUL TRANSCEIVER_6 63 SINGLE UART
04 MINI_PCI_CONNECTOR 24 FLASH 44 T1068NL 64 USB TRANSCEIVER
05 EURO_CONNECTOR 25 DIGITAL SWITCH 45 T1068NL 65 ETHERNET TRANSCEIVER
06 EURO_CONNECTOR 26 DIGITAL SWITCH 46 CYCLONE IV FPGA_1 66 WAN PLL INPUT
07
COMMUNICATION PROCESSOR 27 ETH1_KSZ9021RN 47 CYCLONE IV FPGA_2 67 POWER SUPPLY_12V
C C
08
COMMUNICATION PROCESSOR 28 ETH1_KSZ9021RN 48 CYCLONE IV FPGA_3 68 GENERATION OF VOLTAGES
09
COMMUNICATION PROCESSOR 29 ETH1_KSZ9021RN 49 CYCLONE IV FPGA_4 69 GENERATION OF VOLTAGES
10
COMMUNICATION PROCESSOR 30 ETH1_KSZ9021RN_DECAP 50 CYCLONE IV FPGA_5 70 PS_SEQUENCER & MONITOR
11
COMMUNICATION PROCESSOR 31 ETH2_KSZ9021RN 51 EEPROM 71
12 32 ETH2_KSZ9021RN 52 MEMORY CONTROLLER_1 72

COMMUNICATION PROCESSOR
13 COMMUNICATION PROCESSOR 33 ETH2_KSZ9021RN 53 MEMORY CONTROLLER_2 73
14 34 ETH2_KSZ9021RN_DECAP 54 MEMORY CONTROLLER_3 74

15 35 DSP_TRANS 55 MEMORY CONTROLLER_4 75
16 36 ETHERNET INTERFACE 56 MEMORY CONTROLLER_5 76
B
COMMUNICATION PROCESSOR B
17 37 H1102NL 57 MEMORY CONTROLLER_6

COMMUNICATION PROCESSOR 77
18 DDR2 SDRAM 38 HAUL TRANSCEIVER_1 58
MEMORY CONTROLLER_7 78
19 DDR2 SDRAM 39 HAUL TRANSCEIVER_2 59 MEMORY CONTROLLER_8 79
20 TRANSCEIVER 40 HAUL TRANSCEIVER_3 60 DECAPS OF DSP
A A
Title
USP_V2
Size Document Number Rev

C <Doc> 1
Date: Monday, July 09, 2012 Sheet 1 of 70

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U1A VCC 3V3

MINI PCI(1OF 2)
1 2 3V3
3V3 3V3 3 TIP RING 4
5 8PMJ-3 8PMJ-1 6
7 8PMJ-6 8PMJ-2 8 R1 4.7K
9 8PMJ-7 8PMJ-4 10
11 8PMJ-8 8PMJ-5 12 R2 4.7K
4.7K 13 LED1_GRNP LED2_YELP 14
15 LED1_GRNN LED2_YELN 16 R3 4.7K
17 CHSGND RSV5 18
19 INTBn 5V 20
3.3V_1 INTAn PCI_INT0n
R4 21 22
23 RSV1 RSV6 24
25 GND_7 3.3VAUX1 26
C PCI_CLKOUT CLK RSTn PCI_RSTn C
27 28
29 GND_1 3.3V_4 30
PCI_REQn REQn GNTn PCI_GNT0n
31 32
PCI_AD31 33 3.3V GND_6 34
PCI_AD29 35 AD[31] PMEn 36
37 AD[29] RSV7 38 PCI_AD30
PCI_AD27 39 GND_2 AD[30] 40
PCI_AD25 41 AD[27] 3.3V_3 42 PCI_AD28
43 AD[25] AD[28] 44 PCI_AD26
45 RSV2 AD[26] 46 PCI_AD24
PCI_C_BE3n PCI_AD23 47 CBE3 AD[24] 48 R5 33E PCI_AD23
49 AD[23] IDSEL 50
PCI_AD21 51 GND_3 GND_5 52 PCI_AD22
PCI_AD19 53 AD[21] AD[22] 54 PCI_AD20
55 AD[19] AD[20] 56
GND PAR PCI_PAR
PCI_AD17 57 58 PCI_AD18
59 AD[17] AD[18] 60 PCI_AD16
PCI_C_BE2n 61 CBE2n AD[16] 62
PCI_IRDYn 63 IRDYn GND_4 64
3.3V_2 FRAMEn PCI_FRAMEn
MINI_PCI_TYPE3
B B
PCI_AD[0:31]
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
VCC 3V3 3V3

U1B
MINI PCI(2OF 2)
65 66 PCI_TRDYn
MPCI_CLKRUNn 67 CLKRUNn TRDYn 68
PCI_SERRn SERRn STOPn PCI_STOPn
69 70
71 GND_1 3.3V_3 72
PCI_PERRn PERRn DEVSELn PCI_DEVSELn
73 74
PCI_C_BE1n PCI_AD14 75 CBE1n GND_7 76 PCI_AD15
77 AD[14] AD[15] 78 PCI_AD13
PCI_AD12 79 GND AD[13] 80 PCI_AD11
PCI_AD10 81 AD[12] AD[11] 82
C AD[10] GND_6 C
83 84 PCI_AD9
PCI_AD8 85 GND_2 AD[09] 86
AD[08] CBE0n PCI_C_BE0n
PCI_AD7 87 88
89 AD[07] 3.3V_2 90 PCI_AD6 3V3
PCI_AD5 91 3.3V_1 AD[06] 92 PCI_AD4
93 AD[05] AD[04] 94 PCI_AD2
PCI_AD3 95 RSV3 AD[02] 96 PCI_AD0 R6
97 AD[03] AD[00] 98 4.7K
PCI_AD1 99 5V RSV_WIP1 100
101 AD[01] RSV_WIP2 102
103 GND_3 GND_5 104
AC_SYNC M66EN PCI_M66_EN
105 106
107 AC_SDATA_IN AC_SDATA_OUT 108
109 AC_BIT_CLK AC_CODEC_ID0 110
111 AC_CODEC_ID1 AC_RESETn 112
113 MOD_AUD_MON RSV8 114
115 AUD_GND1 GND_4 116
117 AUD_OUT AUDIO_IN 118
119 AUD_OUT_GND AUDIO_IN_GND 120
121 AUD_GND2 AUD_GND 122
123 RSV4 MPCIACTn 124
VCC5VA 3.3VAUX2
B B
MINI_PCI_TYPE3
PCI_AD[0:31]
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
E1 TRUNK CONNECTOR
D J1A D
E1_TXTIP1 a1 J1B J1C

a2 A1 b1 c1
E1_RXTIP1 A2 B1 E1_TXRING1 C1
E1_TXTIP2 a3 b2 c2
a4 A3 b3 B2 E1_RXRING1 c3 C2
E1_TXTIP3 a5 b4 c4
a7 b6 c6
a9 A8 b8 B7 c8 C7
E1_TXTIP4 A9 B8 C8
a10 b9 E1_TXRING4 c9
E1_RXTIP4 a11 A10 b10 B9 c10 C9
E1_TXTIP5 A11 B10 E1_RXRING4 C10
E1_RXTIP5 a13 A12 b12 B11 c12 C11
E1_RXTIP6 a15 A14 b14 B13 c14 C13
a16 A15 b15 B14 E1_RXRING6 c15 C14
a17 A16 b16 B15 c16 C15
E1_TXTIP7 A17 B16 C16
E1_RXTIP7 a19 A18 b18 B17 c18 C17
E1_RXTIP8 a21 A20 b20 B19 c20 C19
E1_RXTIP9 a23 A22 b22 B21 c22 C21
C A23 B22 E1_RXRING9 C22 C
a24 b23 c23
a25 A24 b24 B23 c24 C23
E1_TXTIP10 A25 B24 C24
E1_RXTIP10 a27 A26 b26 B25 c26 C25
E1_RXTIP11 a29 A28 b28 B27 c28 C27
E1_RXTIP12 a31 A30 b30 B29 c30 C29
a32 A31 b31 B30 E1_RXRING12 c31 C30
A32 b32 B31 c32 C31
B32 C32
EURO CONN
EURO CONN
EURO CONN
B B
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
E1 TRUNK & RS-232 CONNECTOR
D D
J2A J2B J2C

RS232_TX1 a1 b1 c1
a2 A1 b2 B1 RS232_RX1 c2 C1
a3 A2 b3 B2 c3 C2
RS232_TX2 A3 B3 RS232_RX2 C3
a4 b4 c4
a5 A4 b5 B4 c5 C4
a6 A5 b6 B5 c6 C5
A6 BPC0 B6 C6
RS232_DSP_TX a7 BPC1 b7 c7
a8 A7 b8 B7 RS232_DSP_RX c8 C7
A8 BPC2 B8 C8
PCMOUT_CONN0 a9 BPC3 b9 c9
a10 A9 b10 B9 PCMIN_CONN0 c10 C9
PCMOUT_CONN1 A10 B10 PCMIN_CONN1 C10
PCMOUT_CONN2 a11 CONN_SPARE1 b11 c11
a12 A11 b12 B11 PCMIN_CONN2 c12 C11
PCMOUT_CONN3 A12 CONN_SPARE2 B12 PCMIN_CONN3 C12
a13 b13 c13
a14 A13 b14 B13 c14 C13
EURO_8MCLK A14 B14 EURO_SYNC C14
a15 b15 c15
a16 A15 b16 B15 c16 C15
a17 A16 b17 B16 c17 C16
E1_TXTIP13 A17 B17 E1_TXRING13 C17
a18 PB16 b18 c18
E1_RXTIP13 a19 A18 b19 B18 E1_RXRING13 c19 C18
E1_TXTIP14 A19 PB17 B19 E1_TXRING14 C19
a20 b20 c20
C E1_TXTIP15 A21 B21 E1_TXRING15 C21 C
a22 b22 c22
a24 A23 b24 B23 c24 C23
a25 A24 b25 B24 c25 C24
E1_TXTIP16 A25 B25 E1_TXRING16 C25
a26 b26 c26
a28 A27 b28 B27 c28 C27
a29 A28 b29 B28 c29 C28
a30 A29 b30 B29 c30 C29
a31 A30 b31 B30 c31 C30
a32 A31 b32 B31 c32 C31
A32 B32 C32
EURO CONN EURO CONN EURO CONN
B B
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U2B
POWERQUICC II PRO INTEGRATED
COMMUNICATIONS PROCESSOR
(2 OF 12)
K3
D J2 CE_PE0/GPIO110/ENET7_TXD[0]/TDMH_TXD0/UPC1_RXADDR5 D
TDMC_TSYNC CE_PE1/GPIO111/ENET7_TXD[1]/TDMC_TSYNC/UPC1_TXADDR3
TDMG_RSYNC F1
G2 CE_PE2/GPIO112/ENET7_TXD[2]/TDMG_RSYNC/UPC1_RXADDR0
U2A TDMG_TSYNC CE_PE3/GPIO113/ENET7_TXD[3]/TDMG_TSYNC/UPC1_TXADDR0
J5
POWERQUICC II PRO INTEGRATED R707 33E H3 CE_PE4/GPIO114/ENET7_TX_EN/TDMH_TSYNC/UPC1_RXADDR2
COMMUNICATIONS PROCESSOR TDMG_TXD G1 CE_PE5/GPIO115/ENET7_TX_ER/TDMG_TXD0/UPC1_RXADDR1
(1 OF 12) R708 33E H2 CE_PE6/GPIO116/ENET7_RXD[0]/UPC1_TXADDR5/TDMH_RSYNC
AA6 TDMC_TXD K6 CE_PE7/GPIO117/ENET7_RXD[1]/TDMC_TXD0/UPC1_RXADDR4
PB14 UPC1_TXSOC/CE_PB14/GPIO42/ENET4_TXD[0] TDMG_RXD CE_PE8/GPIO118/ENET7_RXD[2]/TDMG_RXD0/UPC1_TXADDR1
AA4 J3
PB15 AA2 UPC1_TXEN0/CE_PB15/GPIO43/ENET4_TXD[1] TDMG_CLK0 K5 CE_PE9/GPIO119/ENET7_RXD[3]/UPC1_POSSTPA/TDMF_RXD0
PB16 Y6 UPC1_TXCLAV0/CE_PB16/GPIO44/ENET4_TXD[2] K4 CE_PE10/GPIO120/ENET7_COL/UPC1_POSRRVAL/TDMF_TXD0
PB17 Y4 UPC1_TXD15/CE_PB17/GPIO45/ENET4_TXD[3] TDMC_RXD L6 CE_PE11/GPIO121/ENET7_CRS/TDMC_RXD0/UPC1_RXADDR3
Y3 UPC1_TXD14/CE_PB18/GPIO46/ENET4_TX_EN P6 CE_PE12/GPIO122/ENET7_RX_DV/TDMH_RXD0/UPC1_TXADDR2
UPC1_TXD13/CE_PB19/GPIO47/ENET4_TX_ER TDMC_RSYNC CE_PE13/GPIO123/ENET7_RX_ER/TDMC_RSYNC/UPC1_TXADDR4
Y2 P4
Y1 UPC1_TXD12/CE_PB20/GPIO48/ENET4_RXD[0] P3 CE_PE14/GPIO124/ENET8_TXD[0]
W6 UPC1_TXD11/CE_PB21/GPIO49/ENET4_RXD[1] P1 CE_PE15/GPIO125/ENET8_TXD[1]
UPC1_TXD10/CE_PB22/GPIO50/ENET4_RXD[2] TDMH_RSYNC CE_PE16/GPIO126/ENET8_TXD[2]/ENET5_TXD0
W5 TDMH_TSYNC N4
W2 UPC1_TXD9/CE_PB23/GPIO51/ENET4_RXD[3] N5 CE_PE17/GPIO127/ENET8_TXD[3]/ENET5_TXD1
V5 UPC1_TXD8/CE_PB24/GPIO52/ENET4_COL R709 33E N2 CE_PE18/GPIO128/ENET8_TX_EN
UPC1_TXD7/CE_PB25/GPIO53/ENET4_CRS TDMH_RXD CE_PE19/GPIO129/ENET8_TX_ER/ENET5_RXD1
V3 N1
V2 UPC1_TXD6/CE_PB26/GPIO54/ENET4_RX_DV M2 CE_PE20/GPIO130/ENET8_RXD[0]
UPC1_TXD5/CE_PB27/GPIO55/ENET4_RX_ER R710 33E M3 CE_PE21/GPIO131/ENET8_RXD[1]
TDMH_TXD M5 CE_PE22/GPIO132/ENET8_RXD[2]/ENET5_RXD0
E11 TDMH_CLK0 M6 CE_PE23/GPIO133/ENET8_RXD[3]/ENET5_TXEN
C UPC1_TXD4/CE_PD0/GPIO82/ENET5_TXD[0] CE_PE24/GPIO134/ENET8_COL/ENET5_RXDVCRS C
D9 L1
C8 UPC1_TXD3/CE_PD1/GPIO83/ENET5_TXD[1] L2 CE_PE25/GPIO135/ENET8_CRS/ENET5_RXER
F11 UPC1_TXD2/CE_PD2/GPIO84/ENET5_TXD[2] L4 CE_PE26/GPIO136/ENET8_RXDVCRS
A7
E9
UPC1_TXD1/CE_PD3/GPIO85/ENET5_TXD[3]
UPC1_TXD0/CE_PD4/GPIO86/ENET5_TX_EN
Optional CE_PE27/GPIO137/ENET8_RX_ER
C7 UPC1_RXSOC/CE_PD5/GPIO87/ENET5_TX_ER V1
A6 UPC1_RXEN0/CE_PD6/GPIO88/ENET5_RXD[0] U6 CE_PC0/GPIO56/CLK1/TDMC_TXCLK
F10 UPC1_RXCLAV0/CE_PD7/GPIO89/ENET5_RXD[1] C19 CE_PC1/GPIO57/CLK2/TDMD_TXCLK
UPC1_RXD15/CE_PD8/GPIO90/ENET5_RXD[2] TDMC_CLK CE_PC7/GPIO63/CLK8/TDMA_RXCLK
B6
D7 UPC1_RXD14/CE_PD9/GPIO91/ENET5_RXD[3]
E8 UPC1_RXD13/CE_PD10/GPIO92/ENET5_COL U4
B5 UPC1_RXD12/CE_PD11/GPIO93/ENET5_CRS U3 CE_PC4/GPIO60/CLK5/TDMB_RXCLK
A5 UPC1_RXD11/CE_PD12/GPIO94/ENET5_RX_DV T6 CE_PC5/GPIO61/CLK6/UPC2_RXCLKIN
C2 UPC1_RXD10/CE_PD13/GPIO95/ENET5_RX_ER T5 CE_PC6/GPIO62/CLK7/RMII_RXCLKEVEN
E4 UPC1_RXD9/CE_PD14/GPIO96/ENET6_TXD[0] T4 CE_PC10/GPIO66/CLK11/TDMB_TXCLK
F5 UPC1_RXD8/CE_PD15/GPIO97/ENET6_TXD[1] T2 CE_PC11/GPIO67/CLK12/TDMC_RXCLK
B1 UPC1_TXERR/CE_PD16/GPIO98/ENET6_TXD[2] T1 CE_PC12/GPIO68/CLK13/UPC1_TXCLKO
D2 UPC1_RXERR/CE_PD17/GPIO99/ENET6_TXD[3] R5 CE_PC13/GPIO69/CLK14/TDMD_RXCLK/UPC1_TXEN3
UPC1_RXD7/CE_PD18/GPIO100/ENET6_TX_EN TDMG_CLK CE_PC14/GPIO70/CLK15/UPC1_RXCLKIN
G5 R3
D1 UPC1_RXPRTY/CE_PD19/GPIO101/ENET6_TX_ER R1 CE_PC15/GPIO71/CLK16/RMII_RXCLKODD
UPC1_RXD6/CE_PD20/GPIO102/ENET6_RXD[0] TDMH_CLK CE_PC16/GPIO72/CLK17/TDME_TXCLK/UPC1_TXCLAV3
E2 C11
H6 UPC1_RXD5/CE_PD21/GPIO103/ENET6_RXD[1] D12 CE_PC17/GPIO73/CLK18/TDMF_RXCLK/UPC1_RXCLAV3
F3 UPC1_TXPRTY/CE_PD22/GPIO104/ENET6_RXD[2] F13 CE_PC18/GPIO74/CLK19/TDMF_TXCLK
E1 UPC1_RXD4/CE_PD23/GPIO105/ENET6_RXD[3] B10 CE_PC19/GPIO75/CLK20/TDMG_RXCLK/XUPC1_RXEN3
B B
F2 UPC1_RXD3/CE_PD24/GPIO106/ENET6_COL C10 CE_PC20/GPIO76/CLK21/TDMG_TXCLK/XUPC1_TXEN2
G3 UPC1_RXD2/CE_PD25/GPIO107/ENET6_CRS E12 CE_PC21/GPIO77/CLK22/TDMH_RXCLK/XUPC1_RXEN2
H4 UPC1_RXD1/CE_PD26/GPIO108/ENET6_RX_DV A9 CE_PC22/GPIO78/CLK23/UPC1_POSTMOD/XTDMH_TXCLK
UPC1_RXD0/CE_PD27/GPIO109/ENET6_RX_ER B8 CE_PC23/GPIO79/CLK24/UPC1_POSRMOD/XTDME_RXCLK
D10 CE_PC24/GPIO80/UPC1_REOP
E15 CE_PC25/GPIO81/UPC1_TEOP
MPC8360E CE_PC27
MPC8360E
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U2C
D POWERQUICC II PRO INTEGRATED D
(3 OF 12)
ETH1_RXD0 F7
B3 CE_PA9/GPIO6/ENET1_RXD[0]
ETH1_RXD1 CE_PA10/GPIO7/ENET1_RXD[1]
ETH1_RXD2 E6
B4 CE_PA11/GPIO8/ENET1_RXD[2]
ETH1_RXD3 CE_PA12/GPIO9/ENET1_RXD[3]
AG1
AE1 CE_PA13/GPIO10/TDMA_TXD0/UPC1_TXCLV1/ENET1_COL/RXD[4]
AE2 CE_PB1/GPIO29/ENET3_TXD1/ENET1_RXD[5]
AD2 CE_PB0/GPIO28/ENET3_TXD0/ENET1_RXD[6]
B2 CE_PB4/GPIO32/ENET3_TXEN/ENET1_RXD[7]
ETH1_RX_DV CE_PA15/GPIO12/ENET1_RX_DV
AF6
AF4 CE_PA14/GPIO11/TDMA_RSYNC/UPC1_RXEN1/ENET1_CRS
F8 CE_PA16/GPIO13/TDMA_TSYNC/UPC1_TXEN1/ENET1_RX_ER
ETH1_RX_CLK CE_PA0/ENET1_RXCLK
R12 33E C5
ETH1_TX_CLK A4 CE_PC9/GPIO65/CLK10/ENET1_GTXCLK
ETH_GTX125 CE_PC8/GPIO64/CLK9/ENET1_INPUT125M
D15
1 8 RN1 F6 CE_PC29/ENET1-TBIRXCLK1
ETH1_TXD0 2 7 D4 CE_PA3/GPIO0/ENET1_TXD[0]
ETH1_TXD1 3 6 C3 CE_PA4/GPIO1/ENET1_TXD[1]
ETH1_TXD2 4 5 E5 CE_PA5/GPIO2/ENET1_TXD[2]
ETH1_TXD3 AC5 CE_PA6/GPIO3/ENET1_TXD[3]
22E AC4 CE_PB6/GPIO34/ENET3_RXD0/ENET1_TXD[4]
C CE_PB7/GPIO35/ENET3_RXD1/ENET1_TXD[5] C
USBRXP AC1
AB5 CE_PB9/GPIO37/ENET4_TXD0/ENET1_TXD[6]
USBRXD CE_PB10/GPIO38/ENET4_TXD1/ENET1_TXD[7] ETH_GTX125
R14 R A3
ETH1_TX_EN AG3 CE_PA7/GPIO4/ENET1_TXEN R16
CE_PA8/GPIO5/TDMA_RXD0/UPC1_RXCLAV1/ENET1_TX_ER
ETH2_RXD0 C18 3V3 3V3
D18 CE_PA23/GPIO20/TDMF_RSYNC/ENET2_RXD[0]
ETH2_RXD1 CE_PA24/GPIO21/TDMD_RSYNC/ENET2_RXD[1]
ETH2_RXD2 E18 4.99E
A18 CE_PA25/GPIO22/TDMD_RXD0/ENET2_RXD[2] R18 R19
ETH2_RXD3 CE_PA26/GPIO23/TDME_RSYNC/ENET2_RXD[3]
AF2 C1
GPIO24 AB3 CE_PA27/GPIO24/TDMB_RXD0/UPC1_TXCLAV2/ENET2_COL/RXD[4]
AB1 CE_PB12/GPIO40/ENET3_RXDVCRS/ENET2_RXD[5] Y1 22pF
AB4 CE_PB13/GPIO41/ENET3_RXER/ENET2_RXD[6] 10K CXO_8M_125MHZ 1K
USBRXN CE_PB11/GPIO39/ENET4_TXEN/ENET2_RXD[7]
ETH2_RX_DV B19 1 3 3V3
CE_PA29/GPIO26/TDME_RXD0/ENET2_RX_DV E_D OUT
BEAD
AE6 2 4 1 2
GPIO25 AE5 CE_PA28/GPIO25/UPC2_RXADDR5/TDMB_RSYNC/ENET2_CRS GND VCC
GPIO27 F16 CE_PA30/GPIO27/TDME_TXD0/ENET2_RX_ER FB1
ETH2_RX_CLK CE_PA31/ENET2_GRXCLK
R21 33E C16 C2 C3 C4
ETH2_TX_CLK A15 CE_PC2/GPIO58/CLK3/ENET2_GTXCLK 0.1uF 0.1uF 0.01uF
ETH_GTX125
B14 CE_PC3/GPIO59/CLK4/TDMA_TXCLK/ENET2_INPUT125M 125 MHz
CE_PC28/ENET2-TBIRXCLK1
B B
RN21 8 B16
ETH2_TXD0 2 7 A16 CE_PA17/GPIO14/TDME_TSYNC/ENET2_TXD[0]
ETH2_TXD1 3 6 E17 CE_PA18/GPIO15/TDMD_TSYNC/ENET2_TXD[1]
ETH2_TXD2 4 5 A17 CE_PA19/GPIO16/TDMD_TXD0/ENET2_TXD[2]
ETH2_TXD3 22E AD5 CE_PA20/GPIO17/TDMB_TSYNC/ENET2_TXD[3]
USBOEN CE_PB2/GPIO30/ENET4_RXD1/ENET2_TXD[4]
USBTXP AD3
AC6 CE_PB3/GPIO31/ENET4_RXDVCRS/ENET2_TXD[5]
AC2 CE_PB5/GPIO33/ENET4_RXER/ENET2_TXD[6]
USBTXP CE_PB8/GPIO36/ENET4_RXD0/ENET2_TXD[7]
R26 33E B17
ETH2_TX_EN AF3 CE_PA21/GPIO18/TDMF_TSYNC/ENET2_TX_EN
CE_PA22/GPIO19/TDMB_TXD0/UPC1_RXCLAV2/ENET2_TX_ER
ETH_MDIO AH1
R30 22E AG5 CE_PA1/SPI_MDIO
ETH_MDC CE_PA2/SPI_MDC
MPC8360E
3V3
A A
C5
0.1uF
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
LAD[0:15] LAD[16:31] U2D LBCK0 LCLK0

POWERQUICC II PRO INTEGRATED R33 22E
(4 OF 12) AC37
LAD0 5 4 RS_LAD0 RS_LAD0 N32 LA27 AA32
LAD1 6 3 RS_LAD1 LAD16 5 4 RS_LAD16 RS_LAD1 N33 LAD0 LA28 AC36
LAD2 7 2 RS_LAD2 LAD17 6 3 RS_LAD17 RS_LAD2 N35 LAD1 LA29 AC34
LAD3 8 1 RS_LAD3 LAD18 7 2 RS_LAD18 RS_LAD3 N36 LAD2 LA30 AD36
D 22E RN3 LAD19 8 1 RS_LAD19 RS_LAD4 P37 LAD3 LA31 M37 R687 0E D
LAD4 LALE LALE
22E RN4 RS_LAD5 P32
RS_LAD6 P34 LAD5 AD33 R34 22E VCC
LAD6 LCS0 nLCS0 J48
RS_LAD7 R36 AG37 R35 22E nLCS1
RS_LAD8 R35 LAD7 LCS1 AF34
LAD4 5 4 RS_LAD4 RS_LAD9 R34 LAD8 LCS2 AE33 R36 22E 3
LAD9 LCS3 nLCS3
LAD5 6 3 RS_LAD5 LAD20 5 4 RS_LAD20 RS_LAD10 R33 AD32 R37 22E nLCS4 LGPL5 2
LAD6 7 2 RS_LAD6 LAD21 6 3 RS_LAD21 RS_LAD11 T37 LAD10 LCS4 AH37 1
LAD7 8 1 RS_LAD7 LAD22 7 2 RS_LAD22 RS_LAD12 T35 LAD11 LCS5
22E RN5 LAD23 8 1 RS_LAD23 RS_LAD13 T34 LAD12 AG35
LAD13 LWE0 nLWE0
22E RN6 RS_LAD14 T33 AG34 nLWE1 JUMPER
RS_LAD15 U37 LAD14 LWE1 AH36
RS_LAD16 T32 LAD15 LWE2 AE32
LAD8 5 4 RS_LAD8 RS_LAD17 U36 LAD16 LWE3 AD35 R688 0E
LAD17 LBCTL LBCTL
LAD9 6 3 RS_LAD9 LAD24 5 4 RS_LAD24 RS_LAD18 U34 VCC
LAD18 J49
LAD10 7 2 RS_LAD10 LAD25 6 3 RS_LAD25 RS_LAD19 V36 G36
LAD11 8 1 RS_LAD11 LAD26 7 2 RS_LAD26 RS_LAD20 V35 LAD19 LCKE J33 LBCK0
22E RN7 LAD27 8 1 RS_LAD27 RS_LAD21 W37 LAD20 LCLK0 J34 3
22E RN8 RS_LAD22 W35 LAD21 LCLK1/LCS_B6 G37 LGPL0 2
RS_LAD23 V33 LAD22 LCLK2/LCS7/CORE_CLK_OUT/CE_CLK_OUT 1
RS_LAD24 V32 LAD23 AB37 R39 4.7K
LAD12 5 4 RS_LAD12 LAD28 5 4 RS_LAD28 RS_LAD25 W34 LAD24 LDP0/CKSTOP_OUT_B AB36
LAD13 6 3 RS_LAD13 LAD29 6 3 RS_LAD29 RS_LAD26 Y36 LAD25 LDP1/CKSTOP_IN_B AB35 R40 4.7K
LAD14 7 2 RS_LAD14 LAD30 7 2 RS_LAD30 RS_LAD27 W32 LAD26 LDP2/LCS_B6 AA33 HEADER 3
C LAD27 LDP3/LCS_B7 C
LAD15 8 1 RS_LAD15 LAD31 8 1 RS_LAD31 RS_LAD28 AA37 LGPL[0:5]
22E RN9 22E RN10 RS_LAD29 Y33 LAD28
RS_LAD30 AA35 LAD29 AB32 LGPL0
RS_LAD31 AA34 LAD30 LSDA10_LGPL0/CFG_RESET_SOURCE[0] AE37 LGPL1 3V3
LAD31 LSDWE/LGPL1/CFG_RESET_SOURCE[1] AD34 LGPL3 VCC
LSDCAS/LGPL3/CFG_RESET_SOURCE[2] J50
AE35 LGPL4 LGPL4
LGTA/LGPL4/LUPWAIT_LPBSE AF36 LGPL5 R41 10K
LGPL5/CFG_CLKIN_DIV 3
LGPL1 2
AC33 LGPL2 1
LSDRAS/LGPL2_LOE_B/RST_LOE_B
F34
G35 LSYNC_OUT
C8 LSYNC_IN C7 HEADER 3
100pF
100pF MPC8360E
SHORT
VCC
J51
R44 0E R45 0E
B B
3
LGPL3 2
R46 0E R47 0E 1
LONG
HEADER 3
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U2E
D COMMUNICATIONS PROCESSOR D
(5 OF 12)
AN13 AN18
AP15 MEMC2_MECC7 MEMC1_MECC7 AM22
AP13 MEMC2_MECC6 MEMC1_MECC6 AM23
AN17 MEMC2_MECC5 MEMC1_MECC5 AM24
AM17 MEMC2_MECC4 MEMC1_MECC4 AN19
AM16 MEMC2_MECC3 MEMC1_MECC3 AM19
AP18 MEMC2_MECC2 MEMC1_MECC2 AN22
AN16 MEMC2_MECC1 MEMC1_MECC1 AP24
AL1 MEMC2_MECC0 MEMC1_MECC0 AP26
AN24 MEMC2_MDQS8/MEMC1_MCK5 MEMC1_MDQS8 AP27
MEMC2_MDM8/MEMC1_MCK4 MEMC1_MDM8
AR29 33E 1 8 RN12

MEMC1_MDQ31 MEMC1_MDQ31
MEMC2_MDQ31 RN11 1 8 33E AH3 AN27 2 7
MEMC1_MDQ63/MEMC2_MDQ31 MEMC1_MDQ30 MEMC1_MDQ30
MEMC2_MDQ30 2 7 AK4 AP29 3 6
MEMC2_MDQ29 3 6 AH4 AN29 4 5
MEMC2_MDQ28 4 5 AJ3 AT32 33E 1 8 RN14
MEMC2_MDQ27 RN13 1 8 33E AJ2 AR30 2 7
MEMC2_MDQ26 2 7 AK3 AM27 3 6
MEMC2_MDQ25 3 6 AH5 AP31 4 5
MEMC2_MDQ24 4 5 AL2 AM26 33E R50
MEMC1_MDQ56/MEMC2_MDQ24 MEMC1_MDQS3 MEMC1_MDQS3
MEMC2_MDQS3 R51 33E AJ5 AN28 33E R52 MEMC1_MDM3
C MEMC1_MDQS7/MEMC2_MDQS3 MEMC1_MDM3 C
R53 33E AJ6
MEMC2_MDM3 MEMC1_MDM7/MEMC2_MDM3
MEMC2_MDQ23 RN15 1 8 33E AM2 AM30 33E 1 8 RN16

MEMC2_MDQ22 2 7 AN4 AM33 2 7
MEMC2_MDQ21 3 6 AL5 AM34 3 6
MEMC2_MDQ20 4 5 AN5 AN33 4 5
MEMC2_MDQ19 RN17 1 8 33E AN3 AM31 33E 1 8 RN18
MEMC2_MDQ18 2 7 AP3 AP32 2 7
MEMC2_MDQ17 3 6 AM5 AR32 3 6
MEMC2_MDQ16 4 5 AP4 AP34 4 5
MEMC2_MDQS2 R54 33E AL4 AN31 33E R55
MEMC1_MDQS6/MEMC2_MDQS2 MEMC1_MDQS2 MEMC1_MDQS2
R56 33E AM3 AP33 33E R57 MEMC1_MDM2
MEMC2_MDM2 MEMC1_MDM6/MEMC2_MDM2 MEMC1_MDM2
MEMC2_MDQ15 RN19 1 8 33E AT3 AT35 33E 1 8 RN20

MEMC2_MDQ14 2 7 AR5 AR36 2 7
MEMC2_MDQ13 3 6 AT5 AP36 3 6
MEMC1_MDQ45MEMC2_MDQ13 MEMC1_MDQ13 MEMC1_MDQ13
MEMC2_MDQ12 4 5 AT6 AP37 4 5
MEMC2_MDQ11 1
RN21 8 33E AR3 AT34 33E 1 8 RN22
MEMC2_MDQ10 2 7 AR4 AR34 2 7
MEMC2_MDQ9 3 6 AP6 AN35 3 6
MEMC2_MDQ8 4 5 AU6 AN37 4 5
B MEMC2_MDQS1 R58 33E AU3 AP35 33E R59 B
R60 33E AU4 AN34 33E R61 MEMC1_MDM1
MEMC2_MDQ7 RN23 1 8 33E AP7 AM36 33E 1 8 RN24

MEMC2_MDQ6 2 7 AT7 AK32 2 7
MEMC2_MDQ5 3 6 AN9 AK34 3 6
MEMC2_MDQ4 4 5 AP9 AJ33 4 5
MEMC2_MDQ3 RN25 1 8 33E AM6 AL35 33E 1 8 RN26
MEMC2_MDQ2 2 7 AM8 AL33 2 7
MEMC2_MDQ1 3 6 AN7 AK33 3 6
MEMC2_MDQ0 4 5 AN8 AJ34 4 5
MEMC2_MDQS0 R62 33E AT8 AK35 33E R63
R64 33E AT9 AL36 33E R65 MEMC1_MDM0
MPC8360E
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U2F
POWERQUICC II PRO INTEGRATED RN27 22E
D COMMUNICATIONS PROCESSOR MEMC1_MA9 1 8 D
(6 OF 12) RS_MEMC1_MA9
MEMC1_MA7 2 7 RS_MEMC1_MA7 RN28 22E
MEMC2_MBA2 AU13 AT30 MEMC1_MBA2 MEMC1_MA1 3 6 RS_MEMC1_MA1 MEMC2_MA3 1 8 RS_MEMC2_MA3
MEMC2_MBA1 AU15 MEMC2_MBA2 MEMC1_MBA2 AU30 MEMC1_MBA1 MEMC1_MA12 4 5 MEMC2_MA7 2 7
MEMC2_MBA1 MEMC1_MBA1 RS_MEMC1_MA12 RS_MEMC2_MA7
MEMC2_MBA0 AU12 AU29 MEMC1_MBA0 MEMC2_MA9 3 6 RS_MEMC2_MA9
MEMC2_MBA0 MEMC1_MBA0 MEMC2_MA6 4 5 RS_MEMC2_MA6
RN29 22E
MEMC2_MA0 AT12 AU21 MEMC1_MA0 MEMC1_MA8 1 8 RS_MEMC1_MA8
MEMC2_MA1 AP11 MEMC2_MA0 MEMC1_MA0 AP22 MEMC1_MA1 MEMC1_MA13 2 7 RN30 22E
MEMC2_MA1 MEMC1_MA1 RS_MEMC1_MA13
MEMC2_MA2 AT13 AP21 MEMC1_MA2 MEMC1_MA4 3 6 RS_MEMC1_MA4 MEMC2_MA4 1 8 RS_MEMC2_MA4
MEMC2_MA3 AT14 MEMC2_MA2 MEMC1_MA2 AT21 MEMC1_MA3 MEMC1_MA0 4 5 MEMC2_MA13 2 7
MEMC2_MA3 MEMC1_MA3 RS_MEMC1_MA0 RS_MEMC2_MA13
MEMC2_MA4 AR13 AU25 MEMC1_MA4 MEMC2_MA8 3 6 RS_MEMC2_MA8
MEMC2_MA5 AR15 MEMC2_MA4 MEMC1_MA4 AU26 MEMC1_MA5 MEMC2_MA12 4 5
MEMC2_MA6 AR16 AT23 MEMC1_MA6
MEMC2_MA7 AT16 MEMC2_MA6 MEMC1_MA6 AR26 MEMC1_MA7 RN31 22E
MEMC2_MA8 AT18 MEMC2_MA7 MEMC1_MA7 AU24 MEMC1_MA8 MEMC1_MA14 1 8 RN32 22E
MEMC2_MA9 AT17 AR23 MEMC1_MA9 MEMC1_MA11 2 7 RS_MEMC1_MA11 MEMC2_MA14 1 8 RS_MEMC2_MA14
MEMC2_MA10 AP10 MEMC2_MA9 MEMC1_MA9 AR28 MEMC1_MA10 MEMC1_MA2 3 6 MEMC2_MA11 2 7
MEMC2_MA10 MEMC1_MA10 RS_MEMC1_MA2 RS_MEMC2_MA11
MEMC2_MA11 AR20 AU23 MEMC1_MA11 MEMC1_MA6 4 5 RS_MEMC1_MA6 MEMC2_MA2 3 6 RS_MEMC2_MA2
MEMC2_MA12 AR17 MEMC2_MA11 MEMC1_MA11 AR22 MEMC1_MA12 MEMC2_MA00 4 5
MEMC2_MA13 AR14 AU20 MEMC1_MA13
MEMC2_MA14 AR11 MEMC2_MA13 MEMC1_MA13 AR18 MEMC1_MA14
MEMC2_MA14 MEMC1_MA14 RN33 22E
MEMC1_MA10 1 8 RS_MEMC1_MA10 RN34
C C
MEMC2_MCAS_n AU11 AT24 MEMC1_MCAS_n MEMC1_MA3 2 7 RS_MEMC1_MA3 MEMC2_MA10 1 8 22E RS_MEMC2_MA10
MEMC2_MRAS_n AT11 MEMC2_MCAS MEMC1_MCAS AT29 MEMC1_MCAS_n
MEMC1_MRAS_n MEMC1_MA5 3 6 MEMC2_MA1 2 7
MEMC2_MRAS MEMC1_MRAS RS_MEMC1_MA5 RS_MEMC2_MA1
MEMC2_MWE_n AU10 AT26 MEMC1_MWEn 4 5 MEMC2_MA5 3 6 RS_MEMC2_MA5
MEMC2_MWE MEMC1_MWE 4 5
MEMC2_MODT0 AT1 AG33 MEMC1_MODT0
AK2 MEMC1_MODT2/MEMC2_MODT0 MEMC1_MODT0 AJ36
AU7 MEMC1_MODT3/MEMC2_MODT1 MEMC1_MODT1 RN35 22E
1V8 MEMC2_MCS0_n AU8 MEMC2_MCS1_n_MEMC1_MCS3_n MEMC1_MBA0 1 8
MEMC2_MCS0_n_MEMC1_MCS2_n RS_MEMC1_MBA0
MEMC2_MCKE0 AN25 AT27 MEMC1_MWEn 2 7 RS_MEMC1_MWE_n RN36 22E
AK1 MEMC2_MCKE1/MEMC1_MCK4 MEMC1_MCS1 AU27 MEMC1_MCSO_n MEMC1_MBA2 3 6 MEMC2_MBA2 1 8
MEMC2_MCKE1/MEMC1_MCK5 MEMC1_MCS0 RS_MEMC1_MBA2 RS_MEMC2_MBA2
4 5 MEMC2_MWE_n 2 7 RS_MEMC2_MWE_n
MEMC2_MBA1 3 6 RS_MEMC2_MBA1
R66 18E AH6 AL32 MEMC1_MCKE0 4 5
R67 18E AP30 MDIC0 MEMC1_MCKE0 AU33
MDIC1 MEMC1_MCKE1 RN37
MEMC1_MBA1 1 8 RS_MEMC1_MBA1 RN38 22E
AU32 AT2 R68 33E RS_MEMC2_MCK1 MEMC1_MRAS_n 2 7 RS_MEMC1_MRAS_n MEMC2_MCAS_n 1 8 RS_MEMC2_MCAS_n
AN20 MVREF2 MEMC2_MCK1/MEMC1_MCK3 AR2 R69 33E MEMC1_MCAS_n 3 6 MEMC2_MRAS_n 2 7
DDR_VREF MVREF1 MEMC2_MCK1/MEMC1_MCK3 RS_MEMC2_MCK1_n RS_MEMC1_MCAS_n RS_MEMC2_MRAS_n
4 5 MEMC2_MBA0 3 6 RS_MEMC2_MBA0
4 5
AU34 AN1 R70 33E RS_MEMC2_MCK0 22E
TEST_SEL_N MEMC2_MCK0/MEMC1_MCK2 AP2 R71 33E
MEMC2_MCK0/MEMC1_MCK2 RS_MEMC2_MCK0_n
B B
AH32 AT37 R72 33E RS_MEMC1_MCK1
AU18 SPARE3 MEMC1_MCK1 AT36 R73 33E
SPARE4 MEMC1_MCK1 RS_MEMC1_MCK1_n
AP1
SPARE5
AK37 R74 33E RS_MEMC1_MCK0
MEMC1_MCK0 AL37 R75 33E
MEMC1_MCK0 RS_MEMC1_MCK0_n
MEMC2_MODT0 R76 22E RS_MEMC2_MODT0
MPC8360E MEMC2_MCS0_n R77 22E RS_MEMC2_MCS0_n
MEMC2_MCKE0 R78 22E RS_MEMC2_MCKE0
MEMC1_MODT0 R79 22E RS_MEMC1_MODT0
MEMC1_MCS0_n R80 22E RS_MEMC1_MCS0_n
A MEMC1_MCKE0 R81 22E RS_MEMC1_MCKE0 A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
TRSTn
TDO
TMS
TCK
TDI
3V3
0E 0E 0E 0E 0E
U2G U7 3V3
POWERQUICC II PRO INTEGRATED R90 1 EEPROM
D COMMUNICATIONS PROCESSOR 2 A0 D
(7 OF 12) 3 A1 8
B13 B36 A2 VCC
R82 R83 R84 R85 R86 SPI_CSn C14 CE_PE31/SPISEL_B QUIESCE 10K C9
SPI_CLK CE_PE30/SPICLK UART1_SOUT
C13 E34 BOOT_WP 7
SPI_MISO CE_PE29/SPIMISO MCP_OUT WP
E14 3V3 0.1uF
SPI_MOSI CE_PE28/SPIMOSI E32 R87 33E 4
UART1_SOUT 6 GND
I2C1_SCL SCL
L32 A35 R93 R94 I2C1_SDA 5
K34 TRST UART1_RTS SDA
K33 TDI B34 AT24C256
TCK UART1_SIN UART1_SIN
J36
3V3 TMS C34 R92 10K
UART1_CTS
BOOT EEPROM
H37 10K 10K
TDO M33
SRESET SRESET_n
R97 10K L37 L36 HRESET_n
PORESETN HRESET
PORESETn R98 0E L35 3V3 U8 3V3
TEST F35 1 EEPROM
IRQ1 MPC_IRQ1n A0
F36 R102 R103 R104 R99 2
IRQ2 MPC_IRQ2n A1
R100 0E AP19 H34 3 8
THERM0 IRQ3 MPC_IRQ3n A2 VCC
R101 0E AT31 G33
THERM1 IRQ4 MPC_IRQ4n
G32 C10
C IRQ5 MPC_IRQ5n C
E35 CKSTOP_OUTn BOARD_WP 7
C37 CS6/CKSTOP_OUT/IRQ_6 H36 WP 0.1uF
MPC_IRQ0n IRQ0_MCP_IN_n LCS7/CKSTOP_IN/IRQ7 CKSTOP_INn
4.7K 4.7K 4.7K 4.7K 4
MPC_CLKIN E37 C35 6 GND
CLKIN IIC2_SCL I2C2_SCL I2C2_SCL SCL
I2C2_SDA 5
R105 E33 SDA
IIC2_SDA I2C2_SDA
A12 AT24C256
D13 CE_PF2/UART2_RTS D34
CE_PF1/UART2_CTS IIC1_SDA I2C1_SDA
R711 0E F14
R689 A11 CE_PF0/UART2_SOUT B35
CE_PF3/UART2_SIN IIC1_SCL I2C1_SCL BOARD EEPROM
10K
AH2
0E PC30_PTP_REF_CLK
UART1_SOUT
B11 A14
UART2_SIN
SPARE1 CE_PC26/RTC_PIT_CLOCK
MPC8360E
B B
3V3
JTAG FOR MPC 3V3 3V3
R108 R109 R106 R107 22E PCI_CLK

3V3 10K
R114 R111 R112 R113 Y2 R110 22E MPC_CLKIN
CXO_8M_25MHZ
1 3
10K 10K J4 E_D OUT FB2 3V3
TDO 1 2 2 4 1 2
TDI 3 4 10K 10K 10K 10K R116 R117 R118 R119 R120 R121 R122 R123 GND VCC
TRSTn
5 6 33 MHz C11 C12 C13
TCK 7 8 R115 0E CKSTOP_INn BEAD
TMS 9 10 0.1uF 0.1uF 0.01uF
SRESET_n R213 0E 11 12
HRESET_n 13 14
A 15 16 10K 10K 10K 10K 10K 10K 10K 10K A
CKSTOP_OUTn
MPC_IRQ0n
MPC_IRQ1n
MPC_IRQ2n
MPC_IRQ3n
MPC_IRQ4n
MPC_IRQ5n
R124 0E
CKSTOP_INn
CKSTOP_OUTn HEADER 8X2
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U2H 3V3
PCI_AD[0:31] (8 OF 12)
PCI_AD31 D20
PCI_AD30 D21 PG31/UPC2_RXEN_B[2]/PCI_AD31
PCI_AD29 A24 PG30/UPC2_TXEN_B[1]/PCI_AD30 R712
PCI_AD28 B23 PG29/UPC2_TXDATA[6]/PCI_AD29
PCI_AD27 C23 PG28/UPC2_TXDATA[7]/PCI_AD28
PCI_AD26 E23 PG27/UPC2_TXDATA[8]/PCI_AD27 4.7K
PCI_AD25 A26 PG26/UPC2_TXDATA[9]/PCI_AD26 W1
PCI_AD24 B21 PG25/UPC2_TXDATA[10]/PCI_AD25
PCI_AD23 C24 PG24/UPC2_RXCLAV[2]/PCI_AD24 1 2
PG23/UPC2_TXDATA[12]/PCI_AD23 FPGA_WD U82
PCI_AD22 C25
PCI_AD21 D25 PG22/UPC2_TXDATA[13]/PCI_AD22 uP VOLTAGE
PCI_AD20 B25 PG21/UPC2_TXDATA[14]/PCI_AD21 JUMPER MONITOR
PCI_AD19 E24 PG20/UPC2_TXDATA[15]/PCI_AD20 3 2
PCI_AD18 F24 PG19/UPC2_M_TXCLAV[0]/PCI_AD19 MR_n RESET_n PORESET_n
PCI_AD17 A27 PG18/UPC2_M_TXEN_B[0]/PCI_AD18 4 1
C PG17/UPC2_TXSOC/PCI_AD17 VCC GND C
PCI_AD16 A28
PCI_AD15 F27 PG16/UPC2_TXPRTY/PCI_AD16
PG15/UPC2_RXPRTY/PCI_AD15 MAX811
PCI_AD14 A30
PCI_AD13 C30 PG14/UPC2_TXDATA[4]/PCI_AD14 SW6
PG13/UPC2_TXCLAV[1]/PCI_AD13
1
2
PCI_AD12 D30
PCI_AD11 E29 PG12/UPC2_TXCLAV[2]/PCI_AD12
PCI_AD10 B31 PG11/UPC2_RXCLAV[1]/PCI_AD11
PCI_AD9 C31 PG10/UPC2_TXDATA[5]/PCI_AD10
PCI_AD8 D31 PG9/UPC2_TXDATA[11]/PCI_AD9
PCI_AD7 D32 PG8/UPC2_RXDATA[2]/PCI_AD8
PCI_AD6 A32 PG7/UPC2_M_TXADDR[4]/PCI_AD7
NOTE: IDSEL pin should be PG6/UPC2_RXDATA[7]/PCI_AD6
tied to low in HOST mode PCI_AD5 C33
PCI_AD4 B33 PG5/UPC2_M_TXADDR[2]/PCI_AD5 5
PCI_AD3F30 PG4/UPC2_M_TXADDR[1]/PCI_AD4
PCI_AD2 E31 PG3/UPC2_M_TXADDR[0]/PCI_AD3
PCI_AD1 A34 PG2/UPC2_RXDATA[3]/PCI_AD2
PCI_AD0 D33 PG1/UPC2_RXDATA[4]/PCI_AD1 SWICTH_1
3
4
R125 R F22 PG0/UPC2_RXDATA[8]/PCI_AD0
PF17/UPC2_RXDATA[12]/PCI_IDSEL
E22
PCI_C_BE3n B26 PF10/UPC2_TXDATA[0]/PCI_C_BE3
PCI_C_BE2n E28 PF9/UPC2_TXDATA[1]/PCI_C_BE2
PCI_C_BE1n F28 PF8/UPC2_TXDATA[2]/PCI_C_BE1
PCI_C_BE0n PF7/UPC2_TXDATA[3]/PCI_C_BE0
B B
MPC8360E
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U2I
3V3 (9 OF 12)
C20
B20 PF25/UPC2_RXEN_B[1]/PCI_GNT[2] 3V3
E20 PF24/UPC2_M_RXADDR[4]/PCI_GNT[1]
PCI_GNT0n PF23/UPC2_M_RXADDR[3]/PCI_GNT[0]
R691 0E C21
R690 0E A21 PF22/UPC2_M_TXADDR[3]/PCI_REQ[2] R692 4.7K
PF21/UPC2_M_RXADDR[2]/PCI_REQ[1] PCI_INT0n
PCI_REQ0n F19
PF20/UPC2_TXEN_B[2]/PCI_REQ[0]
PCI_IRDYn R693 4.7K
C C
PCI_FRAMEn D26
E26 PF12/UPC2_M_RXEN_B[0]/PCI_FRAME
PCI_DEVSELn PF16/UPC2_RXDATA[13]/PCI_DEVSEL
PCI_IRDYn C28 PCI_FRAMEn R694 4.7K
C27 PF14/UPC2_RXDATA[15]/PCI_IRDY
PCI_TRDYn PF13/UPC2_M_RXCLAV[0]/PCI_TRDY
PCI_PERRn A29
B29 PF19/UPC2_RXDATA[10]/PCI_PERR R695 4.7K
PCI_SERRn PF18/UPC2_RXDATA[11]/PCI_SERR PCI_SERRn
PCI_PAR D28
B28 PF11/UPC2_RXSOC/PCI_PAR
PCI_STOPn PF15/UPC2_RXDATA[14]/PCI_STOP
PCI_INTn A20 PCI_PERRn R696 4.7K
E19 PF5/UPC2_M_RXADDR[0]/INTA
PCI_RSTn PF6/UPC2_M_RXADDR[1]/PCI_RSTO
PCI_TRDYn R697 4.7K
A23
D22 PF28/UPC2_RXCLAV[3]/PCI_CLK[2]
B22 PF27/UPC2_TXEN_B[3]/PCI_CLK[1] R698 4.7K
PCI_CLKOUT CE_PF26/PCI_CLK0 PCI_STOPn
PCI_MODE D36
PCI_MODE
PCI_SYNC_OUT D37 PCI_DEVSELn R699 4.7K
PF29/UPC2_TXCLAV[3]/PCI_SYNC_OUT
PCI_SYNC_IN M36
PCI_SYNC_IN
PCI_M66_EN B37
PF4/UPC2_RXDATA[6]/PCI_M66EN
B MPC8360E B
SHORT
R214 0E PCI_CLK
PCI_CLK
R91 0E R88 0E
PCI_SYNC_OUT PCI_SYNC_IN
PCI_SYNC_OUT PCI_SYNC_IN
R95 0E R89 0E
LONG
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U2J
(10 OF 12)
H1 AU14
K1 VSS0 VSS50 C15
M1 VSS1 VSS51 AP16
U1 VSS2 VSS52 D17
W1 VSS3 VSS53 AP17
AD1 VSS4 VSS54 A19
AJ1 VSS5 VSS55 D19
A2 VSS6 VSS56 AR19
P2 VSS7 VSS57 AT19
D3 VSS8 VSS58 AT20
L3 VSS9 VSS60 AP20
T3 VSS10 VSS59 A22
AA3 VSS11 VSS61 AU22
AC3 VSS12 VSS62 D23
AL3 VSS13 VSS63 AN23
C4 VSS14 VSS64 B24
F4 VSS15 VSS65 AR24
C VSS16 VSS66 C
J4 A25
R4 VSS17 VSS67 E25
W4 VSS18 VSS68 AP25
AE4 VSS19 VSS69 AT25
AG4 VSS20 VSS70 C26
AJ4 VSS21 VSS71 B27
AM4 VSS22 VSS72 D27
AT4 VSS23 VSS73 AU28
H5 VSS24 VSS74 B30
L5 VSS25 VSS75 E30
P5 VSS26 VSS76 AN30
U5 VSS27 VSS77 A31
AA5 VSS28 VSS78 AR31
C6 VSS29 VSS79 C32
AG6 VSS30 VSS80 H32
AN6 VSS31 VSS81 J32
AR6 VSS32 VSS82 AC32
B7 VSS33 VSS83 AG32
E7 VSS34 VSS84 AJ32
A8 VSS35 VSS85 A33
D8 VSS36 VSS86 H33
AP8 VSS37 VSS87 L33
AR8 VSS38 VSS88 W33
C9 VSS39 VSS89 AF33
B B
AR9 VSS40 VSS90 G34
AT10 VSS41 VSS91 L34
D11 VSS42 VSS92 M34
B12 VSS43 VSS93 Y34
AP12 VSS44 VSS94 AE34
A13 VSS45 VSS95 AL34
E13 VSS46 VSS96 M35
D14 VSS47 VSS97 P35
AP14 VSS48 VSS98 U35
VSS49 VSS99
MPC8360E
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
1V2
C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D D
1V2
C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
C C
1V2
U2K
(11 OF 12) C36
AC35 VDD53 D35
AH35 VSS100 VDD52 AB33
AJ35 VSS101 VDD51 P33
AR35 VSS102 VDD50 F33
AU35 VSS103 VDD49 AM32
A36 VSS104 VDD48 AF32
E36 VSS105 VDD47 Y32
P36 VSS106 VDD46 U32
W36 VSS107 VDD45 R32 1V2
AE36 VSS108 VDD44 M32
AK36 VSS109 VDD43 K32
F37 VSS110 VDD42 F32 1uF 1uF 1uF 1uF 330uF 220uF
J37 VSS111 VDD41 F31 + +
N37 VSS112 VDD40 F29
V37 VSS113 VDD39 D29
AD37 VSS114 VDD38 AM28 C71 C72 C73 C74 C75 C76
AJ37 VSS115 VDD37 AN26
AR37 VSS116 VDD36 F26
VSS117 VDD35 AM25
B B
VDD34 F25
Y5 VDD33 F23
G6 VDD0 VDD32 AN21
J6 VDD1 VDD31 AM21
N6 VDD2 VDD30 F21
R6 VDD3 VDD29 F20
V6 VDD4 VDD28 AM18
AB6 VDD5 VDD27 F18
AD6 VDD6 VDD26 AU17
AK6 VDD7 VDD25 F17
AL6 VDD8 VDD24 E16
AM7 VDD9 VDD23 AN15
F9 VDD10 VDD22 AM15
AM9 VDD11 VDD21 F15
AU9 VDD12 VDD20 AM14
AM10 VDD13 VDD19 AM13
AM11 VDD14 VDD18 AM12
F12 VDD15 VDD17
VDD16
MPC8360E
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
1V8
1V8
C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90
IuF IuF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
+ +
U2L
1V8 3V3
D POWERQUICC II PRO INTEGRATED D
COMMUNICATIONS PROCESSOR C91 C92
(12 OF 12)
AF1 C1
AM1 GVDD1 OVDD0 J1 1V8
AR1 GVDD2 OVDD1 AA1
AG2 GVDD3 OVDD2 K2
AN2 GVDD4 OVDD3 R2
AU2 GVDD5 OVDD4 U2
AE3 GVDD6 OVDD5 AB2 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106
AD4 GVDD7 OVDD6 E3
AF5 GVDD8 OVDD7 N3
AK5 GVDD9 OVDD8 W3
AP5 GVDD10 OVDD9 G4 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
AU5 GVDD11 OVDD10 M4 3V3
AR7 GVDD12 OVDD11 V4
AN10 GVDD13 OVDD12 B9
AR10 GVDD14 OVDD13 A10
AN11 GVDD15 OVDD14 E10 3V3
AN12 GVDD16 OVDD15 C12 C107 C108
AR12 GVDD17 OVDD16 B15
AN14 GVDD18 OVDD17 C22 + +
AT15 GVDD19 OVDD18 D24
AU16 GVDD20 OVDD19 E27 C109 C110 C111 C112 C113 C114
C GVDD21 OVDD20 C
AR21 C29 220uF 330uF
AT22 GVDD22 OVDD21 B32
AP23 GVDD23 OVDD22 U33
AR25 GVDD24 OVDD23 N34 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
AR27 GVDD25 OVDD24 V34
1V2 AP28 GVDD26 OVDD25 AB34
AT28 GVDD27 OVDD26 H35 3V3
R126 10E AU31 GVDD28 OVDD27 J35
AN32 GVDD29 OVDD28 Y35
C115 C116 AH33 GVDD30 OVDD29 T36
AR33 GVDD31 OVDD30 AA36 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128
AT33 GVDD32 OVDD31 R37
2.2uF 2.2uF AH34 GVDD33 OVDD32 Y37
AF35 GVDD34 OVDD33
AM35 GVDD35 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
AG36 GVDD36 B18 3V3
1V2 AN36 GVDD37 LVDD22 E21
AU36 GVDD38 LVDD21
AF37 GVDD39 C17
AM37 GVDD40 LVDD12 D16 3V3
R127 10E GVDD41 LVDD11
C129 C130 D6
K35 LVDD02 D5
B B
K36 AVDD1 LVDD01 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143
AM29 AVDD2
2.2uF 2.2uF K37 AVDD5 AM20
AVDD6 NC1 AU19
NC2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1V2
R128 10E MPC8360E

3V3
C144 C145
2.2uF 2.2uF
C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156
1V2
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
R129 10E
C157 C158
A A
2.2uF 2.2uF
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U9 U10
RS_MEMC1_MA0 M8 G8 RS_MEMC1_MA0 M8 G8
A0 DQ0 MEMC1_MDQ0 A0 DQ0 MEMC1_MDQ16
RS_MEMC1_MA2 M7 H7 RS_MEMC1_MA2 M7 H7
RS_MEMC1_MA3 N2 H3 RS_MEMC1_MA3 N2 H3
RS_MEMC1_MA6 N7 F1 RS_MEMC1_MA6 N7 F1
D A6 DQ6 MEMC1_MDQ6 A6 DQ6 MEMC1_MDQ22 D
RS_MEMC1_MA7 P2 F9 RS_MEMC1_MA7 P2 F9
RS_MEMC1_MA8 P8 C8 RS_MEMC1_MA8 P8 C8
RS_MEMC1_MA10 M2 D7 RS_MEMC1_MA10 M2 D7
RS_MEMC1_MA11 P7 D3 RS_MEMC1_MA11 P7 D3
RS_MEMC1_MA12 R2 D1 RS_MEMC1_MA12 R2 D1
D9 D9
DQ13 MEMC1_MDQ13 DQ13 MEMC1_MDQ29
B1 B1
RS_MEMC1_MBA0 L2 B9 RS_MEMC1_MBA0 L2 B9
BA0 DQ15 MEMC1_MDQ15 BA0 DQ15 MEMC1_MDQ31
RS_MEMC1_MBA1 L3 RS_MEMC1_MBA1 L3
L1 BA1 RS_MEMC1_MBA2 L1 BA1
RS_MEMC1_MBA2 BA2 BA2
F7 F7
LDQS MEMC1_MDQS0 LDQS MEMC1_MDQS2
E8 E8
J8 LDQS_N_NU J8 LDQS_N_NU
RS_MEMC1_MCK0 CK RS_MEMC1_MCK1 CK
RS_MEMC1_MCK0_n JK8 B7 RS_MEMC1_MCK1_n JK8 B7
CK_N UDQS MEMC1_MDQS1 CK_N UDQS MEMC1_MDQS3
PRIMARY DDR2 MEMORY

RS_MEMC1_MCKE0 K2 A8 RS_MEMC1_MCKE0 K2 A8
CKE UDQS_N_NU CKE UDQS_N_NU
RS_MEMC1_MCS0_n L8 R8 RS_MEMC1_MCS0_n L8 R8
CS_N RFU1 RS_MEMC1_MA13 CS_N RFU1 RS_MEMC1_MA13
MEMC1_MDM0 F3 R3 MEMC1_MDM2 F3 R3
LDM RFU2 RS_MEMC1_MA14 LDM RFU2 RS_MEMC1_MA14
MEMC1_MDM1 B3 R7 R130 0E MEMC1_MDM3 B3 R7 R131 0E
K9 UDM RFU3 RS_MEMC1_MODT0 K9 UDM RFU3
RS_MEMC1_MODT0 ODT ODT
A3 A3
C VSS1 VSS1 C
RS_MEMC1_MRAS_n K7 E3 RS_MEMC1_MRAS_n K7 E3
L7 RAS_N VSS2 J3 RS_MEMC1_MCAS_n L7 RAS_N VSS2 J3
RS_MEMC1_MCAS_n CAS_N VSS3 CAS_N VSS3
RS_MEMC1_MWE_n K3 N1 RS_MEMC1_MWE_n K3 N1
WE_N VSS4 P9 WE_N VSS4 P9
VSS5 VSS5
1V8 A1 1V8 A1
E1 VDD1 A7 E1 VDD1 A7
M9 VDD2 VSSQ1 B2 M9 VDD2 VSSQ1 B2
R1 VDD3 VSSQ2 B8 R1 VDD3 VSSQ2 B8
J9 VDD4 VSSQ3 D2 J9 VDD4 VSSQ3 D2
VDD5 VSSQ4 D8 VDD5 VSSQ4 D8
VSSQ5 E7 VSSQ5 E7
VSSQ6 F2 VSSQ6 F2
1V8 A9 VSSQ7 F8 1V8 A9 VSSQ7 F8
C1 VDDQ1 VSSQ8 H2 C1 VDDQ1 VSSQ8 H2
C7 VDDQ3 VSSQ10 1V8 C7 VDDQ3 VSSQ10 1V8
C9 VDDQ4 C9 VDDQ4
G3 VDDQ5 J7 G3 VDDQ5 J7
E9 VDDQ6 VSSDL J1 E9 VDDQ6 VSSDL J1
G1 VDDQ7 VDDL J2 DDR_VREF G1 VDDQ7 VDDL J2 DDR_VREF
G7 VDDQ8 VREF A2 C159 G7 VDDQ8 VREF A2 C160
G9 VDDQ9 NC1 E2 G9 VDDQ9 NC1 E2
VDDQ10 NC2 VDDQ10 NC2
B B
10nF 10nF
MT47H64M16 MT47H64M16
1V8
1V8
C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 C171 C172 C173 C174 C175 R132 C176
DDR_VREF
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 100E 10nF
RS_MEMC1_MCK0 R133 100E RS_MEMC1_MCK0_n R135

C177 C178 C179 C180 C181
RS_MEMC1_MCK1 R134 100E RS_MEMC1_MCK1_n
1V8
10nF 10nF 100E 10nF 10nF 10nF
A A
C182 C183 C184 C185 C186 C187 C188 C189 C190 C191 C192 C193 C194 C195 C196
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U11 U12
RS_MEMC2_MA2 M7 H7 RS_MEMC2_MA2 M7 H7
RS_MEMC2_MA6 N7 F1 RS_MEMC2_MA6 N7 F1
RS_MEMC2_MA7 P2 F9 RS_MEMC2_MA7 P2 F9
D A8 DQ8 MEMC2_MDQ8 A8 DQ8 MEMC2_MDQ24 D
RS_MEMC2_MA10 M2 D7 RS_MEMC2_MA10 M2 D7
RS_MEMC2_MA11 P7 D3 RS_MEMC2_MA11 P7 D3
RS_MEMC2_MA12 R2 D1 RS_MEMC2_MA12 R2 D1
D9 D9
B1 B1
RS_MEMC2_MBA0 L2 B9 RS_MEMC2_MBA0 L2 B9
BA0 DQ15 MEMC2_MDQ15 BA0 DQ15 MEMC2_MDQ31
RS_MEMC2_MBA1 L3 RS_MEMC2_MBA1 L3
L1 BA1 RS_MEMC2_MBA2 L1 BA1
RS_MEMC2_MBA2 BA2 BA2
F7 F7
LDQS MEMC2_MDQS0 LDQS MEMC2_MDQS2
E8 E8
J8 LDQS_N_NU J8 LDQS_N_NU
RS_MEMC2_MCK0 CK RS_MEMC2_MCK1 CK
RS_MEMC2_MCK0_n JK8 B7 RS_MEMC2_MCK1_n JK8 B7
CK_N UDQS MEMC2_MDQS1 CK_N UDQS MEMC2_MDQS3
PRIMARY DDR2 MEMORY

RS_MEMC2_MCKE0 K2 A8 RS_MEMC2_MCKE0 K2 A8
CKE UDQS_N_NU CKE UDQS_N_NU
RS_MEMC2_MCS0_n L8 R8 RS_MEMC2_MCS0_n L8 R8
CS_N RFU1 RS_MEMC2_MA13 CS_N RFU1 RS_MEMC2_MA13
MEMC2_MDM0 F3 R3 MEMC2_MDM2 F3 R3
LDM RFU2 RS_MEMC2_MA14 LDM RFU2 RS_MEMC2_MA14
MEMC2_MDM1 B3 R7 R136 0E MEMC2_MDM3 B3 R7 R137 0E
K9 UDM RFU3 RS_MEMC2_MODT0 K9 UDM RFU3
RS_MEMC2_MODT0 ODT ODT
A3 A3
K7 VSS1 E3 RS_MEMC2_MRAS_n K7 VSS1 E3
RS_MEMC2_MRAS_n RAS_N VSS2 RAS_N VSS2
RS_MEMC2_MCAS_n L7 J3 RS_MEMC2_MCAS_n L7 J3
C CAS_N VSS3 CAS_N VSS3 C
RS_MEMC2_MWE_n K3 N1 RS_MEMC2_MWE_n K3 N1
WE_N VSS4 P9 WE_N VSS4 P9
VSS5 VSS5
1V8 A1 1V8 A1
E1 VDD1 A7 E1 VDD1 A7
M9 VDD2 VSSQ1 B2 M9 VDD2 VSSQ1 B2
R1 VDD3 VSSQ2 B8 R1 VDD3 VSSQ2 B8
J9 VDD4 VSSQ3 D2 J9 VDD4 VSSQ3 D2
VDD5 VSSQ4 D8 VDD5 VSSQ4 D8
VSSQ5 E7 VSSQ5 E7
VSSQ6 F2 VSSQ6 F2
1V8 A9 VSSQ7 F8 1V8 A9 VSSQ7 F8
C7 VDDQ3 VSSQ10 1V8 C7 VDDQ3 VSSQ10 1V8
C9 VDDQ4 C9 VDDQ4
G3 VDDQ5 J7 G3 VDDQ5 J7
E9 VDDQ6 VSSDL J1 E9 VDDQ6 VSSDL J1
G1 VDDQ7 VDDL J2 G1 VDDQ7 VDDL J2 DDR_VREF
VDDQ8 VREF DDR_VREF VDDQ8 VREF
G7 A2 C197 G7 A2 C198
G9 VDDQ9 NC1 E2 G9 VDDQ9 NC1 E2
VDDQ10 NC2 VDDQ10 NC2
10nF 10nF
B MT47H64M16 MT47H64M16 B
1V8
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
1V8
A A
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
3V3
U17
U16 LA[16:31]
C237 100nF 1 16 C238 100nF U15 TRANS LATCH
C1_p Vcc LA[0:15] LAD[16:31]
3 TRANS LATCH 16-BIT LV CMOS
C1_n LAD[0:15]
2 C240 100nF 16-BIT LV CMOS LAD16 47 2 R714 0E LA16
V_p LAD0 47 2 R715 0E LA0 LAD17 46 D0 O0 3 R716 0E LA17
C239 100nF 4 LAD1 46 D0 O0 3 R717 0E LA1 LAD18 44 D1 O1 5 R718 0E LA18
5 C2_p 6 C241 100nF LAD2 44 D1 O1 5 R719 0E LA2 LAD19 43 D2 O2 6 R720 0E LA19
C2_n V_n LAD3 43 D2 O2 6 R721 0E LA3 LAD20 41 D3 O3 8 R722 0E LA20
LAD4 41 D3 O3 8 R723 0E LA4 LAD21 40 D4 O4 9 R724 0E LA21
11 14 LAD5 40 D4 O4 9 R725 0E LA5 LAD22 38 D5 O5 11 R726 0E LA22
UART1_SOUT T1_IN T1_OUT RS232_TX1 D5 O5 D6 O6
UART2_SOUT 10 7 RS232_TX2 LAD6 38 11 R713 0E LA6 LAD23 37 12 R727 0E LA23
T2_IN T2_OUT LAD7 37 D6 O6 12 R728 0E LA7 LAD24 36 D7 O7 13 R729 0E LA24
13 12 LAD9 35 D8 O8 14 R732 0E LA9 LAD26 33 D9 O9 16 R733 0E LA26
RS232_RX1 R1_IN R1_OUT UART1_SIN D9 O9 D10 O10
RS232_RX2 8 9 UART2_SIN LAD10 33 16 R734 0E LA10 LAD27 32 17 R735 0E LA27
R2_IN R2_OUT LAD11 32 D10 O10 17 R736 0E LA11 LAD28 30 D11 O11 19 R737 0E LA28
15 LAD12 30 D11 O11 19 R738 0E LA12 LAD29 29 D12 O12 20 R739 0E LA29
GND LAD13 29 D12 O12 20 R740 0E LA13 LAD30 27 D13 O13 22 R741 0E LA30
C MAX3232_A D14 O14 D15 O15 C
LAD15 26 23 R744 0E LA15
D15 O15
LALE 48
48 25 LE1
LALE LE1 LE2
25
LE2
1 4
1 4 24 OE1 GND1 10
24 OE1 GND1 10 3V3 OE2 GND2 15
3V3 OE2 GND2 15 GND3 21
GND3 21 18 GND4 28
18 GND4 28 7 VCC1 GND5 34
7 VCC1 GND5 34 42 VCC2 GND6 39
42 VCC2 GND6 39 31 VCC3 GND7 45
31 VCC3 GND7 45 VCC4 GND8
VCC4 GND8
3V3
74LCX16373_LATCH
U18 74LCX16373_LATCH
C242 100nF 1 16 C243 100nF

3 C1_p Vcc
C1_n 2 C244 100nF
V_p
B B
C245 100nF 4
5 C2_p 6 C246 100nF 3V3
C2_n V_n 3V3
11 14
10 T1_IN T1_OUT 7 C251 C252 C253 C254
POC_PR_TXD T2_IN T2_OUT RS232_DSP_TX
C247 C248 C249 C250
13 12
8 R1_IN R1_OUT 9 10nF 10nF 10nF 10nF
RS232_DSP_RX R2_IN R2_OUT POC_PR_RXD
10nF 10nF 10nF 10nF
15
GND
MAX3232_A
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U19
BLA[0:31] 74LCX16245 LA[0:31]
U35
TRANSCEIVER BLA[0:31] 74LCX16245 LA[0:31]
BLA15 2 47 LA15
BLA14 3 B0 A0 46 LA14 BLA31 2 TRANSCEIVER 47 LA31
BLA13 5 B1 A1 44 LA13 BLA30 3 B0 A0 46 LA30
BLA12 6 B2 A2 43 LA12 BLA29 5 B1 A1 44 LA29
8 B3 A3 41 BLA28 6 B2 A2 43 LA28
BPC0 B4 A4 PC0 B3 A3
BPC1 9 40 PC1 BLA27 8 41 LA27
11 B5 A5 38 BLA26 9 B4 A4 40 LA26
BPC2 B6 A6 PC2 B5 A5
BPC3 12 37 PC3 BLA25 11 38 LA25
13 B7 A7 36 BLA24 12 B6 A6 37 LA24
BLGPL2 B8 A8 LGPL2 B7 A7
14 35 BLA23 13 36 LA23
BLALE B9 A9 LALE B8 A8
3V3 3V3 16 33 BLA22 14 35 LA22
BLCS3n B10 A10 nLCS3 B9 A9
17 32 3V3 3V3 BLA21 16 33 LA21
R140 R141 19 30 BLA20 17 32 LA20
C BLWE0n B12 A12 nLWE0 B11 A11 C
20 29 R216 R215 BLA19 19 30 LA19
BLWE1n B13 A13 nLWE1 B12 A12
22 27 BLA18 20 29 LA18
BLBCTL B14 A14 nLBCTL B13 A13
23 26 BLA17 22 27 LA17
BLA16 23 26 LA16
1K B15 A15
1K 1 1K
24 T_R1_N 4 1K 1
T_R2_N GND1 10 24 T_R1_N 4
48 GND2 15 T_R2_N GND1 10
25 OE1_N GND3 21 48 GND2 15
OE2_N GND4 28 25 OE1_N GND3 21
GND5 34 OE2_N GND4 28
7 GND6 39 GND5 34
3V3 18 VCC1 GND7 45 7 GND6 39
31 VCC2 GND8 3V3 18 VCC1 GND7 45
42 VCC3 31 VCC2 GND8
C255 C256 C257 C258 VCC4 42 VCC3
C312 C313 C314 C315 VCC4
74LCX16245
74LCX16245
10nF 10nF 10nF 10nF
10nF 10nF 10nF 10nF
B B
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
FIRST LEVEL DATA BUFFER SECOND LEVEL DATA BUFFER

LBD[0:15] LAD[0:15] BLBD[0:15] LBD[0:15]
U21 U22
74LCX16245 74LCX16245
LBD15 R751 0E 2 TRANSCEIVER 47 LAD15 BLBD15 2 TRANSCEIVER 47 LBD15
D LBD14 R745 0E 3 B0 A0 46 LAD14 BLBD14 3 B0 A0 46 LBD14 D
LBD13 R746 0E 5 B1 A1 44 LAD13 BLBD13 5 B1 A1 44 LBD13
B15 A15 B15 A15
LBCTL 1 BLBCTL 1
24 T_R1_N 4 24 T_R1_N 4
RN45 T_R2_N GND1 10 T_R2_N GND1 10
BLBD[0:15] GND2 GND2
48 15 48 15
BLBD0 1 5 25 OE1_N GND3 21 25 OE1_N GND3 21
OE2_N GND4 28 OE2_N GND4 28
3V3 GND5 34 3V3 GND5 34
C GND6 GND6 C
BLBD1 2 7 39 7 39
18 VCC1 GND7 45 18 VCC1 GND7 45
31 VCC2 GND8 31 VCC2 GND8
BLBD2 3 42 VCC3 42 VCC3
VCC4 VCC4
BLBD3 4 74LCX16245 74LCX16245
BLBD4 6
BLBD5 7
BLBD6 8
BLBD7 9 10
3V3
RC6B470J220M7 3V3
RN46
B B
C263 C264 C265 C266
BLBD15 1 5 C267 C268 C269 C270
BLBD14 2 10nF 10nF 10nF 10nF

10nF 10nF 10nF 10nF
BLBD13 3
BLBD12 4
BLBD11 6
BLBD10 7
BLBD9 8
BLBD8 9 10
A A
RC6B470J220M7
SOURCE TERMINATION Title

USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
RN47
BLA[12:31]
3V3
BLA25 1 5
BLBD[0:15]
BLA26 2 RN49
BLBD0 1 5
BLA27 3 BLBD1 2
D BLBD2 3 D
BLBD3 4
BLA28 4 BLBD4 6
BLBD5 7
BLBD6 8
BLA29 6 BLBD7 9 10
TR8SIP_BCN31_8R
BLA30 7 RN51
BLBD8 1 5
BLBD9 2 3V3
BLA31 8 BLBD10 3
BLBD11 4 RN48
BLBD12 6
BLGPL2 9 10 BLBD13 7 BLWE0n 1 5
BLBD14 8 BLWE1n 2
BLBD15 9 10 BLA[12:31] 3
RC6B470J220M7 BLA12 4
TR8SIP_BCN31_8R BLA13 6
BLA14 7
BLA15 8
BLA16 9 10
TR8SIP_BCN31_8R
C C
RN54 RN50
BLBD[0:15] RN53 BLA17 1 5
BLA18 2
BLWE0n 1 5 BLA19 3
BLBD0 1 5 BLA20 4
BLA21 6
BLWE1n 2 BLA22 7
BLBD1 2 BLA23 8
BLA24 9 10
BLA[12:31] 3
BLBD2 3 TR8SIP_BCN31_8R
RN52
BLA12 4 BLA25 1 5
BLBD3 4 BLA26 2
BLA27 3
BLA13 6 BLA28 4
BLBD4 6 BLA29 6
BLA30 7
BLA14 7 BLA31 8
BLBD5 7 BLGPL2 9 10
BLA15 8 TR8SIP_BCN31_8R
BLBD6 8
B B
BLA16 9 10
BLBD7 9 10
RC6B470J220M7
RC6B470J220M7 RN56
RN55
BLA17 1 5
BLBD15 1 5
BLA18 2
BLBD14 2
BLA19 3
BLBD13 3
BLA20 4
BLBD12 4
BLA21 6
BLBD11 6
A
BLA22 7 DESTINATION TERMINATION A
BLBD10 7
BLA23 8
BLBD9 8
BLA24 9 10 Title
USP_V2
BLBD8 9 10
RC6B470J220M7 Size Document Number Rev
B <Doc> 1
RC6B470J220M7
5 4 3 2 1
5 4 3 2 1
3V3 3V3
R761 R762
D
BOOT 0E EXTRA 0E
D
U23 U24
BOOT_FC1_RY_BYN BOOT_FC2_RY_BYN
LA[0:31] 1GB FLASH MEMORY LA[0:31] 1GB FLASH MEMORY
LA5 R145 0E 55 LA5 R144 0E 55
LA6 R146 0E 56 A25_NC LA6 R147 0E 56 A25_NC
LA7 R148 0E 1 A24_NC LA7 R149 0E 1 A24_NC
A23_NC LBD[0:15] A23_NC LBD[0:15]
LA8 2 17 LA8 2 17
LA9 15 A22 RY_BY_N LA9 15 A22 RY_BY_N
LA10 12 A21 LA10 12 A21
LA11 11 A20 51 LBD0 LA11 11 A20 51 LBD0
LA12 18 A19 DQ15_A_1 49 LBD1 LA12 18 A19 DQ15_A_1 49 LBD1
LA13 19 A18 DQ14 47 LBD2 LA13 19 A18 DQ14 47 LBD2
C A9 DQ5 A9 DQ5 C
LA22 10 44 LBD11 LA22 10 44 LBD11
LA27 24 A4 DQ0 LA27 24 A4 DQ0
LA28 25 A3 52 LA28 25 A3 52
LA29 26 A2 VSS1 33 3V3 LA29 26 A2 VSS1 33 3V3
3V3 LA30 31 A1 VSS2 3V3 LA30 31 A1 VSS2
A0 43 A0 43
VCC 29 VCC 29
32 VIO 32 VIO
nLCS0 CE_N nLCS1 CE_N
LGPL2 34 LGPL2 34
13 OE_N 27 13 OE_N 27
nLWE0 WE_N NC1 nLWE0 WE_N NC1
R150 10K 53 28 R151 10K 53 28
14 BYTE_N NC2 30 14 BYTE_N NC2 30
PORESETn RESET_N NC3 PORESETn RESET_N NC3
BOOT_FL1_WPn 16 BOOT_FL2_WPn 16
WP_N_ACC WP_N_ACC
S29GL01G 3V3 3V3 S29GL01G
B B
R763 R764
0E 0E
3V3
3V3
C271 C272 BOOT_FL1_WPn

C273 C274 C275 C276
+ +
BOOT_FL2_WPn
1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
TIME SWITCH
D D
U25A
DIGITAL SWITCH 4K X 4K
PCMOUT_FR[0:3] PCMIN_FR[0:3]
(01 OF 02)
PCMOUT_FR0 A1 B5 PCMIN_FR0
PCMOUT_FR1 A2 RX0 TX0 A5 PCMIN_FR1
PCMOUT_FR2 B3 RX1 TX1 C6 PCMIN_FR2
PCMOUT_FR3 A3 RX2 TX2 B6 PCMIN_FR3
RX3 TX3
C4 A6 R152 10K
B4 RX4 TX4 C7 R153 10K
RX5 TX5
DSP_TDM_RXD[0:11]
DSP_TDM_TXD[0:11]
DSP_TDM_TXD0 A4 B7 R154 10K DSP_TDM_RXD0
DSP_TDM_TXD1 C5 RX6 TX6 A7 R155 10K DSP_TDM_RXD1
DSP_TDM_TXD2 C8 RX7 TX7 C10 R156 10K DSP_TDM_RXD2
DSP_TDM_TXD3 B8 RX8 TX8 B11 R157 10K DSP_TDM_RXD3
DSP_TDM_TXD4 A8 RX9 TX9 A11 R158 10K DSP_TDM_RXD4
DSP_TDM_TXD5 C9 RX10 TX10 A12 R159 10K DSP_TDM_RXD5
DSP_TDM_TXD6 A9 RX11 TX11 B12 R160 10K DSP_TDM_RXD6
C RX12 TX12 C
DSP_TDM_TXD7 B9 C11 R161 10K DSP_TDM_RXD7
DSP_TDM_TXD8 B10 RX13 TX13 C12 R162 10K DSP_TDM_RXD8
DSP_TDM_TXD9 A10 RX14 TX14 D10 R163 10K DSP_TDM_RXD9
DSP_TDM_TXD10 D11 RX15 TX15 G10 R164 10K DSP_TDM_RXD10
DSP_TDM_TXD11 D12 RX16_IC 0EI0_TX16 G11 R165 10K DSP_TDM_RXD11
RX17_IC 0EI1_TX17
PCMIN_CONN[0:3]
PCMOUT_CONN[0:3]
PCMIN_CONN0 F12 G12 R166 10K PCMOUT_CONN0
PCMIN_CONN1 E10 RX18_IC 0EI2_TX18 H10 R167 10K PCMOUT_CONN1
RX21_IC 0EI5_TX21
TDM1_RXD F10 J10 TDM1_TXD

F11 RX22_IC 0EI6_TX22 J12
TDM2_RXD RX23_IC 0EI7_TX23 TDM2_TXD
TDM3_RXD J11 L10 TDM3_TXD
K11 RX24_IC 0EI8_TX24 M10
RX25_IC 0EI9_TX25
K12 K9
K10 RX26_IC 0EI10_TX26 L9
L11 RX27_IC 0EI11_TX27 M9
L12 RX28_IC 0EI12_TX28 K8
M12 RX29_IC 0EI13_TX29 L8
B B
M11 RX30_IC 0EI14_TX30 M8
RX31_IC 0EI15_TX31
D1
TMS D3
TDI E1
TDO E2
TCK E3
TRSTn
IDT72V71643
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
3V3 3V3
U25B
DIGITAL SWITCH 4K X 4K
BLA[16:30]
(02 OF 02) C277 C278 C279 C280 C281 C282
BLA30 G1 D4
BLA29 G2 A0 VCC_1 D5
BLA28 G3 A1 VCC_2 D6
BLA27 H1 A2 VCC_3 D7 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
BLA26 H2 A3 VCC_4 D8
BLA25 H3 A4 VCC_5 D9
BLA24 J1 A5 VCC_6 E4
BLA23 J2 A6 VCC_7 E9
BLA22 J3 A7 VCC_8 F4
BLA21 K1 A8 VCC_9 F9 3V3
BLA20 K2 A9 VCC_10 G4
BLA19 L1 A10 VCC_11 G9
BLA18 L2 A11 VCC_12 H9
BLA17 M1 A12 VCC_13 J5 C283 C284 C285 C286 C287 C288
BLA16 H4 A13 VCC_14 J6
A14 VCC_15 J7
VCC_16 J8
C VCC_17 C
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
TS_CLK B1
C1 CLK
TS_FOIn FOIn
TS_FE_HCLK C2
D2 FE_HCLK
TS_WFPS WFPS
TD_DSn F1 E5
F2 DSn GND_1 E6
TS_CSn CSn GND_2
TS_R/Wn F3 E7 3V3
K3 R_Wn GND_3 E8
TS_DTAn DTAn GND_4 F5
GND_5 F6
BLBD[0:15] GND_6 F7 C289 C290 C291 C292 C293
BLBD15 K7 GND_7 F8
BLBD14 L7 D0 GND_8 G5
BLBD13 M7 D1 GND_9 G6
BLBD12 K6 D2 GND_10 G7 3V3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
BLBD11 L6 D3 GND_11 G8
BLBD10 M6 D4 GND_12 H5
BLBD9 K5 D5 GND_13 H6
BLBD8 L5 D6 GND_14 H7
BLBD7 M5 D7 GND_15 H8 R765
BLBD6 K4 D8 GND_16 J9
D9 GND_17 0E
BLBD5 M4
BLBD4 L4 D10
B B
BLBD3 L3 D11
BLBD2 M3 D12
BLBD1 M2 D13
BLBD0 J4 D14
D15 C3
RESETn TS_RESETn
B2
ODE TS_ODE
IDT72V71643
3V3
R170 1K
TS_DTAn
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
Strapping Pins
ETH1_DVDDH ETH1_DVDDH ETH1_DVDDH ETH1_DVDDH
R172 R173 R174 R175
D D
ETH1_CLK125_NDO
J5 10K J6 J7 J8
10K 10K 10K
1 1 1 1
C297 22pF XO 2 ETH1_RXD3 2 ETH1_RXD2 2 ETH1_RXD1 2 ETH1_RXD0
ETH1_RSTn
ETH1_INTn
3 3 3 3
R176 R177 R178 R179
Y3
HEADER 3 HEADER 3 HEADER 3 HEADER 3
25MHZ
C299 22pF XI
1K 1K 1K 1K
ETH1_DVDDL
R180 ETH1_DVDDH
ETH_MDIO
MODE3 MODE2 MODE1 MODE0
ETH1_AVDDL
4.99K MODE[3:0] Description MODE[3:0] Description
ETH1_AVDDH
ETH1_AVDDL_PLL 0000 reserved
0001 reserved 1000 reserved
C 0010 reserved 1001 reserved C
0011 NAND Tree mode 1010 reserved
1011 reserved
0100 reserved 1100 Advertise 1000BT full-duplex only (RGMII)
0101 reserved 1101 Advertise 1000BT full- and half-duplex only (RGMII)
0110 Chip Power Down 1110 Advertise all capabilites, except 1000BT half-duplex (RGMII)
49
48
47
46
45
44
43
42
41
40
39
38
37
0111 reserved 1111 Advertise all capabilites (RGMII)
ISET
XI
XO
LDO_O
CLK125_NDO
MDIO
P_GND
AVDDH
AVDDL_PLL
RESET_N
DVDDH_2
DVDDL_4
INT_N
1
2 AVDDH_2 36 2V5
ETH1_TXRXP_A TXRXP_A MDC ETH_MDC
3 35 R766 0E ETH1_RX_CLK
ETH1_TXRXM_A 4 TXRXM_A RX_CLK 34 R182
5 AVDDL KSZ9021RN/48pin QFN DVDDH 33 R767 0E
ETH1_TXRXP_B TXRXP_B RX_DV ETH1_RX_DV
6 32 R768 0E ETH1_RXD0
ETH1_TXRXM_B 7 TXRXM_B RXD0 31 R769 0E
ETH1_TXRXP_C TXRXP_C
KSZ9021RN RXD1 ETH1_RXD1
8 48-pin QFN 30
ETH1_TXRXM_C 9 TXRXM_C DVDDL_3 29
AVDDL_1 Paddle Ground VSS 1K
10 28 R770 0E ETH1_RXD2
ETH1_TXRXP_D 11 TXRXP_D (bottom of chip) RXD2 27 R771 0E
ETH1_TXRXM_D TXRXM_D RXD3 ETH1_RXD3 ETH_MDIO
12 26
AVDDH_1 DVDDL_2 25
TX_EN ETH1_TX_EN
DVDDH_1
GTX_CLK
DVDDL_5
B
DVDDL_1 B
VSS_PS
DVDDL
TXD0
TXD1
TXD2
TXD3
LED2
LED1
ETH1_DVDDH
13
14
15
16
17
18
19
20
21
22
23
24
U26 ETH1_RSTn
R181
R772 4.7K
ETH1_TX_CLK
4.7K TP2
ETH1_INTn
ETH1_TXD3
ETH1_TXD2
INT_N
ETH1_TXD1
ETH1_LED[1:2] ETH1_TXD0
ETH1_LED2
ETH1_LED1
A A
RGMII Loopback
Title
USP_V2
Giga Bit Ethernet Interface Size Document Number Rev

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
Strapping Pins
Single LED Mode
D
Pin Description R227 R228 R229 R230
D
LED2 1 : Link off

0 : Link on (any speed), solid color J21 10K J22 J23 J24
10K 10K 10K
LED1 Blinking : Activity (RX, TX) 1 1 1 1
2 ETH1_RX_DV 2 ETH1_RX_CLK 2 ETH1_LED2 2 ETH1_LED1
3 3 3 3
R231 R232 R233 R234

3V3
ETH1_LED[1:2]
1K 1K 1K 1K
D5 LED R235 220E
D6 LED R236 220E
Strapping Pin CLK125_EN PHYAD2 PHYAD1 PHYAD0
C C
ETH1_DVDDH
Single LED Mode RGMII Clock Delay (option)

R237
10K
Trace Delay is 180ps/1000mil for stripline layer
(inside PCB layer) for FR-4 PCB.
ETH1_CLK125_NDO
Place R238 on PCB Component Side.
Place R239 on PCB Solder Side.
Tri-color Dual LED Mode
LED MODE
R238 4.99 ETH1_RX_CLK
TP9 TP10
R239 0E ETH1_GTX_CLK 10000mils
B B
T POINT T POINT
TP11 TP12
T POINT T POINT
2500mils
Route these RGMII nets on layer 3.
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
T1 CHGND
Differential Differential
Pair Pair
ETH1_TXRXP_A 12 13
TD4- MX4-
ETH1_TXRXM_A 11 14
TD4+ MX4+
10
12
RJ1
C318 0.1uF ETH1_TCT4 10 15 R327 75E ETH1_MCT_CHASSIS 1
CGND
NC
TCT4 MCT4 2 DA+
3 DA-
Pair Pair
9 16 4 DB+
ETH1_TXRXP_B TD3- MX3- DB-
5
6 DC+
7 DC-
CGND1
8 17 8 DD+
ETH1_TXRXM_B
NC1
C TD3+ MX3+ DD- C
11
C319 0.1uF ETH1_TCT3 7 18 R328 75E ETH1_MCT_CHASSIS
TCT3 MCT3
Pair Pair RJ45 Belfuse SS-6488S-A-FLS-50 ETH1_MCT_CHASSIS
ETH1_TXRXP_C 6 19
TD2- MX2- CHGND
ETH1_TXRXM_C 5 20 C320
TD2+ MX2+ 1000pF/2kV
C321 0.1uF
C322 0.1uFETH1_TCT2 4 21 R329 75E ETH1_MCT_CHASSIS
TCT2 MCT2
Pair Pair C323 0.1uF
ETH1_TXRXP_D 3 22
TD1- MX1-
C324 0.1uF
B ETH1_TXRXM_D 2 23 B
TD1+ MX1+
BEAD FB3
C325 0.1uF ETH1_TCT11 24 R330 75E ETH1_MCT_CHASSIS 1 2
TCT1 MCT1
H5007NL CHGND
PULSE H5007NL Transformer
Place FB3 ground bridge for ENET_CGND to

GND (signal ground) return close to GND at
input power to board.
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D
STEWARD D
ETH1_AVDDL U25 - KSZ9021RN
1V2 HI1206N101R-00 ETH1_AVDDL Decouple Pins 4, 9
TP25
BEAD 1 2FB4
C326
C327 C328 C329 C330
+ AVDDL +
10uF/16V 10nF ETH1_DVDDL U25 - KSZ9021RN

0.1uF 47uF/16V 10nF Decouple Pins 14, 18, 23, 26, 30, 39
STEWARD
HI1206N101R-00 ETH1_AVDDL_PLL C345 C346 C347 C348 C349 C350 C351
TP26
+
BEAD 1 2 FB6
10nF 10nF 10nF 10nF 10nF 10nF
47uF/16V
AVDDL_PLL
ETH1_AVDDL_PLL U25 - KSZ9021RN
Decouple Pin 44
STEWARD
ETH1_DVDDL
HI1206N101R-00 C336 C337 C338
C TP27 C
+
BEAD 1 2 FB7
10nF 10nF
C339 47uF/16V
+ C340 DVDDL
10uF/16V 0.1uF
U25 - KSZ9021RN
ETH1_AVDDH Decouple Pins 1,12,47
ETH1_DVDDH U25 - KSZ9021RN
B Decouple Pins 16,34,40 B
2V5 3V3
ETH1_DVDDH ETH1_AVDDH C365
FB8 FB9
C366 C367 C368
TP28 TP29
C355 +
1 2 C356 C357 C358 1 2
+
C353 C354 C363 C364 47uF/16V 10nF 10nF 10nF
+ T POINT + T POINT
BEAD 47uF/16V 10nF 10nF 10nF BEAD
10uF/16V 0.1uF 10uF/16V 0.1uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
Strapping Pins
R187 R188 R189 R190
D D
ETH2_CLK125_NDO
J9 10K J10 J11 J12
10K 10K 10K
1 1 1 1
C301 22pF XO 2 ETH2_RXD3 2 ETH2_RXD2 2 ETH2_RXD1 2 ETH2_RXD0
ETH2_RSTn
ETH2_INTn
3 3 3 3
R191 R192 R193 R194
Y4
25MHZ
C302 22pF XI
1K 1K 1K 1K
ETH2_DVDDH
R196 MODE3 MODE2 MODE1 MODE0

ETH2_DVDDL
ETH2_AVDDL
ETH_MDIO
4.99K MODE[3:0] Description MODE[3:0] Description
ETH2_AVDDH
ETH2_AVDDL_PLL 0000 reserved
0001 reserved 1000 reserved
C 0010 reserved 1001 reserved C
0011 NAND Tree mode 1010 reserved
1011 reserved
0100 reserved 1100 Advertise 1000BT full-duplex only (RGMII)
0101 reserved 1101 Advertise 1000BT full- and half-duplex only (RGMII)
0110 Chip Power Down 1110 Advertise all capabilites, except 1000BT half-duplex (RGMII)
49
48
47
46
45
44
43
42
41
40
39
38
37
0111 reserved 1111 Advertise all capabilites (RGMII)
ISET
XI
XO
LDO_O
CLK125_NDO
MDIO
P_GND
AVDDH
AVDDL_PLL
RESET_N
DVDDH_2
DVDDL_4
INT_N
ETH2_DVDDH
1
2 AVDDH_2 36 ETH2_RSTn
ETH2_TXRXP_A TXRXP_A MDC ETH_MDC
3 35 R774 0E ETH2_RX_CLK R198
ETH2_TXRXM_A 4 TXRXM_A RX_CLK 34 R773 4.7K
5 AVDDL KSZ9021RN/48pin QFN DVDDH 33 R775 0E
ETH2_TXRXP_B TXRXP_B RX_DV ETH2_RX_DV
6 32 R776 0E ETH2_RXD0
ETH2_TXRXM_B 7 TXRXM_B RXD0 31 R777 0E
ETH2_TXRXP_C TXRXP_C
KSZ9021RN RXD1 ETH2_RXD1
8 48-pin QFN 30
ETH2_TXRXM_C 9 TXRXM_C DVDDL_3 29 4.7K TP4
10 AVDDL_1 Paddle Ground VSS 28 R778 0E ETH2_INTn
ETH2_TXRXP_D TXRXP_D RXD2 ETH2_RXD2
11 (bottom of chip) 27 R779 0E ETH2_RXD3
ETH2_TXRXM_D 12 TXRXM_D RXD3 26 INT_N
AVDDH_1 DVDDL_2 25
TX_EN ETH2_TX_EN
DVDDH_1
GTX_CLK
DVDDL_5
B
DVDDL_1 B
VSS_PS
DVDDL
TXD0
TXD1
TXD2
TXD3
LED2
LED1
13
14
15
16
17
18
19
20
21
22
23
24
U29
ETH2_TX_CLK
ETH2_TXD3
ETH2_TXD2
ETH2_TXD1
ETH2_TXD0
A
ETH2_LED[1:2] ETH2_LED2 A
RGMII Loopback
ETH2_LED1
Title
USP_V2
Giga Bit Ethernet Interface Size Document Number Rev

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
Strapping Pins
Single LED Mode
D
Pin Description R268 R269 R270 R271
D
LED2 1 : Link off

0 : Link on (any speed), solid color J25 10K J26 J27 J28
10K 10K 10K
LED1 Blinking : Activity (RX, TX) 1 1 1 1
2 ETH2_RX_DV 2 ETH2_RX_CLK 2 ETH2_LED2 2 ETH2_LED1
3 3 3 3
R272 R273 R274 R275

3V3
ETH2_LED[1:2]
1K 1K 1K 1K
D7 LED R266 220E
D8 LED R267 220E
Strapping Pin CLK125_EN PHYAD2 PHYAD1 PHYAD0
C C
ETH2_DVDDH
Single LED Mode RGMII Clock Delay (option)

R276
10K
Trace Delay is 180ps/1000mil for stripline layer
(inside PCB layer) for FR-4 PCB.
ETH2_CLK125_NDO
Place R252 on PCB Component Side.
Place R253 on PCB Solder Side.
Tri-color Dual LED Mode
LED MODE
R252 4.99 ETH2_RX_CLK
TP13 TP16
R253 0E ETH2_GTX_CLK 10000mils
B B
T POINT T POINT
TP14 TP15
T POINT T POINT
2500mils
Route these RGMII nets on layer 3.
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
T8 CHGND
Pair Pair
ETH2_TXRXP_A 12 13
TD4- MX4-
ETH2_TXRXM_A 11 14
TD4+ MX4+
10
12
RJ2
C716 0.1uF ETH2_TCT4 10 15 R679 75E ETH2_MCT_CHASSIS 1
CGND
NC
TCT4 MCT4 2 DA+
3 DA-
Pair Pair
9 16 4 DB+
ETH2_TXRXP_B TD3- MX3- DB-
5
6 DC+
7 DC-
CGND1
8 17 8 DD+
ETH2_TXRXM_B
NC1
C TD3+ MX3+ DD- C
11
C717 0.1uF ETH2_TCT3 7 18 R680 75E ETH2_MCT_CHASSIS
TCT3 MCT3
Pair Pair RJ45 Belfuse SS-6488S-A-FLS-50 ETH2_MCT_CHASSIS
ETH2_TXRXP_C 6 19
TD2- MX2- CHGND
ETH2_TXRXM_C 5 20 C720
C713 0.1uF
C718 0.1uFETH2_TCT2 4 21 R681 75E ETH2_MCT_CHASSIS
TCT2 MCT2
ETH2_TXRXP_D 3 22
TD1- MX1-
C715 0.1uF
B ETH2_TXRXM_D 2 23 B
TD1+ MX1+
BEAD FB15
C719 0.1uF ETH2_TCT11 24 R682 75E ETH2_MCT_CHASSIS 1 2
TCT1 MCT1
H5007NL CHGND

A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D
STEWARD D
ETH2_AVDDL U29 - KSZ9021RN
1V2 HI1206N101R-00 ETH2_AVDDL Decouple Pins 4, 9
TP42
BEAD 1 2FB18
C746
C748 C740 C741 C742
+ AVDDL +
10uF/16V 10nF ETH2_DVDDL U29 - KSZ9021RN

0.1uF 47uF/16V 10nF Decouple Pins 14, 18, 23, 26, 30, 39
STEWARD
HI1206N101R-00 ETH2_AVDDL_PLL C732 C734 C735 C737 C736 C739 C738
TP43
+
BEAD 1 2 FB19
10nF 10nF 10nF 10nF 10nF 10nF
47uF/16V
AVDDL_PLL
ETH2_AVDDL_PLL U29 - KSZ9021RN
Decouple Pin 44
STEWARD
ETH2_DVDDL
HI1206N101R-00 C743 C744 C745
C TP44 C
+
BEAD 1 2 FB20
10nF 10nF
C749 47uF/16V
+ C750 DVDDL
10uF/16V 0.1uF
U29 - KSZ9021RN
ETH2_AVDDH Decouple Pins 1,12,47
ETH2_DVDDH
B U29 - KSZ9021RN B
2V5 Decouple Pins 16,34,40 3V3
ETH2_DVDDH ETH2_AVDDH C721
FB16 FB17
C722 C724 C723
TP40 TP41
C729 +
1 2 C730 C731 C733 1 2
+
C725 C728 C726 C727 47uF/16V 10nF 10nF 10nF
+ T POINT + T POINT
BEAD 47uF/16V 10nF 10nF 10nF BEAD
10uF/16V 0.1uF 10uF/16V 0.1uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
T9 CHGND
Pair Pair
DSP_MDI_P_0 12 13
TD4- MX4-
DSP_MDI_N_0 11 14
TD4+ MX4+
10
12
RJ3
C754 0.1uF DSP_TCT4 10 15 R683 75E DSP_MCT_CHASSIS 1
CGND
NC
TCT4 MCT4 2 DA+
3 DA-
Pair Pair
9 16 4 DB+
DSP_MDI_P_1 TD3- MX3- DB-
5
6 DC+
7 DC-
CGND1
8 17 8 DD+
DSP_MDI_N_1
NC1
C TD3+ MX3+ DD- C
11
C755 0.1uF DSP_TCT3 7 18 R684 75E DSP_MCT_CHASSIS
TCT3 MCT3
Pair Pair RJ45 Belfuse SS-6488S-A-FLS-50 DSP_MCT_CHASSIS
DSP_MDI_P_2 6 19
TD2- MX2- CHGND
DSP_MDI_N_2 5 20 C758
C751 0.1uF
C756 0.1uFDSP_TCT2 4 21 R685 75E DSP_MCT_CHASSIS
TCT2 MCT2
DSP_MDI_P_3 3 22
TD1- MX1-
C753 0.1uF
B DSP_MDI_N_3 2 23 B
TD1+ MX1+
BEAD FB21
C757 0.1uF DSP_TCT1 1 24 R686 75E DSP_MCT_CHASSIS 1 2
TCT1 MCT1
H5007NL CHGND

A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
D22
LED
D U41 D
10 BASE-T/100 BASE TX
PHY TRANSCEIVER
FET_RMII_RXP 4 R674
3 RXP 12 R676 22E R675
FET_RMII_RXM RXM RXD1 FET_RM_RXD1
C369 22pF FET_RMII_TXP 6 13 R677 22E FET_RM_RXD0
5 TXP RXD0 17 R678 22E
FET_RMII_TXM TXM RXER FET_RM_RX_ER
4.7K 220E
Y7 8
7 XI 15
XO CRS_DV_PHYAD FET_RM_CRS
23 ETH3_TS
C371 22pF R338 R 16 LED0_ANEN_SPEED
FET_RM_REF_CLK 9 REF_CLK 22
11 REXT GND
MDC MDC
10
R339 MDIO 19 MDIO
FET_RMTX_EN TXEN
FET_TXD0 20
21 TXD0
FET_TXD1 TXD1
DSP_ETH_RST2_n 24
6.49K 3V3 18 RST_N
3V3 DSP_ETH_INT2_n INTRP
FB10
14
1 VDDIO
1 2 2 VDD_1V2
C VDDA_3V3 C
BEAD
KSZ8031RNL
C372 C373
C374 C375
10uF 0.1uF
C376 C377
0.1uF
10uF
10uF 0.1uF
B B
3V3 3V3
3V3 3V3
R340 R341
R342 R343
10K 4.7K
DSP_ETH_RST2_n FET_RM_CRS
C378 R344
10K 10K
10uF
1K MDIO DSP_ETH_INT2_n
A A
Title
USP_V2

B <Doc>
1
5 4 3 2 1
5 4 3 2 1
D D
T2 J38
16
FET_ETH_TXP
1 FET_ETH_TXP 1
FET_RMII_TXP 15 R346 75E R345 75E 2
C FET_TERM1 FET_ETH_TXN C
2 FET_ETH_RXP 3
14 FET_TERM1 4
FET_ETH_TXN
3 11 FET_TERM1 5
FET_RMII_TXM FET_ETH_RXP
FET_RMII_RXP 6 FET_ETH_RXN 6
10 R347 75E R348 75E FET_TERM2 7
FET_TERM2
7 FET_TERM2 8
9
FET_ETH_RXN
FET_RMII_RXM 8
C379
H1102NL_T1 HEADER 8
C380 C381
1000pF
100nF 100nF
CHGND
B B
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3V
U42C
LONG/SHORT HAUL TRANSCEIVER
D 3V3 D
F5 A10 C383 C384
G5 VDDIO_1 VDDAR(1) C9
H5 VDDIO_2 VDDAR(2) A5
C385 C386 C387 J5 VDDIO_3 VDDAR(3) A4
J12 VDDIO_4 VDDAR(4) G16 CAP CAP
K5 VDDIO_5 VDDAR(5) H15
K12 VDDIO_6 VDDAR(6) M15
CAP CAP CAP L12 VDDIO_7 VDDAR(7) N16 3V3
M12 VDDIO_8 VDDAR(8)
VDDIO_9
1V8
H6 B12 C390 C391
C388 C389 H7 VDDC_1 VDDAT(1) B9
H8 VDDC_2 VDDAT(2) B5
J6 VDDC_3 VDDAT(3) A3
J7 VDDC_4 VDDAT(4) E15 CAP CAP
CAP CAP J8 VDDC_5 VDDAT(5) H14
J9 VDDC_6 VDDAT(6) M16 3V3
J10 VDDC_7 VDDAT(7) P16
J11 VDDC_8 VDDAT(8)
K6 VDDC_9 C12 C392 C393
K7 VDDC_10 VDDAX(1) B8
C VDDC_12 VDDAX(3) C
K9 B2
K10 VDDC_13 VDDAX(4) E14 CAP CAP
K11 VDDC_14 VDDAX(5) J15
L6 VDDC_15 VDDAX(6) K15
L7 VDDC_16 VDDAX(7) R15 3V3
L8 VDDC_17 VDDAX(8)
L9 VDDC_18
L10 VDDC_19 A13
L11 VDDC_20 VDDAP D12
VDDC_21 VDDAB
C395
B3 C394
E5 GNDA_1 B6
E6 GNDD_1 GNDA_2 B10
E7 GNDD_2 GNDA_3 B11 CAP
E8 GNDD_3 GNDA_4 C3 CAP
E9 GNDD_4 GNDA_5 C5
E10 GNDD_5 GNDA_6 C6
F6 GNDD_8 GNDA_9 C10
F7 GNDD_9 GNDA_10 D3
B B
F11 GNDD_13 GNDA_14 F13
G6 GNDD_15 GNDA_16 G13
G8 GNDD_17 GNDA_18 J14
G9 GNDD_18 GNDA_19 K13
G11 GNDD_20 GNDA_21 L14
H9 GNDD_22 GNDA_23 M14
H10 GNDD_23 GNDA_24 N13
H11 GNDD_24 GNDA_25 P13
GNDD_26 GNDA_27 P15
GNDA_28
IDT82P2288
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
C382 CAP
FRAMER FOR 1-8 TRUNKS
D CXO_7050 D
1 3 R349 R FRM_OSCI
NC_E_D OUT
2 4
U42A GND DCIN
LONG/SHORT HAUL TRANSCEIVER Y10
BLA[21:31] BLBD[0:7]
BLA31 M7 M10 BLBD7
BLA30 N7 A(0) SDO_D(0) T10 BLBD6
BLA29 P7 A(1) D(1) R10 BLBD5
BLA28 R7 A(2) D(2) P10 BLBD4
BLA27 T7 A(3) D(3) M9 BLBD3
BLA26 M8 A(4) D(4) N9 BLBD2 3V3 3CN11G33
BLA25 N8 A(5) D(5) T9 BLBD1 1 3
BLA24 P8 A(6) D(6) R9 BLBD0 STBY_n OUT
BLA23 R8 A(7) D(7) 4 2
BLA22 T8 A(8) C16 R350 R VDD GND
BLA21 P9 A(9) REFR
Y11
A(10) T11
INT_N FRM1_INTn
FRM1_RESETn A14
RESET_N A15
REFA_OUT FRM1_REFA_OUT
FRM1_THZ B16
R351 R THZ B14
REFB_OUT FRM1_REFB_OUT
FRM1_CSn R11
C CS_N C
E13 FRM1_GPIO0
P11 GPIO(0)
FRM_WRn RW_N_WR_N_SDI D13 FRM1_GPIO1 3V3
3V3 N10 GPIO(1)
FRM_RDn DS_N_RD_N_SCLK B13 C747 CAP
OSCI FRM1_INCLK
R352 R M11
MPM C13
3V3 R353 R N11 OSCO CXO_7050
SPIEN A16 1 3 R787 R
D15 CLK_GEN_1.544 NC_E_D OUT
FRM1_CLK_SEL0 CLK_SEL(0)
FRM1_CLK_SEL1 C14 D14 FRM1_CLK_2M 2 4
R354 R355 R356 B15 CLK_SEL(1) CLK_GEN_2.048 GND DCIN
Y15
R357 R R13 A12
TRST_N TTIP(1) TXTIP1
T14 A8
TMS TTIP(2) TXTIP2
T15 A7
TCK TTIP(3) TXTIP3
T13 A1
TDI TTIP(4) TXTIP4
R R R R14 E16 J53
TDO TTIP(5) TXTIP5
FRM1_CLK_SEL2 J16
TTIP(6) TXTIP6
FRM1_CLK_SEL1 K16 1
TTIP(7) TXTIP7
FRM1_CLK_SEL0 RXTIP1 C11 T16 2 FRM1_INCLK
RTIP(1) TTIP(8) TXTIP8
RXTIP2 D8 3
RTIP(2) FRM1_CLK
RXTIP3 D6
R358 R359 B4 RTIP(3) A11
B RXTIP4 TXRING1 B
F14 RTIP(4) TRING(1) A9 HEADER 3
RXTIP5 RTIP(5) TRING(2) TXRING2
RXTIP6 J13 A6
RTIP(6) TRING(3) TXRING3
RXTIP7 L13 A2
RXTIP8 N14 F16 J54
R R H16
TRING(6) TXRING6
L16 1
TRING(7) TXRING7
RXRING1 D11 R16 2 FRM2_INCLK
RRING(1) TRING(8) TXRING8
RXRING2 D9 3
RRING(2) FRM2_CLK
RXRING3 D5
C4 RRING(3)
RXRING4 RRING(4) HEADER 3
RXRING5 G14
H13 RRING(5)
RXRING6 RRING(6)
RXRING7 M13
N15 RRING(7)
RXRING8 RRING(8)
IDT82P2288
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U42B
D D
FRM1_TXDA1 G2 P3 FRM1_RXDA1
G4 MTSDA1_TSD(1) MRSDA1_RSD(1) R2
FRM1_TXDB MTSDB1_TSD(2) MRSDB1_RSD(2) FRM1_RXDB1
F2 R1
F4 TSD(3) RSD(3) P1
E2 TSD(4) RSD(4) N2
FRM1_TXDA2 MTSDA2_TSD(5) MRSDA2_RSD(5) FRM1_RXDA2
FRM1_TXDB2 E4 M4 FRM1_RXDB2
D2 MTSDB2_TSD(6) MRSDB2_RSD(6) M2
C2 TSD(7) RSD(7) L5
TSD(8) RSD(8)
G3 T2
F1 MTSIGA1_TSIG(1) MRSIGA1_RSIG(1) T1
F3 MTSIGB1_TSIG(2) MRSIGB1_RSIG(2) P2
E1 TSIG(3) RSIG(3) N3
D1 MTSIGA2_TSIG(5) MRSIGA2_RSIG(5) M3
C1 MTSIGB2_TSIG(6) MRSIGB2_RSIG(6) M1
B1 TSIG(7) RSIG(7) L4
TSIG(8) RSIG(8)
C C
FRM1_TSYNC L2 R6 FRM1_RSYNC
K4 MTSFS_TSFS(1) MRSFS_RSFS(1) N6
K2 TSFS(2) RSFS(2) T5
J4 TSFS(3) RSFS(3) P5
J2 TSFS(4) RSFS(4) M5
H1 TSFS(5) RSFS(5) R4
H3 TSFS(6) RSFS(6) N4
G1 TSFS(7) RSFS(7) R3
TSFS(8) RSFS(8)
FRM1_TCLK L3 T6 FRM1_RCLK
L1 MTSCK_TSCK(1) MRSCK_RSCK(1) P6
K3 TSCK(2) RSCK(2) M6
K1 TSCK(3) RSCK(3) R5
J3 TSCK(4) RSCK(4) N5
J1 TSCK(5) RSCK(5) T4
H2 TSCK(6) RSCK(6) P4
H4 TSCK(7) RSCK(7) T3
TSCK(8) RSCK(8)
N12 T12
P12 IC1 IC4 C15
B B
R12 IC2 IC5 D16
IC3 IC6
IDT82P2288
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
FRAMER FOR 9-16 TRUNKS
D U43A D
BLA[21:31] BLBD[0:7]
BLA31 M7 M10 BLBD7
BLA30 N7 A(0) SDO_D(0) T10 BLBD6
BLA29 P7 A(1) D(1) R10 BLBD5
BLA28 R7 A(2) D(2) P10 BLBD4
BLA27 T7 A(3) D(3) M9 BLBD3
BLA26 M8 A(4) D(4) N9 BLBD2
BLA25 N8 A(5) D(5) T9 BLBD1
BLA24 P8 A(6) D(6) R9 BLBD0
BLA23 R8 A(7) D(7)
BLA22 T8 A(8) C16 R384 R
BLA21 P9 A(9) REFR
A(10) T11
INT_N FRM2_INTn
FRM2_RESETn A14
RESET_N A15
REFA_OUT FRM2_REFA_OUT
FRM2_THZ B16
R385 R THZ B14
REFB_OUT FRM2_REFB_OUT
FRM2_CSn R11
CS_N E13
GPIO(0) FRM2_GPIO0
FRM_WRn P11
RW_N_WR_N_SDI D13
GPIO(1) FRM2_GPIO1
3V3 FRM_RDn N10
C DS_N_RD_N_SCLK C
B13
OSCI FRM2_INCLK
R386 R M11
MPM C13
3V3 R387 R N11 OSCO
SPIEN A16
D15 CLK_GEN_1.544
FRM2_CLK_SEL1 C14 D14 FRM2_CLK_2M
R388 R389 R390 B15 CLK_SEL(1) CLK_GEN_2.048
R391 R R13 A12
TRST_N TTIP(1) TXTIP9
T14 A8
TMS TTIP(2) TXTIP10
T15 A7
TCK TTIP(3) TXTIP11
T13 A1
TDI TTIP(4) TXTIP12
R R R R14 E16
TDO TTIP(5) TXTIP13
FRM2_CLK_SEL2 J16
TTIP(6) TXTIP14
FRM2_CLK_SEL1 K16
TTIP(7) TXTIP15
FRM2_CLK_SEL0 RXTIP9 C11 T16
RTIP(1) TTIP(8) TXTIP16
RXTIP10 D8
D6 RTIP(2)
RXTIP11 RTIP(3)
R392 R393 RXTIP12 B4 A11
RXTIP13 F14 A9
RXTIP14 J13 A6
RXTIP15 L13 A2
B RXTIP16 N14 F16 B
R R H16
TRING(6) TXRING14
L16
TRING(7) TXRING15
RXRING9 D11 R16
RRING(1) TRING(8) TXRING16
RXRING10 D9
D5 RRING(2)
RXRING11 RRING(3)
RXRING12 C4
G14 RRING(4)
RXRING13 RRING(5)
RXRING14 H13
M13 RRING(6)
RXRING15 RRING(7)
RXRING16 N15
RRING(8)
IDT82P2288
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U43B
FRM2_TXDA1 G2 P3 FRM2_RXDA1
G4 MTSDA1_TSD(1) MRSDA1_RSD(1) R2
FRM2_TXDB MTSDB1_TSD(2) MRSDB1_RSD(2) FRM2_RXDB1
F2 R1
F4 TSD(3) RSD(3) P1
E2 TSD(4) RSD(4) N2
FRM2_TXDA2 MTSDA2_TSD(5) MRSDA2_RSD(5) FRM2_RXDA2
FRM2_TXDB2 E4 M4 FRM2_RXDB2
D2 MTSDB2_TSD(6) MRSDB2_RSD(6) M2
C2 TSD(7) RSD(7) L5
TSD(8) RSD(8)
G3 T2
F1 MTSIGA1_TSIG(1) MRSIGA1_RSIG(1) T1
F3 MTSIGB1_TSIG(2) MRSIGB1_RSIG(2) P2
C TSIG(3) RSIG(3) C
E1 N3
D1 MTSIGA2_TSIG(5) MRSIGA2_RSIG(5) M3
C1 MTSIGB2_TSIG(6) MRSIGB2_RSIG(6) M1
B1 TSIG(7) RSIG(7) L4
TSIG(8) RSIG(8)
FRM2_TSYNC L2 R6 FRM2_RSYNC
K4 MTSFS_TSFS(1) MRSFS_RSFS(1) N6
K2 TSFS(2) RSFS(2) T5
J4 TSFS(3) RSFS(3) P5
J2 TSFS(4) RSFS(4) M5
H1 TSFS(5) RSFS(5) R4
H3 TSFS(6) RSFS(6) N4
G1 TSFS(7) RSFS(7) R3
TSFS(8) RSFS(8)
FRM2_TCLK L3 T6 FRM2_RCLK
L1 MTSCK_TSCK(1) MRSCK_RSCK(1) P6
K3 TSCK(2) RSCK(2) M6
K1 TSCK(3) RSCK(3) R5
B B
J3 TSCK(4) RSCK(4) N5
J1 TSCK(5) RSCK(5) T4
H2 TSCK(6) RSCK(6) P4
H4 TSCK(7) RSCK(7) T3
TSCK(8) RSCK(8)
N12 T12
P12 IC1 IC4 C15
R12 IC2 IC5 D16
IC3 IC6
IDT82P2288
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3V
U43C
D 3V3 D
F5 A10 C404 C408 C409
G5 VDDIO_1 VDDAR(1) C9
H5 VDDIO_2 VDDAR(2) A5
C405 C410 J5 VDDIO_3 VDDAR(3) A4
J12 VDDIO_4 VDDAR(4) G16 CAP CAP CAP
K5 VDDIO_5 VDDAR(5) H15
K12 VDDIO_6 VDDAR(6) M15
CAP CAP L12 VDDIO_7 VDDAR(7) N16 3V3
M12 VDDIO_8 VDDAR(8)
VDDIO_9
1V8
H6 B12 C411 C412
C406 C407 H7 VDDC_1 VDDAT(1) B9
H8 VDDC_2 VDDAT(2) B5
J6 VDDC_3 VDDAT(3) A3
CAP J7 VDDC_4 VDDAT(4) E15 CAP CAP
CAP J8 VDDC_5 VDDAT(5) H14
J9 VDDC_6 VDDAT(6) M16 3V3
J10 VDDC_7 VDDAT(7) P16
J11 VDDC_8 VDDAT(8)
K6 VDDC_9 C12 C413 C414
C VDDC_12 VDDAX(3) C
K9 B2
K10 VDDC_13 VDDAX(4) E14 CAP CAP
K11 VDDC_14 VDDAX(5) J15
L6 VDDC_15 VDDAX(6) K15
L7 VDDC_16 VDDAX(7) R15
L8 VDDC_17 VDDAX(8) 3V3
L9 VDDC_18
L10 VDDC_19 A13
L11 VDDC_20 VDDAP D12
VDDC_21 VDDAB
C415 C416
B3
E5 GNDA_1 B6
E6 GNDD_1 GNDA_2 B10
E7 GNDD_2 GNDA_3 B11 CAP CAP
E8 GNDD_3 GNDA_4 C3
E9 GNDD_4 GNDA_5 C5
F6 GNDD_8 GNDA_9 C10
B B
G8 GNDD_17 GNDA_18 J14
H9 GNDD_22 GNDA_23 M14
H10 GNDD_23 GNDA_24 N13
GNDD_26 GNDA_27 P15
GNDA_28
IDT82P2288
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
T3 T4
TXTIP1 R360 R 1 40 TXTIP5 R361 R 1 40

E1_TXTIP1 E1_TXTIP5
C396 CAP 39 C397 CAP 39
TXRING1 R367 R 2 38 TXRING5 R362 R 2 38

E1_TXRING1 E1_TXRING5
3 37 3 37
RXRING1 E1_RXRING1 RXRING5 E1_RXRING5
R363 R364
4 4
R1 5 36 R1 5 36
RXTIP1 E1_RXTIP1 RXTIP5 E1_RXTIP5
TXTIP2 R365 R 6 35 TXTIP6 R366 R 6 35
E1_TXTIP2 E1_TXTIP6
C C
C398 CAP 34 C399 CAP 34

8 32 8 32
R370 R371
9 9
R1 10 31 R1 10 31
TXTIP3 R372 R 11 30 TXTIP7 R373 R 11 30
E1_TXTIP3 E1_TXTIP7
C400 CAP 29 C401 CAP 29

13 27 13 27
R376 R377
14 14
R1 15 26 R1 15 26
TXTIP4 R378 R 16 25 TXTIP8 R379 R 16 25
E1_TXTIP4 E1_TXTIP8
C402 CAP 24 C403 CAP 24

B 18 22 18 22 B
R382 R383
19 19
R1 20 21 R1 20 21
T1068NL T1068NL
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
T5 T6
TXTIP9 R394 R 1 40 TXTIP13 R395 R 1 40

E1_TXTIP9 E1_TXTIP13
C417 CAP 39 C418 CAP 39

3 37 3 37
R398 R399
4 4
R1 5 36 R1 5 36
TXTIP10 R400 R 6 35 TXTIP14 R401 R 6 35
C C
C419 CAP 34 C420 CAP 34

8 32 8 32
R404 R405
9 9
R1 10 31 R1 10 31
TXTIP11 R406 R 11 30 TXTIP15 R407 R 11 30
C421 CAP 29 C422 CAP 29

13 27 13 27
R410 R411
14 14
R1 15 26 R1 15 26
TXTIP12 R412 R 16 25 TXTIP16 R413 R 16 25
C423 CAP 24 C424 CAP 24

B 18 22 18 22 B
R416 R417
19 19
R1 20 21 R1 20 21
T1068NL T1068NL
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
R418
U45A
CYCLONE IV FPGA
(1 OF 5)
10K
H5 N2 FRM1_RESETn
D TS_INIT_DONE R419 22.1E B2 IO1 IO37_DIFFIO_L16P N1 D
PCMOUT_FR0 IO2_DIFFIO_L1P IO38_DIFFIO_L16N FRM1_CSn
R420 22.1E B1 L7 FRM2_RESETn
PCMOUT_FR1 R421 22.1E G5 IO3_DIFFIO_L1N IO39 M5
PCMOUT_FR2 IO4 IO40_VREFB2N0 FRM2_CSn
E4 P2 FRM1_THZ 3V3
R422 22.1E E3 IO5_DIFFIO_L2P_NRESET IO41_DIFFIO_L17P P1
PCMOUT_FR3 IO6_DIFFIO_L2N IO42_DIFFIO_L17N FRM_RDn
R423 22.1E C2 R2 FRM_WRn U44 BPFD_OUT1
R428 22.1E C1 IO7_DIFFIO_L3P IO43_DIFFIO_L18P R1 DUAL OPAMP
IO8_DIFFIO_L3N IO44_DIFFIO_L18N FRM2_THZ
R424 22.1E D2 N5 FRM1_CLK 1 8
D1 IO9_DIFFIO_L4P IO45 P4 2 A_OUT V+ 7 C425 68KpF
ADSO1 IO10_DIFFIO_L4N_DATA1_ASDO IO46_DIFFIO_L19P FRM2_CLK A_IN- B_OUT
PCMIN_FR0 H7 P3 PFD_OUT1 3 6
IO11_VREFB1N0 IO47_DIFFIO_L19N FRM1_REFA_OUT A_IN+ B_IN-
PCMIN_FR1 H6 U2 4 5 R425 22.1K R426 22.1K
IO12_DIFFIO_L5P IO48_DIFFIO_L20P FRM1_REFB_OUT V- B_IN+
R427 22.1E J6 U1
IO13_DIFFIO_L5N IO49_DIFFIO_L20N FRM2_REFA_OUT
nCSO1 E2 V2 C426
IO14_DIFFIO_L6P_FLASH_NCE_NCSO IO50_DIFFIO_L21P FRM2_REFB_OUT
PCMIN_FR2 E1 V1 LM358
IO15_DIFFIO_L6N IO51_DIFFIO_L21N FRM2_CLK_2M
PCMIN_FR3 F2 P5
F1 IO16_DIFFIO_L7P IO52 N6 33KpF
IO17_DIFFIO_L7N IO53_DIFFIO_L22P FRM1_CLK_2M
R429 22.1E G4 M7
R430 22.1E G3 IO18_DIFFIO_L8P IO54_DIFFIO_L22N M8
IO19_DIFFIO_L8N IO55_DIFFIO_L23P FRM2_GPIO0
N8
IO56_DIFFIO_L23N FRM2_GPIO1
W2
IO57_DIFFIO_L24P FRM1_GPIO0
nSTATUS1 K6 W1
NSTATUS IO58_DIFFIO_L24N FRM1_GPIO1
Y2 FRM2_TXDA1
IO59_DIFFIO_L25P Y1
IO60_DIFFIO_L25N FRM2_TXDA2
L8 T3 FRM2_TXDB1
C IO20_DIFFIO_L9P IO61_VREFB2N1 C
K8 N7 FRM2_TXDB2 3V3
J7 IO21_DIFFIO_L9N IO62_DIFFIO_L26P P7 Y12
IO22_DIFFIO_L10P IO63_DIFFIO_L26N FRM1_TXDA1
K7 AA1 TCXO
IO23_DIFFIO_L10N IO64_DIFFIO_L27N FRM1_TXDA2
J4 V4 FRM1_TXDB1 BPFD_OUT1 1 4
H2 IO24 IO65_RUP1 V3 CV VD
IO25_DIFFIO_L11P IO66_RDN1 FRM1_TXDB2
R431 22.1E H1 P6 FPGA_8MCLK1 2 3 PLL_CLK1
R432 22.1E J3 IO26_DIFFIO_L11N IO67_DIFFIO_L28P R5 GND OUT
IO27_VREFB1N1 IO68_DIFFIO_L28N TPM_SYNC
LGPL4 J2 T4 TCXO7050
J1 IO28_DIFFIO_L12P IO69 T5 32.768MHZ
IO29_DIFFIO_L12N IO70_DIFFIO_L29P FAN_FAIL
R6
IO71_DIFFIO_L29N R7
K2 IO72_DIFFIO_L30P T7
DCLK1 DCLK IO73_DIFFIO_L30N P8
K1 IO74_DIFFIO_L31P R8
DATA1 IO30_DATA0 IO75_DIFFIO_L31N R9
IO76_DIFFIO_B1P T8
K5 IO77_DIFFIO_B1N R10
nCONFIG1 NCONFIG IO78_DIFFIO_B2P
TDI1 L5 T9
L2 TDI IO79_DIFFIO_B2N V6
TCK1 TCK IO80_DIFFIO_B3P FPGA_WD
TMS1 L4 V5
TMS IO81_DIFFIO_B3N ETH1_INTn
TDO1 L1 U7
TDO IO82_DIFFIO_B4P ETH2_INTn
nCE1 L3 U8
NCE IO83_DIFFIO_B4N Y4
IO84_VREFB3N1 PCI_INT0n
B R11 B
G1 IO85_DIFFIO_B5P R12
LCLK0 CLK1_DIFFCLK_0N IO86_DIFFIO_B5N
PLL_CLK1 T2 Y3
T1 CLK2_DIFFCLK_1P IO87_DIFFIO_B6P Y6
FPGA_25MHZ CLK3_DIFFCLK_1N IO88
L6
M6 IO31_DIFFIO_L13P
M2 IO32_DIFFIO_L13N
M1 IO33_DIFFIO_L14P
DSP_WDOUTn IO34_DIFFIO_L14N
M4
M3 IO35_DIFFIO_L15P
CONF0 IO36_DIFFIO_L15N
EP4CE15F23C8N
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
U45B
CYCLONE IV FPGA R439
(2 OF 5)
D D
AA3 AA17 DTK14 U46
AB3 IO89_PLL1_CLKOUTP IO133_DIFFIO_B25P AB17 ZERO DELAY
IO90_PLL1_CLKOUTN IO134_DIFFIO_B25N DTK15
R440 R W6 R13 BUFFER
TDMC_RXD IO91_DIFFIO_B7P IO135 ETH1_TS
R437 R V7 V13 10K 9 2 R441 22.1E TDMC_CLK
TDMH_RXD IO92_DIFFIO_B7N IO136 ETH2_TS S1 CLKA1
R438 R AA4 W14 8 3 R442 22.1E TDMH_CLK
TDMG_RXD IO93_DIFFIO_B8P IO137_VREFB4N1 ETH3_TS S2 CLKA2
R443 R AB4 U13 SHUT_DOWN 14 R444 22.1E TDMG_CLK
AA5 IO94_DIFFIO_B8N IO138_DIFFIO_B26P V14 1 CLKA3 15 R445 22.1E
IO95_DIFFIO_B9P IO139_DIFFIO_B26N USBSPDn PCM_8MCLK REF CLKA4
AB5 V15
IO96_DIFFIO_B9N IO140_DIFFIO_B27P USBENn
W7 W15 6
Y7 IO97_DIFFIO_B10P IO141_DIFFIO_B27N T14 16 CLKB1 7 R446 22.1E
TDMC_TXD IO98_DIFFIO_B10N IO142_DIFFIO_B28P FBK CLKB2 DSP_8MCLK
U9 T15 10
TDMH_TXD V8 IO99_DIFFIO_B11P IO143_DIFFIO_B28N AB18 CLKB3 11 R788 22.1E
TDMG_TXD IO100_DIFFIO_B11N IO144 CLKB4 EURO_8MCLK
FRM2_RXDA1 W8 AA18
AA7 IO101 IO145 AA19 CY2308
FRM2_RXDA2 IO102_DIFFIO_B12P IO146_RUP2
FRM2_RXDB1 AB7 AB19 DSP_RESET_n
Y8 IO103_DIFFIO_B12N IO147_RDN2 W17
FRM2_RXDB2 IO104_DIFFIO_B13P IO148_DIFFIO_B29P POC_PR_FAIL
FRM1_RXDA1 V9 Y17
V10 IO105_VREFB3N0 IO149_DIFFIO_B29N V16
FRM1_RXDA2 IO106 IO150_VREFB4N0
FRM1_RXDB1 T10 AA20 HRESET_n
U10 IO107_DIFFIO_B14P IO151_DIFFIO_B30P AB20
FRM1_RXDB2 IO108_DIFFIO_B14N IO152_DIFFIO_B30N POR_n
FRM2_TSYNC AA8
AB8 IO109_DIFFIO_B15P
FRM1_TSYNC IO110_DIFFIO_B15N
FRM2_RSYNC T11
C IO111 C
FRM1_RSYNC AA9 T16 LRESET_n
AB9 IO112_DIFFIO_B16P IO153_PLL4_CLKOUTP R16
ETH1 IO113_DIFFIO_B16N IO154_PLL4_CLKOUTN DSP_NM1n
U11
ETH2 V11 IO114
DSP0 W10 IO115_DIFFIO_B17P U15
DSP1 IO116_DIFFIO_B17N IO155_DIFFIO_B31P MSEL2_1
Y10 U14
DIS_CLK IO117_DIFFIO_B18P IO156_DIFFIO_B31N SYNC_4M
AA10 R14 MSEL3_1
DISP_PBUT_n AB10 IO118_DIFFIO_B18N IO157_DIFFIO_B32P R15
DTK0 IO119 IO158_DIFFIO_B32N AA21 R447 R448
IO159_DIFFIO_R35P MSEL0_1
P14 LRESETNM1ENn
AA11 IO160 T17 R449
CLK_8M CLK15_DIFFCLK_6P IO161_RUP3
CLK_16M AB11 T18
CLK14_DIFFCLK_6N IO162_RDN3 SYNC_8M
CLK_32M AA12 W20 1K
AB12 CLK13_DIFFCLK_7P IO163_DIFFIO_R34N W19
CLK12_DIFFCLK_7N IO164_DIFFIO_R34P SYNC_16M
Y22 1K
IO165_DIFFIO_R33N SYNC_32M
Y21 1K
IO166_DIFFIO_R33P TDM2_TXD
U20 R450 22.1E TDM2_RXD
AA13 IO167_DIFFIO_R32N U19 R451 22.1E
DTK1 IO120_DIFFIO_B19P IO168_DIFFIO_R32P TDM1_RXD
AB13 N14
DTK2 IO121_DIFFIO_B19N IO169 TDM1_TXD
AA14 W22
DTK3 IO122_DIFFIO_B20P IO170_DIFFIO_R31N FRM2_TCLK
AB14 W21
DTK4 IO123_DIFFIO_B20N IO171_DIFFIO_R31P FRM1_TCLK
V12 P15
DTK5 IO124 IO172_DIFFIO_R30N FRM2_RCLK
W13 P16
DTK6 IO125_DIFFIO_B21P IO173_DIFFIO_R30P FRM1_RCLK
B Y13 R17 B
DTK7 IO126_DIFFIO_B21N IO174_VREFB5N1 CLK_2M
AA15 M15
DTK8 IO127_DIFFIO_B22P IO175_DIFFIO_R29N TDM3_TXD
AB15 N15 R789 22.1E TDM3_RXD
DTK9 U12 IO128_DIFFIO_B22N IO176_DIFFIO_R29P P17
DTK10 IO129_DIFFIO_B23P IO177 PFD_OUT1
T12 V22 3V3 2V5
DTK11 AA16 IO130_DIFFIO_B23N IO178_DIFFIO_R28N V21
DTK12 IO131_DIFFIO_B24P IO179_DIFFIO_R28P DPLL_RST_n
AB16 R20 R452
DTK13 IO132_DIFFIO_B24N IO180 PCM_8MCLK
U22 DPLL_FREF R453
IO181_DIFFIO_R27N U21
IO182_DIFFIO_R27P
10K
nSTATUS1 1K
EP4CE15F23C8N
MSEL1_1
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
FPGA PROM
PROGRAMMER CONNECTOR
R454 R455
J39 3V3
U45C
CYCLONE IV FPGA 1 2
D DCLK1 D
(3 OF 5) 3 4
PORESETn R18 F22 CONF_DONE_TS 10K 10K 5 6
R19 IO183_DIFFIO_R26N IO220_DIFFIO_R11N F21 7 8
HRESETn IO184_DIFFIO_R26P IO221_DIFFIO_R11P BLALE BLA[12:31]
N16 H20 BLA12 nCONFIG1 9 10 nCE1
R22 IO185 IO222_DIFFIO_R10N H19 BLA13
R21 IO186_DIFFIO_R25N IO223_DIFFIO_R10P E22 BLA14
FRM1_INTn IO187_DIFFIO_R25P IO224_DIFFIO_R9N_NWE DATA1 nCSO1
P20 E21 BLA15
P22 IO188_VREFB5N0 IO225_DIFFIO_R9P_NOE H18 BLA16 HDR5X2 R456
IO189_IFFIO_R24N IO226_VREFB6N0 ADSO1
P21 J17 BLA17
N20 IO190_DIFFIO_R24P IO227_DIFFIO_R8N H16 BLA18
N19 IO191_DIFFIO_R23N IO228_DIFFIO_R8P D22 BLA19
FRM2_INTn
JTAG CONNECTOR
N17 IO192_DIFFIO_R23P IO229_DIFFIO_R7N D21 BLA20
TS_CLK IO193_DIFFIO_R22N IO230_DIFFIO_R7P
TS_FOIn N18 F20 BLA21
N22 IO194_DIFFIO_R22P IO231_DIFFIO_R6N_NAVD F19 BLA22 2V5 10K
TS_FE_HCLK IO195_DIFFIO_R21N_DEV_OE IO232_DIFFIO_R6P
TS_WFPS N21 G18 BLA23
M22 IO196_DIFFIO_R21P_DEV_CLRN IO233_DIFFIO_R5N_PADD23 H17 BLA24
TD_DSn IO197_DIFFIO_R20N IO234_DIFFIO_R5P
TS_CSn M21 C22 BLA25
M20 IO198_DIFFIO_R20P IO235_DIFFIO_R4N C21 BLA26
TS_R/Wn
FPGA
M19 IO199_DIFFIO_R19N IO236_DIFFIO_R4P B22 BLA27 R457 R458
TS_DTAn M16 IO200_DIFFIO_R19P IO237_DIFFIO_R3N_PADD22 B21 BLA28 2V5
TS_RESETn IO201 IO238_DIFFIO_R3P_PADD21 C20 BLA29
IO239_DIFFIO_R2N_PADD20 D20 BLA30
IO240_DIFFIO_R2P F17 BLA31 J40
T22 IO241_DIFFIO_R1N G17
C CLK7_DIFFCLK_3N IO242_DIFFIO_R1P BLBD0 C
T21 F16 10K 10K R459
CLK6_DIFFCLK_3P IO243_DIFFIO_T32N BLBD1
G22 E16 1 2
CLK5_DIFFCLK_2N IO244_DIFFIO_T32P BLBD2 TCK1
G21 F15 3 4
CLK4_DIFFCLK_2P IO245_DIFFIO_T31N BLBD3
G16 TDO1 5 6
IO246_DIFFIO_R31P BLBD4
G15 7 8
IO247_DIFFIO_R30N BLBD5
CONF_DONE_TS M18 F14 9 10
CONF_DONE IO248_DIFFIO_R30P BLBD6 TMS1
G14 R
IO249 BLBD7
MSEL0_1 M17 D17
MSEL0 IO250_VREFB7N0 BLBD8 TDI1
MSEL1_1 L18 C19
MSEL1 IO251_DIFFIO_T29N BLBD9
MSEL2_1 L17 D19 R460 HDR5X2
MSEL2 IO252_DIFFIO_T29P BLBD10
MSEL3_1 K20
MSEL3
A20
IO253_PLL2_CLKOUTN BLBD11
L16 B20
TS_ODE IO202_DIFFIO_R18N IO254_PLL2_CLKOUTP BLBD12
L15
L22 IO203_DIFFIO_R18P 10K
L21 IO204_DIFFIO_R17N_INIT_DONE C17
IO205_DIFFIO_R17P_CRC_ERROR IO255 BLBD13
K15 H15
ETH1_RSTn IO206 IO256_DIFFIO_T28N BLBD14
K19 H14
IO207_VREFB6N1 IO257_DIFFIO_T28P BLBD15
J15 B19
ETH2_RSTn IO208 IO258_RUP4 BLWE0n
K22 A19
DSP_ETH_RST1n IO209_IFFIO_R16N_NCEO IO259_RDN4 BLWE1n
K21 A18
DSP_ETH_RST2n IO210_DIFFIO_R16P_CLKUSR IO260_DIFFIO_T27N BLGPL2
J22 B18
SLF_HE_n_TS IO211_DIFFIO_R15N IO261_DIFFIO_T27P_PADD BLCS3n
B J21 D15 B
SLF_SYNC_TS IO212_DIFFIO_R15P IO262_DIFFIO_T26N BLCS2n
J16 E15
SLF_CLK_TS IO213_DIFFIO_R14N IO263_DIFFIO_T26P BLCS4n
K16 G13 3V3 3V3
H22 IO214_DIFFIO_R14P IO264 A17
H21 IO215_DIFFIO_R13N IO265_DIFFIO_T25N_PADD1 B17
K17 IO216_DIFFIO_R13P IO266_DIFFIO_T25P_PADD2 A16 D15
IO217_DIFFIO_R12N IO267_DIFFIO_T24N I2C_IRQn
K18 B16 D14 3V3 D16 D17
IO218_DIFFIO_R12P IO268_DIFFIO_T24P I2C_RESETn
J18 3V3
IO219
U47
EP4CE15F23C8N BAT54C BAT54C FLASH MEMORY
nCSO1 1 8 BAT54C BAT54C
2 NCS VCC3 7
DATA1 DATA VCC2
3 6 DCLK1
C428 C430 4 VCC1 DCLK 5
GND ASDI ADSO1
EPCS4 C427 C429
10pF 10pF 10pF 10pF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U45D
CYCLONE IV FPGA
(4 OF 5)
HPI_HD[0:15]
HPI_HD0 C15 C6
IO269_VREFB7N1 IO314_DATA7 SD_CLK
HPI_HD1 E14 A4
HPI_HD2 F12 IO270_DIFFIO_T23N_PADD3 IO315_DIFFIO_T5N B4
HPI_HD3 H13 IO271_DIFFIO_T23P IO316_DIFFIO_T5P_DATA8 F8
HPI_HD4 H12 IO272_DIFFIO_T22N IO317_DIFFIO_T4N_DATA9 G8
IO273_DIFFIO_T22P IO318_DIFFIO_T4P SD_FPGA_CLK
HPI_HD5 G12 A3
HPI_HD6 F13 IO274_DIFFIO_T21N IO319_DIFFIO_T3N_DATA10 B3
HPI_HD7 A15 IO275_DIFFIO_T21P_PADD4 IO320_DIFFIO_T3P_DATA11 D6
HPI_HD8 B15 IO276_DIFFIO_T20N_PADD5 IO321_VREFB8N1 E7
IO277_DIFFIO_T20P_PADD6 IO322 PB14
HPI_HD9 C13 C3
IO278_DIFFIO_T19N_PADD7 IO323_DIFFIO_T2N PB15
HPI_HD10 D13 C4
IO279_DIFFIO_T19P_PADD8 IO324_DIFFIO_T2P_DATA12 GPIO25
HPI_HD11 E13 F7
IO280 IO325_DIFFIO_T1N GPIO27
HPI_HD12 A14 G7
IO281_DIFFIO_T18N_PADD9 IO326_DIFFIO_T1P GPIO24
HPI_HD13 B14 E6
IO282_DIFFIO_T18P_PADD10 IO327_PLL3_CLKOUTN BOARD_WP
HPI_HD14 A13 E5
IO283_DIFFIO_T17N_PADD11 IO328_PLL3_CLKOUTP BOOT_WP
HPI_HD15 B13
E12 IO284_DIFFIO_T17P_PADD12
HPI_HAS IO285
HPI_CNTL0 E11
F11 IO286_DIFFIO_T16N_PADD13
HPI_CNTL1 IO287_DIFFIO_T16P_PADD14
C C
L10
A12 GND1 L11
B12 CLK10_DIFFCLK_4N GND2 M10
A11 CLK11_DIFFCLK_4P GND3 M11
B11 CLK8_DIFFCLK_5N GND4 L12
CLK9_DIFFCLK_5P GND5 L13
GND6 M12
GND7 M13
H11 GND8 N11
HPI_HCS D10 IO288 GND9 K11
HPI_HDS1 E10 IO289_DIFFIO_T15N GND10 N12
HPI_HDS2 A10 IO290_DIFFIO_T15P GND11 K12
HPI_HWIL B10 IO291_DIFFIO_T14N GND12 K13
HPI_RW A9 IO292_DIFFIO_T14P_PADD15 GND13 N13
HPI_INT B9 IO293_DIFFIO_T13N_PADD16 GND14 N10
HPI_RD C10 IO294_DIFFIO_T13P_PADD17 GND15 K10
PCM_SYNC31_OUT G11 IO295 GND16 J9
A8 IO296 GND17 D7
PCM_CLK01_OUT B8 IO297_DIFFIO_T12N_DATA2 GND18 J5
A7 IO298_DIFFIO_T12P_DATA3 GND19 H8
PCM_CLK11_OUT B7 IO299_DIFFIO_T11N_PADD18 GND20 A1
A6 IO300_DIFFIO_T11P_DATA4 GND21 C5
PCM_CLK21_OUT B6 IO301_DIFFIO_T10N_PADD19 GND22 C9
B B
E9 IO302_DIFFIO_T10P_DATA15 GND23 C11
PCM_CLK31_OUT C8 IO303_VREFB8N0 GND24 C12
MPC_IRQ0n IO304_DIFFIO_T9N_DATA14 GND25
MPC_IRQ1n C7 C14
G10 IO305_DIFFIO_T9P_DATA13 GND26 C16
MPC_RQ2n IO306_DIFFIO_T8N GND27
MPC_IRQ3n G9 A22
H10 IO307_DIFFIO_T8P GND28 E20
H9 IO308_DIFFIO_T7N GND29 G20
A5 IO309_DIFFIO_T7P GND30 L20
B5 IO310_DATA5 GND31 P19
F9 IO311 GND32 V20
F10 IO312_DIFFIO_6N GND33 Y20
GPIO15 IO313_DIFFIO_T6P_DATA6 GND34 AB22
GND35
EP4CE15F23C8N
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
1V2
C431 C432 C433 C434 C435 C436 C437 C438 C439
U45E 3V3
CYCLONE IV FPGA 22uF 0.1uF 22uF 0.1uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF
D (5 OF 5) D
Y18 D4
Y16 GND36 VCCIO1_1 F4
Y12 GND37 VCCIO1_2 K4
Y11 GND38 VCCIO1_3 H4 2V5A 1V2D
Y9 GND39 VCCIO1_4
Y5 GND40
AB1 GND41 N4
N3 GND42 VCCIO2_1 U4 C440 C441 C442 C443 C444 C445 C446 C447 C448 C449 C450 C451
U3 GND43 VCCIO2_2 W4
W3 GND44 VCCIO2_3 R4
D3 GND45 VCCIO2_4
F3 GND46 22uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF 0.1uF 22uF 0.1uF 0.1uF 0.1uF
K3 GND47 AB2
G2 GND48 VCCIO3_1 W5
AA2 GND49 VCCIO3_2 W9
AA22 GND50 VCCIO3_3 W11
H3 GND51 VCCIO3_4 AA6
R3 GND52 VCCIO3_5
AB6 GND53
Y15 GND54 AB21 3V3
T20 GND55 VCCIO4_1 W12
J19 GND56 VCCIO4_2 W16
C18 GND57 VCCIO4_3 W18
C GND58 VCCIO4_4 C
D8 Y14 C452 C453 C454 C455 C456 C457 C458 C459 C460 C461 C462
GND59 VCCIO4_5
P18
VCCIO5_1 V19
U5 VCCIO5_2 Y19 22uF 0.1uF 22uF 0.1uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
E18 GNDA1 VCCIO5_3 T19
F5 GNDA2 VCCIO5_4
V18 GNDA3 E19
GNDA4 VCCIO6_1 G19
VCCIO6_2 L19
VCCIO6_3 J20 3V3
J11 VCCIO6_4
J12 VCCINT1 A21
L14 VCCINT2 VCCIO7_1 D12
M14 VCCINT3 VCCIO7_2 D14 C463 C464 C465 C466 C467 C468 C469 C470 C471 C472
P11 VCCINT4 VCCIO7_3 D16
P12 VCCINT5 VCCIO7_4 D18
L9 VCCINT6 VCCIO7_5
1V2 M9 VCCINT7 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
J13 VCCINT8 A2
J14 VCCINT9 VCCIO8_1 D5
K14 VCCINT10 VCCIO8_2 D9
J10 VCCINT11 VCCIO8_3 D11 2V5A
K9 VCCINT12 VCCIO8_4 E8
B B
N9 VCCINT13 VCCIO8_5
P9 VCCINT14 T6
P10 VCCINT15 VCCA1 F18
P13 VCCINT16 VCCA2 G6
U16 VCCINT17 VCCA3 U18
U17 VCCINT18 VCCA4 1V2D
T13 VCCINT19
J8 VCCINT20 U6 2V5 2V5A 1V2 1V2D
VCCINT21 VCCD_PLL1 FB11 FB12
E17
VCCD_PLL2 F6
VCCD_PLL3 V17 1 2 1 2
VCCD_PLL4
BEAD BEAD
EP4CE15F23C8N C473 C474 C475 C476
CAP CAP
CAP CAP
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3 3V3 3V3 3V3 3V3 3V3 3V3
R484 R485 R489 R490

D R486 R487 R488 D
1K 1K 1K R
R R 1K
GP00_HPI_EN GP01_UTOPIA_EN GP02_TSIP0_EN GP03_TSIP1_EN GP04_TSIP2_EN GP05_EMAC1_EN GP06_BOOTMODE0
R491 R492 R493 R494 R495 R496 R497
1K 1K R R R R 1K
3V3 3V3 3V3 3V3 3V3 3V3 3V3
R498 R499 R500 R501 R502 R503

C C
R504
R
1K R
R R R R
GP07_BOOTMODE1 GP08_BOOTMODE2 GP09_BOOTMODE3 GP10_CFGGP0 GP11_CFGGP1 GP12_CFGGP2 GP13_CFGGP3
R505 R506 R507 R508 R509 R510 R511
R 1K 1K 1K 1K 1K 1K
3V3
B B
3V3 3V3 R512 R513 R514 R515
R516 R517
R R R R U49 3V3
1 EEPROM
1K 1K 2 A0
3 A1 8
A2 VCC
GP14_CFGGP4 GP15_SYSCLKOUTEN
R518 R519 7 C483
WP 0.1uF
4
6 GND
SCL SCL
R R SDA 5
SDA
AT24C256
A A
Title
USP_V2
NOTE : NU = NOT USED
B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3 3V3 3V3 3V3
D
Digital Signal Processor(DSP) R463 R464 R465 R461
D
R R R 1K
MACSEL0_0 MACSEL0_1 MACSEL0_2 DDREN
U48A R466 R467 R468 R469

CONFIG/RESET/PLL/TIMER/ 1K 1K 1K R
GPIO/RAPIDIO PINS
(01 OF 09)
MACSEL0_0 AE6 M1
MACSEL0(0) GP00_HPI_EN GP00_HPI_EN
3V3 MACSEL0_1 AG5 N5
MACSEL0(1) GP01_UTOPIA_EN GP01_UTOPIA_EN
MACSEL0_2 AF6
MACSEL0(2) M3
GP02_TSIP0_EN GP02_TSIP0_EN
R462 MACSEL1_0 AF5 K5
MACSEL1(0) GP03_TSIP1_EN GP03_TSIP1_EN
MACSEL1_1 AH5 M5
MACSEL1(1) GP04_TSIP2_EN GP04_TSIP2_EN
N4
GP05_EMAC1_EN GP05_EMAC1_EN
DDREN E20 3V3 3V3 3V3 3V3
U26 DDREN L5
RIOEN RIOEN GP06_BOOTMODE0 GP06_BOOTMODE0
1K LENDIAN AH4 L4
LENDIAN GP07_BOOTMODE1 GP07_BOOTMODE1
AH23 K3
HOUT HOUT GP08_BOOTMODE2 GP08_BOOTMODE2
K4 R470 R471 R472 R473
C GP09_BOOTMODE3 GP09_BOOTMODE3 C
LRESETn J4 R 1K R R
G1 LRESET_N M2
DSP_RESETn RESET_N GP10_CFGGP0 GP10_CFGGP0
N3
GP11_CFGGP1 GP11_CFGGP1
M4
GP12_CFGGP2 GP12_CFGGP2
CORESEL0 H3 L1
CORESEL0 GP13_CFGGP3 GP13_CFGGP3 MACSEL1_0 MACSEL1_1 LENDIAN RIOEN
CORESEL1 G3 L2
CORESEL1 GP14_CFGGP4 GP14_CFGGP4
CORESEL2 G2 L3
CORESEL2 GP15_SYSCLKOUTEN GP15_SYSCLKOUTEN
R474 R475 R476 R477
1K R 1K 1K
3V3 LRESETNMIENn J3 U25
LRESETNMIEN_N RIOCLKP SRIO_CLKP_U25
DSP_NMIn K2 T25
NMI_N RIOCLKN SRIO_CLKN_T25
POR_n H1
J5 POR_N P27 C477 0.1uF
RESETSTATn RESETSTAT_N RIORXP0 SRIO_RX0P
K1 N27 C478 0.1uF
BOOTACTIVE RIORXN0 SRIO_RX0N
LED D18 R478 100E TP34
DSP_CLKIN1 K28
AH13 CLKIN1 T29C479 0.1uF
DSP_CLKIN2 CLKIN2 RIORXP1 SRIO_RX1P
DSP_CLKIN3 A23 U29 C480 0.1uF
SYSCLKOUT RIORXN1 SRIO_RX1N
K27
TP35 CLKIN3 N29
RIOTXP0 SRIO_TX0P
LED D19 R479 100E P29 SRIO_TX0N
V27 RIOTXN0
DSP_WDOUTn H2 WDOUT_N
TP36 TIMO2
B CLK_8.192MHz V28 U27 SRIO_TX1P B
V29 TIMI0 RIOTXP1 T27
TIMI1 RIOTXN1 SRIO_TX1N
TMS320TC16486
3V3 DSP_RESET_n R480 4.7K
SRIO_CLKP C481 0.1uF SRIO_CLKP_U25

R481
POR_n R482 4.7K
LED D20 R483 100E RESETSTATn
R
SRIO_CLKN C482 0.1uF SRIO_CLKN_T25
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U48B
D DDR2 MEMORY CONTROLLER D
(02 OF 09)
C16 B19
DDR_DQM3 BSDDQM3 BED31 DDR_DQ31
B15 D17
G4 C18 RN57
A3 B18 RS_DDR_BA2 2 7
DDR_DQM0 BSDDQM0 BED28 DDR_DQ28 DDR_BA2
D16 RS_DDR_BA1 3 6
BED27 DDR_DQ27 DDR_BA1
R520 R E9 A17 RS_DDR_BA0 1 8
BCS1_N BED26 DDR_DQ26 DDR_BA0
A4 D15
DDR_CS_n BCS0_N BED25 DDR_DQ25
R521 10E C15 RN
BED24 DDR_DQ24
BSDCAS_n D6 RN58
D7 BSDCAS_N D14 4 5
BSDRAS_n BSDRAS_N BED23 DDR_DQ23 RS_DDR_A0 DDR_A0
BSDWE_n E8 A16 RS_DDR_A1 1 8
BSDWE_N BED22 DDR_DQ22 DDR_A1
BSDCKE C6 C14 RS_DDR_A2 2 7
BSDCKE BED21 DDR_DQ21 DDR_A2
E13 RS_DDR_A3 3 6
BED20 DDR_DQ20 DDR_A3
B13
BED19 DDR_DQ19
RS_DDR_BA2 A6 A15 RN8
BBA2 BED18 DDR_DQ18
RS_DDR_BA1 B6 C12
BBA1 BED17 DDR_DQ17
RS_DDR_BA0 C7 A13
BBA0 BED16 DDR_DQ16
RN59
RS_DDR_A0 B12 F2 RS_DDR_A4 4 5
BEA00 BED15 DDR_DQ15 DDR_A4
RS_DDR_A1 A12 G5 RS_DDR_A5 3 6
RS_DDR_A2 A11 D1 RS_DDR_A6 1 8
RS_DDR_A3 B11 E2 RS_DDR_A7 2 7
C BEA03 BED12 DDR_DQ12 DDR_A7 C
RS_DDR_A4 C11 F4
BEA04 BED11 DDR_DQ11
RS_DDR_A5 D11 F5
BEA05 BED10 DDR_DQ10
RS_DDR_A6 A9 E4
BEA06 BED9 DDR_DQ9
RS_DDR_A7 C10 C1 RN60
BEA07 BED8 DDR_DQ8
RS_DDR_A8 D10 RS_DDR_A8 4 5
BEA08 DDR_A8
RS_DDR_A9 C9 E5 RS_DDR_A9 3 6
RS_DDR_A10 B8 D3 RS_DDR_A10 1 8
RS_DDR_A11 A7 B2 RS_DDR_A11 2 7
RS_DDR_A12 B7 C3 RN8
BEA12 BED4 DDR_DQ4
RS_DDR_A13 D9 D5
BEA13 BED3 DDR_DQ3
DDR_DQS3_P C17 B3 RN8
BSDDQS3P BED2 DDR_DQ2
DDR_DQS3_N B17 C5 RS_DDR_A12 R522 10E
BSDDQS3N BED1 DDR_DQ1 DDR_A12
B4
BED0 DDR_DQ0
DDR_DQS2_P D13 RN61
C13 BSDDQS2P C8 1 8
DDR_DQS2_N BSDDQS2N BECLKOUTP CLKOUT_P BSDCAS_n DDR_CASn
D8 BSDRAS_n 2 7
BECLKOUTN CLKOUT_N DDR_RASn
BSDWE_n 3 6
DDR_WEn
DDR_DQS1_P E3 BSDCKE 4 5
BSDDQS1P TP37 T POINT DDR_CKE
DDR_DQS1_N F3 RN8
BSDDQS1N E14
BSDDQGATE3 B16 R523 10E
D4 BSDDQGATE2 D2 R524 10E
DDR_DQS0_P BSDDQS0P BSDDQGATE1 RS_DDR_A13 DDR_A13
DDR_DQS0_N C4 C2 R525 10E
BSDDQS0N BSDDQGATE0
B B
TMS320TC16486 TP38 T POINT
CLKOUT_P RN62 DDR_CLK2_P

3 6
4 5 DDR_CLK1_P
1 8
CLKOUT_N 2 7 DDR_CLK2_N
RN8 DDR_CLK1_N
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
U48C
D UTOPIA/I2C/HPI16 R526 D
(03 OF 09)
J29 J28
AE27 URCLK URCLAV H27 U50
AA25 URENB_N UXCLAV F29 1K GP BUFFER
J26 URSOC UXSOC FOUR O/P PCI-X
AA26 UXCLK 3V3 1 3 R527 33.2E

UXENB_N CLK_25MHZ BUF_IN OUTPUT1 DSP_CLKIN1
G25 2 5 R528 33.2E DSP_CLKIN2
UXDATA0 F26 6 OE OUTPUT2 7 R529 33.2E
UXDATA1 VDD OUTPUT3 ETH_PHY
Y29 E27 4 8 R530 33.2E
Y28 URADDR0 UXDATA2 H25 GND OUTPUT4
Y27 URADDR1 UXDATA3 G26 CY2304NZ R531 R
URADDR2 UXDATA4 RGCLK1
Y26 F27
Y25 URADDR3 UXDATA5 E28
URADDR4 UXDATA6 E29
UXDATA7 FPGA_25MHz
J25
AA29 UXDATA8 H26
AA28 URDATA0 UXDATA9 G27
AA27 URDATA1 UXDATA10 F28
AB27 URDATA2 UXDATA11 G28
AB26 URDATA3 UXDATA12 H28
AB25 URDATA4 UXDATA13 J27
AC29 URDATA5 UXDATA14 H29
AC28 URDATA6 UXDATA15 3V3
C URDATA7 U51 C
AC27 HPI_HD[0:15]
AC26 URDATA8
AC25 URDATA9 3 1
AD29 URDATA10 AG27 U52OSC_CO43_46_RAL C484 C485 3 1
AD28 URDATA11 HD00 AH28 R532 R 1 4
AD27 URDATA12 HD01 AE24 INHn VD CAP CAP 2
AF29 URDATA13 HD02 AF25 2 3 GND
AD26 URDATA14 HD03 AG26 GD OUT R533 R
URDATA15 HD04 NFM18CC
AJ28 37.5MHz
HD05 AG25 3V3 3V3
W29 HD06 AH26 U53
W28 UXADDR0 HD07 AE22
W27 UXADDR1 HD08 AF23 3 1
W26 UXADDR2 HD09 AG24 C486 C487 3 1
W25 UXADDR3 HD10 AJ26 U54OSC_CO43_46_RAL
UXADDR4 HD11 AH24 R700 R701 R534 R 1 4 CAP CAP 2
HD12 AG23 INHn VD GND
AD25 HD13 AJ24 2 3
HPI_HAS HAS_N HD14 GD OUT NFM18CC
AF26 AF22
HPI_CNTL0 AF24 HCNTL0 HD15 0E 0E 3V3
37.5MHz DSP_CLKIN3
HPI_CNTL1 AF28 HCNTL1 U55
HPI_HCS AE25 HCS_N AG28
HPI_HDS1 HDS1_N HINT_N HPI_INT
AE23 AE26 HPI_RD 3 1
HPI_HDS2 AG29 HDS2_N HRDY_N 3 1
B B
HPI_HWIL AF27 HHWIL U56OSC_CO43_46_RAL C488 C489
HPI_RW HR_W_N K26 R535 4.75K 1 4 R536 2
SDA SDA INHn VD GND
L25 SCL 0.1uF 0.1uF
SCL 2 3
GD OUT NFM18CC
TMS320TC16486 R537 R538 37.5MHz
33.2E
3V3
CLK_25MHZ
10K 10K
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U48D
D ETHERNET MAC/JTAG EMULATION/MDIO D
(04 OF 09)
FET_RMRXD0 AH11 AF8 R539 33.2E FET_RMTXD0

AG12 MRXD00_RMRXD00_SRXD0 MTXD00_RMTXD00_STXD0 AH7 R540 33.2E
FET_RMRXD1 MRXD01_RMRXD01_SRXSYNC0 MTXD01_RMTXD01_STXSYNC0 FET_RMTXD1
AJ11 AG8
AJ10 MRXD02_SRXD1 MTXD02_STXD1 AF9
AH9 MRXD03_SRXSYNC1 MTXD03_STXSYNC1 AE7
AG7 MRXD04_RMRXD10 MTXD04_RMTXD10_STXCLK1 AJ7
R543 1K AJ13 MRXD05_RMRXD11 MTXD05_RMTXD11 AE11
AJ6 MRXD06_RMRXER1 MTXD06_RMTXEN1 AG11
AG10 MRXD07 MTXD07_STXCLK0 AF11 R544 33.2E
MRCLK0_SRXCLK1 MTXEN0_RMTXEN0 FET_RMTX_EN
AE12 3V3
AF12 MRXDV0_RMCRSDV1 AH19
FET_RMRX_ER MREXR0_RMRXER0_SRXCLK0 RGTXC0
FET_RM_CRS AF10 AH17 R545 33.2E DSP_TX_CLK
AJ9 MCRS0_RMCRSDV0 RGTXC1
FET_RM_REF_CLK MTCLK0_REFCLK0_SREFCLK0
AE8 AF19 R546 4.7K
MCOL0 RGTXCTL0 AH16 R547 33.2E
RGTXCTL1 DSP_TX_EN
R548 4.7K 3V3
R549 1K AH21 AG20
AG15 RGRXC0 RGCLK0 AG16 R550 R R551 4.7K
DSP_RX_CLK RGRXC1 RGCLK1 RGCLK1
R552 1K AJ21 AE18
AJ16 RGRXCTL0 RGTD00 AG19
C DSP_RX_DV RGRXCTL1 RGTD01 DSP_TRST_n C
AF17 3V3 DSP_TMS J41
AF21 RGTD02 AJ19
R553 1K AG21 RGRD00 RGTD03 AH18 R554 33.2E
RGRD01 RGTD10 DSP_TXD0 DSP_TDI
AF20 AG17 R555 33.2E DSP_TXD1 1 2 3V3
AE19 RGRD02 RGTD11 AE16 R556 33.2E R558 4.7K 3 4
RGRD03 RGTD12 DSP_TXD2
DSP_RXD0 AE15 AF16 R557 33.2E DSP_TXD3 5 6
AF15 RGRD10 RGTD13 7 8
DSP_RXD1 RGRD11 DSP_TDO
DSP_RXD2 AH15 AH10 MDIO 9 10 R560
AJ15 RGRD12 GMDIO AG18 R559 4.7K 11 12
DSP_RXD3 RGRD13 RGMDIO 4.7K
13 14
AG9 MDC DSP_TCK
C27 GMDCLK AF18
DSP_TCK TCLK RGMDCLK
DSP_TDI D27 DSP_EMU0
B28 TDI HEADER 7X2
DSP_TMS TMS
DSP_TRST_n C28 R561 4.7K
TRST_N
D28
A27 EMU8 B27
DSP_EMU0 EMU0 EMU9
D29 E22
D25 EMU1 EMU10 E25
D23 EMU2 EMU11 A24
C24 EMU3 EMU12 D24
C26 EMU4 EMU13 C25
E23 EMU5 EMU14 B29
B B
D22 EMU6 EMU15 D26
EMU7 EMU16 E24
EMU17 A26
AG6 EMU18
GMTCLK0_REFCLK1_SREFCLK1
DSP_TDO C29
TDO
TMS320TC16486
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U48E
TSIP/RESERVED
DSP_TDM_TXD[0:3]
(05 OF 09)
D U3 U2 R562 22.1E D
TSIP0_CLK CLKA0 TX00
R563 1K R4 R5 R566 22.1E
CLKB0 TX01 T4 R564 22.1E
TX02 P4 R567 22.1E
V2 TX03 P2
TSIP0_SYNC FSA0 TX04
R565 1K Y1 R1
FSB0 TX05 P3
DSP_TDM_RXD[0:3] TX06 P1 DSP_TDM_TXD[4:7]
T3 TX07
U4 TR00 AA3 R568 22.1E
AA1 TR01 TX10 AF2 R569 22.1E
V1 TR02 TX11 Y4 R570 22.1E 3V3
P5 TR03 TX12 AD3 R571 22.1E
R2 TR04 TX13 AH2
R3 TR05 TX14 AD2 R572
U1 TR06 TX15 AD1
TR07 TX16 Y2
TX17 DSP_TDM_TXD[8:11]
U57
V3 AF4 R573 22.1E 1K GP BUFFER
TSIP1_CLK CLKA1 TX20 FOUR O/P PCI-X
R574 1K AC1 AA5 R575 22.1E
CLKB1 TX21 AD5 R576 22.1E 3V3 1 3 R577 33.2E
TX22 FPGA_8MCLK1 BUF_IN OUTPUT1 TSIP0_CLK
AC5 R578 22.1E 2 5 R579 33.2E TSIP1_CLK
AF1 TX23 AC4 6 OE OUTPUT2 7 R580 33.2E
TSIP1_SYNC FSA1 TX24 VDD OUTPUT3 TSIP2_CLK
R581 1K T5 Y5 4 8 R582 33.2E CLK_8.192MHz
C FSB1 TX25 GND OUTPUT4 C
DSP_TDM_RXD[4:7] AE3
TX26 AG3 CY2304NZ
AC3 TX27 3V3
AB3 TR10
Y3 TR11
W5 TR12 H5 R583
W4 TR13 RSV01 B20
AC2 TR14 RSV02 E21
AG2 TR15 RSV07 AG22 U58
AG1 TR16 RSV08 AF7 1K GP BUFFER
TR17 RSV09 AH6
FOUR O/P PCI-X
RSV10 AJ3 3V3 1 3 R584 33.2E
RSV11 TPM_SYNC BUF_IN OUTPUT1 TSIP0_SYNC
TSIP2_CLK V4 AG4 2 5 R585 33.2E TSIP1_SYNC
R586 1K AA2 CLKA2 RSV12 M28 6 OE OUTPUT2 7 R587 33.2E
CLKB2 RSV13 VDD OUTPUT3 TSIP2_SYNC
AE13 4 8
RSV14 A20 GND OUTPUT4
W3 RSV15 L29 CY2304NZ
TSIP2_SYNC FSA2 RSV16
R588 1K U5 L28
FSB2 RSV17 E19
DSP_TDM_RXD[8:11] RSV18 E18
AB5 RSV19 R26
AH3 TR20 RSV20 E26
AF3 TR21 RSV21 B24
AE5 TR22 RSV22 B23
B B
AE4 TR23 RSV23 B9 R589 R
TR24 RSV24 DDR_ODT
AA4 A8
AD4 TR25 RSV25
AB4 TR26 R590 R R591 10K
TR27
TMS320TC16486
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
1V8_DSP_DDR 1V8_DSP_ETH 1V1 1v1

3v3
D R592 R593 R594 R595 D

C490 C491 C511 C512 C492 C493 C494 C495 C496 C497 C513 C498 C499
U48F 1v1 1v1 + + +

SUPPLY VOLTAGE
(06 OF 09) 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0E 0E 0E 0E AE9 U10 10uF 10uF 10uF
AG13 CVDDMON CVDD37 U12
D12 DVDD15MON CVDD38 U14 R597
V5 DVDD18MON CVDD39 U16 1v1
DVDD33MON CVDD40 U18
R596 220E C20 CVDD41 V11
R602 220E C19 PTV18P CVDD42 V13
1V8_DSP_ETH 1V8_DSP_DDR PTV18N CVDD43 V15
R598 220E AF14 CVDD44 V17 0E C500 C501 C502 C503 C514 C504 C505 C506 C507 C508 C515 C516 C509 C510 C517 C518
R599 220E AE14 PTV15P CVDD45 V19
PTV15N CVDD46 V25 + + +
R600 0E AF13 CVDD47 W10
R601 0E D20 HHV15EN CVDD48 W12 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF 560pF
1v1 HHV18EN CVDD49 W14 10uF 10uF 10uF
CVDD50 W16
1v1 R603 0E AE10 CVDD51 W18
U59 C21 CVDD1 CVDD52 W20
G19 CVDD2 CVDD53 Y11
C CVDD3 CVDD54 C
1 3 C519 C520 C521 G20 Y13
1 3 K15 CVDD4 CVDD55 Y15
K17 CVDD5 CVDD56 Y17
2 K19 CVDD6 CVDD57 Y19
GND 0.1uF 0.1uF 0.1uF L10 CVDD7 CVDD58
L12 CVDD8
NFM18CC CVDD9
L14 A25
L16 CVDD10 DVDD33_1 A28
L18 CVDD11 DVDD33_2 AA24
L20 CVDD12 DVDD33_3 AA6 1V8
1v1 M11 CVDD13 DVDD33_4 AB2 1V8_DSP_ETH
M13 CVDD14 DVDD33_5 AB7
M19 CVDD17 DVDD33_8 AC6 3v3
N10 CVDD18 DVDD33_9 AC8 F1 FUSE
N12 CVDD19 DVDD33_10 AC10
N14 CVDD20 DVDD33_11 AC12 C522
N16 CVDD21 DVDD33_12 AC22
N18 CVDD22 DVDD33_13 AC24 1V8_DSP_DDR +
P11 CVDD23 DVDD33_14 AD11 C523
P13 CVDD24 DVDD33_15 AD13
P15 CVDD25 DVDD33_16 AD23 + 10uF
P17 CVDD26 DVDD33_17 AD7 C524
B B
R10 CVDD27 DVDD33_18 AD9 F2 FUSE
R12 CVDD28 DVDD33_19 AE2 10uF +
R14 CVDD29 DVDD33_20 AE28
R16 CVDD30 DVDD33_21 AH22 1V8_DSP_PLL
R18 CVDD31 DVDD33_22 AH25 10uF
T11 CVDD32 DVDD33_23 AH27
T13 CVDD33 DVDD33_24 AH29
T15 CVDD34 DVDD33_25 AH8 F3 FUSE
T17 CVDD35 DVDD33_26 AJ1
CVDD36 DVDD33_27 C525
TMS320TC16486 +
10uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
U60 1V8_DSP_PLL
U48G 3 1
SUPPLY VOLTAGE C526 C528 3 1
(07 OF 09)
AJ12 B21 + 2
3V3 AJ4 DVDD33_28 AVDDA3 R28 GND C527
D B22 DVDD33_29 DVDDR 0.1uF 0.1uF D
DVDD33_30 NFM18CC
R604 0E B26 H4 10uF
C22 DVDD33_31 AVDDA4_1 A21
R605 0E C23 DVDD33_32 AVDDA4_2
F21 DVDD33_33
F23 DVDD33_34 T23
F25 DVDD33_35 DVDDD1 V23 U61
G22 DVDD33_36 DVDDD2
G24 DVDD33_37 A1 3 1
H23 DVDD33_38 DVDD18_1 A19 C529 C530 3 1
J2 DVDD33_39 DVDD18_2 B10
3V3 J24 DVDD33_40 DVDD18_3 B14 + 2
K23 DVDD33_41 DVDD18_4 B5 GND C531
K25 DVDD33_42 DVDD18_5 E1 0.1uF 0.1uF
DVDD33_43 DVDD18_6 NFM18CC
K7 E12 1V8_DSP_DDR 10uF
L24 DVDD33_44 DVDD18_7 E16
L6 DVDD33_45 DVDD18_8 E6
M23 DVDD33_46 DVDD18_9 F15
M7 DVDD33_47 DVDD18_10 F17
N2 DVDD33_48 DVDD18_11 F19
N6 DVDD33_49 DVDD18_12 G10 U62
P7 DVDD33_50 DVDD18_13 G12
R6 DVDD33_51 DVDD18_14 G14 3 1
T2 DVDD33_52 DVDD18_15 G16 C533 C534 3 1 1V8_DSP_ETH
C DVDD33_53 DVDD18_16 VREFHSTL C
T7 G18
U6 DVDD33_54 DVDD18_17 G6 + 2
V7 DVDD33_55 DVDD18_18 G8 GND C532 R606 1K R607 1K
W2 DVDD33_56 DVDD18_19 H7 0.1uF 0.1uF
DVDD33_57 DVDD18_20 NFM18CC
W24 J6 10uF C535 C536
W6 DVDD33_58 DVDD18_21
Y23 DVDD33_59 N25
Y7 DVDD33_60 AVDDT1 R25
DVDD33_61 AVDDT2 0.1uF 0.1uF
AC14
F7 DVDD15_1 AC16
F9 CVDD1_1 DVDD15_2 AC18 1V8_DSP_ETH
1V2 F11 CVDD1_2 DVDD15_3 AC20
F13 CVDD1_3 DVDD15_4 AD15 1V8_DSP_DDR
CVDD1_4 DVDD15_5 VRESSTL
K11 AD17
K13 CVDD1_5 DVDD15_6 AD19
N20 CVDD1_6 DVDD15_7 AD21 R608 1K R609 1K
P19 CVDD2_1 DVDD15_8 AH14
R20 CVDD2_2 DVDD15_9 AH20 1V8_DSP_PLL C537 C538
T19 CVDD2_3 DVDD15_10 AJ18
U20 CVDD2_4 DVDD15_11
R24 CVDD2_5
U24 AVDDA_1 AE17 0.1uF 0.1uF
B VREFHSTL B
AVDDA_2 VREFHSTL E10
VRESSTL VRESSTL U63
M29 3 1
AVDDA1 AG14 C539 C540 3 1
AVDDA2
+ 2
TMS320TC16486 GND C541
0.1uF 0.1uF
NFM18CC
10uF
U64
3 1
C542 C543 3 1
+ 2
GND C544
0.1uF 0.1uF
NFM18CC
10uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
U48H
GND PINS
(08 OF 09)
A10 B25 U48I
A14 GND1 GND51 D18 GND PINS
A18 GND2 GND52 D19 (09 OF 09)
A2 GND3 GND53 D21 L27 T1
A22 GND4 GND54 E11 M10 GND101 GND145 T10
AA23 GND7 GND57 E7 M16 GND104 GND148 T16
AA7 GND8 GND58 F1 M18 GND105 GND149 T18
AB1 GND9 GND59 F10 M20 GND106 GND150 T20
AC7 GND13 GND63 F18 M27 GND110 GND154 T6
AC9 GND14 GND64 F20 M6 GND111 GND155 U11
AC11 GND15 GND65 F22 N1 GND112 GND156 U13
C GND19 GND69 GND116 GND160 C
AC19 G11 N17 U23
AC21 GND20 GND70 G13 N19 GND117 GND161 U28
AC23 GND21 GND71 G15 N23 GND118 GND162 U7
AD10 GND22 GND72 G17 N24 GND119 GND163 V10
AD18 GND26 GND76 G7 P10 GND123 GND167 V18
AD20 GND27 GND77 G9 P12 GND124 GND168 V20
AD22 GND28 GND78 H24 P14 GND125 GND169 V24
AD24 GND29 GND79 H6 P16 GND126 GND170 V26
AD6 GND30 GND80 J1 P18 GND127 GND171 V6
AD8 GND31 GND81 J23 P20 GND128 GND172 W1
AE1 GND32 GND82 J7 P23 GND129 GND173 W11
AE20 GND33 GND83 K10 P24 GND130 GND174 W13
AH1 GND36 GND86 K16 P28 GND133 GND177 W19
AH12 GND37 GND87 K18 P6 GND134 GND178 W23
AJ14 GND38 GND88 K20 R11 GND135 GND179 W7
AJ17 GND39 GND89 K24 R13 GND136 GND180 Y10
AJ22 GND42 GND92 L7 R19 GND139 GND183 Y16
B B
AJ5 GND47 GND97 L19 GND144 GND188
AJ8 GND48 GND98 L23 TMS320TC16486
B1 GND49 GND99 L26
GND50 GND100
TMS320TC16486
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3 DECAPS OF DSP
D C577 C578 C579 C580 C581 C582 C583 C584 C585 C586 C587 C588 C589 C590 C591 C592 C593 C594 C595 D
+ + +
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF 560pF 560pF
10uF 10uF 10uF
3V3
C596 C597 C598 C599 C600 C601 C602 C603 C604 C605 C606 C607 C608 C609 C610 C611 C612 C613 C614
+ + +
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF 560pF 560pF
10uF 10uF 10uF
C C
1V8_DSP_DDR 1V8_DSP_DDR
C615 C616 C617 C618 C619 C620 C621 C622 C623 C624 C625 C626 C627 C628 C629 C630 C631 C632 C633 C634
+ + + +
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF
10uF 10uF 10uF 10uF
B B
1V8_DSP_ETH
1V2
C635 C636 C637 C638 C639 C640 C641 C642

C643 C644 C645 C646 C647 C648 C649
+ +
+
0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF
10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
RN63
DDR_DQS0_P 1 8
RS_DDR_DQS0_P
DDR_DQS0_N 2 7
D RS_DDR_DQS0_N D
U65
DDR_A0 M8 G8 RS_DDR_DQ0 RN8
M3 A0 DQ0 G2 RS_DDR_DQ1
DDR_A1 A1 DQ1
DDR_A2 M7 H7 RS_DDR_DQ2
N2 A2 DQ2 H3 RS_DDR_DQ3
DDR_A3 A3 DQ3
DDR_A4 N8 H1 RS_DDR_DQ4
N3 A4 DQ4 H9 RS_DDR_DQ5 RN64
DDR_A5 A5 DQ5
DDR_A6 N7 F1 RS_DDR_DQ6 DDR_DQS1_P 3 6
A6 DQ6 RS_DDR_DQS1_P
DDR_A7 P2 F9 RS_DDR_DQ7 DDR_DQS1_N 4 5
A7 DQ7 RS_DDR_DQS1_N
DDR_A8 P8 C8 RS_DDR_DQ8
P3 A8 DQ8 C2 RS_DDR_DQ9 RN8
DDR_A9 A9 DQ9
DDR_A10 M2 D7 RS_DDR_DQ10
P7 A10 DQ10 D3 RS_DDR_DQ11
DDR_A11 A11 DQ11
DDR_A12 R2 D1 RS_DDR_DQ12 RN65
A12 DQ12 D9 RS_DDR_DQ13 1 8
DQ13 DDR_DQM0 RS_DDR_DQM0
B1 RS_DDR_DQ14 DDR_DQM1 2 7
DQ14 RS_DDR_DQM1
DDR_BA0 L2 B9 RS_DDR_DQ15
L3 BA0 DQ15 RN8
DDR_BA1 BA1
DDR_BA2 L1
BA2 F7
LDQS RS_DDR_DQS0_P
E8
LDQS_N_NU RS_DDR_DQS0_N
DDR_CLK1_P J8 1V8_DSP_DDR
JK8 CK B7
DDR_CLK1_N CK_N UDQS RS_DDR_DQS1_P
DDR_CKE K2 A8 RN66
C CKE UDQS_N_NU RS_DDR_DQS1_N C
DDR_DQ0 4 5
RS_DDR_DQ0
DDR_DQ1 1 8 C545 C546 C552 C553 C547 C548 C549 C550 C551
RS_DDR_DQ1
DDR_CSn L8 R8 R610 0E DDR_DQ2 2 7
CS_N RFU1 RS_DDR_DQ2
RS_DDR_DQM0 F3 R3 DDR_DQ3 3 6 +
LDM RFU2 RS_DDR_DQ3
RS_DDR_DQM1 B3 R7 R611 R
UDM RFU3 DDR_A13
DDR_ODT K9 RN8 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF 560pF 560pF
ODT 10uF
A3
K7 VSS1 E3
DDR_RASn RAS_N VSS2
DDR_CASn L7 J3 RN67
K3 CAS_N VSS3 N1 4 5
DDR_WEn WE_N VSS4 DDR_DQ4 RS_DDR_DQ4
P9 DDR_DQ5 1 8
VSS5 RS_DDR_DQ5
DDR_DQ6 2 7
RS_DDR_DQ6
A1 DDR_DQ7 3 6
VDD1 RS_DDR_DQ7
E1 A7
M9 VDD2 VSSQ1 B2
R1 VDD3 VSSQ2 B8 RN8
1V8_DSP_DDR J9 VDD4 VSSQ3 D2 RN68
VDD5 VSSQ4 D8
VSSQ5 E7 4 5
VSSQ6 DDR_DQ8 RS_DDR_DQ8
F2 DDR_DQ9 1 8
VSSQ7 RS_DDR_DQ9
A9 F8 DDR_DQ10 2 7
VDDQ1 VSSQ8 RS_DDR_DQ10
C1 H2 DDR_DQ11 3 6
B C3 H8 B
C7 VDDQ3 VSSQ10 1V8_DSP_DDR
C9 VDDQ4 RN8
G3 VDDQ5 J7
E9 VDDQ6 VSSDL J1 RN69
G1 VDDQ7 VDDL J2 C554 0.1uF
G7 VDDQ8 VREF A2 4 5
VDDQ9 NC1 DDR_DQ12 RS_DDR_DQ12
G9 E2 DDR_DQ13 1 8
VDDQ10 NC2 RS_DDR_DQ13
DDR_DQ14 2 7
RS_DDR_DQ14
DDR_DQ15 3 6
VRESSTL RS_DDR_DQ15
MT47H64M16
RN8
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
RN70
U66 DDR_DQS2_P 1 8
RS_DDR_DQS2_P
DDR_A0 M8 G8 DDR_DQS2_N 2 7
A0 DQ0 RS_DDR_DQ16 RS_DDR_DQS2_N
DDR_A1 M3 G2
A1 DQ1 RS_DDR_DQ17
DDR_A2 M7 H7 RN8
D A2 DQ2 RS_DDR_DQ18 D
DDR_A3 N2 H3
A3 DQ3 RS_DDR_DQ19
DDR_A4 N8 H1
A4 DQ4 RS_DDR_DQ20
DDR_A5 N3 H9
A5 DQ5 RS_DDR_DQ21
DDR_A6 N7 F1
A6 DQ6 RS_DDR_DQ22
DDR_A7 P2 F9 RN71
A7 DQ7 RS_DDR_DQ23
DDR_A8 P8 C8 DDR_DQS3_P 3 6
A8 DQ8 RS_DDR_DQ24 RS_DDR_DQS3_P
DDR_A9 P3 C2 DDR_DQS3_N 4 5
A9 DQ9 RS_DDR_DQ25 RS_DDR_DQS3_N
DDR_A10 M2 D7
A10 DQ10 RS_DDR_DQ26
DDR_A11 P7 D3 RN8
DDR_A12 R2 D1
D9
DQ13 RS_DDR_DQ29
B1 RN72
DQ14 RS_DDR_DQ30
DDR_BA0 L2 B9 DDR_DQM2 1 8
BA0 DQ15 RS_DDR_DQ31 RS_DDR_DQM2
DDR_BA1 L3 DDR_DQM3 2 7
BA1 RS_DDR_DQM3
DDR_BA2 L1
BA2 F7 RN8
LDQS RS_DDR_DQS2_P
E8
LDQS_N_NU RS_DDR_DQS2_N
DDR_CLK2_P J8 1V8_DSP_DDR
JK8 CK B7
DDR_CLK2_N CK_N UDQS RS_DDR_DQS3_P
DDR_CKE K2 A8
CKE UDQS_N_NU RS_DDR_DQS3_N
RN73 C559 C555 C556 C560 C557 C561 C558 C562 C563
DDR_CSn L8 R8 R612 0E DDR_DQ16 4 5
CS_N RFU1 RS_DDR_DQ16
RS_DDR_DQM2 F3 R3 DDR_DQ17 1 8 +
C LDM RFU2 DDR_A13 RS_DDR_DQ17 C
RS_DDR_DQM3 B3 R7 R613 R DDR_DQ18 2 7
UDM RFU3 RS_DDR_DQ18
DDR_ODT K9 DDR_DQ19 3 6 0.1uF 0.1uF 0.1uF 0.1uF 560pF 560pF 560pF 560pF
ODT RS_DDR_DQ19
10uF
A3 RN8
K7 VSS1 E3
DDR_RASn RAS_N VSS2
DDR_CASn L7 J3
K3 CAS_N VSS3 N1
DDR_WEn WE_N VSS4 P9 RN74
VSS5 4 5
DDR_DQ20 RS_DDR_DQ20
A1 DDR_DQ21 1 8
VDD1 RS_DDR_DQ21
E1 A7 DDR_DQ22 2 7
VDD2 VSSQ1 RS_DDR_DQ22
M9 B2 DDR_DQ23 3 6
VDD3 VSSQ2 RS_DDR_DQ23
R1 B8
1V8_DSP_DDR J9 VDD4 VSSQ3 D2
VDD5 VSSQ4 D8 RN8
VSSQ5 E7 RN75
VSSQ6 F2
A9 VSSQ7 F8 4 5
VDDQ1 VSSQ8 DDR_DQ24 RS_DDR_DQ24
C1 H2 DDR_DQ25 1 8
C3 H8 DDR_DQ26 2 7
C7 1V8_DSP_DDR DDR_DQ27 3 6
VDDQ4 RS_DDR_DQ27
C9
G3 VDDQ5 J7
E9 VDDQ6 VSSDL J1 RN8
B B
G1 VDDQ7 VDDL J2 C564 0.1uF
G7 VDDQ8 VREF A2 RN76
G9 VDDQ9 NC1 E2
VDDQ10 NC2 4 5
DDR_DQ28 RS_DDR_DQ28
DDR_DQ29 1 8
VRESSTL RS_DDR_DQ29
MT47H64M16 DDR_DQ30 2 7
RS_DDR_DQ30
DDR_DQ31 3 6
RS_DDR_DQ31
RN8
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
3V3
3V3
R615
R614
D 3V3 D
1V8
U67
10K 1K
SINGLE UART WITH U68
I2C BUS/SPI DUAL VOLTAGE
A0_CSn 2 4 CLAMP
3 A0_CS_n SO 6 2 7
A1_SI A1_SI SDA SDA A1 B1 GATE
SCL 5 7 I2C_IRQn DIODE D23 RGMDIO 3 6 MDIO
8 SCL_SCLK IRQ_n 10 R790 10K 4 A2 B2 5
I2C_SPI_n RTS_n DSP_LED0 RGMDC A3 B3 MDC
11 GATE 8 1
13 CTS_n 12 GATE GND 3V3
POC_PR_RXD RX TX POC_PR_TXD
3V3 I2C_RESETn 14 SN74TVC3306 R630 150E
15 RESET_n 1
16 XTAL1 VDD 9 3V3 DIODE D24 R631 150E
R616 10K XTAL2 VSS R791 10K
DSP_LED1
SC16IS740
Y13
25MHZ
C569
C570
C C
22pF 22pF
R619 49.9K DSP_MDI_P_0

3V3 C571 0.1uF 3V3
3V3 R620 49.9K DSP_MDI_N_0
3V3
R621 R622 3V3
200K R625 GATE
R792
R623 49.9K DSP_MDI_P_1 C575
C572 0.1uF
R R R624 49.9K DSP_MDI_N_1
B 10K B
A0_CSn A1_SI C573 0.1uF
I2C_RESETn 0.1uF
R627 R628 R626 49.9K DSP_MDI_P_2
C574 0.1uF
R629 49.9K DSP_MDI_N_2
10K 10K
R632 49.9K DSP_MDI_P_3
C576 0.1uF
R633 49.9K DSP_MDI_N_3
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
SPI MMC INTERFACE

3V3
3V3
R794
U83 R793
SPI_CSn 1 4 VCC
2 CS- 3.3V 8 J55
SPI_MOSI DATAIN NC
SPI_MISO 7 3
5 DATAOUT GND1 6 1.5K 1.5K 1
SPI_CLK CLK GND2 USB TRANSCEIVER
R796 24.3R 2
MMC 3
R795 24.3R 4
5
3V3 6
3V3
U84
USBOEN 2 14 R797 USB

C OE VCC C
USBSPDn 9
13 SPEED 10
USBTXN VMO/FSEO D-
USBTXP 12 11
VPO D+ 10K
USBRXD 3 6 USBENn
RCV SUSPND
USBRXP 4 1
VP MODE 8
NC
USBRXN 5 7
VM GND
PDS CARD CONNECTOR
USB1T11AMX
3V3 J56
1 18
ETH1 2 19 PORESETn
ETH2 3 20 FAN_FAIL
DSP0 4 21 DSP1
DTK0 5 22 DTK8
DTK1 6 23 DTK9
B DTK2 7 24 DTK10 B
DTK3 8 25 DTK11
DTK4 9 26 DTK12
DTK5 10 27 DTK13
DTK6 11 28 DTK14
DTK7 12 29 DTK15
3V3 VCC DISP_PBUT_n 13 30 DIS_CLK
14 31
15 32
16 33
17 34
HEADER34
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
ETHERNET TRANSCEIVER
U85A
1V8_DSP_ETH 1V2 3V3_AVDDC U85B
DSP_MDI_N_0 30 6 DSP_LED0
D 31 MDIN(0) LED(0) 8 D
DSP_MDI_P_0 MDIP(0) LED(1) DSP_RX_CLK
9 DS1 LED
25 LED(2) R798 100E 66 90
DSP_MDI_N_1 MDIN(1) PWRVIA1 PWRVIA25
DSP_MDI_P_1 26 35 R799 49.9E 67 91
MDIP(1) HSDACN 36 C797 C791 C792 C793 C794 C795 C796 68 PWRVIA2 PWRVIA26 92
23 HSDACP 32 R800 49.9E 69 PWRVIA3 PWRVIA27 93
DSP_MDI_N_2 MDIN(2) TSTPT PWRVIA4 PWRVIA28
DSP_MDI_P_2 24 70 94
MDIP(2) 71 PWRVIA5 PWRVIA29 95
19 39 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 72 PWRVIA6 PWRVIA30 96
DSP_MDI_N_3 MDIN(3) XTAL_OUT PWRVIA7 PWRVIA31
DSP_MDI_P_3 20 44 73 97
MDIP(3) TDO 17 74 PWRVIA8 PWRVIA32 98
60 CTRL18 75 PWRVIA9 PWRVIA33 99
DSP_TX_CLK TX_CLK PWRVIA10 PWRVIA34
DSP_TX_EN 63 53 R801 32.2E DSP_RX_CLK 76 100
TX_CTRL RXCLK 49 R802 32.2E 77 PWRVIA11 PWRVIA35 101
RX_CTRL DSP_RX_DP PWRVIA12 PWRVIA36
DSP_TXD0 62 78 102
61 TXD(3) 79 PWRVIA13 PWRVIA37 103
DSP_TXD1 TXD(2) PWRVIA14 PWRVIA38
1V8_DSP_ETH DSP_TXD2 59 55 R803 32.2E DSP_RXD0 80 104
58 TXD(1) RXD(3) 54 R804 32.2E 81 PWRVIA15 PWRVIA39 105
DSP_TXD3 TXD(0) RXD(2) DSP_RXD1 PWRVIA16 PWRVIA40
51 R805 32.2E DSP_RXD2 82 106
48 RXD(1) 50 R806 32.2E 83 PWRVIA17 PWRVIA41 107
RGMDC MDC RXD(0) DSP_RXD3 PWRVIA18 PWRVIA42
RGMDIO 45 1V8_DSP_ETH 84 108
MDIO 1V8_DSP_ETH 85 PWRVIA19 PWRVIA43 109
R807 2.21K 43 21 1V8_DSP_ETH 86 PWRVIA20 PWRVIA44 110
41 TDI AVDD1 22 87 PWRVIA21 PWRVIA45 111
C TMS AVDD2 PWRVIA22 PWRVIA46 C
42 27 88 112
R808 4.75K 11 TCK AVDD3 29 89 PWRVIA23 PWRVIA47 113
TRST_n AVDD4 3V3_AVDDC PWRVIA24 PWRVIA48 114
64 34 C798 C799 C800 C801 C802 C803 PWRVIA49
CONFIG0 CONFIG(0) AVDDC1
CONFIG1 1 37 1V8_DSP_ETH
1V8_DSP_ETH 2 CONFIG(1) AVDDC2 +
LED1 CONFIG(2) 88E1116
CONFIG3 3 14
CONFIG(3) AVDDR1 15 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R809 4.75K 4 AVDDR2 4.7uF
10 COMA_n
DSP_RESET_n RESET_n
57
R810 38 VREF 16
1V8_DSP_ETH XTAL_IN AVDDX
1K
R811 4.99K 33 5
REST DVDD1 13 1V2 1V8_DSP_ETH
4.75K 12 DVDD2 40
R812 DIS_REG12 DVDD3 47
DVDD4
R813 4.75K 18
NC1 7
R814 R815 0E 28 VDDO1 46
1K NC2 VDDO2 1V8_DSP_ETH C804 C805 C806 C807 C808 C809
B 52 DSP_LED1 B
65 VDDOR1 56
EPAD VDDOR2 1V8_DSP_ETH
DSP_LED0
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
88E1116
R816 R817 R818 R819 R820 R821 R822

3V3 3V3_AVDDC
1V8_DSP_ETH BEAD
1 2 NU 0E 0E NU NU 0E NU
C810 FB27
C811
+
DSP_RESET_n R823 1K
4.7uF 0.1uF
CONFIG0
A A
CONFIG1
CONFIG3 Title
USP_V2
NOTE : NU-NOT USED Size

B
Document Number
<Doc> 1
Rev

5 4 3 2 1
5 4 3 2 1
3V3
D D
U86
R824 R826 WAN PLL WITH SINGLE

REFERENCE INPUT
DPLL_FREF 5 49
R R FREF OSC_O
10 50
F_SEL1 CSC_I FRM_OSCI
9
FSEL0 44
R R827 2 LOCK
R829 R825 1 MODE_SEL1 52
R R828 MODE_SEL0 HOLDOVER
46
4 NORMAL
DPLL_RST_n RST_n
R R 51
3V3 3 FREERUN
TCLR_n 25
C32O_n CLK_32M
56 24 CLK_16M
TIE_EN C16O_n 23
C8O CLK_8M
45 20
R830 R FLOCK C4O_n
17 CLK_2M
C C2O C
16
32 C3O_n 15
30 TDI C1.5O 14
R831 R 28 TRST_n C6O
31 TCK 40
TMS F32O_n SYNC_32M
29 39 SYNC_16M
TDO F16O_n 36
F8O SYNC_8M
6 33 SYNC_4M
7 IC1 F0O_n
8 IC2
11 IC3 41
21 IC4 RSP 42
22 IC5 TSP
34 IC6
35 IC7 53
43 IC8 IC0_VSS 54
3V3 IC9 IC1_VSS 55
IC2_VSS
13 12
19 VDD1 VSS1 18
26 VDD2 VSS2 27
37 VDD3 VSS3 38
48 VDD4 VSS4 47
VDD5 VSS5
B B
IDT82V3001
C812 C813 C814 C815 C816
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
Power Supply 12V

D D
TRANSFORMER P0V
J43 F4 FUSE
C651 C652 C653
2
1.5SMC62A
D21 C650
1
2 SW5 T7 10KpF 4.7uF 330nF
3 3 VR26
N48V
3
4 2 10KpF
1
C654
Switch 4.7nF
HEADER 4
C655 C656
C C
CHGND
CAP CAP
CHGND
CHGND
P12V
P12V
J44
1 U69
2 P0V 1 8 C657
VIN_P VO_P 7 C658 C659
R634 0E 2 SENSE_P 6
ON_OFF ADJUST 5 R635 +
B B
HEADER 2 3 SENSE_N 4 0.1uF
N48V VIN_N VO_N 1uF
PS1 10uF
J45
R CHGND
1
2
HEADER 2
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
Power Supply - Generation of Voltages

D D
P12V 1V2
U70
2 4 P12V 1V8
Vin Vout C668 C662 C669 C663 U71
C664 C665 C666 C667 C660 C661 1 2 4
Inhibit_n + Vin Vout C676 C677 C678 C679
+ 3 5 C670 C671 C672 C673 C674 C675 1
GND Vo_Adj 10uF 10uF 0.1uF Inhibit_n +
0.1uF 0.1uF 0.1uF 10uF 10uF PTR08060W 100uF + 3 5
100uF GND Vo_Adj 10uF 10uF 0.1uF
0.1uF 0.1uF 0.1uF 10uF 10uF PTR08060W 100uF
R636 100uF
R637
D
U72 2K
2K
D
C U73 C
EN_1V2 G BSS138
R638
EN_1V8 G BSS138
S
R639
S
1K
1K
3V3
B P12V P12V 1V1 B
U74 U75
2 4 2 4
Vin Vout C686 C687 C688 C689 Vin Vout C696 C697 C698 C699
C680 C681 C682 C683 C684 C685 1 C690 C691 C692 C693 C694 C695 1
Inhibit_n + Inhibit_n +
+ 3 5 + 3 5
GND Vo_Adj 10uF 10uF 0.1uF GND Vo_Adj 10uF 10uF 0.1uF
0.1uF 0.1uF 0.1uF 10uF 10uF PTR08060W 100uF 0.1uF 0.1uF 0.1uF 10uF 10uF PTR08060W 100uF
100uF 100uF
R640 R641
2K 2K
D
D
U76 U77
EN_3V3 G BSS138 EN_1V1 G BSS138
R642 R643
S
S
A A
1K 1K
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
D D
VCC VCC 2V5
P12V C700 100nF

R644 R645
C701
U78 3V3
121E 2 C702 22uF U79
3 Vout VOLTAGE REG
IN 1 2 4 10.5K 68pF
ADJ_GND C703 C704 1 VIN VOUT 5
LM1117DTX 3 SD_n ADJ 6
+ C706 C707 VCC + GD CASE_GD C705 C708 R646
10uF 100nF R647 VR2
10KpF +
+ C709 TP39 100uF
C C
10uF 10KpF
365E 47uF 10K
T POINT
EN_2V5
B B
A A
Title
USP_V2

B <Doc> 1

5 4 3 2 1
5 4 3 2 1
R648 0E EN_1V2
R649 0E EN_3V3
R650 0E EN_1V8
D D
R651 0E EN_1V1
R652 0E EN_2V5
3V3 2V5 1V1 LDO_3V3 1V2 1V8
R655
1
FB14
U80
8 CHANNEL PS
BEAD SEQUENCER & MONITOR
2
499E
6 23 R657 10M
7 MON1 EN1 24 R658 10M
R656 8 MON2 EN2 11 R659 10M
18 MON3 EN3 10 R660 10M 3V3
19 MON4 EN4 12 R661 10M
9 MON5 EN5 13 R662 10M
C MON6 EN6 C
15 14 R663 10M
16 MON7 EN7 R664 10M
2.2K 5 MON8
29 RST_n 25 R665 10M
TEST EN8_ADDR1_GPO1 26
ADDR2_GPO2 27
22 ADDR3_GPO3 28 R666 10M R667 10M
IIC_SDA SCL ADDR4_GPO4
IIC_SCL 21
3 SDA 2
R668 100K 32 XIN NC1 4 R669 10M R670 10M
1 ROSC NC2 17
R673 30 VSS NC3 20
C710 VCC NC4 31 R671 10M R672 10M
NC5
C711 33
0.1uF THERMAL_PAD
1KpF LDO_3V3
10K UCD9081
C712 10uF
+
B B
LDO_3V3
P12V
LDO_3V3
LDO_3V3 J52
U81 R706
C790 1 5
IN OUT 1 2
2 R702 3 4
CAP GND 5 6 R
3 4 7 8
EN NC/FB R705 9 10 IIC_SDA
R704 TPS76933
287K C789
CAP
HDR5X2
R
R R703 IIC_SCL
A 169K A
Title
USP_V2

B <Doc> 1

5 4 3 2 1

Index: No No Title Title Title No Title No

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Index: No No Title Title Title No Title No

Загружено:

Авторское право:

Доступные форматы

5 4 3 2 1

02 BLOCK DIAGRAM 22 SOURCE TERMINATION 42 HAUL TRANSCEIVER_5 62 DDR2 SDRAM

03 MINI_PCI_CONNECTOR 23 DESTINATION TERMINATION 43 HAUL TRANSCEIVER_6 63 SINGLE UART

04 MINI_PCI_CONNECTOR 24 FLASH 44 T1068NL 64 USB TRANSCEIVER

05 EURO_CONNECTOR 25 DIGITAL SWITCH 45 T1068NL 65 ETHERNET TRANSCEIVER

06 EURO_CONNECTOR 26 DIGITAL SWITCH 46 CYCLONE IV FPGA_1 66 WAN PLL INPUT

12 32 ETH2_KSZ9021RN 52 MEMORY CONTROLLER_1 72

14 34 ETH2_KSZ9021RN_DECAP 54 MEMORY CONTROLLER_3 74

17 37 H1102NL 57 MEMORY CONTROLLER_6

19 DDR2 SDRAM 39 HAUL TRANSCEIVER_2 59 MEMORY CONTROLLER_8 79

20 TRANSCEIVER 40 HAUL TRANSCEIVER_3 60 DECAPS OF DSP

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 1 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 2 of 70

U1A VCC 3V3

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 3 of 70

VCC 3V3 3V3

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 4 of 70

E1_TXTIP1 a1 J1B J1C

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 5 of 70

E1 TRUNK & RS-232 CONNECTOR

J2A J2B J2C

EURO CONN EURO CONN EURO CONN

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 6 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 7 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 8 of 70

LAD[0:15] LAD[16:31] U2D LBCK0 LCLK0

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 9 of 70

AR29 33E 1 8 RN12

MEMC2_MDQ23 RN15 1 8 33E AM2 AM30 33E 1 8 RN16

MEMC2_MDQ15 RN19 1 8 33E AT3 AT35 33E 1 8 RN20

MEMC2_MDQ7 RN23 1 8 33E AP7 AM36 33E 1 8 RN24

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 10 of 70

MPC8360E MEMC2_MCS0_n R77 22E RS_MEMC2_MCS0_n

MEMC2_MCKE0 R78 22E RS_MEMC2_MCKE0

MEMC1_MODT0 R79 22E RS_MEMC1_MODT0

MEMC1_MCS0_n R80 22E RS_MEMC1_MCS0_n

A MEMC1_MCKE0 R81 22E RS_MEMC1_MCKE0 A

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 11 of 70

R108 R109 R106 R107 22E PCI_CLK

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 12 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 13 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 14 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 15 of 70

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 16 of 70

R128 10E MPC8360E

Size Document Number Rev

Date: Monday, July 09, 2012 Sheet 17 of 70