instruction formats of 8086 : The instruction format of 8086 has one or more number of fields associated with it.

The first filled is called operation code field or opcode field, which indicates the type of operation. The instruction format also contains other fields known as operand fields. There are six general formats of instructions in 8086 instruction set. The length of an instruction may vary from one byte to sic bytes. a) One byte Instruction : This format is only one byte long and may have the implied data or register operands. The least significant 3 bits of the opcode are used for specifying the register operand, if any. Otherwise, all the eight bits form an opcode and the operands are implied. For example: 11111000 F 8H CLC : clear carry

This is an operation without any operand, which clear the carry flag bit. Exchange register with accumulator 10010 reg

Depending on the register (reg = RRR), the contents of the specified register will be exchanged with the accumulator. This operation is having one operand which is specified in a register. ASC P Adjust for addition AAA 00110111 37 H Here the operand to this instruction is implicit and it take the contents of register AL. b) Register to Register : This format is 2 bytes long. The first byte of the code specifies the operation code and the width of the operand specifies by w bit. The second byte of the opcode shows the register operands and RIM field. D7 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 OP CODE d w 11 REG R/M

The register represented by the REG field is one of the operands. The RIM field specifies another register or memory location, ie., the other operand. The register specified by REG is a source operand if D = 0 , else it is a destination operand. For example: MOV : data transfer operation from Register to Register. Op-code is 100010dw 10001000 REG = 0 0 0 REG = 0 0 1 11REG 88H C1H

11 000 001 indicates Register AL indicates Register CL

w = 0 indicates it is a byte operation (8 bit) d = 0 indicates AL is a source register. This instruction indicates MOV CL, AL, i.e CL AL C) Register to/from memory with no displacement : This format is also 2 bytes long and similar to the register to register format except for the MOD field. D7 OP CODE D1 D0 d w D7 D6 D5 D4 D3 MOD REG D2 D1 D0 R/M

The MOD field shows the MOD of addressing. In case of no displacement. MOD = 00 For example : MOV : Data transfer Register/memory to/from register. 100010dw mod reg rim

This format is similar to register to register transfer. The difference is in mood field. For register to register, mod = 11 For register to/from memory with no displacement, mod = 00. When mod = 0 0, the r/m fields indicates the address to memory location. As for example r/m = 1 1 1 indicates (Bx) The instruction 1 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 indicates the instruction MOV AX, [BX] In hexadecimal, the instruction is 8 AH O 7 H Here the data is present in a memory location in DS whose offset address is in BX. The effective address of the data is given as 10H DS + [ BX ] There d = 1 indicates AX is a destination register so it moves the data from memory to register. d) Register to/from Memory with Displacement : This type of instruction format contains one or two additional bytes for displacement along with 2-byte the format of the register to/from memory without displacement. D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 opcode D7 D0 MOD REG R/M Low byte of displacement

High byte of displacement

MOD = 0 1 indicates displacement of 8 bytes (instruction is of size 3 bytes) MOD = 1 0 indicates displacement of 16 bytes. (instruction is of size 4 bytes) Already we have seen the other two options of MOD MOD = 1 1 indicates register to register transfer MOD = 0 0 indicates memory without displacement In this case, R/M fields indicates a memory when MOD is not 1 1 R/M = 1 1 1 indicates (BX) When MOD = 0 1, the offset address is ( BX ) + D8

When MOD = 1 0, the offset address is ( BX ) + D16 e) Immediate operand to register In this format, the first byte as well as the 3 bites from the second byte which are used for REG field in case of register to register format are used for opcode. It also contains one or two bytes of immediate data. D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 Op code D7 Lower byte DATA w D0 11 D7 Higher byte DATA op code D0 R/M

When w = 0 , the size of immediate data is 8 bits and the size of instruction is 3 bytes. When w = 1 , the size of immediate data is 16 bits and the size of instruction is 4 bytes. f) immediate operand to memory with 16-bit displacement : This type of instruction format requires 5 to 6 bytes for coding. The first two bytes contain the information regarding OPCODE, MOD and R/M fields. The remaining 4 bytes contain 2 bytes of displacement and 2 bytes of data. D7 Op code D7 Higher byte of displacement D0 w D0 D7 D6 D5 D4 op code D0 D3 D2 D1 D0 R/M D7 D0 Higher byte of DATA

MOD D7

Lower byte of DATA

The REG code of the different registers (either a source or destination operands) in the opcode byte are assigned with binary code.

w bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Register code (3 bit) 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111

Registers AL CL DL BL AH CH DH BH AX CX DX BX SP BP SI DI

Segment register code (2 bit) 00 01 10 11

Segment register ES CS SS DS

Coding of different registers. Addressing Modes of 8086 : The different addressing modes of the 8086 instructions along with corresponding MOD, REG and R/M field are given in the table. operands MOD RIM 000 001 010 011 100 101 110 111 Memory operands No Displacement Displacement 8 bits 00 01 Displacement 16 bits 10 Register operands
w=0 AL

11

( BX ) + ( SI ) ( BX ) + ( DI ) ( BP ) + ( SI ) ( BP ) + ( DI ) ( SI ) ( DI )
D16

( BX )

( BX ) + ( SI ) + D8 ( BX ) + ( SI ) + D16 ( BX ) + ( DI ) + D8 ( BX ) + ( DI ) + D16 ( BP ) + ( SI ) + D8 ( BP ) + ( SI ) + D16 ( BP ) + ( DI ) + D8 ( BP ) + ( DI ) + D16 ( SI ) + D8 ( SI ) + D16 ( DI ) + D8 ( DI ) + D16 ( BP ) + D8 ( BP ) + D16 ( BX ) + D8 ( BX ) + D16

w =1 AX

CL DL BL AH CH DH BH

CX DX BX SP BP SS DI

D8 and D16 represent 8 and 16 bit displacement respectively. The default segment for the addressing modes using BP and SP is SS. For all other addressing modes the default segments are DS or ES. Addressing mode indicates a way of locating data or operands. Different addressing modes of 8086 :

1. Immediate : In this addressing mode, immediate data is a part of instruction, and appears in the form of successive byte or bytes. ex. MOV AX, 005 OH Here 005OH is the immediate data and it is moved to register AX. The immediate data may be 8-bit or 16-bit in size. 2. Direct : In the direct addressing mode, a 16 bit address (offset) is directly specified in the instruction as a part of it. ex. MOV AX [1 0 0 0 H] Here data resides in a memory location in the data segment, whose effective address is 10 H DS + 1000 H 3. Register : In register addressing mode, the data is stored in a register and it is referred using the particular register. All the registers except IP may be used in this mode. ex. MOV AX,BX 4. Register Indirect: In this addressing mode, the address of the memory location which contains data or operand is determined in an indirect way using offset registers. The offset address of data is in either BX or SI or DI register. The default segment register is either DS or ES. e.g. MOV AX, [ BX ] The data is present in a memory location in DS whose offset is in BX. The effective address is 10H DS + [ BX ] 5. Indexed : In this addressing mode offset of the operand is stored in one of the index register. DS and ES are the default segments for index registers SI and DI respectively e.g. MOV AX, [ SI ] The effective address of the data is 10H DS + [ SI ] 6. Register Relative : In this addressing mode the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default either DS or ES segment. e.g. MOV AX, 50H [ BX ] The effective address of the data is 10 H DS + 50 H + [ BX ] 7. Based Indexed: In this addressing mode the effective address of the data is formed by adding the content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be ES or DS. e.g MOV , [ BX ] [ SI ] The effective address is 10H DS + [ BX ] + [ SI ] 8. Relative Based Indexed : The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents of any one of the base register (BX or BP) and any one of the index registers in a default segment. e.g. MOV AX, 50H [ BX ] [ SI ]

Here 50H is an immediate 10 H DS + [ BX ] + [ SI ] + 50 H .

displacement.

The

effective

address

is

9. Intrasegment Direct Mode: In this mode, the address to which the control is to be transferred lies in the segment in which the control transfer instruction lies and appears directly in the instruction as an immediate displacement value. The displacement is computed relative to the content of the instruction pointer IP. 10. Intrasegment Indirect Mode: This mode is similar to intrasegment direct mode except the displacement to which control is to be transferred is passed to the instruction indirectly. Here the branch address is found as the content of a register or a memory location. 11. Intersegment Direct Mode: In this mode, the address to which the control is to be transferred is in a different segment. This addressing mode provides a means of branching from one code segment to another code segment. Here, the CS and IP of the destination address are specified directly in the instruction. 12. Intersegment Indirect Mode: This mode is similar to intersegment direct mode except the address to which the control is to be transferred is passed to the instruction indirectly. This information is kept in a memory block of 4 bytes: IP(LSB), IP(MSB), LS(LSR) and CS(MSB) sequentially. The starting address of the memory block may be referred using any of the addressing modes, except immediate mode. Instruction set of 8086 The 8086 instructions are categorized into eight different groups. a) Data Transfer Instruction: This type of instructions are used to transfer data from source operand to destination operand. All the store, load, move, exchange, input and output operations belong to this category. b) Arithmatic and Logical Instructions: All the instructions performing arithmetic , logical, increment, decrement, compare and scan instructions belong to this category. c) Branch Instructions: These instructions transfer control of execution to the specified address. All the call, jump, interrupt and return instructions belong to this category. d) Loop Instructions: The LOP, LOOPNZ and LOOPZ instructions belong to this category. These are useful to implement different loop structures. e) machine control Instructions: These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belongs to this category. f) Flag Manipulation Instructions: All instructions which directly affect the flag register belong to this category. The instructions CLD, STD, CLI, STI etc. belong to this category. g) Shift and Rotate Instructions: These instructions involve the bitwise shifting or rotation in either direction with or without a count in CX. h) String Instructions: These instruction involve string manipulation operations like load, love, scan. Compare, store etc. These instructions are only to be operated upon the string.

Data Transfer operation: MOV : move PUSH: Push to stack POP: pop from stack XCHG: Exchange IN: Input from the port OUT: Output to the port XLAT: Translate LEA: Load effective address LDS/LES: Load pointer to DS/ES LAHF: Load AH from lower byte of Flag register SAHF: Store AH to lower byte of Flag register PUSHF: push Flags to stack POPF: pop Flags from stack Arithmatic operations ADD: add ADC: Add with carry INC: Increment DEC: Decrement SUB: Subtract SBB: Subtract with Borrow CMP: compare AAA: ASCll Adjust After Addition AAS: ASCll Adjust After Subtraction AAM: ASCll Adjust for multiplication AAD: ASCll Adjust for division DAA: Decimal Adjust Accumulator DAS: Decimal Adjust After Subtraction NEG: Negative MUL: Unsigned multiplication Byte or word. IMUL : Signed multiplication CBW: Convert signed Byte to Word CWD: Convert signed word to double word DIV: Unsigned Division IDIV: Signed Division Logical Instructions: Logical Instructions: AND: Logical OR: Logiacl OR NOT: Logical Invert XOR: Logical Exclusive OR TEST: Logical compare Instruction SHL/SAL: Shift logical/Arithmatic left SHR: Shift logical Right SAR: Shift Arithmatic Right ROR: Rotate Right without carry ROL: Rotate Left without carry RCR: Rotate Right through carry RCL: Rotate Left through carry String Manipulation Instructions PEP : Repeat Instruction prefix MOVSB/MOVSW: Move string Byte or string word. CMPS: Compare sting Byte or String word. SCAS: Scan string Byte or string word LODS: Load string Byte or String word STOS: Store String Byte or String word Control transfer or Branching Instructions:

-Unconditional Branch Instructions. CALL: Unconditional Call RET: Return from the procedure INT N: Interrupt type N INTO: Interrupt on overflow JMP: Unconditional Jump JRET: Return from ISR LOOP: Loop unconditionally -Conditional Branch Instruction: JZ Label : Transfer control to Label if ZF = 1 JZ Label : Transfer control to Label if ZF = 1 JNZ Label : Transfer control to Label if ZF = 0 JS Label : Transfer control to Label if SF = 1 JNS Label : Transfer control to Label if SF = 0 JO Label : Transfer control to Label if OF = 1 JNO Label : Transfer control to Label if OF = 0 JP Label : Transfer control to Label if PF = 1 JNP Label : Transfer control to Label if PF = 0 JB Label : Transfer control to Label if CF = 1 JNB Label : Transfer control to Label if CF = 0 JBE Label : Transfer control to Label if CF = 1 or ZF = 1 JNBE Label : Transfer control to Label if CF = 0 or ZF = 0 JL Label : Transfer control to Label if SF = 1 or OF = 1 JNL Label : Transfer control to Label if SF = 0 or OF = 0 JLE Label : Transfer control to Label if ZF = 1 or neither SF nor OF is 1 JNLE Label : Transfer control to Label if ZF = 0 or at least any one of SF and OF is 1 LOOPZ label : Loop through a sequence of instructions from Label while ZF = 1 and CX 0 LOOPNZ label : Loop through a sequence of instructions from Label while ZF = 0 and CX 0 . Flag manipulator and Processor control instructions: CLC Clear carry flag CMC- Complement carry flag STC- Set carry flag CLD- Clear direction flag STD- Set direction flag CLI- Clear interrupt flag STI- Set Interrupt flag WAIT- wait for test input pin to go low HLT- Halt the processor NOP- No operation ESC- Escape to external device like NDP (numeric co-processor) LOCK- Bus lock instruction prefix.

GENERAL BUS OPERATION

The 8086 has a combined address and data bus commonly referred to as a time multiplexed address and data bus. The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, whenever required. Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3 and T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle. During T2, i.e. the next cycle, the bus is tristated for changing the direction of bus for the following data read cycle. The data transfer takes place during T3 and T4. In case, an addressed device is slow and shows NOT READY status the wait states Tw are inserted between T3 and T4. These clock states during wait period are called idle states (Ti), wait states (Tw) or inactive states. The processor uses these cycles for internal housekeeping. The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN/ MX input. The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0 , S1 and S 2 are used to indicate the type of operation. Status bits S 3 to S 7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while the status bits S3 to S7 are valid during T2 through T4. The Fig.1.7 shows a general bus operation cycle of 8086.

MINIMUM MODE 8086 SYSTEM AND TIMINGS

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/ MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signal. They are controlled by two signals, namely, DEN and DT/ R . The DEN signal indicates that the valid data is available on the data bus, while DT/ R indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROMS are used for monitor storage, while RAMs

for users program storage. A system may contain I/O devices for communication with the processor as well as some special purpose I/O devices. The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system. The clock generator also synchronizes some external signals with the system clock. The general system organisation is shown in Fig. 1.8. Since it has 20 address lines and 16 data lines, the 8086 CPU requires three octal address latches and two octal data buffers for the complete address and data separation.

The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal and also M/IO signal. During the negative going edge of this signal, the valid address is latched on the local bus. The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/ IO signal indicate a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read ( RD ) control signal is also activated in T2. The read ( RD ) signal causes the

addressed device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers. A write cycle also begins with the assertion of ALE and the emission of the address. The M/ IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or written. The M/ IO , RD and WR signals indicate the types of data transfer as specified in Table1.5.

M/ IO 0 0 1 1

RD 0 1 0 1

WR 1 0 1 0

Indications I/O Read I/O Write Memory Read Memory Write

Figure 1.9(a) shows the read cycle while the Fig. 1.9(b) shows the write cycle.

MAXIMUM MODE 8086 SYSTEM AND TIMINGS

In the maximum mode, the 8086 is operated by strapping the MN/ MX pin to ground. In this mode, the processor derives the status signals S 2 , S1 and S 0 . Another chip called

bus controller derives the control signals using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The other components in the system are the same as in the minimum mode system. The basic functions of the bus controller chip 1C8288, is to derive control signals like RD and WR (for memory and I/O devices), DEN , DT/ R , ALE, etc. using the information made available by the processor on the status lines. The bus controller chip has input lines and S 2 , S1 and S 0 CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN , DT/ R , MRDC , MWTC , AMWC , IORC , IOWC and AIOWC . The AEN , IOB and CEN pins are specially useful for multiprocessor systems. AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/ PDEN output depends upon the status of the IOB pin. If IOB is grounded, it acts as master cascade enable to control cascaded 8259A, else it acts as peripheral data enable used in the multiple bus configurations. INTA pin is used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC , IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the addressed port. The MRDC , MWTC are memory read command and memory write command signals respectively and may be used as memory read and write signals. All these command signals instruct the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AMWC and AIOWC are available. They also serve the same purpose, but are activated one clock cycle earlier than the IOWC and MWTC signals, respectively. The maximum mode system is shown in Fig. 1.10. The maximum mode system timing diagrams are also divided in two portions as read (input) and write (output) timing diagrams. The address/data and address/status timings are similar to the minimum mode. ALE is asserted in T1, just like minimum mode. The only difference lies in the status signals used and the available control and advanced command signals.