3042 1

Case 5:05-cv-00334-RMW Document 3042-2 Filed 01/09/2009 Page 1 of 30
Exhibit 1
IN THE UNITED STATES DISTRICT COURT

FOR THE NORTHERN DISTRICT OF CALIFORNIA
SAN JOSE DIVISION
RAMBUS INC., Case No. C-05-00334 RMW
Plaintiffs, SUPPLEMENTAL EXPERT REPORT OF

JOSEPH C. MCALEXANDER
v. REGARDING INVALIDITY OF
U.S. PATENT NUMBERS
HYNIX SEMICONDUCTOR INC., 6,182,184; 6,266,285; 6,314,051;
HYNIX SEMICONDUCTOR AMERICA 6,324,120; 6,378,020; 6,426,916;
INC., HYNIX SEMICONDUCTOR 6,452,863; 6,546,446; 6,584,037; AND
MANUFACTURING AMERICA, INC. 7,751,696 IN LIGHT OF THE BENNETT
AND NOVAK REFERENCES
SAMSUNG ELECTRONICS CO., LTD.,
SAMSUNG ELECTRONICS AMERICA,
INC., SAMSUNG SEMICONDUCTOR,
INC., SAMSUNG AUSTIN
SEMICONDUCTOR, L.P.,
NANYA TECHNOLOGY
CORPORATION, NANYA
TECHNOLOGY CORPORATION
U.S.A.,
Defendants.
Plaintiff,
v.
SAMSUNG ELECTRONICS CO., LTD.,

SAMSUNG ELECTRONICS AMERICA,
INC., SAMSUNG SEMICONDUCTOR,
INC., SAMSUNG AUSTIN
SEMICONDUCTOR, L.P.,
Defendants.
(CAPTION CONTINUED)
CONFIDENTIAL - ATTORNEY’S EYES ONLY
CONTAINS REFERENCES TO MATERIALS DESIGNATED AS
CONFIDENTIAL OR HIGHLY CONFIDENTIAL
Plaintiff,
v.
MICRON TECHNOLOGY INC., MICRON

SEMICONDUCTOR PRODUCTS, INC.,
and MICRON TECHNOLOGY, INC.
Defendants.
TABLE OF CONTENTS
Page
1. INTRODUCTION......................................................................................................................1
2. SUMMARY 1
3. DOCUMENTS, DEPOSITIONS, AND OTHER MATERIALS CONSIDERED ...............1
4. BASIS OF OPINIONS FORMED............................................................................................2
5. OPINIONS TO BE EXPRESSED ............................................................................................2

5.1. OPINIONS TO BE EXPRESSED REGARDING BENNETT ...................................2
5.1.1 BENNETT DISCLOSES SINGLE-CHIP MEMORY DEVICES AND
METHODS OF OPERATION THEREOF ..........................................................3
5.1.2 BENNETT DISCLOSES THAT A VALUE STORED IN A
PROGRAMMABLE REGISTER CHANGES READ AND WRITE
LATENCY............................................................................................................7
5.1.3 BENNETT DISCLOSES TWO FORMS OF BLOCK SIZE
INFORMATION.................................................................................................10
5.1.4 BENNETT DISCLOSES A SET REGISTER REQUEST.................................13
5.2. OPINIONS TO BE EXPRESSED REGARDING NOVAK .....................................14
SUPPLEMENTAL EXPERT REPORT OF JOSEPH C. MCALEXANDER REGARDING INVALIDITY OF Case Nos C-05-00334 RMW,
U.S. PATENT NUMBERS 6,182,184; 6,266,285; 6,314,051; 6,324,120; 6,378,020; 6,426,916; C-05-02298 RMW, C-06-00244 RMW
6,452,863; 6,546,446; 6,584,037; AND 7,751,696 IN LIGHT OF THE BENNETT AND NOVAK
REFERENCES i
____________________________________________________
SUPPLEMENTAL EXPERT REPORT OF JOSEPH C. McALEXANDER

REGARDING INVALIDITY OF U.S. PATENT NUMBERS
6,182,184; 6,266,285; 6,314,051; 6,324,120; 6,378,020;
6,426,916; 6,452,863; 6,546,446; 6,584,037; AND 7,751,696
IN LIGHT OF THE BENNETT AND NOVAK REFERENCES
____________________________________________________
1. INTRODUCTION
1. I have been asked to supplement the opinions provided in my original invalidity
report in order to address the November 14, 2008 Supplemental Expert Report of Robert J.
Murphy.
2. My supplemental opinions formed are provided below in Section 5. A summary of
these opinions can be found in Section 2. Any additional documents reviewed and considered in
preparing this supplemental report are identified in Section 3.
2. SUMMARY
3. I have concluded that the Supplemental Expert Report of Robert J. Murphy and the
opinions provided therein are either not relevant to the validity issues raised by the
Manufacturers or are in error. Section 4 of this report addresses the bases for my opinion that
Mr. Murphy's Supplemental Report fails to detract from the strong case for invalidity.
3. DOCUMENTS, DEPOSITIONS, AND OTHER MATERIALS CONSIDERED
4. In addition to the documents, depositions, and other materials identified in my
previous expert report, I have reviewed and considered, in the preparation of this report,
materials and testimony, including the patents in suit, U.S. Patent No. 4,734,909 to Bennett et al.
SUPPLEMENTAL EXPERT REPORT OF JOSEPH C. MCALEXANDER REGARDING INVALIDITY OF Case Nos. C-05-00334 RMW,
REFERENCES 1
(“Bennett”) (attached hereto as Exhibit 1); U.S. Patent No. 4,663,735 to Novak et al. (“Novak”)
(attached hereto as Exhibit 2); November 14, 2008 Supplemental Expert Report of Robert J.
Murphy Regarding Validity in Light of the Bennett and Novak References (“Murphy Supp.
Rep.”) (attached hereto as Exhibit 3); Intel MCS-4 Micro Computer Set ("MCS-4 Datasheet”)
(attached hereto as Exhibit 4); U.S. Patent No. 4,330,852 to Redwine et al. (“Redwine”)
(attached hereto as Exhibit 5); Order Denying Hynix's Motion for Summary Judgment of
Invalidity of U.S. Patent Nos. 6,378,020 and 5,915,105 Under 35 U.S.C. §§ 102 and/or 103,
Hynix Semiconductor Inc. v. Rambus Inc., No. CV-00-20905 RMW (“Hynix I”) (N.D. Cal. Feb.
28, 2006) (“Redwine MSJ Order”) (attached hereto as Exhibit 6); and Transcript of October 13,
2008 Deposition of Robert J. Murphy (“Murphy Dep. Tr.”) (attached hereto as Exhibit 7).
4. BASIS OF OPINIONS FORMED
5. The supplemental opinions provided herein are based in part on the above-
mentioned review and analysis of documents, depositions, and other materials. I have also relied
on my education, experience, and knowledge of engineering practices.
5. OPINIONS TO BE EXPRESSED
5.1. OPINIONS TO BE EXPRESSED REGARDING BENNETT
6. The Manufacturers moved for summary judgment that claim 16 of U.S. Patent
6,266,285 ("claim '285-16"), claim 27 of U.S. Patent 6,314,051 ("claim '051-27"), claim 43 of
U.S. Patent 6,314,051 ("claim '051-43"); claim 28 of U.S. Patent 6,426,916 ("claim '916-28");
and claim 16 of U.S. Patent 6,452,863 ("claim '863-16") are each invalid as anticipated by
Bennett.
REFERENCES 2
7. In opposition to Summary Judgment of invalidity, Rambus submitted an opposition
relying on the Supplemental Expert Report of Mr. Murphy, which concluded that four elements
of the claims were not disclosed by Bennett: (1) a single chip memory device; (2) programmable
read and write delays; (3) block size information; and (4) a set register request.
5.1.1 BENNETT DISCLOSES SINGLE-CHIP MEMORY DEVICES AND

METHODS OF OPERATION THEREOF
8. Mr. Murphy opines that Bennett fails to disclose single-chip memory devices, but
rather describes contemporary memory cards. (See Ex. 3, Murphy Supp. Report at 2.) In
support of his conclusion, Mr. Murphy cites Bennett's disclosure of a "'large memory' that may
contain . . . up to 232 addresses of 32 bit words," which Mr. Murphy opines is a reference to a
conventional memory card. (Id.) Mr. Murphy also relies upon the assertion that the number of
pins required for the Bennett interface is too large for a memory chip and instead must be
"multiple memory cards containing multiple conventional DRAM chips per card. " (Id.)
9. I disagree with Mr. Murphy's opinion, which contradicts the express and
unambiguous disclosure of Bennett.
10. As depicted in Figure 1 of Bennett, the synchronous Versatile Bus Interface and one
of a variety of different types of "User Devices" should be integrated together on a single VLSIC
chip. Bennett explains that
[t]he apparatus of the invention for realizing the objects thereof is

called the Versatile Bus Interface Logics 102a and is normally
implemented in VLSI circuitry upon the same chip substrate as the
VLSI User Device 106a.
(Ex. 1, Bennett col. 12:28-32.) Bennett further states that
REFERENCES 3
[e]ach Versatile Bus Interface Logics, for example Versatile Bus

Interface Logics 102a, interfaces a User module, for example VLSI
Circuit User Device 106a which is pictorially represented in
shadow line within FIG. 1 as existing on the same VLSIC chip
substrate as Versatile Bus Interface Logics 102a, to the Versatile
Bus and onto physical bus 101.
(Id. col. 36:19-25.) Thus, Bennett clearly and unambiguously describes integrating a User
Device and the Versatile Bus Interface on to a single chip.
11. Bennett also provides memory as an example User Device. Bennett explains that
[t]he Versatile Buses family is a specification for a spectrum of

configurably compatible interfaces intended to be built with a
CPU, IOC, Memory, or similar User device for signal and data
exchange.
(Id. col. 35:59-62.) Similarly, Bennett states that
[a] 'User' is the logics (e.g., a central processor or a memory or

whatever) which communicates through the Versatile Bus
Interface Logics, such as are taught by this specification, onto the
Versatile Bus.
(Id. col. 40:52-55.) Thus, Bennett clearly and unambiguously describes that one of the User
Devices that can be integrated onto a chip with a Versatile Bus Interface is memory.
12. That Bennett discloses memory chips including the Versatile Bus Interface is, in my
opinion, confirmed by the description of "memory" as a kind of "chip type" that is a "Versatile
Bus interconnected device”:
The User announces to all other Versatile Bus interconnected

devices both this recently assigned, device unique, address and
some arbitrary, system designer specified, code ID indicative of
the User chip type (i.e., CPU or memory).
(Id. col. 58:17-21.) This passage explains that memory chips that include a Versatile Bus
Interface can be connected to the Versatile Bus.

REFERENCES 4
13. The description in Bennett of a "large memory" having "up to 232 addresses of 32 bit
words" is not a reference to memory cards as stated by Mr. Murphy. Instead, this is a reference
to the theoretical maximum number of addresses that can be provided on the Versatile Bus, i.e.,
that the bus can use up to 32 bit addresses. The size of the address space does not control the
amount of physical main memory that is actually available in a particular system or on a memory
device. Instead, systems generally include less physical memory than the maximum available
address space. Further, Bennett unambiguously discloses that each memory device on the
Versatile Bus is individually addressable, explaining in figure 35 of Bennett that each slave
memory device has a unique Slave I.D. (Mem. I.D.). The disclosure of individually addressable
memory devices each having a unique I.D. is inconsistent with Mr. Murphy's interpretation of
Bennett. Instead, Bennett clearly describes the large memory of Bennett as comprising a
plurality of such synchronous devices.
14. Thus, a person having ordinary skill in the art would have understood Bennett to
disclose a large amount of memory comprising a plurality of synchronous DRAM chips, each
including 1) a synchronous Versatile Bus Interface and 2) a User Device comprising arrays of
dynamic random access memory cells.
15. Mr. Murphy's opinion, which relies on the address space of the "large memory," is
also inconsistent with the description in Bennett of the "large memory." Bennett explains that
the 32 bit addresses are only exemplary, and that addresses of 16, 24, or 32 bits can be used.
(See Ex. 1, Bennett col. 94:35-36.) By disclosing that the address space can be far smaller than
the maximum address space relied upon by Mr. Murphy, the Bennett specification contradicts
Mr. Murphy's conclusion that the Bennett memory devices were necessarily card based.
REFERENCES 5
16. Mr. Murphy's opinion, which relies on the address space of the "large memory," is
also inconsistent with the description in Bennett of a "fast memory." Bennett specifically
explains that the "fast memory" is smaller than the large memory (id. col. 94:26-36), and thus,
the Bennett specification contradicts Mr. Murphy's conclusion that the Bennett memory devices
were necessarily card based.
17. In my opinion, a person having ordinary skill in the art would have understood the
small fast memory of Bennett to be comprised of either dynamic random access memory
(DRAM) cells or static random access memory (SRAM) cells. The specific memory cell type
used would depend on factors including the size of the memory and the required speed of the
memory. It was well-known at the relevant time that SRAM memory provided improved speed
at the cost of greater size (i.e., lower density). Both SRAM and DRAM chips, during the
relevant time frame, comprised multiple arrays of memory cells, with each DRAM memory cell
comprised of a single capacitor and a single transistor, and with each SRAM memory cell
comprised of at least four transistors.
18. The fact that Bennett is not referring to memory cards is confirmed in Bennett's
description of memory cards as background to the invention. (Ex. 1, Bennett col. 37:26-36)
Read in context, Bennett was describing an improvement over, rather than the use of, card-based
devices.
19. Mr. Murphy also states that implementing the Versatile Bus Interface on a memory
device would have been expensive because of the large number of pins necessary. (See Murphy
Supp. Report at 2.) Mr. Murphy's conclusion is inconsistent with Bennett, which explains that a
smaller number of pins can be used. (Id. cols. 17:40-45, 118:20-23.) Further, according to my
REFERENCES 6
understanding of the legal principles of anticipation, the expense involved in implementing a
disclosed invention is not relevant to whether the invention is disclosed.
20. Mr. Murphy's conclusion relies on the flawed predicate that the memory devices in
Bennett would necessarily have been asynchronous. (See Ex. 3, Murphy Supp. Report at 4) This
conclusion ignores the existence in the prior art of synchronous DRAM devices, including the
MCS 4002 DRAM chips from the 1970s. (See Ex. 4, MCS-4 Datasheet at 1-2.) The use of
synchronous DRAMs was also described in Intel's U.S. Patent No. 3,821,715 to Hoff et al.
("Hoff"). Mr. Murphy's conclusion also ignores Bennett's adoption of a synchronous protocol to
address the significant shortcomings of the communication protocols used by asynchronous
devices. (See Ex. 1, Bennett col. 66:9-67:18.) The Bennett patent unambiguously describes
placing a synchronous Versatile Bus Interface and a User Device on a single semiconductor chip,
and explains that the User Device can be memory.
5.1.2 BENNETT DISCLOSES THAT A VALUE STORED IN A

PROGRAMMABLE REGISTER CHANGES READ AND WRITE
LATENCY
21. Mr. Murphy opines that Bennett fails to disclose programmable read and write
latency. In support of his conclusion, Mr. Murphy states that Bennett fails to describe any of the
values stored in the register as controlling latency. (See Ex. 3, Murphy Supp. Report at 4.) Mr.
Murphy also states that the "objective" served by changing the latency in Bennett is different
from the objective served by changing the latency in the claims. (Id. at 6.) Mr. Murphy also
states that the configuration register disclosed in Bennett does not actually determine the
configuration, but rather defines "a ceiling on the various configurations that the device must
support." (Id. at 5.) Mr. Murphy discounts the disclosure in Figures 25a and 25b as "just an
REFERENCES 7
example." (Id. at 6.) Finally, Mr. Murphy states that because the responsive data to a read
request will not always occur at the programmed time, programmable latency is not disclosed.
(Id.)
unambiguous disclosure of Bennett and is directed to irrelevant matters.
23. As depicted in Figures 25a and 25b and as described in the corresponding text of the
specification, when the value stored in the configuration register is changed from the 25a
configuration to the 25b configuration the amount of latency between receiving the memory
request and its associated data signal is reduced by one clock cycle. The 25a configuration value
is representative of a latency that is one clock cycle longer than the latency represented by the
25b configuration. (See Ex. 1, Bennett col. 86:31-41.) Based on the value stored in the
configuration register of a specific device, the latency of that device can be uniquely determined.
This disclosure of latency anticipates the programmable read and write latency recited in
Rambus's claims.
24. Mr. Murphy's statement regarding the names given to the values stored in the
configuration register is irrelevant. (See Ex. 3, Murphy Supp. Report at 4.) The claims require
that a value stored in a register represent the amount of latency. There is no requirement that the
prior art refer to the value by a particular name. The requirements of the claims, as written and
as construed, are indisputably met by Bennett.
25. Mr. Murphy's conclusion about the underlying "objective" in changing the amount of
latency in Bennett is irrelevant. The claims require that a value stored in a register represent the
amount of latency. There is no requirement that the prior art change the amount of latency to
REFERENCES 8
support a particular underlying objective. The requirements of the claims, as written and as
construed, are indisputably met. Further, it is important to note that the "objective" of changing
the configuration values in both Bennett and the accused devices is identical – to configure the
device to communicate properly on a given bus. In the accused devices, the adjustment is to
account for different bus speeds whereas in Bennett the adjustment is to account for different bus
widths, but the underlying objective is the same.
26. Mr. Murphy's conclusion that the register value in Bennett merely provides a
"ceiling" is both incorrect and inconsistent with the Bennett specification. The programmable
devices of Bennett must be capable of operating under a number of different configurations prior
to being programmed. (See Ex. 1, Bennett col. 15:39-53.) Once placed into a system and
programmed, the device operates as configured. (Id. col. 15:60-61) As Bennett explains,
"[a] Versatile Bus is configured by loading the eight digits of the

configuration number . . . into eight three-binary-bit cells of a
configuration register within the Versatile Bus Interface at each
interconnected chip."
(Id. col. 38:56-60 (emphasis added).) Bennett is clear that the programmed value determines the
actual configuration of the device.
27. Further, Mr. Murphy's conclusion that the programmed value is merely a ceiling is
inconsistent with how a person having ordinary skill in the art would understand a configuration
register to function. Such a person would understand that the configuration register defines the
communication protocol to be used by devices connected to the shared Versatile Bus. In order
for the devices to properly receive and decide the messages sent by the Versatile Bus connected
devices, all of the devices would need to communicate using the same communication protocol.
REFERENCES 9
28. Mr. Murphy's statement that Figures 25a and 25b are merely exemplary is incorrect
and irrelevant. The timing diagrams of Figures 25a and 25b depict examples of actual Versatile
Bus configurations. Each of the depicted Versatile Bus signals occurs in a single clock cycle as
determined by the value stored in the configuration register.
29. Finally, Mr. Murphy's citation to examples where a response to a memory
transaction in Bennett may not occur at the time specified by the communication protocol is
irrelevant. Rambus's patents themselves provide examples where the response to a memory
transaction will not occur at the time specified:
In some cases, a slave may not be able to respond correctly to a

request, e.g., for a read or write. In such a situation, the slave
should return an error message, sometimes called a
N(o)ACK(nowledge) or retry message . . . . The master then must
wait . . . and then resend the request.
('184 Patent col. 12:2-23; see also id. col. 12:25-27.) In such a case, the memory does not
respond after a programmable or predetermined delay time, as recited in the claims. What is
important is that Bennett discloses that a response to a memory transaction can occur at the time
specified by the communication protocol.
5.1.3 BENNETT DISCLOSES TWO FORMS OF BLOCK SIZE

INFORMATION
30. Mr. Murphy opines that Bennett fails to disclose receiving block size information
from a memory controller that defines the amount of data to be output by the memory device in
response to an operation code. In support of his conclusion, Mr. Murphy concludes that
configuration-register based block size information does not determine the "number of data
words to be transmitted." (See Ex. 3, Murphy Supp. Report at 9.) As support for this
REFERENCES 10
conclusion, Mr. Murphy states that the value stored in the configuration register is merely a
"ceiling." (Id.) Mr. Murphy also states that block read and block write operations do not provide
block size information based on the BUSY signal. (Id. at 8.) Mr. Murphy attempts to support
that opinion by stating that the BUSY signal "is not received prior to the transfer of data." (Id.)
Finally, Mr. Murphy analogizes the BUSY signal to a "burst terminate" signal.
31. I disagree with Mr. Murphy's opinions, which contradict the express and
32. With respect to the block size information stored in the configuration-register,
Bennett makes clear that the seventh and eighth configuration values stored in the register
control the data format, which determines the number of data bits to be sent per clock cycle and
the number of clock cycles necessary to complete a read or write of a data word. (See Ex. 1,
Bennett col. 17:4-31, fig. 3.) By setting this data format, Bennett controls the total amount of
data to be received or sent in response to a Read or Write request, which respectively read and
write a single data word. (See id. figs. 31, 34.) When the maintenance processor (which is or
would obviously have been implemented as a memory controller or master) programs a memory
device with a particular data format, that device will operate according to the programmed
format when a Read or Write transaction is requested. (Id. cols. 92:15-96:42, figs. 31-36.) The
Read and Write transactions differ from the Block Read and Block Write transactions, where the
total amount of data is controlled by the BUSY signal rather than by the configuration register.
(Id. col. 91:54-68, figs. 32, 34.)
33. With respect to Mr. Murphy's "ceiling" statement, again this statement ignores the
express and unambiguous disclosure in Bennett that the value stored in the configuration
REFERENCES 11
registers of all of the devices on the Versatile Bus determine the communication protocol of the
bus. (See id. col. 38:56-60.)
34. With respect to Mr. Murphy's discussion of the operation of the BUSY signal during
Block Read and Block Write operations (a further disclosure of block size information), Mr.
Murphy's conclusion that the BUSY signal does not provide block size information is incorrect.
The request for a Block Read or Block Write comprises two signals, the Function/ID code,
which instructs the receiving device which type of operation to perform (e.g., a read or a write)
and the BUSY signal which instructs the receiving device how much data to send or receive.
(See id. col. 91:54-68; figs. 32, 34.) The total amount of data to be sent or received is controlled
by the BUSY signal, which comprises information that specifies the total amount of data that is
to be transferred on the bus based on the number of clock cycles that the BUSY signal is sent
active. (Id.) For example, Figure 52b shows that the transmission of BUSY for two clocks
during a block operation results in the transmission of three data words. (Id. col. 109:29-35) If
the BUSY signal had remained active for three clock cycles, the total amount of data would have
been four data words, and so on.
35. Mr. Murphy also states that the BUSY signal is not block size information because it
"is not received prior to the transfer of data." (See Ex. 3, Murphy Supp. Rep. at 8.) This
statement is incorrect. As shown in Figure 52b, the BUSY signal is sent prior to the transfer of
data. (See Ex. 1, Bennett col. 109:29-35.) In fact, based on the protocol described in Bennett,
the BUSY signal must always precede the data with which it is associated in order to instruct the
receiving device whether to send or receive that data. (Id.)
REFERENCES 12
36. Finally, with respect to Mr. Murphy's "burst terminate" statement, I disagree with the
premise of Mr. Murphy's statement—that the use of the BUSY signal is the same as a signal that
is sent to end a transaction. In a system employing burst terminate, the memory device has a
predefined burst length that controls the size of the data burst to be sent unless a signal is sent
during the transmission to end the transfer early. As discussed above, the BUSY signal is sent
ahead of its associated data, and by the number of clock cycles that the BUSY signal remains
active, the receiving device determines the total amount of data to send. In a system using burst
terminate, the terminate signal itself does not provide the required information.
5.1.4 BENNETT DISCLOSES A SET REGISTER REQUEST
37. Mr. Murphy opines that Bennett fails to disclose a set register request. As support
for this conclusion, Mr. Murphy states that the signals used to store information into Bennett's
configuration register are voltage levels that must be held for an extended period of time rather
than "one or more bits." (See Ex. 3, Murphy Supp. Report at 9-10.)
39. Mr. Murphy admits that the maintenance processor sends the (SCAN/SET
ENABLE), (SCAN/SET SELECT), and (SEL LOOP D) signals to control the storage of
information into the configuration register. (See Murphy Supp. Report at 9-10) Indeed, in order
to start the process of storing a value into the control register, the maintenance processor must
transition the three signals to their specific low – low – high (binary "0 – 0 – 1") pattern. (See
Ex. 1, Bennett cols. 118:55-119:3, 125:46-56.) This transition must occur on the leading edge of
clock φ1. (Id. col. 118:55-62.) The sole basis for Mr. Murphy's conclusion is that holding the
REFERENCES 13
three signals means that those signals are not bits as construed by the Court. (See Ex. 3, Murphy
Supp. Report at 9-10) I disagree. At the very least, the transition to low-low-high to begin the
programming sequence is sufficient to meet the construction of set register request. (See Ex. 1,
Bennett col. 125:46-56) Further, Bennett makes clear that the control signals are bits equal to
binary "0" and "1." (Id. col. 118:64-3) Thus, Bennett describes sending bits to a memory device
to store information into a control register as required by the claim.
5.2. OPINIONS TO BE EXPRESSED REGARDING NOVAK
40. Mr. Murphy expressed various opinions in his supplemental expert report as to why
Novak does not anticipate various claims of the patents in suit. (See Ex. 3, Murphy Supp. Rep.
¶¶ 24-48.) I have been asked to respond to those opinions, and do so in the opinions expressed
below.
41. Calling the Novak memory a “VRAM” is irrelevant to whether it qualifies as a
“synchronous memory device” under the Court’s construction. While it is true that the Novak
memory device can operate as a conventional asynchronous DRAM, it can also be clocked by an
external clock and operate as a synchronous device.
42. Novak discloses an external clock Φ that is periodic. As Novak explains:
A control bus 9 coupling the microprocessor 8 to the memory 5

provides the basic clock frequency signal Φ which clocks the serial
video data onto the CRT input line 2, and which also provides the
memory control signals such as Address Latch, Row Address
Strobe (RAS\) Column Address Strobe (CAS\), Serial Select,
Output Enable (SOE\), Write Enable, Write (W\), Increment
(INC), etc., as may be required because of characteristics of both
the memory device 5 and the microcomputer 6."
REFERENCES 14
(Ex. 2, Novak col. 4:40-50.) Additionally, Novak implicitly explains that the external clock is
periodic, stating, “the Φ generator need not be synchronized with the clock of the microcomputer
8.” (Id. col. 15:22-23.) By explaining that it “need not be,” Novak thereby discloses that Φ can
actually be synchronized to the microprocessor clock, but can alternatively be synchronized to
something else (e.g., the video display clock).
43. The external clock Φ disclosed in Redwine is in all relevant aspects the same as the
external clock Φ disclosed in Novak. (See, e.g., Ex. 5, Redwine col. 3:39-63) In fact, Figures
2d, 2e, and 2f in Redwine are the same as Figures 4d, 4e, and 4f in Novak. These figures contain
the same external clock Φ. Additionally, Figure 1 in Redwine and Figure 2 in Novak are
virtually indistinguishable insofar as Φ is concerned. This Court in Hynix I found that Redwine
disclosed the external clock Φ limitation. (See Ex. 6, Redwine MSJ Order at 4-5.) Therefore, in
my opinion, the external clock Φ in Novak satisfies the external clock limitation. In addition,
Novak expressly discloses that Φ is or can be the system clock, as discussed above, so it is even
clearer in Novak that Φ is an external clock.
44. In Redwine, CS\ is used to “gate” the external clock Φ and allow it to pass through
to the interior of the chip where Φ is used for the period that it is needed. Novak does not
expressly disclose a similar gate, but that has no bearing on how the external clock signal Φ is
received at the chip or on how various aspects of the chips are synchronized with respect to that
external clock. Further, one of skill in the art would understand that Novak does include an
internal gate to generate the internal clock shown in Figure 4 (which is shown to be periodic only
for the time when data is actually being sampled or output) from the continuously periodic
external clock.
REFERENCES 15
45. Mr. Murphy’s opinion that Redwine does not disclose an external clock signal is
contrary to the Court’s holding in Hynix I. The Court specifically held that “Redwine discloses
the ‘external clock signal’ limitation.” (Ex. 6, Redwine MSJ Order at 5.)
46. Mr. Murphy contends that Novak does not disclose a write request or operation code
because “in order to specify a serial write operation,” it is necessary for Φ to toggle to load the
data into the shift register, after which TR\ must transition to active-low, followed by W\
transitioning to active-low, followed by RAS\ transitioning to active-low to transfer the data into
the array; Mr. Murphy states
the serial write … operation[] in Novak cannot be specified simply

by a code consisting of a series of bits, because it is not simply the
values of the relevant control signals at a particular point in time
that specify the operations. Rather, the control signals must
transition in the correct order and be held for the required time
periods.
(Ex. 3, Supp. Murphy Rep. ¶ 29.) Although it may in fact be necessary to engage in this
sequence of transitions of signals to carry out a complete serial write operation, this sequence is
not necessary to request a write of data (i.e., write request) or to specify a type of action (i.e.,
operation code). All that is necessary to request a write of data is for signals TR\ and W\, which
contain bit values, to be active (low) when RAS\ goes active. The actual write command is W\
(low) (See Ex. 2, Novak col. 6:51) while the state of TR\ determines whether the write operation
is to be a serial write or a random write. (See id. cols. 6:51, 6:35-44, 8:30-39) As such, either
separately or together, TR\ and W\ constitute operation codes because they specify a type of
action: read when W\ is high, write when W\ is low, serial when TR\ is high, and random when
REFERENCES 16
TR\ is low. They specify the type of operation that is to be conducted. The constructions of
write request and operation code only required that the type of operation be specified.
47. In addition, the Court specifically held that Redwine disclosed an operation code in
the form of the W\ signal. (See Ex. 6, Redwine MSJ Order at 5.) Therefore, the same W\ signal
disclosed in Novak should be an operation code as well.
48. It is irrelevant that Redwine does not discuss the TR\ signal. This in no way should
affect whether the W\ signal in Novak is an operation code. This Court in Hynix I clearly held
that W\ in Redwine constituted an operation code. The same W\ signal is disclosed in Novak
and, therefore, consistent with Hynix I, should be an operation code. Mr. Murphy appears to
disagree with the Court’s previous ruling in Hynix I regarding W\ being an operation code. Mr.
Murphy incorrectly argues that the states of RAS\ and W\ are not by themselves sufficient to
specify a serial or write operation because the relative transition times must also satisfy certain
conditions that are not captured by the bits alone. Mr. Murphy makes the same argument that he
did in Hynix I to argue against W\ being an operation code. However, the Court rejected this
argument:
Rambus counters that Redwine teaches commands using

“transition-based signals” as opposed to bits specifying a read or
write action, i.e., Redwine “discloses commands based on the
transition of, not the state of, the RAS signal and the W signal held
high or low.” Murphy Decl. ¶ 45. As support, Rambus notes that
the Redwine patent discusses “when RAS goes low,” indicating
that it teaches commands using transition-based signals. See id.
Hynix responds that the W signal when high specifies a read

operation, and when low specifies a write operation. See Redwine
Patent at 4:8-11. Based on the Redwine patent specification, it
appears clear that neither the read nor write operations is signaled
based on when the W signal is transitioning from one state to
REFERENCES 17
another. In addition, even assuming that W was a transition-based

signal, W would still constitute a bit specifying a read or write
operation. The court finds that the W signal constitutes an
operation code.
(Id.)
49. Mr. Murphy contends that the operation code in Novak is sensed rather than
sampled, but his contention is technically inaccurate. This Court’s construction of “sample”
merely requires the bit value of the operation code to be obtained at a discrete point in time. The
bit value of the operation codes (including TR\ and W\) are always obtained at a discrete point in
time, i.e., during the falling edge of RAS\:
“To load the shift register or transfer its contents into the array,
TR\ must be low during the falling edge o[f] RAS\. If W\ is held
high during the falling edge of RAS\ then data in the columns of
the selected row will be shifted into the register by the transfer
gates 21. … If W\ is held low during the falling edge of RAS\,
then data is transferred from the shift register to the array columns
and into the row selected by the row address bits. If TR\ is held
high when RAS\ falls low then the shift register and array operate
independent of each other, i.e., the shift register may shift data our
or in and the array is available for random access.” (See Novak,
Col. 10:18-52)
That is, the values of TR\ or W\ are sampled at a discrete point in time, namely during the falling
edge of RAS\. Thus, the operation code in Novak is sampled.
50. Novak discloses that there is a known timing relationship between the system clock
and W\, TR\, RAS\, and CAS\. As illustrated in Figure 8 of Novak, W\, TR\, RAS\, and CAS\
are generated by the Arbitration and RAM Cycle Generation circuit, which uses the system clock
as an input. One skilled in the art reading Novak would understand that the W\, TR\, RAS\, and
CAS\ are generated in relation to a system clock. As discussed above, Novak teaches that the
REFERENCES 18
clock signal Φ may be synchronized with the system clock. In that circumstance, W\, TR\,
RAS\, and CAS\ would also have a known timing relationship with clock signal Φ.
51. Novak discloses sampling block size information with a known timing relationship
to Φ. The address latches in the input receiver circuitry receive block size information
synchronously with respect to the RAS\ signal because there is a known timing relationship
between the time when address latches receive and latch the block size information and when
RAS\ goes low. As Novak explains, “when RAS\ goes low as seen in Figure 4a, clocks derived
from RAS\ cause the buffers 14 to accept and latch the eight row address bits then appearing on
the input lines 15.” (Ex. 2, Novak col. 8:25-28.)
52. Similarly, the column address bits, including A6, A7, used to denote the number of
bits to be transferred, are latched onto the chip upon the falling transition of CAS\. (See id. cols.
5:44-57, 8:14-20.) Since there is a known timing relationship between Φ and CAS\ and a known
timing relationship between CAS\ and sampling block size information (e.g., A6, A7), it follows
that there is a known timing relationship between Φ and sampling block size information.
53. Novak discloses inputting and sampling data in response to a write request and
operation code. As described in Novak, the loading (i.e., writing) of the shift register is done in
response to the state of TR\, which constitutes part of the write request/operation code:
Thus, the timing of the TR\, W\, CAS\ and RAS\ signals is
different for serial reads and writes, and random reads and writes.
The voltages and timings of these control signals are seen in FIGS.
4a-4i for serial operations and 4j-4r for random operations. To
load the shift register …, TR\ must be low during the falling edge
o[f] RAS\. … The serial shift clock Φ, FIG 4f, then shifts the data
out of the shift register at the desired data rate in response to the
frequency of the clock Φ. If W\ is held low during the falling edge
of RAS\, then data is transferred from the shift register to the array
REFERENCES 19
columns and into the row selected by the row address bits. If TR\
is held high when RAS\ falls low then the shift register and array
operate independent of each other, i.e., the shift register may shift
data out or in and the array is available for random access. … Thus
the timing of W\ is different in the random access mode and the
serial mode of operation of the memory device. More specifically,
W\ is set up and held relative to the falling edge of CAS\ during a
random access operation. However, W\ is set up and held relative
to the falling edge of RAS\ during a serial access operation.” ()
(Id. col. 10:18-52.) As such, Novak discloses inputting and sampling data (including loading the
shift register) in response to a write request or operation code.
54. Novak discloses a synchronous memory device. The Court has construed
“synchronous memory device” as “a memory device that receives an external clock signal which
governs the timing of the response to a transaction request.” The Court has also construed
“transaction request” as “a series of bits used to request performance of a transaction with a
memory device.” The memory device in Novak receives an external clock signal ϕ, which
governs the timing of the read or write of data, which is a response to the read or write request,
each of which constitutes a transaction request which specifies the type (serial or parallel) of read
or write to perform.
55. Mr. Murphy offers several additional opinions about why Novak does not disclose a
synchronous memory device, all of which are incorrect. First, he declares that the disclosure of
Novak is limited to a VRAM that is a conventional asynchronous DRAM with an added shift
register. The memory device in Novak is not limited to a VRAM, however; Novak explicitly
teaches using it in other applications, such as voice or digital communication devices or a
magnetic disk drive. (See, e.g., Ex. 2, Novak col. 16:29-66) Additionally, Novak is synchronous
since it has an external clock signal as an input, and, as Mr. Murphy admits, uses both the rising
REFERENCES 20
and falling edges of Φ both to input and to output data from the serial port of the chip. This
external synchronous clock, Φ, thus “governs” both the reading and the writing of data
respectively out of and into the DRAM chip. Calling the Novak memory a “VRAM” is not
relevant to whether it qualifies as a “synchronous memory device” under the Court’s
construction. Second, Mr. Murphy opines that ϕ cannot “govern” the response to a write request
because it has loaded data into the shift register and become inactive before the transitions
constituting the write request have occurred. I an not sure what Mr. Murphy means when he
opines that ϕ has become inactive, but it is clear from Novak that ϕ governs the timing of the
writing of data into the memory device in Novak. (See id. figs. 1, 2, 4; see also col. 6:19-34
(“The shift register 20 may be … loaded into the column lines for a write cycle … . Data input
to the device for serial write is by a data-in terminal 22 (2a of FIG.1) which is connected by a
multiplex circuit 23 to inputs 24a and 24b of the shift register halves. … The shift register 20 is
operated by a clock ϕ which is used to shift the bits through the stages of the register, two stages
for each clock cycle.”).) Such a write of data is indisputably a response to a transaction request,
i.e., a write request. (See, e.g., id. col. 6:50-51 (“In a serial write operation, the sense amplifiers
11 are operated by a write command, W\ … .”).) Also, as discussed above, ϕ is an external clock
signal which is periodic; it is also periodic internally, even though it is gated to operate internally
only when data is actually being input (sampled) or output. Third, Mr. Murphy opines that, for a
serial read operation, ϕ cannot determine the length of time between the transitions of the control
signals that constitute a read request and the output of date from the shift register. It is entirely
unclear, even if true, why this leads Mr. Murphy to conclude that ϕ cannot govern the timing of
the response to a read request. Novak is clear that ϕ governs the timing of the data being read
REFERENCES 21
out from the memory device, which occurs in response to a read request. (See, e.g., id. col. 6:55-
69) Nothing in the construction requires that the external clock govern the timing of the start of
the response to a transaction request relative to the sampling of an operation code, but even if it
did, that would be satisfied here, because RAS\ and CAS\ would be known to be generated with
respect to the external system clock.
56. As stated above, it is my opinion that Novak discloses a memory device that
operates synchronously. Whether it uses the word “synchronous” in its name (e.g., “VRAM”) is
not relevant to whether a particular device satisfies the Court's construction.
57. Novak also discloses block size information. Mr. Murphy acknowledges that Novak
discloses four taps that are used to select “whether one, two, three or all four 64-bit shift registers
are accessed.” (Ex. 2, Novak col. 7:16-17) While Novak does identify one advantage of these
taps as allowing the user to access any bit of data in “64 shifts or less, rather than 256 shifts,”
(See id. col. 7:39-40), Novak also teaches that the taps allow the user to select the total amount of
data that is to be transferred, as required by the Court’s construction of block size information:
“[I]f the two bits are both 0, then all 256 bits in the shift register
may be shifted out. If the two bits are 01, then 192 bits, starting at
bit 64, may be shifted out. If the two bits are 10, then 128 bits,
starting at bit 128, may be shifted out. The two bit code 11, selects
the last 64 bits starting at bit number 192 and then these last 64 bits
may be shifted out.”
(Id. col. 7:48-56.) As such, Novak discloses block size information.
58. Novak also discloses block size information by specifying the amount of data to be
transferred on the bus. Mr. Murphy opines that the data transferred from the shift register is not
transferred on the bus but rather is transferred on a “separate signal line” that connects directly to
REFERENCES 22
the video display or CRT tube, and further that the “bus” at issue is the set of signal lines that
connect the memory controller to the memory device. There is nothing in the claims or the claim
constructions that requires that the “bus” for transferring data be the connection only between the
memory and the memory controller. As Mr. Murphy notes in his supplemental report, the Court
construed “block size information” as “information that specifies the total amount of data that is
to be transferred on the bus in response to a transaction request.” There is no requirement that
the “bus” at issue needs to be the same set of signal lines that connect the memory controller to
the memory device. According to the Court’s claim construction, a bus is simply “a set of signal
lines to which a number of devices are connected, and over which information is transferred
between devices.” Nothing in this construction requires that the “devices” be any particular type
of device, as long as they are connected to the “bus,” just as the Novak memory is connected to a
CRT or other serial device such as a disk drive (see Ex. 2, Novak col. 16:53-63), or
communication system (id. col. 29-53).
59. The “separate signal line” of Novak clearly fits the Court's construction of “bus.” It
is a signal line that connects a number of devices (memory and video display, etc.) and over
which information (data) is transferred between the devices. To the extent that Mr. Murphy is of
the opinion that a “set of signal lines” must have more than one line, Novak expressly discloses
that the serial output can be 1 bit or 8 bits wide (i.e., comprise 1 line or 8 lines from a single
chip). (See, e.g., id. col. 12:60-62) All of the requirements of “block size information” are
disclosed in Novak.
60. Novak discloses sampling data in response to an operation code after a
predetermined number of clock cycles. As discussed above, Novak discloses an operation code
REFERENCES 23
specifying a write operation. Novak explicitly discloses that serial data can be shifted into the
register halves while data is being shifted out, and so a write operation can begin just after a read
operation is initiated; although not needed in the system of Figure 1, this feature is important for
other embodiments. (See, e.g., id. col. 8:48-52) As shown in Figures 4d and 4e of Novak, the
start of the write operation (“Data In”) is shown as being delayed one-half clock cycle after the
start of a read (“Data Out”). This delay constitutes a predetermined number of clock cycles.
61. Novak discloses “one or more bits indicating whether the sense amplifiers and/or
bits lines (or a portion of the sense amplifiers and/or bits lines) should be precharged.” Each
time a new row address is selected, the row is refreshed after transferring the row of data either
from the memory cells to the shift register (for a read operation) or from the shift register to the
memory cells (for a write operation): “Refresh occurs every time a row address appears on the
inputs 15 and RAS goes low, as seen in FIG. 4a and 4c.” (Id. col. 8:40-42) When a row is
addressed for serial-read or serial-write, this also refreshes the data in this row; likewise, a
parallel access refreshes a row upon read or write. As Mr. Murphy admitted in his deposition,
one of ordinary skill would understand that, in a DRAM, refreshing a row necessarily includes a
precharging operation. (See Ex. 7, Murphy Dep. Tr. at 749:6-22.) Therefore, one of ordinary
skill in the art would understand that a command initiating a serial-read or serial-write operation,
necessarily including a refresh operation, contains one or more bits indicating whether the sense
amplifiers and/or bits lines (or a portion of the sense amplifiers and/or bits lines) should be
precharged. Mr. Murphy opines that RAS\ does not constitute a bit of information contained in
an operation code because the control signals in Novak must transition in a particular order and
be sensed over extended periods of time for the device to operate correctly. This assessment is
REFERENCES 24
incorrect. Each time a new row address is selected (on the activation of RAS\), a read or write
operation is conducted, along with a refresh, which includes a precharge operation. In addition,
as discussed above, each time a new row address is selected (by RAS\ going low (active)), an
operation code is latched into the Novak DRAM. Therefore, each RAS\ activation, accompanied
by an operation code, automatically causes a precharge—i.e., indicates that the sense amplifiers
and bit lines of the memory array should be precharged.
62. Mr. Murphy’s reference to the Hynix I Claim Construction Order does not support
his stated conclusion. The section of the Order that Mr. Murphy cites references the
“autoprecharge” operation and separate “precharge / save-data switch” (AccessType[3])
disclosed in the specification of the Rambus patents. Neither the language of the claims at issue
here nor the Court’s claim construction in this litigation includes Mr. Murphy’s addition to
both—that the precharge information must indicate whether or not to precharge the sense
amplifiers and/or bit lines. Both the claim language and the Court’s construction are satisfied by
an operation code that, as in Novak, includes an indication that the sense amplifiers be
precharged.
Dated: December 23, 2008
___________________________________
Joseph C. McAlexander
REFERENCES 25
EXHIBITS:
1. U.S. Patent No. 4,734,909 to Bennett et al. (“Bennett”)
2. U.S. Patent No. 4,663,735 to Novak et al. (“Novak”)
3. November 14, 2008 Supplemental Expert Report of Robert J. Murphy Regarding Validity
in Light of the Bennett and Novak References (“Murphy Supp. Rep.”)
4. Intel MCS-4 Micro Computer Set ("MCS-4 Datasheet”)
5. U.S. Patent No. 4,330,852 to Redwine et al. (“Redwine”)
6. Order Denying Hynix's Motion for Summary Judgment of Invalidity of U.S. Patent Nos.
6,378,020 and 5,915,105 Under 35 U.S.C. §§ 102 and/or 103, Hynix Semiconductor Inc.
v. Rambus Inc., No. CV-00-20905 RMW (“Hynix I”) (N.D. Cal. Feb. 28, 2006)
(“Redwine MSJ Order”)
7. Transcript of October 13, 2008 Deposition of Robert J. Murphy (“Murphy Dep. Tr.”)
REFERENCES 26

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Case 5:05-cv-00334-RMW Document 3042-2 Filed 01/09/2009 Page 1 of 30

IN THE UNITED STATES DISTRICT COURT

RAMBUS INC., Case No. C-05-00334 RMW

Plaintiffs, SUPPLEMENTAL EXPERT REPORT OF

RAMBUS INC., Case No. C-05-02298 RMW

SAMSUNG ELECTRONICS CO., LTD.,

RAMBUS INC., Case No. C-06-00244 RMW

MICRON TECHNOLOGY INC., MICRON

3. DOCUMENTS, DEPOSITIONS, AND OTHER MATERIALS CONSIDERED ...............1

4. BASIS OF OPINIONS FORMED............................................................................................2

5. OPINIONS TO BE EXPRESSED ............................................................................................2

SUPPLEMENTAL EXPERT REPORT OF JOSEPH C. McALEXANDER

1. I have been asked to supplement the opinions provided in my original invalidity

2. My supplemental opinions formed are provided below in Section 5. A summary of

preparing this supplemental report are identified in Section 3.

3. DOCUMENTS, DEPOSITIONS, AND OTHER MATERIALS CONSIDERED

4. In addition to the documents, depositions, and other materials identified in my

4. BASIS OF OPINIONS FORMED

on my education, experience, and knowledge of engineering practices.

5.1. OPINIONS TO BE EXPRESSED REGARDING BENNETT

7. In opposition to Summary Judgment of invalidity, Rambus submitted an opposition

5.1.1 BENNETT DISCLOSES SINGLE-CHIP MEMORY DEVICES AND

unambiguous disclosure of Bennett.

chip. Bennett explains that

[t]he apparatus of the invention for realizing the objects thereof is

(Ex. 1, Bennett col. 12:28-32.) Bennett further states that

[e]ach Versatile Bus Interface Logics, for example Versatile Bus

Device and the Versatile Bus Interface on to a single chip.

[t]he Versatile Buses family is a specification for a spectrum of

(Id. col. 35:59-62.) Similarly, Bennett states that

[a] 'User' is the logics (e.g., a central processor or a memory or

Bus interconnected device”:

The User announces to all other Versatile Bus interconnected

Interface can be connected to the Versatile Bus.

plurality of such synchronous devices.

dynamic random access memory cells.

were necessarily card based.

comprised of at least four transistors.

understanding of the legal principles of anticipation, the expense involved in implementing a

disclosed invention is not relevant to whether the invention is disclosed.

address the significant shortcomings of the communication protocols used by asynchronous

and explains that the User Device can be memory.

5.1.2 BENNETT DISCLOSES THAT A VALUE STORED IN A

unambiguous disclosure of Bennett and is directed to irrelevant matters.

as construed, are indisputably met by Bennett.

widths, but the underlying objective is the same.

"[a] Versatile Bus is configured by loading the eight digits of the

actual configuration of the device.

determined by the value stored in the configuration register.

29. Finally, Mr. Murphy's citation to examples where a response to a memory

transaction will not occur at the time specified:

In some cases, a slave may not be able to respond correctly to a

specified by the communication protocol.

5.1.3 BENNETT DISCLOSES TWO FORMS OF BLOCK SIZE

unambiguous disclosure of Bennett.

(Id. col. 91:54-68, figs. 32, 34.)

bus. (See id. col. 38:56-60.)

been four data words, and so on.

receiving device whether to send or receive that data. (Id.)

5.1.4 BENNETT DISCLOSES A SET REGISTER REQUEST

unambiguous disclosure of Bennett.

to store information into a control register as required by the claim.