ASIC Design Flow Tutorial

by Mehmet Ali Yildirim

Hacettepe University Department of Electrical and Electronics Engineering

Ankara, Turkey

Chapter 1: Starting the Design Chapter 2: Simulation with Modelsim Chapter 3: Synthesis Using Leonardo Spectrum Chapter 4: Creating a Schematic Chapter 5: Design Architect and Viewpoint Creation Chapter 6: Simulation in Accusim Chapter 7: IC Station Chapter 8: Parasitic Extraction and Backannotation

Chapter 1 Starting the Design

1.1 Introduction to the design flow 1.2 Setting up the environment 1.3 Writing the VHDL source

1.1 Introduction to the design flow

This tutorial has been prepared to introduce the basics of ASIC design using VHDL. We will follow a design flow methodology based on our studies at the VLSI Design Laboratory at Hacettepe University. EDA tools provided by Mentor Graphics will be used. The flow and the tools are shortly described below. As seen on the figure the flow starts from VHDL. Firstly, the behavior of the circuit is described in VHDL. The whole description can be written by the designer as well as it can be generated by using a design automation software such as Mentor Graphics' Renoir. The VHDL syntax or Renoir will not be covered in this tutorial. It is assumed that you already know how to write VHDL codes.

Once the code has been written, you should check it to ensure that it is correct. This step is very similar to debugging a program in any programming language. The tool we will be using for this check is Modelsim, which is the HDL compiler and simulator. The compiled source code will be simulated using it.

After simulation, we come to the synthesis step. Synthesis is the process of synthesizing a schematic or netlist of the

design from the HDL code. The schematic consists of transistors, logic gates or other elements. The tool we will be using for this step is Leonardo Spectrum. It is a sophisticated tool which synthesizes netlists satisfying the specifications you enter. Leonardo has many output file options, but we will take the output in EDIF format for compatibility with the tools we will use later on.

The EDIF files cannot be directly used in the rest of the tools. Hence they should be transferred into EDDM schematics. Firstly, EDIF file will be converted into an EDDM file using a script, and then that file will be converted into a visible schematic using Schematic Generator. The generated EDDM schematic is suitable for all the tools for simulation and layout creation.

Design Architect is the primary tool to draw a schematic using the components in either its own libraries or user defined libraries. It is possible to draw the whole design or some part of it in Design Architect, but this will not be explained in detail. We will just use it to check the generated EDDM schematic and to create a symbol.

The following step is Accusim II, the analog simulation tool. It will be used to simulate the schematic. This simulation can be done by using a digital simulator such as Quicksim, or by both simulators.

The last tool to be used is IC Station, in which the layout of the design will be created and checked.

The last step of our design flow is to backannotate the layout. Backannotation : parasitic capacitance and resistance values will be extracted from the layout and the design will be re-simulated in Accusim with the added parasitic values.

If the design satisfies your specifications after backannotation, your chip is ready for fabrication.

Keep in mind that the flow described above needs going back and forth in most of the steps if undesired simulation results are obtained. You should go one or more steps back and reconsider your design.

1.2 Setting up the environment

Let us begin by creating some folders to keep our data in. Inside your home folder create a new folder named tutorial and create four subfolders in it source, modelsim, leonardo, accusim. In UNIX prompt the commands should be as : # cd $home # mkdir tutorial # cd tutorial # mkdir source # mkdir modelsim # mkdir leonardo # mkdir accusim After creating the folders, copy the .cshrc file into your home folder # cp /.cshrc $home/ The next step will be to set your working directory as tutorial. Open your .cshrc file using any text editor, find the line containing setenv MGC_WD and change it to: setenv MGC_WD /export/home/<your_username>/tutorial save the file and exit the editor. To make the changes effective write the command # source .cshrc

1.3 Writing the VHDL source

Firstly the specifications of the design should be determined, then they should be implemented in VHDL. We will design a four-bit up-down counter with enable and reset inputs. When enable is high (logic 1) it should count, when low the counter should stop. The input cnt_up should determine the direction of count. Reset should cause the output to be zero (0000).

A possible VHDL description fulfilling the requirements is mycounter.vhd.

Save the above code inside the folder source with the name mycounter.vhd Now we are ready to go one step further. We will compile and simulate mycounter.vhd in the next chapter.
--- file name: mycounter.vhd -LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY mycounter IS PORT(clock,reset,cnt_up,enable : IN std_logic; Y3,Y2,Y1,Y0 : OUT std_logic); END mycounter; ARCHITECTURE arch OF mycounter IS SIGNAL cnt : std_logic_vector(3 downto 0) := "0000"; BEGIN counting: PROCESS(clock,reset,cnt_up,enable) BEGIN IF (reset = '1') THEN cnt<="0000"; ELSIF (clock'EVENT AND clock = '1') THEN IF (enable = '1') THEN IF (cnt_up = '1') THEN cnt <= cnt + "0001"; ELSE cnt <= cnt - "0001"; END IF; END IF; END IF;

END PROCESS; Y3 Y2 Y1 Y0 <= <= <= <= cnt(3); cnt(2); cnt(1); cnt(0);

END arch; --- end VHDL code --

Chapter 2 Simulation with Modelsim

2.1 Before simulation 2.2 Simulation

2.1 Before simulation

In a terminal change your directory to modelsim directory and start Modelsim as # cd

$MGC_WD/modelsim # vsim -gui If the Welcome Dialog Box appears you may click Done or close it. We start by creating a new library. Choose Design>Create a New Library pull down menu.

Fill the dialog box as

Click OK.

The next step is to compile the source. Modelsim needs the compiled source for simulations. Click on the Compile button on the toolbar or you can do the same by Design>Compile menu item. When the dialog box appears browse for mycounter.vhd choose it and press on Compile.

After compilation is finished, click Done. If there are any errors in the source you may use Edit Source to correct them. Now, select the Load Design button Design>Load New Design pull down menu. on the toolbar or

Choose mycounter and then click on Load. The design is ready for simulation.

2.2 Simulation

Use the View>All pull down menu to see all of the simulation windows. We will not be using all the windows, but it may be useful to view them all sometimes.

In the Signals window you can see all the inputs, outputs and the internal signal cnt.

To see all signals in the Wave window use the menu selection View>Wave>Signals in Region

The Wave window should seem as

Now, let us assign values to inputs. In Signals window again select clock and use the menu Edit >Clock. Define the clock as it is in the following figure.

Click OK to the dialog box. Select reset and assign 0 to it from the Edit >Force menu.

Then force enable to 1 and cnt_up to 1 yourself. After all inputs are forced we can run the simulator. i) To run the simulator you can write in the command line >run {runs for 100 ns} >run 550 {runs for 500 ns} ii) you can click the run symbol on toolbars of main window or wave window. The default duration is 100 ns, but any duration can be specified. iii)from main window Run >Run 100ns Then you can press run all for a whole run. You should click break to pause, continue to go on. After the run you should see the wave window as

The input values given above do not contain the all possible inputs, but they are sufficient to get a general idea about the tool. After simulating for enough time, force your own values to inputs and check if the source file is correct. When reset = 1 output should be "0000", when enable = 0 counter should stop, when cnt_up = 0 it should count downwards. If you notice any errors or wrong operation, you can edit the source using the source window. You can add breakpoints on executable lines (shown in green) by just clicking on them. You can examine the variables by stepping over. There are some other windows in Modelsim, but they are not very important at the moment. Now, you are ready to start chapter 3.

Chapter 3 Synthesis Using Leonardo Spectrum

Invoke Leonardo by entering the command # leonardo We shall be using Leonardo Spectrum Level 3. Leonardo will be used to synthesize VHDL descriptions and to create ASIC schematics using AMI libraries. It is a very important tool of ADK (Asic Design Kit), it converts technology independent VHDL into technology specific schematics. When Leonardo window appears, click Toggle Advanced FlowTabs button on the toolbar. This will bring you the advanced options. Click on " Technology" and choose ami05_typ.(We could select any technology from the ASIC part.) Press on Load Library.

After technology library is loaded click "Input" next to "Technology".

In the "Input" window you can specify the working directory, folder ~/tutorial/leonardo can be used here. Click the open files button and browse for mycounter.vhd which is inside the folder source then open the file. In the "Input" window again, click the Read button. Go to the "Constraints" window. Specify clock frequency as 200 Mhz inside the Global sub-section. Go to the "Optimize" section. Area, delay and also timing optimizations can be made in here. Let us optimize for delay; click the appropriate options and then press the Optimize button as shown in the following figure.

Go to the "Report" section. You can get both area and delay reports, either written into a file if you enter a filename or displayed on the screen if filename part is left blank. Leonardo can also report you the maximum clock frequency your design can operate at.

If you would like to see the maximum clock frequency just put a tick to the Report Clock Frequency option in the Report Delay sub-section. The last section of Leonardo is the "Output" section. Change the output files format to EDIF. In the EDIF Out Options sub-section change the EDIF GND value to TRUE then Apply.

Go back to the Output Files sub-section shown in the above image and click Write. The EDIF netlist has been written. Our primary goal in using Leonardo was to create that netlist. After finishing synthesis procedure we are now ready to see the schematic of our design. Leonardo provides the RTL Schematic and Technology Schematic of the design and also the Critical Path Schematic showing the longest delay path in the design. Those schematics can be opened by clicking the corresponding icons on the toolbar. You will see the Technology Schematic divided into two sheets as sheet1 and sheet2.

The RTL Schematic and the Critical path schematic will be as shown here.

This much is enough for now. Let us continue with the next chapter.

Chapter 4 Creating a Schematic

4.1 Converting EDIF into EDDM 4.2 Generating a Schematic

4.1 Converting EDIF into EDDM

Leonardo creates schematics, but they can not be understood by other tools. Hence, the output of Leonardo should be converted into the EDDM format which is used by the other ADK tools, in order to simulate the schematic and create the layout. We will use the command # enread <path>/design.edf -r -rcf <path2>/configB <path> is the path of the directory in which the EDIF file has been saved. design.edf is the name of the design. -r : replace while writing -rcf : read command file <path2> :path of the command file configB :name of the command file. Write the following script using a text editor and save it inside your home folder with the name configB.

setup character substitution "<>" "()" -names map path $ADK/parts ami05_fast -external map path $ADK/parts ami05_typ -external map path $ADK/parts ami05_slow -external map path $MGC_WD/ /work map path ami_fast PRIMITIVES map path ami_typ PRIMITIVES map path ami_slow PRIMITIVES
We saved mycounter.edf in the folder ~/tutorial/leonardo/ and assume the command file is in your home folder, our UNIX command will be :

# enread $MGC_WD/leonardo/mycounter.edf -r -rcf ~/configB enread creates a subdirectory named work inside your working directory and saves the created component mycounter inside work. The next step is to generate a schematic for our component mycounter.

4.2 Generating a schematic

Start Schematic Generator with the command # sg Use File >Open Component From Model menu item. When the dialog box appears choose arch inside mycounter. Click OK.

Then the dialog box should seem like this.

Click OK. From the toolbar choose Setup >Symbol >Use Genlib Classifications. Next, press F3 or type generate and press Return. All the Mentor Graphics' tools we will be using from now on allows you to enter commands by typing. When you start typing, a popup command line appears at the location of the mouse pointer and you can enter any command, copy, move, generate, etc. by this way. Type '*'(a star) and then press ( 'Control'-'Shift'-'/ ') at the same time to view the list of all the available commands. After schematic is properly generated save it using File >Save, and exit Schematic Generator. The next step of the flow will be to check the schematic, create a symbol for mycounter and save the component into another directory. Design Architect will be used in the next chapter.

Chapter 5 Design Architect and Viewpoint Creation

5.1 Opening, Checking and Saving a Schematic in Design Architect 5.2 Generating a Symbol 5.3 Creating Viewpoints

5.1 Opening, Checking and Saving a Schematic in Design Architect

Invoke Design Architect with the command # adk_da

Click the Open Sheet button on the session palette

or use File >Open >Sheet

Using the navigator choose sheet1 inside $MGC_WD/work/mycounter/arch/ then click OK to the dialog box.

In Design Architect Open Sheet is used for two purposes: either to open an existing sheet or to create a new one. If you enter a new name for the Component Name field a blank sheet is opened for you to draw your schematic.

When the sheet is opened, use View >View All or write the command view all or press (Shift-F8) to see the whole schematic. As you see there are many alternative ways of doing the same job in Mentor's tools. Now, check the sheet using Check >Sheet >With Defaults. Ignore any warnings, if there are no errors you can save the sheet, if there is any correct the errors. Use File >Save Sheet As option to save into a different location. We do this in order not to overwrite the original schematic. You may need the original schematic sometime and it may not be that easy to regenerate it. Save the sheet inside your working directory with component name mycounter. Click OK.

5.2 Generating a Symbol

Use Miscellaneous >Generate Symbol

Specify component name as $MGC_WD/mycounter and schematic name as arch. Enter mycounter in the symbol name field. If you would like to change an existing symbol click Yes to Replace Existing? Press OK to accept the dialog box. Check the symbol : Check >With Defaults. There may be warnings about the I/O pins. If there are no errors that is enough. Save the symbol File >Save Symbol >Default Registration. Close the symbol window. When the schematic window is active, check the schematic Check >Schematic >With Defaults. This option checks the correspondence of the schematic with the symbol. Now let us see some interesting properties of Mentor tools. Pressing the middle mouse button draw a question mark (with a two-button mouse press both buttons at the same

time). This will bring you the help window of strokes. You will see how you can use the middle mouse button to ease your job. Try to get used to the strokes. The strokes exist in many Mentor Graphics tools, but they vary from tool to tool. Simply draw a question mark, if you can and learn the strokes specific to that tool. Exit Design Architect.

5.3 Creating Viewpoints

In order to simulate the design in Accusim and to generate the layout we should create viewpoints. The adk_dve script is used to create all necessary viewpoints. adk_dve prepares the ADK schematics for analog simulation with Accusim, digital simulation with Quicksim, IC layout creation and LVS checking in ICStation. In a terminal change the current directory to your working directory and then run the adk_dve script # cd $MGC_WD # adk_dve mycounter By default the script sets the technology to ami05. To change the technology use -technology option. After running the viewpoint editor you should see five new folders inside the component mycounter. The new folders are accusim, ami05, layout, lvs and sdl. We are ready to simulate our component in Accusim in Chapter 6.

Chapter 6 Simulation in Accusim

6.1 Setting up the Environment 6.2 Simulation

6.1 Setting up the environment

Accusim II is our analog simulator, it can be used to view the delay, rise time, fall time and the fluctuations in the output voltage. A digital simulator can also be used, or we can use them both for a detailed analysis. Start Accusim with the command # accusim mycounter/accusim The general command is # accusim <design>/<viewpoint> This loads the design mycounter with the accusim viewpoint we created inside. If Accusim is started correctly you should see your schematic on the screen. Use the menu item File >Auxiliary Files >Load Model Library. Load the model $ADK/technology/accusim/ami05.mod ( $ADK path in our system is /export/home/ADK)

We must load a model library to show the simulator which model of FETs are used. Models are technology specific spice parameters. We will be using the AMI05 technology again. After loading the library, click on the Setup Analysis icon in the palette.

In the Setup Analysis Dialog Box click on the Transient button. Enter time step as 1N and stop time as 0.3U. N stands for nanoseconds and U for microseconds.

You do not need to make any other changes. Click OK to the dialog box.

6.2 Simulation
In the schematic window select the input clock by clicking on it. You may need to resize the window or zoom in to be able to select it. Use the Add Force icon in the palette menu to force values to clock. In the Force Dialog Box chose Pulse as the Force Type. We are forcing voltage values and enter 0 for the initial value and 5 for the pulsed value. Units are in volts. Click specify width&period and change pulse width to 5N and period to 10N. You can also specify delay time, fall time and rise time in this dialog box. Accept the dialog box.

Now, force the following values to the other inputs. reset: delay = 50N ; pulse width = 5N ; period = 150N cnt_up: delay = 0 ; pulse width = 150N ; period = 300N enable: delay = 25N ; pulse width = 200N ; period = 225N The above values forced to the inputs do not cover the all possibilities. Since simulation of all possible inputs is a difficult task which may need other programs or long script files, I preferred to enter only few values which are enough to understand the basic operation of the simulator. After finishing the forcing procedure select all the inputs and outputs and press Trace button on the palette. Note that the order of selection of the signals is important. They will be displayed in the trace window in the order of selection, from bottom to up.

When the window named chart appears press Run on the palette menu. This will run the simulation for 0.3 microseconds. Note also that we had previously specified that stop time. The analysis results are shown below. The waveforms are Y3, Y2, Y1, Y0, Enable, Cnt_Up, Reset and Clock from top to bottom. We see from the results that our design is operating correctly. You can check whether the results satisfy the VHDL description. Notice that outputs have sharp transitions and there are no obvious delays between inputs and outputs.

You can save your setup for later use. Go to the File >Simulation>Save Setup Data Only menu. Save the setup inside the accusim folder we previously created with the name mycounter_setup. (any name can be given) Also save your waveform DB with File >Waveform DB >Save. Save the forces WDB into the accusim folder with the name forces.

Accusim is finished. Now, we are ready to create the layout of the design in Chapter 7.

Chapter 7 IC Station
7.1 Creating a cell 7.2 Placement and routing 7.3 Design rule checking (DRC) 7.4 LVS checking

7.1 Creating a cell

Invoke ICStation typing the command # adk_ic In the session palette click on create, to create a new layout; open option is used to view existing layouts. Fill the appeared dialog box as follows cell name : mycounter library, process: use the corresponding files inside $ADK/technology/ic/ami05 rules : ami05.rules in the above directory Click with connectivity and EDDM as source type Using the navigator choose the layout viewpoint inside mycounter. EDDM Schematic Viewpoit: $MGC_WD/mycounter/layout Also in logic loading options change logic loading type to "Flat". This is not important in our design, but in large hierarchical designs determining the correct type may be very important.

7.2 Placement and routing

When blank screen is loaded, click on Place & Route in the IC Palettes. This will bring you the Place & Route palette menu. In the Place & Route menu: Click Autofp and then just click OK to the appeared dialog box. IC Station automatically places the floorplan shapes. Now, you should see green lines on the screen. Next thing to do is to place the standard cells (the components used from the AMI library) onto the floorplan. Click StdCel menu item, under Autoplc. Accept the coming dialog box as is.

Now you should see all you standard cells placed, with yellow lines in between. The yellow lines denote the overflows; unconnected nets. The last step of placement is to place our ports. Click on Ports and then press OK in the dialog box, to let IC Station automatically place them. When placement is complete, the overflows should be routed; that is, the unconnected nets should be connected using metal connectors. There are two metal layers in IC Station, metal1 and metal2. You can pass from one layer to another using a via. Let's go back to our job. Click on All under Autorou. Accept the coming dialog box, as we always do. You should see metal paths instead of overflows now. IC Station tries to route all overflows, but sometimes it fails to route a few. You must find out if there is any. Note that you must search for unrouted overflows even if you don't see any; they may not be visible in large designs. Follow the procedure below. Open the Setup Select Filter dialog box from Setup>Select Filter and choose only overflow in the select filter. In the layout window firstly do "unselect all" and then "select all". If "nothing new selected" message appears in the Message Area, there are no overflows left. Otherwise, there are some. Find them and try to route with the OvrFlw command in the place&route palette. If it fails you have to route the overflows manually. After routing is completed open the Setup Select Filter dialog box again and fill the select filter. You can also decrease the area and via count of your chip by using Compct and MinVia commands under PR Edit.

The layout is shown below.

7.3 Design rule checking (DRC)

We have technology specific design rules, such as; metal or via widths, spacing between objects, etc. The design rules must be obeyed if you want a working IC. To see if our design passes DRC do the following Click on ICrules in the IC Palettes menu to go to ICrules palette. Click Check and then accept the appeared dialog box. DRC results are displayed in the Message Area. "Total Results" shows the number of errors. Click First under Set Scan To, the type of error is displayed in the Message Area. Use View to zoom to the error location and Next to see the next error. You must correct every error. Repeat this check until you see "Total Results" is zero.

7.4 LVS Checking

LVS (Layout Versus Schematic) checks the correspondence of the layout to the schematic. Click ICtrace(M) in the IC Palettes menu. In the ICtrace(M) menu click LVS. Specify source name as the lvs viewpoint inside mycounter.

Click on the Setup LVS button. In the Setup LVS form do the following changes and click OK. Ground Names : VSS GND Recognize Gates : Yes

After the check is completed, use Report >LVS to view the results. If there are no errors you should see a tick and a smiling face in the report file. Fix any errors before going to the next chapter.

Chapter 8 Parasitic Extraction and Backannotation

8.1 Parasitic extraction 8.2 Post layout simulation using Accusim Conclusion

8.1 Parasitic extraction

Go to the ICextract(M) palette menu. Since we will simulate the backannotated design in Accusim, "rules file" for Accusim should be loaded. Click Load Rules and specify the rules file as : $ADK/technology/ic/ami05.accusim.rules Click Lumped and fill the form as shown : write database: NO lumped resistance : YES set coupled cap threshold: NO update port properties : NO netlist : NO specify schematic source: YES source name : mycounter/layout source type: eddm lvs report name: lvs.rep backannotate: YES BA name: (leave empty) ASCII BA name: ascii_ba (any name) lumped cap: NO lumped res : NO coupling cap: YES name : cpl_cap_net remove root slash : NO

The form is shown above. Click OK to the form. After the BA file is created you can exit IC Station.

8.2 Post layout simulation using Accusim

Start Accusim without a viewpoint this time. # accusim mycounter Use File >Design >Import Back Annotation menu to import the ascii_ba file we created in IC Station. Specify Ascii BA File as ascii_ba and BA Name as mycounter/ba_vpt ba_vpt is a temporary viewpoint (if you don't save) we are about to create for the post layout simulation.

Click OK in the dialog box. When you see the message "Import/Export Back Annotation is done." you can start simulation. We can use the setup data and WDB we saved previously. Use File > Simulation > Restore Setup data to restore mycounter_setup we saved inside $MGC_WD/accusim/ Also use File >Waveform DB >Load to load our forces. Run the simulator. We can easily see that the post layout analysis results are different from the previous results. In Section 6.2 we saw sharp transitions in the outputs and there were no visible delay, but here we have smoother transitions like a capacitor, and large delays.

There is another thing much worse than delays; the chip is not operating correctly. Look at the Y3 output at time 190ns (just before the second reset comes). It is low, but it must be high, the output decreases from "1000" to "0011". Compare the results with the previous Accusim results. We have just seen the importance of post layout simulation. It would not be a nice thing to find out a fault after fabrication. Although finding a fault in simulations may be very annoying, you still have a chance to correct it.

CONCLUSION

This tutorial is a preliminary version which needs to be developed. Hence, it may contain mistakes. If you encounter any mistakes or if you have any comments about the tutorial, do not hesitate to contact me by e-mail. yildirim@mozart.ee.hacettepe.edu.tr