Acer Aspire La5651p

A
Compal Confidential
2
NAV70 Schematics Document

Intel Pineview Processor with Tigerpoint + DDRII
2010-04-29
3
l.c
om
REV: 2.0
Title
Date:
SCHEMATICS MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Document Number
xa
2007/8/18
Deciphered Date
Rev
401793
Friday, May 21, 2010
he
2006/08/18
f@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
ho
tm
ai
Sheet
of
32
Clock Generator
CK505
page 8
Compal Confidential
Model Name : NAV70
File Name : LA-5651P
CRT Conn
page 10
ZZZ
RGB
DA60000E420
LVDS
LCD Conn.
DDRII-SO-DIMM
page 7
1.8V DDRII 667
22x22mm
page 9
Thermal Sensor
Memory BUS(DDRII)
Pineview
FCBGA 559
PCB
page 4,5,6
EMC1402
page 5
DMI
X2 mode
GEN1
USB
HDA
Tigerpoint
PCI-Express
USB Port X2
PCBGA360
BlueTooth
17x17mm
page 15
SATA
page 11,12,13,14
MINI Card x1
3G
page 15
To I/O Board
WLAN
page 20
page 20
CMOS CAM
To I/O Board
10/100 Ethernet
page 9
HDD
AR8132L
3G
page 16
page 20
page 15
LPC BUS
USB Port x1
To I/O Board Conn.
Transfermer
3
Power ON/OFF
ALC272
RJ45
DC/DC Interface
page 20
Conn. to I/O Board

Aralia Codec
To I/O board
Card Reader
ENE6252
page 20
page 25
I/O Board
page 18
ENE KBC
KB926page
3VALW/5VALW
page 26
DC IN
page 23
BATT IN
0.89VP/1.5VP
0.9VSP/2.5VSP
CHARGER
1.8V/VCCP
page 20
SPI
17
AMP & INT

Speaker
page 28
page 24
Int.KBD
page 25
SPI ROM
page 19
HeadPhone &
MIC Jack
SD/MMC/MS
CONN
I/O Board
page19
page 27
page 17
Touch Pad
INT MIC
CPU_CORE
page 29
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
Size
B
Date:
SCHEMATICS MB A5651
Document Number
Rev
401793
Sheet

E
D
2
of
32
Voltage Rails
External PCI Devices

DEVICE
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
+VCCP
VCCP switched power rail
ON
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+0.89V
Graphic core power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
REQ/GNT #
PIRQ
No PCI Device
EC SM Bus1 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
IDSEL #
+VALW
+V
+VS
Full ON
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011X b
EMC1402
100_1100
Clock
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
ICH7M SM Bus address
BOARD ID Table(Page 17)

VCC
Ra
3.3V
100K
ID BRD ID
NAV60
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
Vab-Min
Vab-Typ
Vab-Max
0
8.2K
18K
33K
56K
100K
200K
NC
0V
0.216V
0.436V
0.712V
1.036V
1.453V
1.935V
2.500V
0V
0.250V
0.503V
0.819V
1.185V
1.650V
2.200V
3.3V
0V
0.289V
0.538V
0.875V
1.264V
1.759V
2.341V
3.3V
Address
Clock Generator
(SLG8SP556VTR)
1101 001Xb
DDR DIMMA
1010 000Xb
l.c
om
NAV50
0
1
2
3
4
5
6
7
Rb
Device
Title
Date:
SCHEMATICS MB A5651
in
Size
B
Document Number
xa
2007/8/18
Deciphered Date
Rev
401793
he
2006/08/18
f@
Compal Secret Data
Issued Date
ho
tm
ai
Sheet
of
32
(7) DDR_A_DQS#[0..7]
PINEVIEW_M
(7) DDR_A_D[0..63]
PINEVIEW_M
U71B
U71A
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1
F3
F2
H4
G3
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
N7
N6
EXP_CLKINN
EXP_CLKINP
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
G2
G1
H3
J2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
(7) DDR_A_DQS[0..7]
DMI_TX0 (13)
DMI_TX#0 (13)
DMI_TX1 (13)
DMI_TX#1 (13)
(7) DDR_A_MA[0..14]
DMI
DMI_RX0_R
DMI_RX#0_R
DMI_RX1_R
DMI_RX#1_R
(8) CLK_CPU_EXP#
(8) CLK_CPU_EXP
R10
R9
N10
N9
EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS
L10
L9
L8
RSVD_TP
RSVD_TP
N11
P11
EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD
K2
J1
M4
L3
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
R162
R203 49.9_0402_1%
750_0402_1%
T38
T39
(5)
(5)
(13)
DMI_RX#0
C435
C436
DMI_RX0_R
2
0.1U_0402_10V7K
DMI_RX#0_R
2
0.1U_0402_10V7K
DMI_RX1_R
2
0.1U_0402_10V7K
(13)
(13)
DMI_RX1
DMI_RX#1
C437
C438
(7) DDR_A_WE#
(7) DDR_A_CAS#
(7) DDR_A_RAS#
K3
L2
M2
N2
(7) DDR_A_BS0
(7) DDR_A_BS1
(7) DDR_A_BS2
XDP_PREQ#
XDP_PRDY#
XDP_BPM#3
XDP_BPM#2
XDP_BPM#3
XDP_BPM#2
(5)
(5)
XDP_BPM#1
XDP_BPM#0
XDP_BPM#1
XDP_BPM#0
R354 1
@
R347 1
@
CPU_ITP
CPU_ITP#
2 1K_0402_5%
2 1K_0402_5%
PLTRST# 1 R348
@
2 1K_0402_1%
(8)
(8)
+VCCP
(5,13,15,17,20) PLTRST#
(5)
(5)
(5)
(5)
Close to CPU
XDP_PREQ#
XDP_PRDY#
(5)
(5)
(5,13) H_PWRGD
(13)
SLPIOVR#
DMI_RX#1_R
2
0.1U_0402_10V7K
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
AK22
AJ22
AK21
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AJ20
AH20
AK11
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_CS#0
DDR_CS#1
AH22
AK25
AJ21
AJ25
DDR_A_CS#_0
DDR_A_CS#_1
DDR_A_CS#_2
DDR_A_CS#_3
DDR_CKE0
DDR_CKE1
AH10
AH9
AK10
AJ8
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
M_ODT0
M_ODT1
AK24
AH26
AH24
AK27
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
Must be placed within 500 mils from Pineview-M pins
(7) DDR_CS#0
(7) DDR_CS#1
JP16
DMI_RX0
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
(5)
XDP_TCK
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
(7) DDR_CKE0
(7) DDR_CKE1
(7) M_ODT0
(7) M_ODT1
(7)
(7)
(7)
(7)
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
ACES_87151-24051
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_CK_0
DDR_A_CK_0#
DDR_A_CK_1
DDR_A_CK_1#
AC15
AD15
AF13
AG13
DDR_A_CK_3
DDR_A_CK_3#
DDR_A_CK_4
DDR_A_CK_4#
AD17
AC17
AB15
AB17
RSVD
RSVD
RSVD
RSVD
AB4
AK8
RSVD
RSVD
R369
10K_0402_5%
+VCCP
R341 1
51 +-1% 0402
XDP_TMS
R342 1
51 +-1% 0402
XDP_TDO
R343 1
51 +-1% 0402
XDP_PREQ#
R344 1
51 +-1% 0402
+1.8V +1.8V
1
XDP_TDI
R370
10K_0402_5%
@ T40
AB11
AB13
T41
R50
1K_0402_1%
+5VS
AG15
AF15
AD13
AC13
+1.8V
XDP Reserve
FAN1 Conn
XDP_TRST#
R345 1
51 +-1% 0402
XDP_TCK
R346 1
51 +-1% 0402
R142
R243
R242 80.6_0402_1%
80.6_0402_1%
1K_0402_1%
RSVD_TP
RSVD_TP
AL28
AK28
AJ26
DDR_VREF
DDR_RPD
DDR_RPU
AK29
RSVD
Modify follow KAV60 schematic 06/12
DDR_A
Modify D38 D39 D40 Pin define

2
2 C314
D40
R256
10K_0402_5%
2
40mil
+VCC_FAN1
(17) FAN_SPEED1
1
C311
100P_0402_50V8J
JP12
1
2
3
1
2
3
G1
G2
4
5
ACES_85204-03001
CONN@
C1150
1000P_0402_50V7K
1
2
1
A
4.7U_0603_6.3V6K
C1151
+3VS
0.01U_0402_16V7K
PJDLC05C_SOT23-3
XDP_TRST#
XDP_TDI
PJDLC05C_SOT23-3
4.7U_0603_6.3V6K
C313 1
D39
APL5607KI-TRG_SO8
D38
3
8
7
6
5
EN_FAN1
GND
GND
GND
GND
(17)
+VCC_FAN1
1
2
R47
330_0402_5%
EN
VIN
VOUT
VSET
XDP_PREQ#
XDP_TDO
U12
1
2
3
4
08/13
XDP_TMS
XDP_TCK
D19@
DAN217_SC59
PJDLC05C_SOT23-3
2.2U_0603_10V6K
+5VS
C312
1
AD3
AD2
AD4
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_DQS_1
DDR_A_DQS#_1
DDR_A_DM_1
AB8
AD7
AA9
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_DQS_2
DDR_A_DQS#_2
DDR_A_DM_2
AD8
AD10
AE8
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_DQS_3
DDR_A_DQS#_3
DDR_A_DM_3
AK5
AK3
AJ3
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_DQS_4
DDR_A_DQS#_4
DDR_A_DM_4
AG22
AG21
AD19
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_DQS_5
DDR_A_DQS#_5
DDR_A_DM_5
AE26
AG27
AJ27
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_DQS_6
DDR_A_DQS#_6
DDR_A_DM_6
AE30
AF29
AF30
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_DQS_7
DDR_A_DQS#_7
DDR_A_DM_7
AB27
AA27
AB26
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
AA24
AB25
W24
W22
AB24
AB23
AA23
W27
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
2 OF 6
Add 2009-6-17
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
Date:
PINEVIEW-M_FCBGA8559
Size Document Number
Custom
5
DDR_A_DQS_0
DDR_A_DQS#_0
DDR_A_DM_0
1 OF 6
(13)
AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10
SCHEMATICS MB A5651
Rev
401793
Sheet

1
of
32
Add 470PF on H_SMI# for known issue 07/08

PINEVIEW_M
U71C
CRT_HSYNC
CRT_VSYNC
M30
M29
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
N31
P30
P29
N30
CRT_DDC_DATA
CRT_DDC_CLK
L31
L30
DAC_IREF
P28
Y30
Y29
AA30
AA31
REFCLKINP
REFCLKINN
REFSSCLKINP
REFSSCLKINN
K29
J30
L5
AA3
W8
W9
HPL_CLKINN
HPL_CLKINP
T22
T23
T24
T25
AA21
W21
T21
V21
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
PM_EXTTS#1
PM_EXTTS#0
H_PWROK
PLTRST#
LVDS_ACLK#
LVDS_ACLK
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
R151
2.37K_0402_1%
CPU_DREFCLK (8)
CPU_DREFCLK# (8)
CPU_SSCDREFCLK (8)
CPU_SSCDREFCLK# (8)
Add INVT_PWM
(9)
0_0402_5%
R200
GMCH_ENBKL
(17) GMCH_ENBKL
(9,17) INVT_PWM
0_0402_5%
R213
@
05/11
LVDS_SCL
(9)
LVDS_SDA
(9) GMCH_ENVDD
PM_DPRSLPVR (13)
U25
U26
R23
R24
N26
N27
R26
R27
LA_CLKN
LA_CLKP
LA_DATAN_0
LA_DATAP_0
LA_DATAN_1
LA_DATAP_1
LA_DATAN_2
LA_DATAP_2
R22
J28
N22
N23
L27
L26
L23
K25
K23
K24
H26
LIBG
LVBG
LVREFH
LVREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
2
470P_0402_50V7K
REV = 1.1
GMCH_CRT_R (10)
GMCH_CRT_G (10)
GMCH_CRT_B (10)
CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#
PINEVIEW_M
U71D
GMCH_CRT_DATA (10)
GMCH_CRT_CLK (10)
R201
665_0402_1%
PM_EXTTS#0 (7)
SMI#
A20M#
FERR#
LINT0
LINT1
IGNNE#
STPCLK#
E7
H7
H6
F10
F11
E5
F8
H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#
DPRSTP#
DPSLP#
INIT#
PRDY#
PREQ#
G6
G10
G8
E11
F15
H_DPRSTP#
H_DPSLP#
H_INIT#
XDP_PRDY#
XDP_PREQ#
THERMTRIP#
E13
H_THERMTRIP#
PROCHOT#
CPUPWRGOOD
C18
W1
H_PROCHOT#
H_PWRGD
GTLREF
VSS
A13
H27
H_GTLREF
RSVD
RSVD
L6
E17
BCLKN
BCLKP
H10
J10
BSEL_0
BSEL_1
BSEL_2
K5
H5
K6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
H30
H29
H28
G30
G29
F29
E29
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
RSVD
RSVD
RSVD
RSVD
L7
D20
H13
D18
RSVD_TP
RSVD_TP
EXTBGREF
K9
D19
K7
H_DPRSTP# (13)
H_DPSLP# (13)
H_INIT# (12)
XDP_PRDY# (4)
XDP_PREQ# (4)
H_THERMTRIP# (12)
H_PWRGD (4,13)
CLK_CPU_HPLCLK# (8)
CLK_CPU_HPLCLK (8)
Del R323 05/11
Modify 08/04
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
@
2
0_0402_5%
R306
1
2
0_0402_5%
H_PWROK
(4)
(4)
(4)
(4)
R305
VGATE
(8,13,17,29)
G11
E15
G13
F13
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
T48
T49
T50
T51
PCH_POK (13,17)
(4)
(4)
(4)
(4)
(4)
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS
XDP_TRST#
T55
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
Place closed to chipset

3 OF 6
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_ENBKL
R307
2
150_0402_1%
1 R308
2
150_0402_1%
1 R309
2
150_0402_1%
R34
100K_0402_5%
T58
XDP_TCK
T59
XDP_TDI
T60
XDP_TDO
T61
XDP_TMS
T62
XDP_TRST#
T63
H_PWRGD
BPM_1_0#
BPM_1_1#
BPM_1_2#
BPM_1_3#
B18
B20
C20
B21
BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD
G5
D14
D13
B14
C14
C16
RSVD
TDI
TDO
TCK
TMS
TRST#
D30
E30
THRMDA_1
THRMDC_1
C30
D31
CLK_CPU_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK# (8)
CLK_CPU_BCLK (8)
CPU_BSEL0 (8)
CPU_BSEL1 (8)
CPU_BSEL2 (8)
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
(29)
(29)
(29)
(29)
(29)
(29)
(29)
T26
T27
H_EXTBGREF
B
THRMDA_2/RSVD
THRMDC_2/RSVD
4 OF 6
+VCCP
+VCCP
H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil
THERM#
EC_SMB_DA2
ALERT#
GND
EC_SMB_DA2 (17)
R58 1
10K_0402_5%
+3VS
2006/08/18
Issued Date
Deciphered Date
2007/8/18
Date:
@ C940
Title
Size
B
EMC1402-1-ACZL-TR MSOP 8P SENSOR
Address:100_1100
1U_0603_10V6K
Compal Secret Data
l.c
om
SMDATA
placed within 0.5"

of processor pin.
placed within 0.5"

of processor pin.
ai
DN
tm
DP
EC_SMB_CK2 (17)
R156
3.3K_0402_1%
ho
EC_SMB_CK2
f@
H_THERMDA
H_THERMDC
2200P_0402_50V7K
SMCLK
Close to Processor
pin
R155
2K_0402_1%
SCHEMATICS MB A5651
Document Number
in
VDD
PM_EXTTS#0
Close to Processor
pin
Rev
xa
@ C939
U2
H_PROCHOT#
1U_0603_10V6K
C80
401793
he
H_GTLREF
R202
68_0402_5%
R143
10K_0402_5%
C79
H_EXTBGREF
CPU THERMAL SENSOR
0.1U_0402_16V4Z
R244
976_0402_1%
R144
1K_0402_1%
+VCCP
+3VS
+3VS
H_SMI# (12)
H_A20M# (12)
H_FERR# (12)
H_INTR (12)
H_NMI
(12)
H_IGNNE# (12)
H_STPCLK# (12)
PLTRST# (4,13,15,17,20)
CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK
MISC
AA7
AA6
R5
R6
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
(10)
(10)
RSVD
PM_EXTTS#_1/DPRSLPVR
PM_EXTTS#_0
PWROK
RSTIN#
T18
T19
T20
T21
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
ICH
R1378
REV = 1.1
CPU
L11
C1171
XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17
LVDS
T37
T2
T12
T3
T4
T13
T5
T6
T7
T14
VGA
2
T8
1K_0402_5% T15
T9
T16
T10
T17
T11
T28
D12
A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8
C10
D10
B11
B10
B12
C11
Sheet
1
of
32
U71F
+CPU_CORE
U71E
GFX supply current: 1.38A

Sustained GFX supply current: 1.05A
PINEVIEW_M
+0.89V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
CPU
T13
T14
T16
T18
T19
V13
V19
W14
W16
W18
W19
GFX/MCH
REV = 1.1
DDR supply current 2.27A

+1.8V
2.2U_0603_10V6K2.2U_0603_10V6K
2
C188 C187
AK13
AK19
AK9
AL11
AL16
AL21
AL25
C186
C85
1
1
1
1
2.2U_0603_10V6K 2.2U_0603_10V6K
+1.8V
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
AK7
AL7
+VCCP
VCCCK_DDR
VCCCK_DDR
1
C428
1U_0402_6.3V6K
1
C429
1
C430
2
22UF 6.3V M X5R 0805

1
C431
C1154
C1152
1U_0402_6.3V6K
22UF 6.3V M X5R 0805
1
C243
1U_0603_10V6K
4.7U_0603_6.3V6K
1
C236
2
AA10
AA11
Display PLL SFR and CRT DAC supply

current: 0.154A
AA19
+ C278
C1160
0.1U_0402_10V6K
Close U71.D4
+RING_EAST
2
0_0603_5%
VCCSENSE
VSSSENSE
+RING_WEST
2
0_0603_5%
D4
VCCP
VCCP
B4
B3
C241
1U_0603_10V6K
+VCC_DMI
1
1
1U_0603_10V6K
C68
C237
1U_0603_10V6K
2
2
VCCSENSE (29)
VSSSENSE (29)
+1.5VS
+VCCPProcessor
VCCP
C242
1U_0603_10V6K
R21
1
C29
B29
Y2
C1161
0.1U_0402_10V6K
R20
R28
1
2
0_0805_5%
VCCSENSE
VSSSENSE
VCCA
+VCCP
C64
1U_0603_10V6K
VCCACK_DDR
VCCACK_DDR
330U 2.5V Y
PLACE IN CAVITY
POWER
1
C55
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
C275
330U 2.5V Y
2
22UF 6.3V M X5R 0805
DDR
U10
U5
U6
U7
U8
U9
V2
V3
V4
W10
W11
C1153
1U_0402_6.3V6K
2 x 330uF(9mohm/2)
DDR analog supply current: 1.32A
22UF 6.3V M X5R 0805
C267
22UF 6.3V M X5R 0805
+CPU_CORE
1U_0402_6.3V6K
A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21
A11
A16
A19
A29
A3
A30
A4
AA13
AA14
AA16
AA18
AA2
AA22
AA25
AA26
AA29
AA8
AB19
AB21
AB28
AB29
AB30
AC10
AC11
AC19
AC2
AC21
AC28
AC30
AD26
AD5
AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10
AG3
AH18
AH23
AH28
AH4
AH6
AH8
AJ1
AJ16
AJ31
AK1
AK2
AK23
AK30
AK31
AL13
AL19
AL2
AL23
AL29
AL3
AL30
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19
1
Core
analog supply current: 0.08A
C391
2 0.01U_0402_16V7K
VCCD_AB_DPL
AC31
1
+VCC_CRT_DAC T30
VCCACRTDAC
+3VS
GIO supply current: 0.006A T31

+RING_EAST
+RING_WEST
J31
C3
B2
C2
A21
+VCCP
+1.8VS
VCCSFR_AB_DPL
VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI
VCCALVDS
VCCDLVDS
V30
W31
VCCA_DMI
VCCA_DMI
VCCA_DMI
T1
T2
T3
+VCC_ALVD
+VCC_DLVD
R25
+VCC_CRT_DAC
1
2
MBK1608601YZF_2P 1
LVDS supply current: 0.06A
LVDS
0_0603_5%
VCCD_HMPLL
DMI
C192
1U_0603_10V6K
R321
2
C189
1U_0603_10V6K
V11
EXP\CRT\PLL
+1.8VS
RSVD
VCCSFR_DMIHMPLL
VCCP
DAC, GIO, LVDS, & LGIO, DPLL, HMPLL

supply current: 0.33A
5 OF 6
P2
AA1
+VCC_DMI
DMI analog supply current: 0.48A
+DMI_HMPLL
+DMI_HMPLL
1 R18
2
0_0603_5%
T56
SFR & DMIHMPLL supply current: 0.104A
E2
R26
1
100NH +-5% LL1608-FSLR10J
+VCCP
1
C1162
C239
1U_0603_10V6K
2
2
1
C69
1U_0603_10V6K
2 H1.25 2
22UF 6.3V M X5R 0805
REV = 1.1
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4
VSS
T29
6 OF 6
+VCC_ALVD
1
C56
0.1U_0402_10V6K
+0.89V
PINEVIEW_M
GND
C1155
1U_0603_10V6K
Follow Intel check list change to 22uF 06/06
Modify to 2.2U
C77
C78
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C75
1U_0402_6.3V6K
C76
1U_0402_6.3V6K
C71
1U_0402_6.3V6K
C70
C81
2.2U_0603_10V6K
C74
R27
1
2
0_0603_5%
+VCC_DLVD
1
+CPU_CORE
VCCSENSE
VSSSENSE
Close Chipset pin

05/11
R32
C235
1U_0603_10V6K
2
100_0402_1%
R31
2
100_0402_1%
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
SCHEMATICS MB A5651
Custom
Date:
Rev
401793
Sheet

1
of
32
(4) DDR_A_DQS#[0..7]
+1.8V
(4) DDR_A_D[0..63]
(4) DDR_A_DM[0..7]
CONN@
C112
2.2U 6.3V M X5R 0402

2
+DIMM_VREF
R62
Share +DIMM_VREF for

1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1
1K_0402_1%
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
C107
0.1U_0402_16V4Z
C108
0.1U_0402_16V4Z
C105
0.1U_0402_16V4Z
C106
0.1U_0402_16V4Z
C94
220U_B2_2.5VM_R35
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D24
DDR_A_D25
DDR_A_DM3
2
DDR_A_D26
DDR_A_D27
(4)
DDR_CKE0
(4) DDR_A_BS2
DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
(4) DDR_A_BS0
(4) DDR_A_WE#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
(4) DDR_A_CAS#
(4)
DDR_CS#1
DDR_A_CAS#
DDR_CS#1
(4)
M_ODT1
M_ODT1
+0.9VS
DDR_A_D32
DDR_A_D33
C446
0.1U_0402_16V4Z
C445
0.1U_0402_16V4Z
C444
0.1U_0402_16V4Z
C443
0.1U_0402_16V4Z
C442
0.1U_0402_16V4Z
C441
0.1U_0402_16V4Z
C440
0.1U_0402_16V4Z
C439
0.1U_0402_16V4Z
C89
0.1U_0402_16V4Z
C118
0.1U_0402_16V4Z
C120
0.1U_0402_16V4Z
C90
0.1U_0402_16V4Z
C91
0.1U_0402_16V4Z
C115
0.1U_0402_16V4Z
C122
0.1U_0402_16V4Z
C88
0.1U_0402_16V4Z
C87
0.1U_0402_16V4Z
C121
0.1U_0402_16V4Z
C86
0.1U_0402_16V4Z
C117
0.1U_0402_16V4Z
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
2
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
+0.9VS
DDR_A_D50
DDR_A_D51
RP5
8
7
6
5
47_0804_8P4R_5%
RP2
1
8
2
7
3
6
4
5
8
7
6
5
1
2
3
4
DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
47_0804_8P4R_5%
RP4
DDR_A_MA6
8
1
DDR_A_MA7
7
2
DDR_A_MA11
6
3
DDR_A_MA14
5
4
47_0804_8P4R_5%
RP3
M_ODT1
1
8
DDR_CS#1
2
7
DDR_A_CAS# 3
6
DDR_A_WE# 4
5
47_0804_8P4R_5%
RP1
8
1 DDR_A_MA5
7
2 DDR_A_MA8
6
3 DDR_A_MA9
5
4 DDR_A_MA12
DDR_A_D56
DDR_A_D57
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
DDR_A_D58
DDR_A_D59
(8,15) CLK_SMBDATA
(8,15) CLK_SMBCLK
+3VS
C116
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
04/30
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 (4)
M_CLK_DDR#0 (4)
DDR_A_D14
DDR_A_D15
47_0804_8P4R_5%
C141
CLK_SMBDATA
CLK_SMBCLK
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
201
G1
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
G2
202
DDR_A_D20
DDR_A_D21
R64
DDR_A_DM2
2
0_0402_5%
PM_EXTTS#0 (5)
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1
DDR_CKE1 (4)
C
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS#0
DDR_A_BS1 (4)
DDR_A_RAS# (4)
DDR_CS#0 (4)
M_ODT0
DDR_A_MA13
M_ODT0 (4)
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
B
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 (4)
M_CLK_DDR#1 (4)
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R66
R65
1
1
2 10K_0402_5%
2 10K_0402_5%
Follow Intel Layout checklist, add C141 05/12

FOX_AS0A426-N4RN-7F
DIMMA
Compal Secret Data
2006/08/18
Issued Date
ho
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
2007/8/18
Deciphered Date
Title
Size
B
Date:
f@
DDR_CKE0
1 R163
2
47_0402_5%
1 R60
2
47_0402_5%
1 R59
2
47_0402_5%
SCHEMATICS MB A5651
Document Number
in
DDR_A_BS2
Rev
xa
DDR_CKE1
tm
ai
47_0804_8P4R_5%
DDR_A_DM7
0.1U_0402_16V4Z
1
2
3
4
0.1U_0402_16V4Z
RP6
DDR_A_MA13
M_ODT0
DDR_CS#0
DDR_A_RAS#
Change to SP07F001720
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
401793
he
C119
0.1U_0402_16V4Z
DDR_A_DQS#4
DDR_A_DQS4
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DDR_A_D18
DDR_A_D19
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
l.c
om
C130
2.2U_0603_6.3V4Z
C109
2.2U_0603_6.3V4Z
C110
2.2U_0603_6.3V4Z
C129
2.2U_0603_6.3V4Z
C128
2.2U_0603_6.3V4Z
+1.8V
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D8
DDR_A_D9
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
1K_0402_1%
2
(4) DDR_A_MA[0..14]
C111
0.1U_0402_16V4Z
2
R61
Layout Note:
Place near JDIM1
(4) DDR_A_DQS[0..7]
+1.8V
JDIM1
20mils
+DIMM_VREF
+1.8V
09/03
Sheet
of
32
Change C174 C175 to 10U_0603 05/14
FSB
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
266
PCI
MHz
100
REF
MHz
33.3
DOT_96 USB
MHz
MHz
14.318
96.0
1
2
R1370_0603_5%
+3VS
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
C174
C172
C1145
47P_0402_50V8J
10U_0603_6.3V6M 0.1U_0402_16V4Z
2
2
48.0
+3VS
C138
2 0.1U_0402_16V4Z
C148
R72
0.1U_0402_16V4Z
+1.05VM_CK505
166
100
33.3
14.318
96.0
48.0
1
C139
1
C1146
C175
47P_0402_50V8J
0.1U_0402_16V4Z
2
10U_0603_6.3V6M
2
333
100
33.3
14.318
96.0
48.0
100
100
33.3
14.318
96.0
48.0
400
100
33.3
14.318
96.0
48.0
(13) ICH_SMBDATA
C167
0.1U_0402_16V4Z
C137
0.1U_0402_16V4Z
C146
0.1U_0402_16V4Z
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
R138
1
2
0_0603_5%
+VCCP
R91
2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
Q10A
C165
+3VS
FSC
+3VM_CK505
0.1U_0402_16V4Z
(13) ICH_SMBCLK
Q10B
2N7002DW-T/R7_SOT363-6
SA000020N00 (Realtek : RTM875N-397-GRT )

SA000020H10 (ICS : ICS9LPRS387BKLFT)
Reserved
Change co-lay Low power clock GEN
+3VS
+3VS
R435
+1.5VS
10K_0402_5%
1
R1348
NORPW@
2
0_0603_5%
1
R1349
LOWPW@
+3VM_CK505
CLK_EN
47P_0402_50V8J
0.1U_0402_16V4Z
1
1
C140
C160
1
C1119
10U_0603_6.3V6M
2
0.1U_0402_16V4Z
2
2
DTC115EUA_SC70-3
+1.5VS
+VCCP
0.1U_0402_16V4Z
2
@
C386 10P_0402_50V8J
1
2
R68 @
1
2
R69
0_0402_5%
09/03 Modify
(13) CLK_PCH_14M
(5,13,17,29) VGATE
R1387
10K_0402_5%
2
1
@
+VCCP
U77
FSA
@
R113
470_0402_5%
1
2
R119
0_0402_5%
XIN/CLKIN
XOUT
FS
GND
VCC
SSEXTR
MR
MODOUT
(13)
PCS3P73Z21BWG-08-CR TDFN 8P
2
1
2
R84
0_0402_5%
(11) CLK_PCI_PCH
1
C389
470_0402_5%
DOT96 / DOT96# 60-3G@2

LCDCLK / LCDCLK#
SRC_0 / SRC_0#
27M/27M_SS
15P 50V J NPO 0402
(17) CLK_PCI_LPC
15P 50V J NPO 0402
1
CPU_BSEL2
R98
10K_0402_5%
2
1
R86
R80
2
33_0402_5%
2
33_0402_5%
CLK_CPU_DREFCLK
31
VDD_PLL3_IO
SRC_0#/DOT_96#
25
CLK_CPU_DREFCLK#
62
VDD_SRC_IO
52
VDD_SRC_IO
VDD_IO
38
VDD_SRC_IO
20
USB_0/FS_A
LCDCLK/27M
28
CPU_SSCDREFCLK
LCDCLK#/27M_SS
29
CPU_SSCDREFCLK#
SRC_2
32
SRC_2#
33
SRC_3
35
SRC_3#
36
CLK_CPU_HPLCLK#
CPU_DREFCLK
CPU_DREFCLK#
(5)
CPU_SSCDREFCLK
(5)
CPU_SSCDREFCLK#
SRC_4
39
CLK_PCIE_WLAN
SRC_4#
40
CLK_PCIE_WLAN#
SRC_6
57
CLK_PCIE_SATA
SRC_6#
56
CLK_PCIE_SATA#
SRC_7
61
CLK_PCIE_PCH
SRC_7#
60
CLK_PCIE_PCH#
SRC_8/CPU_ITP
64
CPU_ITP
SRC_8#/CPU_ITP#
63
CPU_ITP# (4)
NC
CPU_STOP#
PCI_STOP#
XTAL_IN
XTAL_OUT
PCI_1
SRC_9
44
CLK_CPU_EXP
14
PCI_2
SRC_9#
45
CLK_CPU_EXP#
15
PCI_3
SRC_10
50
CLK_PCIE_LAN
SRC_10#
51
CLK_PCIE_LAN#
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
VSS_REF
22
2
R71
10K_0402_5%
@
10K_0402_5%
@
10K_0402_5%
(5)
PCIE_WLAN
PCIE_SATA
PCIE_PCH
CPU_ITP
CLK_CPU_EXP
PCIE_LAN
PCIE_WWAN
CLK_PCIE_WLAN (20)
CLK_PCIE_WLAN# (20)
CLK_PCIE_SATA (12)
CLK_PCIE_SATA# (12)
CLK_PCIE_PCH (13)
CLK_PCIE_PCH# (13)
B
(4)
+3VS
SRC_11
48
CLK_PCIE_WWAN
SRC_11#
47
CLK_PCIE_WWAN#
CLKREQ_3#
37
CLK_CPU_EXP (4)
Add R107 05/04
CLK_CPU_EXP# (4)
WLAN_CLKREQ#
R121 2
1 10K_0402_5%
WWAN_CLKREQ#
R107 2
1 10K_0402_5%
CLK_PCIE_LAN (20)
CLK_PCIE_LAN# (20)
CLK_PCIE_WWAN
CLK_PCIE_WWAN#
REQ PORT LIST
(15)
(15)
PORT
VSS_48
26
VSS_IO
CLKREQ_4#
41
69
VSS_CPU
CLKREQ_6#
58
30
VSS_PLL3
CLKREQ_7#
65
34
VSS_SRC
CLKREQ_9#
43
59
VSS_SRC
SLKREQ_10#
49
42
VSS_SRC
CLKREQ_11#
46
73
VSS
USB_1/CLKREQ_A#
21
Add WWAN_CLKREQ#
WLAN_CLKREQ#
WLAN_CLKREQ# (20)
WWAN_CLKREQ#
WWAN_CLKREQ# (15)
05/04
DEVICE
REQ_3#
REQ_4# PCIE_WLAN
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11# PCIE_WWAN
REQ_A#
ICS9LPRS387BKLFT_QFN72_10X10
PCI4_SEL
13
ITP_EN
PCI2_TME
@
R77
10K_0402_5%
10K_0402_5%
10K_0402_5%
Issued Date
Compal Secret Data
R90
22P 50V J NPO 0402
CLK_XTAL_OUT
R89
2007/10/15
Deciphered Date
2008/10/15
Title
Size
Routing the trace at least 10mil
Date:
(5)
(5)
CPU_SSCDREFCLK
CKPWRGD/PD#
PCI4_SEL
60-3G@
R95
ITP_EN
14.318MHZ_16PF_7A14300083
C164
24
SRC1
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
CLK_CPU_HPLCLK (5)
22P 50V J NPO 0402

Y1
SRC_0/DOT_96
C388
R85
10/16
VDD_CPU_IO
06/05
CLK_XTAL_IN
C161
66
+3VS
+3VS
+3VS
Follow Vendor check change to 22P
CLK_CPU_HPLCLK#
VDD_PLL3
54
R87
Follow Intel check list change to 27P
67
DEVICE
PORT
CLK_CPU_BCLK# (5)
27
53
@
0_0402_5%
CPU_1#
CLK_CPU_BCLK (5)
VDD_48
11
For PCI2_TME:0=Overclocking of CPU and SRC allowed

(ICS only)
1=Overclocking of CPU and SRC NOT allowed
FSC
CPU_1
CLK_CPU_HPLCLK
REF_1
PCI2_TME
For EMI
:
:
:
:
CLK_CPU_BCLK#
68
CLK_XTAL_OUT
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25
Pin28/29
1 = Pin24/25
Pin28/29
70
+VCCP
R92 @
CPU_0#
CLK_PCH_48M
22_0402_5%
R110
@
0_0402_5%
CPU_0
VDD_CPU
REF_0/FS_C/TEST_
CLK_XTAL_IN
T57
1
R1384
VDD_PCI
23
SRC PORT LIST
CLK_SMBCLK (7,15)
19
FS_B/TEST_MODE
H_STP_PCI#
CLK_CPU_BCLK
CLK_SMBDATA (7,15)
72
CPU_BSEL1
R52 1K_0402_1%
FSB
1
2
CLK_SMBCLK
71
(13) H_STP_CPU#
CLK_SMBDATA
10
12
@
1 R1381 2
+3VS
5.1 +-5% 0402
C1157
SS_VDD
1
2@
0.1U_0402_16V7K
1
2
R1382 @ 1M +-5% 0402
SCL
VDD_REF
FSC
1
2
R371
0_0402_5%
SDA
VDD_SRC
FSB
CLK_EN
3G@
1K_0402_5%
@
0.1U_0402_16V4Z
FSA
1 R104
2
33_0402_5%
2
10P_0402_50V8J
1
C390
R73
Add 1K follow
Intel check list 05/11
CLK_48M_CR 1 R74
2
22_0402_5%
1 R75
2
22_0402_5%
T64
(13) CLK_PCH_48M
CPU_BSEL0
470_0402_5%
R76
2.2K_0402_5%
FSA 2
1
(5)
1
C169
R1350
0_0402_5%
+1.05VM_CK505
1
2
NORPW@
R1351
0_0402_5%
1
2
LOWPW@
1
C173
+VCCP
Rename 06/06
(5)
(29) CLK_ENABLE#
55
C1147
Q31
(5)
U4
+1.5VM_CK505
2
0_0603_5%
SCHEMATICS MB A5651
Document Number
Rev
401793
Sheet
1
of
32
LCD POWER CIRCUIT

J1
+LCDVDD
W=20mils
+3VS
R577
Q3
C1108
100K_0402_5%
1
Q4
R578
0.047U_0402_16V4Z
2
G
2N7002W-T/R7_SOT323-3
2
G
C1106 1
4.7U_0603_6.3V6K
1+LCDVDD_R
C1105 1
0.1U_0402_16V4Z
+CAM_VCC
C1107
4.7U_0603_6.3V6K
C1113
0.1U_0402_16V4Z
PJUSB208_SOT23-6
R579 4.7K_0402_5%
470_0402_5%
JUMP_43X39
@
W=20mils
+3VS
+3VS
NTR4101PT1G 1P SOT-23-3
+LCDVDD
USB20_N3_1
+CAM_VCC
CH3
Vp
CH4
CH2
Vn
CH1
Q5
DTC115EUA_SC70-3
USB20_P3_1
D6
@
(5) GMCH_ENVDD
05/14
Add D6
R174
100K_0402_5%
0_0402_5%
1
R1182
@
USB20_N3
USB20_N3 (13)
USB20_P3_1
USB20_P3
USB20_P3 (13)
+3VS
camera
+CAM_VCC
LVDS_ACLK
LVDS_ACLK#
LVDS_SCL (5)
LVDS_SDA
LVDS_SDA (5)
0_0402_5%
1
R1183
LVDS_A0
LVDS_A0#
LVDS_A0 (5)
LVDS_A0# (5)
LVDS_SDA
LVDS_SCL
BKOFF#
INVT_PWM
INVT_PWM
BKOFF#
C1156
220P_0402_50V7K
BKOFF# (17)
INVT_PWM (5,17)
2
C1109
1000P 50V K X7R 0402
For RF
+3VS
+LCDVDD
L2
FBMA-L11-201209-221LMA30T_0805
+LEDVDD
L1 2
2
(20 MIL)
1
B+
FBMA-L11-201209-221LMA30T_0805
1
C1111
330P_0402_50V7K
C1112
100P_0402_50V8J
l.c
om
LVDS_A1 (5)
LVDS_A1# (5)
LVDS_A2 (5)
LVDS_A2# (5)
LVDS_A1
LVDS_A1#
ACES_88341-3000B001
CONN@
LVDS_ACLK (5)
LVDS_ACLK# (5)
LVDS_A2
LVDS_A2#
+LCDVDD_L
WCM2012F2S-900T04_0805
Add for RF 07/02
LVDS_SCL
USB20_P3_1
USB20_N3_1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
JLVDS1
R1181
2.2K_0402_5%
R1180
2.2K_0402_5%
1
2
Modify JLVDS1 08/04
1
C1168
10P_0402_50V8J
@
10P_0402_50V8J
@
C1167
CMOS & LCD/PANEL BD. Conn.
L3
USB20_N3_1
Title
Date:
SCHEMATICS MB A5651
in
Size
B
Document Number
xa
2007/8/18
Deciphered Date
Rev
401793
he
2006/08/18
f@
Compal Secret Data
Issued Date
ho
tm
ai
Sheet
of
32
D18
Close to CRT CONN for ESD.
PJDLC05C_SOT23-3
D17
L15
1
(5) GMCH_CRT_R
L14
(5) GMCH_CRT_G
(5) GMCH_CRT_B
P
2
BK1608LL121-T_2P
2
BLUE
1
1
C307
10P_0402_50V8J
2
C306
10P_0402_50V8J
2
1
C304
10P_0402_50V8J
JVGA_HS
U11
CRT_HSYNC_1
5
1
GREEN
C303
2
RED
BK1608LL121-T_2P
2
JVGA_VS
R249
(5) GMCH_CRT_HSYNC
C308
2
BK1608LL121-T_2P
2
2
0.1U_0402_16V4Z
OE#
1
10P_0402_50V8J
+5VS
1
C301
1
10P_0402_50V8J
C310
10P_0402_50V8J
R250
150_0402_1%
2
1
R253
150_0402_1%
2
1
R255
150_0402_1%
2
1
L12
PJDLC05C_SOT23-3
0615
1
Modify C31- C308 C303 C307 C306 C304 BOM Structure
10_0402_5%
SN74AHCT1G125DCKR_SC70-5
+5VS
Change CRT_DET# From Page 13 to Page 10
CRT_VSYNC_1
OE#
R247
1
(5) GMCH_CRT_VSYNC
10_0402_5%
06/12
+3VS
U10
2
0.1U_0402_16V4Z
1
C298
Place closed to chipset
R149
10K_0402_5%
SN74AHCT1G125DCKR_SC70-5
CRT_DET#
+3VS
Q11
2N7002W-T/R7_SOT323-3
2
G
CRT PORT
06/08
CRT_DET
CRT_DET
(13)
Add R1283 R1284

Change R247 R249 to 10 ohm
Add @ on U10 U11 C301 C298
High: CRT Plugged
0.1U_0402_16V4Z
2.2K_0402_5%
R248
+3VS
D3
R245
2
R246
Change JCRT1 P/N to SP010906182 06/22
2
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RED
VGA_DDC_DAT
GREEN
VGA_DDC_DAT
JVGA_HS
BLUE
Q24B
2N7002DW-T/R7_SOT363-6
2.2K_0402_5%
2
5
4
C142
W=40mils
RB491D_SC59-3
R251
2.2K_0402_5%
(5) GMCH_CRT_DATA
2.2K_0402_5%
(5) GMCH_CRT_CLK
+CRT_VCC
+5VS
+CRT_VCC
VGA_DDC_CLK
JVGA_VS
Q24A
2N7002DW-T/R7_SOT363-6
VGA_DDC_CLK
CONN@
16
17
SUYIN_070546FR015M21RZR
CRT_DET#
R1103
100K_0402_5%
+CRT_VCC
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
Size
B
Date:
SCHEMATICS MB A5651
Document Number
Rev
401793
Sheet

E
D
10
of
32
+3VS
8.2K_0402_5%
R233
8.2K_0402_5%
R235
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
R236
R229
R207
R231
R230
R237
(8) CLK_PCI_PCH
CLK_PCI_PCH
1
C432
22P_0402_50V8J
2
C
PCI_DEVSEL#
CLK_PCI_PCH
PCI_IRDY#
R336
33_0402_5%
TGP
U72A
PCI_SERR#
PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#
A5
B15
J12
A23
B7
C22
B11
F14
A8
A10
D10
A16
PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#
A18
E16
GNT1#
GNT2#
G16
A20
REQ1#
REQ2#
G14
A2
C15
C9
GPIO48/STRAP1#
GPIO17/STRAP2#
GPIO22
GPIO1
B2
D7
B3
H10
E8
D6
H8
F8
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
D11
K9
M13
STRAP0#
RSVD01
RSVD02
For EMI, close to TigerPoint
8.2K_0402_5%
8.2K_0402_5%
R362
10K_0402_5%
@
R232
R209
10K_0402_5%
10K_0402_5%
R291
R292
R363
10K_0402_5%
@
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
R238
R205
R206
R208
R210
R211
R212
R204
8.2K_0402_5%
8.2K_0402_5%
R364
R365
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
H16
M15
C13
L16
TIGERPOINT_ES1_BGA360
SPI
PCI
LPC
l.c
om
Boot BIOS
ho
tm
ai
STRAP1#
GPIO48
B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1
R366
10K_0402_5%
@
STRAP2#
GPIO17
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Title
Size
Date:
SCHEMATICS MB A5651
Document Number
in
2007/8/18
Rev
xa
Deciphered Date
401793
he
2006/08/18
Issued Date
f@
Compal Secret Data
Sheet
1
11
of
32
TGP
R294 8.2K_0402_5%
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
AB16
AE24
AE23
RSVD24
RSVD25
RSVD26
AA14
V14
RSVD27
RSVD28
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9
SATA_CLKN
SATA_CLKP
AD4
AC4
SATARBIAS#
SATARBIAS
SATALED#
AD11
AC11
AD25
SATA_ITX_C_DRX_N0_R
SATA_ITX_C_DRX_P0_R
Del
SATA_DTX_C_IRX_N0 (16)
SATA_DTX_C_IRX_P0 (16)
0.01U_0402_16V7K
C32
0.01U_0402_16V7K
C31
SATA_ITX_C_DRX_N0 (16)
SATA_ITX_C_DRX_P0 (16)
SATA1 04/30
CLK_PCIE_SATA# (8)
CLK_PCIE_SATA (8)
Placed within 500 mils of Tiger point chipset pin.

+3VS
R45
SATARBIAS
R154 24.9_0402_1%
SATA_LED#
SATA_LED# (16)
SATA_LED#
10K_0402_5%
RSVD29
RSVD30
RSVD31
AD23
GPIO36
10K_0402_5%
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THRMTRIP#
U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20
GATEA20
H_A20M#
H_IGNNE#
H_INIT#
H_INTR
H_FERR#
H_NMI
KB_RST#
SERIRQ
H_SMI#
H_STPCLK#
R312
SERIRQ
GATEA20 (17)
H_A20M# (5)
10K_0402_5%
H_IGNNE# (5)
+VCCP
H_INIT# (5)
H_INTR (5)
H_FERR# (5)
H_NMI
(5)
KB_RST# (17)
SERIRQ (17)
H_SMI# (5)
H_STPCLK# (5)
AD16
AB11
AB10
R293
GATEA20
R164
56_0402_5%
56 ohm5% pull-up resistor has

to be within 1" from the Tiger
Point chipset.
+3VS
B
AC17
AB13
AC13
AB15
Y14
HOST
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
SATA
U72C
R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12
H_THERMTRIP# (5)
ESD request
C450 @
1
2 100P_0402_50V8J
H_IGNNE# C451 @
1
2 100P_0402_50V8J
H_INIT#
C452 @
1
2 100P_0402_50V8J
H_INTR
C453 @
1
2 100P_0402_50V8J
H_FERR#
C454 @
1
2 100P_0402_50V8J
H_NMI
C455 @
1
2 100P_0402_50V8J
C456 @
1
2 100P_0402_50V8J
H_STPCLK# C457 @
1
2 100P_0402_50V8J
H_A20M#
+VCCP
R198
56_0402_5%
H_SMI#
H_FERR#
Close to TigerPoint
pin
A
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
SCHEMATICS MB A5651
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
Rev
401793
Sheet

1
12
of
32
USB Port List

PCIE
1
2
LAN
WLAN
WWAN
3
4
TGP
U72B
BATLOW#
DPRSTP#
DPSLP#
RSVD31
+3VALW
R314
GPIO12
8.2K_0402_5%
R315
GPIO14
R316
GPIO15
R301
SMBALERT#
8.2K_0402_5%
8.2K_0402_5%
10K_0402_5% 2
10K_0402_5% 2
R37 1
R38 1
T_PWROK
EC_RSMRST#R
GPIO38
+3VS
EC_LID_OUT#
10K_0402_5% 2
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
2 R223
1
2
1
@ R222
0_0402_5%
100K_0402_5%
+3VALW
R300
R368
R302
EC_THERM#
GPIO0
R241
D37
2 R1184 @1 0_0402_5%
C230
1U_0603_10V4Z~D
1
2
+RTCVCC
3
R374
@ 2.2K_0402_5%
BAS40-04_SOT23-3
RTCRST#
1
C368
12P 50V J NPO 0402
2
1
RTCX1
NC
OUT
C371
12P 50V J NPO 0402
2
1
C1148
0.1U_0402_16V4Z
@
D28A
BAV99DW-7_SOT363
R375
@ 2.2K_0402_5%
Issued Date
RTCX2
Compal Secret Data
2006/08/18
2007/8/18
Deciphered Date
Title
SCHEMATICS MB A5651
Date:
EC_RSMRST#R
D28B
@
+CHGRTC
Routing the trace at least 10mil
Y3
32.768K_1TJS125BJ4A421P
2 NC
IN 1
@ MMBT3906_SOT23-3
1
2
+3VALW
R373
@ 4.7K_0402_5%
tm
Q30
3
(17) EC_RSMRST#
PM_CLKRUN#
R288
10M_0402_5%
2
1
+RTCVCC
modify 05/14
R372
0_0402_5%
2
BAV99DW-7_SOT363
1 R197
2 INTVRMEN
332K_0402_1%
1 R196
2
20K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
RSMRST circuit
R1370
1K_0402_5%
8.2K_0402_5%
R295
R46
R49
R48
+RTCBATT
R1377
10K_0402_5%
60@
MCH_SYNC#
GPIO7
GPIO39
USB_OC#0_1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
(17,23)
1M_0402_5%
R146
1
2 INTRUDER#
R42
ACIN
8.2K_0402_5%
+RTCVCC
D25 RB751V_SOD323
2
1 ACIN
ACIN_C
R1376
10K_0402_5%
50@
ICH_RI#
1
+3VALW
PCH_POK (5,17)
+3VS
R36
R311
2
0_0402_5%
(5,8,17,29)
ai
10K_0402_5% 2
8.2K_0402_5%
R39
VGATE
ho
R240
VGATE
f@
8.2K_0402_5%
DMI_CLKN
DMI_CLKP
1 2
2ICH_PCIE_WAKE#
1 SYS_RST#
W23
W24
R434
@ 22P_0402_50V8J
2
For EMI, Close to TigerPoint
PM_BATT_LOW#
R145
T_PWROK
DMI_ZCOMP
DMI_IRCOMP
R239
1K_0402_5% 1
10K_0402_5% 2
0_0402_5%
1 R310
2
@
H24
J22
SMLINK1
(8) CLK_PCIE_PCH#
(8) CLK_PCIE_PCH
H_DPRSTP# (5)
H_DPSLP# (5)
CLK_PCH_48M (8)
R153 24.9_0402_1%
1
2
SMLINK0
CLK_PCH_48M
+1.5VS
R43
F4
USBRBIAS R152
20 +-1% 0402
220P_0402_50V7K
SB_SPKR (20)
R44
10K_0402_5% 2
8.2K_0402_5%
CLK48
LINKALERT#
G2
G3
ICH_SMBDATA
PM_BATT_LOW#
H_DPRSTP#
H_DPSLP#
USBRBIAS
USBRBIAS#
USB_OC#0_1 (20)
USB_OC#2 (20)
R338
33_0402_5%
@
1 1
ICH_SMBCLK
R40
C1158
R148
PLTRST#
PLTRST# (4,5,15,17,20)
ICH_PCIE_WAKE# (15,20)
PM_SLP_S3# (17)
PM_SLP_S4# (17)
PM_SLP_S5# (17)
R147
B25
AB23
AA18
F20
(15)
(15)
PBTN_OUT# (17)
USB_OC#0_1
USB_OC#0_1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
2.2K_0402_5% 1
2.2K_0402_5% 1
10K_0402_5% 2
10K_0402_5% 2
H20
E25
F21
(20)
(20)
SYS_RST#
PLTRST#
ICH_PCIE_WAKE#
INTRUDER#
T_PWROK
EC_RSMRST#R
INTVRMEN
SB_SPKR
H_PWRGD (4,5)
EC_THERM# (17)
D4
C5
D3
D2
E5
E6
C2
C3
l.c
om
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_ARB
SPI
R2
T1
M8
P9
R4
SLP_S3#
SLP_S4#
SLP_S5#
EC_THERM#
VGATE
MCH_SYNC#
PBTN_OUT#
ICH_RI#
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
SMBALERT#/GPIO11
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
AB22
AB17
V16
AC18
E21
H23
G22
D22
G18
G23
C25
T8
U10
AC3
AD3
J16
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
(20)
(20)
(20)
(20)
(20)
(20)
(9)
(9)
(20)
(20)
(15)
(15)
(15)
(15)
(20)
(20)
E20
H18
E23
H21
F25
F24
(20)
(20)
GPIO38
GPIO39
H_PWRGD
K21
K22
C565 0.1U_0402_10V7K PCIE_ITX_C_DRX_N1_RJ23
C566 0.1U_0402_10V7K PCIE_ITX_C_DRX_P1_R J24
M18
M19
C53 0.1U_0402_10V7KPCIE_ITX_C_DRX_N2_RK24
C49 0.1U_0402_10V7K PCIE_ITX_C_DRX_P2_RK25
L23
L24
C52 0.1U_0402_10V7K PCIE_ITX_C_DRX_N3_RL22
C54
0.1U_0402_10V7K PCIE_ITX_C_DRX_P3_RM21
P17
P18
N25
N24
(20) PCIE_DTX_C_IRX_N1
(20) PCIE_DTX_C_IRX_P1
PCIE_ITX_C_DRX_N1
PCIE_ITX_C_DRX_P1
PCIE_ITX_C_DRX_N2
PCIE_ITX_C_DRX_P2
PCIE_ITX_C_DRX_N3
PCIE_ITX_C_DRX_P3
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
in
SMBALERT#
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
SMLINK0
SMLINK1
PM_CLKRUN#
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
xa
RTCX1
RTCX2
RTCRST#
H_STP_PCI# (8)
1 R367
2
1K_0402_5%
H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2
Rev
401793
he
W4
V5
T5
THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
RI#
SUS_STAT#/LPCPD#
SUSCLK
SYS_RESET#
PLTRST#
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR
SMB
(8) ICH_SMBCLK
(8) ICH_SMBDATA
RTCX1
RTCX2
RTCRST#
CPUPWRGD/GPIO49
MISC
For EMI, Close to TigerPoint
10K_0402_5%
PM_DPRSLPVR (5)
1
2
R1391
H_STP_CPU# (8)
0_0402_5%
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USB
LAN_CLK
LANR_RSTSYNC
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
C433
22P_0402_50V8J
R1390
EC_LID_OUT# (17)
1 0_0402_5%
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
T4
P7
B23
AA2
AD1
AC2
W3
T7
U4
EPROM
DMI_TX#0
DMI_TX0
DMI_RX#0
DMI_RX0
DMI_TX#1
DMI_TX1
DMI_RX#1
DMI_RX1
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK
U3
AE2
T6
V3
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
+3VS
CRT_DET (10)
SLPIOVR# (4)
EC_SMI# (17)
EC_SCI# (17)
HDA_BIT_CLK
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
HDA_SYNC
CLK14
GPIO0
CRT_DET
GPIO7
EC_SMI#
EC_SCI#
ACIN_C
GPIO12
EC_LID_OUT#
GPIO14
GPIO15
2 R17
PCI-E
P6
U2
W2
V2
P8
AA1
Y1
AA3
R159 2
R157 2
R337
33_0402_5%
@
C
1
1
2
2
T15
W16
W14
K18
H19
M17
A24
C23
P5
E24
AB20
Y16
AB19
R3
C24
D19
D20
F22
AC19
U14
AC1
AC23
AC24
R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23
DMI
33_0402_5%
33_0402_5%
R160
R158
RTC
(20) HDA_SDOUT_AUDIO
(20) HDA_SYNC_AUDIO
(8) CLK_PCH_14M
1
1
BMBUSY#/GPIO0
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39
AUDIO
33_0402_5%
33_0402_5%
(20) HDA_BITCLK_AUDIO
(20) HDA_RST_AUDIO#
(20) HDA_SDIN0
LDRQ1#/GPIO23
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LFRAME#/FWH4
LAN
(17) LPC_FRAME#
AA5
V6
AA6
Y5
W8
Y8
Y4
LPC
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
TGP
U72D
(17)
(17)
(17)
(17)
USB Left1
USB Left2
USB Right2
CMOS
CardReader
WWAN
BT
WIMAX
0
1
2
3
4
5
6
7
Port List
Sheet
1
13
of
32
TGP
U72E
D
F12
+V5REF_RUN
6mA
VCC5REF_SUS
F5
+V5REF_SUS
10mA
VCCSATAPLL
Y6
+SATAPLL
50mA
VCC5REF
U72F
F6
10mA
+VCCP
V_CPU_IO
W18
14mA
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
AA8
M9
M20
N22
1.3A
VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4
J10
K17
P15
V10
0.98A
H25
AD13
F10
G10
R10
T9
0.29A
F18
N4
K7
F1
0.13A
C42
+V5REF_RUN
C39
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
2
5
C461
10U_0805_10V4Z
C459
1U_0603_10V6K
1U_0603_10V6K
C61
C460
+1.5VS
+VCCP
10U_0805_10V4Z
1U_0603_10V6K
0.1U_0402_16V4Z
C45
1U_0603_10V6K
C63
C38
C60
1U_0603_10V6K
1U_0603_10V6K
C463
C40
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C48
2
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
+3VS
+3VALW
1U_0603_10V6K
1U_0603_10V6K
+V5REF_SUS
C37
10_0402_5%
0.1U_0402_16V4Z
R35
C44
D10
RB751V-40_SOD323-2
C43
C46
+3VALW
+RTCVCC
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
POWER
1U_0603_10V6K
1U_0603_10V6K
C41
2
0.1U_0402_16V4Z
C59
0.1U_0402_16V4Z
C47
VCCUSBPLL
+DMIPLL
0.01U_0402_16V7K
AE3
Y25
0.1U_0402_16V4Z
VCCRTC
VCCDMIPLL
C62
D12
RB751V-40_SOD323-2
C462
R33
100_0402_5%
+5VALW
TGP
+3VS
+5VS
B
VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25
VSS57
VSS58
VSS59
G24
AE13
F2
RSVD32
AE16
Place closely pin Y25 within 100mlis.

+1.5VS
R30
0_0805_5%
C58
10U_0805_10V4Z
0.01U_0402_16V7K
1
1
1
C28
+DMIPLL
C464
2
4.7U_0603_6.3V6K
Place closely pin Y6 within 100mlis.

+1.5VS
R29
+SATAPLL
0_0805_5%
C57
10U_0805_10V4Z
C27
0.1U_0402_16V4Z
Compal Secret Data
2009/04/15
Issued Date
Deciphered Date
2010/04/15
Title
SCHEMATICS MB A5651
Date:
Rev
401793
Sheet

1
D
14
of
32
1
C1165
C1164
06/23
1
C1166
4.7U_0603_6.3V6K
0.01U_0402_25V7K
C1163
0.1U_0402_16V4Z
Add C1163 C1164 C1165 C1166
+1.5VS
47P_0402_50V8J
+3VS
Add C850 06/12
Mini-Express Card for WWAN
0.1U_0402_16V4Z
2
10U_0805_10V4Z
1
C508
0.01U_0402_25V7K
R501
C850
47P_0402_50V8J
(17)
+3VS
@
1
R504
2
0_1206_5%
2
0_1206_5%
(8) WWAN_CLKREQ#
WWAN_CLKREQ#
(8) CLK_PCIE_WWAN#
(8) CLK_PCIE_WWAN
Change to PCIE_P3 05/13

(13) PCIE_ITX_C_DRX_N3
(13) PCIE_ITX_C_DRX_P3
10U_0805_10V4Z
1
2
C504
WWAN_WAKEUP_R#
+3VS_WWAN
D15
@ CM1293-04SO_SOT23-6
1 CH1
CH4 4
UIM_VPP
UIM_RST
Vn
CH2
Vp
CH3
UIM_DATA
EC_TX_P80_DATA_R
EC_TX_P80_CLK_R
+UIM_PWR
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
GND1
NC
2
4
6
8
10
12
14
16
Close to WWAN CONN
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
NC
54
56
JBT1
+1.5VS
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
(13)
(13)
WXMIT_OFF#
R506 1
2 0_0402_5%
R507 0_0402_5%
1
2 NON3G@
1
2 NON3G@
R508 0_0402_5%
USB20_N5 (13)
USB20_P5 (13)
(9~16mA)
1
R511
WWAN_LED# (16,20)
WLAN_LED# (16,20)
2
0_0402_5%
NON3G@
+3VALW
2
2
WWAN_WAKEUP_R#
2
0_0402_5%
C1115
56P_0402_50V8
@
1
R510
3G@
C513
0.1U_0402_16V4Z
C510
3G@
C1114
56P_0402_50V8
CONN@
1
C512
3G@
TAITW_PMPAT6-06GLBS7N14N0
3G@
+UIM_PWR
1U_0402_6.3V6K
(17) WWAN_WAKEUP#
C1116
8
9
3G@
56P_0402_50V8
GND
GND
5
6
CLK_SMBCLK (7,8)
CLK_SMBDATA (7,8)
+UIM_PWR
UIM_RST
UIM_CLK
22P_0402_50V8J
1
2
3
3G@
1
2
3 GND
4 GND
R509
10K_0402_5%
VCC
RST
CLK
C1117
56P_0402_50V8
R12
10K_0402_5%
2
1
1
C509
3G@ C1118
56P_0402_50V8
22P_0402_50V8J
UIM_DATA
GND
VPP
I/O
DET
22P_0402_50V8J
C511
4
5
6
7
UIM_VPP
USB20_P6
USB20_N6
WXMIT_OFF# (17)
PLTRST# (4,5,13,17,20)
JP3
3
USB20_P6
USB20_N6
1
2
3
4
ACES 88266-04001
CONN@
BELLW_80052-1021
CONN@
UIM_CLK
1
3
5
7
9
11
13
15
(13,20) ICH_PCIE_WAKE#
2
4
6
8
10
12
14
16
+3VS_BT
150U_B_6.3VM_R40M
1
3
5
7
9
11
13
15
0.1U_0402_16V4Z
C403
BT@
C502
3
1
1
R405
+3VS_WWAN
+3VALW
06/29
BT@
+3VS_BT
Q35
AO3413_SOT23-3
S
+3VS_WWAN
JMINI1
ICH_PCIE_WAKE#
BT MODULE CONN
10K_0402_5%
BT@
+3VS
BT_ON#
R4020_0402_5%
1
2 EC_TX_P80_DATA_R
1
2 EC_TX_P80_CLK_R
R403
0_0402_5%
Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T
C411 BT@
0.1U_0402_16V4Z
EC_TX_P80_DATA
EC_RX_P80_CLK
2
1
C506
2
(17) EC_TX_P80_DATA
(17) EC_RX_P80_CLK
0.1U_0402_16V4Z
1
C507
C505
+3VS_WWAN
l.c
om
Reserve for SIM card does not meet rise time

and pull-up is needed.
Title
Size
Date:
SCHEMATICS MB A5651
Document Number
in
2007/8/18
Rev
xa
Deciphered Date
401793
he
2006/08/05
f@
Compal Secret Data
Issued Date
ho
tm
ai
Sheet
15
of
32
ADD LED PCB CONN 06/12

Change JP18 to NEW P/N
LED PCB CONN
06/23
09/03 Change +5VALW , +5VS to +3VALW +3VS

JP18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+3VALW
(17) PWR_LED#
(17) PWR_SUSP_LED#
(17) BATT_GRN_LED#
(17) BATT_AMB_LED#
MEDIA_LED#
NUM_LED#
CAPS_LED#
BT_LED#
(17) NUM_LED#
(17) CAPS_LED#
(17,20) BT_LED#
+3VS
(15,20) WWAN_LED#
(15,20) WLAN_LED#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
GND
17
18
ACES_85201-1605N
CONN@
Y
A
MEDIA_LED#
SATA_LED#
SATA_LED#
(12)
U29
2 B
(20) CARD_LED#
2
+3VS
NC7SZ08P5X_NL_SC70-5
Add U29 5/14
SATA HDD Conn.

JHDD1
(12) SATA_ITX_C_DRX_P0
(12) SATA_ITX_C_DRX_N0
(12) SATA_DTX_C_IRX_N0
(12) SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
2 C380
0.01U_0402_16V7K
SATA_DTX_IRX_P0
2
C383
0.01U_0402_16V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
+5VS
+5VS
0.1U_0402_16V4Z
1
C423
C422
1U_0402_6.3V6K
2
C426
1
2
3
4
5
6
7
C419
10U_0603_6.3V6M
1000P_0402_50V7K
4
GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
4
SUYIN_127043FR022G263ZR_NR
CONN@
Issued Date
Compal Secret Data
2006/08/18
2007/8/18
Deciphered Date
Title
Size
B
SCHEMATICS MB A5651
Document Number
Date:
Rev
401793
G
Sheet
D
16
H
of
32
+3VALW
+EC_AVCC
C523
0.1U_0402_16V4Z
PLTRST#
(8) CLK_PCI_LPC
(4,5,13,15,20) PLTRST#
(13)
EC_RST#
EC_SCI#
EC_SCI#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
C1159
220P_0402_50V7K
KSO[0..15]
(19)
KSO[0..15]
KSI[0..7]
For ESD
(19)
KSO1
WLAN_OFF#
WXMIT_OFF#
KSI1
KSI[0..7]
KSI5
GPIO15
High
High
Low
(24)
(24)
(5)
(5)
KSO1
KSI1
WL_BTN#
KSI5
3G_BTN#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
(13) PM_SLP_S3#
(13) PM_SLP_S5#
(13) EC_SMI#
Change INVT_PWM from Pin21 to Pin25 06/24

(5,9)
INVT_PWM
0_0402_5% R67
INVT_PWM2
1
FAN_SPEED1
(4) FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
(15) EC_TX_P80_DATA
(15) EC_RX_P80_CLK
(18)
ON/OFF#
(16) PWR_SUSP_LED#
(16) NUM_LED#
PWR_SUSP_LED#
NUM_LED#
XCLKI
XCLKO
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
AVCC
PWR_PWM_LED#
BEEP#
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
BATT_TEMP
BATT_OVP
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
EN_FAN1
IREF
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
USB_ON#
@ 1
C1177
TP_CLK
TP_DATA
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
LID_SW#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
PS2 Interface
SPI Flash ROM
GPIO
GND
GND
GND
GND
GND
GPI
BRD_ID
1
0_0402_5%
2
R1389
+0.89V_PG
1
IN
OUT
22P 50V J NPO 0402
VCC
Ra
2
470P_0402_50V7K
22P 50V J NPO 0402
0
1
2
3
4
5
6
7
NAV50
BT_LED# (16,20)
TP_CLK (19)
TP_DATA (19)
1
R1293
LID_SW#
(18)
NAV60
+3VALW
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
0_0402_5% R1309
Add 0 ohm R1309 06/08
1
2
EC_RSMRST# (13)
EC_LID_OUT#
EC_LID_OUT# (13)
EC_ON
RB751V-40TE17_SOD323-2
EC_ON
(18)
D29 @
ICH_POK_EC
1
2 PCH_POK
NC
NC
3
Vab-Typ
Vab-Max
0V
0.216V
0.436V
0.712V
1.036V
1.453V
1.935V
2.500V
0V
0.250V
0.503V
0.819V
1.185V
1.650V
2.200V
3.3V
0V
0.289V
0.538V
0.875V
1.264V
1.759V
2.341V
3.3V
BKOFF# (9)
R1295
1
2
WL_OFF# (20)
WXMIT_OFF# (15) 0_0402_5%
BT_ON# (15)
Del R1294 06/08

PCH_POK (5,13)
1
2
+3VS
R1296 10K_0402_5%
@
PCH_POK
PM_SLP_S4# (13)
GMCH_ENBKL (5)
EAPD
(20)
EC_THERM# (13)
SUSP#
(22,25,27,28)
PBTN_OUT# (13)
LAN_WAKE# (20)
EC_THERM#
SUSP#
PBTN_OUT#
1 R320
20mil 1
@
2
C1178
+3VALW
32.768K_1TJS125BJ4A421P
VGATE
(5,8,13,29)
+3VALW
U75
SPI_CS#
1
3
7
4
+3VALW
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
SPI_CLK_R
SPI_SI
SPI_SO
MX25L512AMC-12G_SO8
@
+3VALW
8M SPI ROM
0.1U_0402_16V4Z
EC_TX_P80_DATA
EC_RX_P80_CLK
RB751V-40TE17_SOD323-2
+3VALW
100K_0402_5%
@
D30
20mils
U76
JP25
2
4.7K_0402_5%
2
4.7K_0402_5%
Vab-Min
0
8.2K
18K
33K
56K
100K
200K
NC
WWAN_WAKEUP# (15)
+5VS
1
R1301
TP_DATA
1
R1303
Rb
FSTCHG (25)
BATT_GRN_LED# (16)
CAPS_LED# (16)
BATT_AMB_LED# (16)
PWR_LED# (16)
SYSON
(22,27)
VR_ON
(29)
ACIN
(13,23)
BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED#
SYSON
EC DEBUG PORT
TP_CLK
Rb
3.3V
100K
ID BRD ID
EC_MUTE# (20)
USB_ON# (20)
C526
X1
R1292
33K +-5% 0402
BOARD ID Table
(28)
EN_FAN1 (4)
IREF
(25)
CALIBRATE# (25)
2
47K_0402_5%
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
C524
ECAGND
11
24
35
94
113
BATT_TEMP (24)
BATT_OVP (25)
ADP_I
(25)
C525
C527
BRD_ID
(25)
Change BT_ON# from Pin98 to Pin108 06/24
XCLK1
XCLK0
KB926QFD3_LQFP128_14X14
ACOFF
50@
SPI Device Interface
SM Bus
PWR_PWM_LED# (18)
BEEP#
(20)
ACOFF
PWM Output
AD
21
23
26
27
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
+3VALW
1
R1297
1
R1298
1
R1299
1
R1300
R1291
100K_0402_5%
60@
12
13
37
20
38
Ra
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
122
123
EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
67
9
22
33
96
111
125
1
2
3
4
5
7
8
10
+3VALW
U6
1
2
3
4
1
2
3
4
ACES_85205-0400
CONN@
FSEL#SPICS# 2
R1302
SPI_CLK
2
R1304
FWR#SPI_SI 2
R1305
SPI_CS#
22_0402_5%
SPI_CLK_R
1
22_0402_5%
SPI_SI
1
22_0402_5%
1
VCC
HOLD
VSS
SPI_SO
2
R1306
FRD#SPI_SO
22_0402_5%
l.c
om
2
1
R1289 @ 10_0402_5%
@ 22P_0402_50V8J
1
2
+3VALW
R1290
47K_0402_5%
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
R1292
470P_0402_50V7K
(12)
SERIRQ
(13) LPC_FRAME#
(13)
LPC_AD3
(13)
LPC_AD2
(13)
LPC_AD1
(13)
LPC_AD0
4.7U_0603_6.3V6K
GATEA20
KB_RST#
C522
2
1
Swap to WLAN
10K_0402_5%
1
(12)
WXMIT_OFF#
AGND
+3VS
(12)
Change R1292 to 0 ohm for BRD ID R01 (EVT) 06/24
69
R41
C519
1000P_0402_50V7K
05/14
C518
@
1000P_0402_50V7K
C521
1000P_0402_50V7K
Change to R_0402
C517
0.1U_0402_16V4Z
C520
0.1U_0402_16V4Z
1 ECAGND
2
1
R1288
0_0402_5%
+EC_AVCC
C516
0.1U_0402_16V4Z
C515
0.1U_0402_16V4Z
C514
0.1U_0402_16V4Z
+3VALW
1
2
MBK1608121YZF_0603
VCC
VCC
VCC
VCC
VCC
VCC
L16
EN25F80-75HCP SOIC 8P
+3VS
ACIN
C531 1
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
C528
2
SPI_CLK_R
10P_0402_50V8J
Compal Secret Data
Issued Date
2006/08/04
Deciphered Date
ai
C530 1
tm
C529 1
BATT_TEMP
ho
BATT_OVP
2007/8/18
Title
f@
EC_SMB_CK2
2.2K_0402_5%
EC_SMB_DA2
2.2K_0402_5%
SCHEMATICS MB A5651
Date:
in
401793
Rev
xa
he
1
R1307
1
R1308
Sheet
D
17
of
32
Add For NAV50 07/06

09/03 Change +5VS to +3VS
ON/OFF Button
+3VS
3
SW1
50@
4
(BLUE)
1
ON/OFFBTN#
51 +-5% 0402
R1388
EVQPLMA15 SPST PANASONIC H1.5
50@
TOP Side
LED1
HT-191NB5-DT BLUE 0603
FOR EMI
50@
+3VALW
@
R186 2
1
0_0805_5%
C1169 1
2 @ 100P_0402_50V8J
ON/OFFBTN#
C1170 1
2 @ 100P_0402_50V8J
@
R194 2
1
0_0805_5%
10mil
R1347
100K_0402_5%
Bottom Side
PWR_PWM_LED#
PWR_PWM_LED#
D14
ON/OFF#
ON/OFFBTN#
51ON#
ON/OFF#
(17)
51ON#
(23)
DAN202U_SC70
1
PWR_PWM_LED#
C4
D1 @
1000P_0402_50V7K
1
RLZ20A_LL34
2
D42
ON/OFFBTN#
PJSOT24C_3P_C/A_SOT-23
1
EC_ON
EC_ON
Q1
2N7002W-T/R7_SOT323-3
<BOM Structure>
2
G
(17)
50@
R3
10K_0402_5%
LID Switch
PWR/B Conn
+3VALW
VDD
+3VS
C155
0.1U_0402_16V4Z
OUTPUT
LID_SW# (17)
1
C150
U5
ACES_85201-0405N
APX9132ATI-TRL SOT-23 3P
10P_0402_50V8J
1
2
3
4
G1
G2
(17) PWR_PWM_LED#
1
2
3
4
5
6
GND
JP23
ON/OFFBTN#
PWR_PWM_LED#
CONN@
Update PW/B Conn 0623
Issued Date
Compal Secret Data
2006/08/18
Deciphered Date
2007/8/18
Title
Size
B
Date:
SCHEMATICS MB A5651
Document Number
Rev
401793
Sheet
18
of
32
To TP/B Conn.
D
KSI[0..7]
KSI[0..7]
KSI1
C135 1
KSI2
JKB1
100P_0402_50V8J
KSO4
C104 1
100P_0402_50V8J
100P_0402_50V8J
KSO5
C103 1
100P_0402_50V8J
C134 1
100P_0402_50V8J
KSO6
C102 1
100P_0402_50V8J
KSI3
C133 1
100P_0402_50V8J
KSO7
C101 1
100P_0402_50V8J
KSI4
C132 1
100P_0402_50V8J
KSO8
C100 1
100P_0402_50V8J
KSI5
C131 1
100P_0402_50V8J
KSO9
C99
100P_0402_50V8J
KSI6
C127 1
100P_0402_50V8J
KSO10
C98
100P_0402_50V8J
KSI7
C126 1
100P_0402_50V8J
KSO11
C97
100P_0402_50V8J
KSO0
C125 1
100P_0402_50V8J
KSO12
C96
100P_0402_50V8J
KSO1
C124 1
100P_0402_50V8J
KSO13
C95
100P_0402_50V8J
KSO2
C114 1
100P_0402_50V8J
KSO14
C93
100P_0402_50V8J
KSO3
C113 1
100P_0402_50V8J
KSO15
C92
100P_0402_50V8J
(17)
(17)
G2
G1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TP_CLK
TP_DATA
TP_CLK
TP_DATA
KSI0
KSI1
KSI2
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14
KSO15
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSO[0..15] (17)
1
2
3
4
5
6
GND
GND
8
7
ACES_85201-0605N
D22
CONN@
PJDLC05C_SOT23-3
C136 1
1
2
3
4
5
6
+5VS
KSO[0..15]
KSI0
INT_KBD Conn.
(17)
JP11
Chage JP11 Pin define & Add D22
05/14
C
Update TP/B Conn 05/04
ACES_85202-24051
CONN@
l.c
om
ho
tm
ai
Title
Size
B
Date:
SCHEMATICS MB A5651
Document Number
in
2007/8/18
Rev
xa
Deciphered Date
401793
he
2006/08/18
Issued Date
f@
Compal Secret Data
Sheet
1
19
of
32
09/03 Change Pin 18, 23 to +1.5VS change Pin7 , 9 to USB20_P7 N7
I/O Board Conn.

(17)
C1021 1
1U_0402_6.3V4Z
BEEP#
R1326
MONO_IN_R
560_0402_5%
JP2
R1327
560_0402_5%
+5VALW
1
SB_SPKR
(13)
C1022 1
1U_0402_6.3V4Z
D36 @
RB751V-40TE17_SOD323-2
(8) CLK_PCIE_WLAN
(8) CLK_PCIE_WLAN#
+1.5VS
R1328
10K_0402_5%
(17) EC_MUTE#
(17)
EAPD
(16,17) BT_LED#
MONO_IN_R
(17) LAN_WAKE#
(17) WL_OFF#
(13,15) ICH_PCIE_WAKE#
(8) WLAN_CLKREQ#
(15,16) WLAN_LED#
(13) HDA_BITCLK_AUDIO
(13) HDA_SDOUT_AUDIO
(13) HDA_SDIN0
(13) HDA_RST_AUDIO#
(13) HDA_SYNC_AUDIO
(8) CLK_PCIE_LAN
(8) CLK_PCIE_LAN#
+3VS
+5VALW
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
+5VS
USB20_P7
USB20_N7
USB20_P7 (13)
USB20_N7 (13)
+3VALW
USB_ON# (17)
USB_OC#2 (13)
PLTRST# (4,5,13,15,17)
WWAN_LED# (15,16)
+1.5VS
CARD_LED# (16)
PCIE_DTX_C_IRX_P2 (13)
PCIE_DTX_C_IRX_N2 (13)
PCIE_ITX_C_DRX_N2 (13)
PCIE_ITX_C_DRX_P2 (13)
PCIE_DTX_C_IRX_N1 (13)
PCIE_DTX_C_IRX_P1 (13)
PCIE_ITX_C_DRX_N1 (13)
PCIE_ITX_C_DRX_P1 (13)
USB20_N4
USB20_P4
USB20_N4 (13)
USB20_P4 (13)
USB20_P2
USB20_N2
USB20_P2 (13)
USB20_N2 (13)
LOTES_YEA-BTB-006-260K12
+USB_VCCC
U13
C244
0.1U_0402_16V4Z
2
1
R224
100K_0402_5%
1
2
3
4
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_OC#0_1 (13)
APL3510BKI-TRG SOP 8P PWR SWITCH
USB_ON#
USB_ON#
1
(17)
C245
@ 1000P_0402_50V7K
2
3
Change JUSB1 JUSB2 to NEW P/N SP010906181
06/23
USB CONN.1
+USB_VCCC
+USB_VCCC
W=40mils
+USB_VCCC
1
C315
USB CONN.2
C316
C317
2
150U 6.3V M B LESR45M T520 H1.9

2
W=40mils
+USB_VCCC
1
C318
470P_0402_50V7K
150U 6.3V M B LESR45M T520 H1.9

2
470P_0402_50V7K
JUSB1
5
6
7
8
GND1
GND2
GND3
GND4
JUSB2
(13) USB20_N1
(13) USB20_P1
2
VCC
DD+
GND
1
2
3
4
1
2
3
4
VCC
DD+
GND
5
6
7
8
GND1
GND2
GND3
GND4
(13) USB20_N0
(13) USB20_P0
D21
D23
SUYIN_020133GB004M25MZL
SUYIN_020133GB004M25MZL
CONN@
PJDLC05C_SOT23-3
CONN@
1
PJDLC05C_SOT23-3
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
Size
B
Date:
SCHEMATICS MB A5651
Document Number
Rev
401793
Sheet

E
20
of
32
Modify Hole location by (ME Drawing 06/12) 0615

H8
H
H20
H
H16
H
H_2P6
H9
H
H7
H
H1
H
@
1
H_3P2X3P7N
H17
H
@
1
09/03 Del H12

FM4
FM3
@
FM1
@
FIDUCIAL_C40M80
FM2
@
@
1
H_3P2
H21
H
H19
H
H18
H
H3
H
H_3P2
1
l.c
om
H11
H
H_3P2N
tm
ai
ho
Title
Size
B
Date:
f@
2007/8/18
SCHEMATICS MB A5651
in
Deciphered Date
Document Number
xa
2006/08/18
Rev
401793
Sheet
he
Issued Date
Compal Secret Data
21
of
32
Change R51 R57 R70 R63 R317 R114 R190 to 0402 SIZE 04/30
Change C221 C218 C223 C 191 C201 C170 C392 C393 C394 to 0603 SIZE 04/30
+5VALW TO +5VS
+3VALW TO +3VS
470_0402_5%
2
1U_0603_10V4Z
C191
R190
C201
1
2
3
10U_0603_6.3V6M 10U_0603_6.3V6M
2
2
C170
C176
10U_0603_6.3V6M
2
470_0402_5%
R114
1U_0603_10V4Z
2
3 1
C219
Q15
C223
10U_0603_6.3V6M
2
Q17B
2N7002DW-T/R7_SOT363-6
C208
SUSP
+VSB
Q12B
2N7002DW-T/R7_SOT363-6
R139
2
33K +-5% 0402
SUSP
5VS_GATE
SI4800BDY-T1-E3_SO8
8
7
6
5
2
1
2
10U_0603_6.3V6M
1
R187
22K +-5% 0402
+3VS
10U_0603_6.3V6M
2
+VSB
C218
Q19
1
2
3
+3VALW
SI4800BDY-T1-E3_SO8
8
7
6
5
C221
+5VS
+5VALW
C179
Q17A
0.1U 25V K X5R 0402

2
2N7002DW-T/R7_SOT363-6
Q12A
SUSP
0.1U 25V K X5R 0402

2
2N7002DW-T/R7_SOT363-6
2
1
SUSP
+5VALW
R141
100K_0402_5%
2
+1.8V to +1.8VS
+1.8V
+1.8VS
SYSON#
ADD +5VS +VCCP +0.89V Cap for EMI

R317
Q14A
(17,27)
SUSP
Q28A
C396
0.1U 25V K X5R 0402
2N7002DW-T/R7_SOT363-6
C1173
C1174
C1175
C1172
@
2
0.01U_0402_25V7K
2N7002DW-T/R7_SOT363-6
+1.8V
0.01U_0402_25V7K
+1.8V
0.01U_0402_25V7K
5
4
R318
200K +-1% 0402
+0.89V
SYSON
SYSON
+VCCP
0.01U_0402_25V7K
Q28B
2N7002DW-T/R7_SOT363-6
1.8VS_GATE
SUSP
470_0402_5%
C1176
+0.9VS
0.01U_0402_25V7K
C395
10U_0603_6.3V6M
2
C394
1
2
3
+5VS
+VSB
Q27
1U_0603_10V4Z
C393
10U_0603_6.3V6M
1
10U_0603_6.3V6M
C392
SI4800BDY-T1-E3_SO8
8
7
6
5
RTCVREF
VL
+VCCP
+0.9VS
+1.8V
SUSP
470_0402_5%
470_0402_5%
R57
R70
R63
Q14B
5
(17,25,27,28) SUSP#
2N7002DW-T/R7_SOT363-6
Q8A
2N7002DW-T/R7_SOT363-6
5 SUSP
2N7002DW-T/R7_SOT363-6
SUSP
4
2
@
3
Q8B
SUSP
Q6A
5
Q6B
2N7002DW-T/R7_SOT363-6
470_0402_5%
R51
1
470_0402_5%
SUSP
(28)
+1.5VS
R173
100K_0402_5%
R172
100K_0402_5%
@
SYSON#
2N7002DW-T/R7_SOT363-6
2006/08/18
Issued Date
Compal Secret Data
2007/8/18
Deciphered Date
Title
Size
B
Date:
SCHEMATICS MB A5651
Document Number
Rev
401793
Sheet

E
22
of
32
PR1
1M_0402_1%
1
2
VIN
VIN
VIN
PR6
22K_0402_5%
1
2
PC1
1000P_0402_50V7K
PR7
20K_0402_1%
PC2
.1U_0402_16V7K
LM358DT_SO8
PD1
RLZ4.3B_LL34
PR8
10K_0402_5%
PC6
1000P_0402_50V7K
1
1
PC5
100P_0402_50V8J
PC4
100P_0402_50V8J
1
PC3
1000P_0402_50V7K
4
3
2
1
GND 4
GND 3
2
1
6
5
PACIN
PR5
10K_0402_5% PU1A
2
1 1 0
(13,17) ACIN
PR3
84.5K_0402_1%
PR4
0_0402_5%
1
2
SP02000GC00
PJP1
@PR2
@
PR2
10K_0402_5%
PL1
HCB2012KF-121T50_0805
1
2
DC_IN_S1
VS
ACES 88266-04001
CONN@
PR9
10K_0402_5%
1
2
(27)
RTCVREF
PACIN
Vin Dectector
PBJ1
2
Min.
H-->L 16.976V
L-->H 17.430V
+RTCBATT
+RTCBATT
Typ
17.525V
17.901V
Max.
17.728V
18.384V
ML1220T13RE
45@
PJ2
JUMP_43X118
PD2
RLS4148_LL34-2
(18) 51ON#
VS
1
PC14
0.1U_0402_25V6
JUMP_43X118
+VCCP
1
PR15
200_0603_5%
PC19
1U_0603_25V6K
2008/09/20
Title
in
Deciphered Date
Custom
Date:
SCHEMATICS MB A5651
xa
2007/09/20
Rev
he
Issued Date
Compal Secret Data
f@
ho
tm
IN
ai
2
1
OUT
N2
GND
G920AT24U_SOT89-3
PC18
1
10U_0603_6.3V6M
+0.89V
l.c
om
PU2
3.3V
1
PR17
560_0603_5%
1
2
1
1
PC197
.1U_0402_16V7K
JUMP_43X79
RTCVREF
+CHGRTC
PJ5
+0.89VP
PR16
560_0603_5%
1
2
+VCCPP
+1.8V
PC13
0.22U_0603_25V7K
<BOM Structure>
TP0610K-T1-E3_SOT23-3
PR14
22K_0402_1%
1
2
PR13
100K_0402_1%
+5VALW
JUMP_43X118
PC195
.1U_0402_16V7K
+1.8VP
PJ4
PQ1
N1
PR11
68_1206_5%
PJ3
PR12
200_0603_5%
1
2
JUMP_43X118
PR10
68_1206_5%
CHGRTCP
PC196
.1U_0402_16V7K
+5VALWP
BATT+
PD3
RLS4148_LL34-2
+3VALW
PC194
.1U_0402_16V7K
+3VALWP
PC193
.1U_0402_16V7K
PJ1
VIN
401793
Sheet

D
23
of
32
VMB
PJP2
PL2
HCB2012KF-121T50_0805
1
2
BATT_S1
TS
EC_SMCA
EC_SMDA
PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 70 degree C
BATT+
B/I
PC22
0.01U_0402_25V7K
VL
VS
VL
PR25
6.49K_0402_1%
2
1
BATT_TEMP (17)
8
+
MAINPWON (28)
PU3A
LM393DR_SO8
PR153
150K_0402_1%
2
1
VL
2
PR156
150K_0402_1%
2
EC_SMB_CK1 (17)
PR154
150K_0402_1%
2
PR152
82.5K_0402_1%
1
2
PC130
1U_0402_6.3V6K
2
1
PC131
1000P_0402_50V7K
1
PR27
1K_0402_1%
PH1
100K_0402_1%_NCP15WF104F03RC
2
1
+3VALWP
PR157
442K_0402_1%
2
TM_REF1
PR220
1K_0402_5%
PC129
0.1U_0402_25V6
PR22
100_0402_1%
PR21
100_0402_1%
PR155
9.76K_0402_1%
SUYIN_200275MR008G15QZR
PC21
1000P_0402_50V7K
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND
GND
EC_SMB_DA1 (17)
PQ3
3
+VSB
VS
PU3B
LM393DR_SO8
PR34
100K_0402_1%
(28) SPOK
PR32
22K_0402_1%
PC200
0.1U_0402_25V6
1
2
TP0610K-T1-E3_SOT23-3
PR30
100K_0402_1%
VL
B+
PQ4
2N7002W-T/R7_SOT323-3
2
G
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2008/09/20
Title
SCHEMATICS MB A5651
Custom
Date:
Rev
401793
Sheet
D
24
of
32
B+
4
2
PC53
4.7U_1206_25V6K
2
1
PC50
4.7U_1206_25V6K
2
1
1 1
SUSP#
SUSP# (17,24,29,30)
PQ16
DTC115EUA_SC70-3
PD13
1SS355TE-17_SOD323-2
1
2
CELLS
CSOP
21
ICOMP
CSIN
20
VCOMP
CSIP
19
ICM
PHASE
18
VREF
UGATE
17
CSON
CSOP
PQ19
SIS412DN-T1-GE3_POWERPAK8-5
PL5
8.2UH_FDV0630-8R2M=P3_3.7A_20%
CHG
1
2
16
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
GND
PGND
13
PC65
0.1U_0603_25V7K
BST_CHGA 2
1
12
26251VDD
PR82
4.7_0603_5%
PC70
4.7U_0805_6.3V6K
BATT+
PR74 0.05_1206_1%
4
PD14
RB751V-40TE17_SOD323-2
6251VDDP
DL_CHG
PQ21
BOOT
CHLIM
DH_CHG
PR78
0_0603_5%
BST_CHG 1
PR68
20_0402_5%
1
2
PC59
0.047U_0603_16V7K
1
2
PR69
20_0402_5%
2
1
PR70
PC62
20_0402_5%
0.1U_0603_25V7K
1
2
PR72
2_0402_5%
LX_CHG
PC68
10U_1206_25V6M
2
1
22
2 PACIN
2N7002W-T/R7_SOT323-3
G
S
CSON
PQ18D
PC67
10U_1206_25V6M
2
1
EN
PR76
4.7_1206_5%
23
ACSET ACPRN
3
2
1
PC57
0.1U_0603_25V7K
2
1
24
DCIN
DCIN
VDD
PC58
0.1U_0603_25V7K
2
1
3
PU5
1
3
2
1
PR81
20K_0402_1%
PR64
200K_0402_1%
1
2 VIN
PC66
680P_0402_50V7K
PR80
100K_0402_1%
VIN
PD10
1SS355TE-17_SOD323-2
ACOFF
1
2
PR62
10K_0402_1%
BAS40CW_SOT-323
.1U_0402_16V7K
PR79
38.3K_0402_1%
6251VREF 1
6251aclim
2
PR58
47K_0402_1%
1
2
FSTCHG (17)
PR67
2
<BOM Structure>
ACOFF
FSTCHG
2 1
ACOFF
6251VREF
PC64
1
2
(17)
IREF
PR73
100_0402_1%
1
2
(17)
6.81K_0402_1%
2
ADP_I
6251_EN
6800P_0402_25V7K
2
2
PC63
@ 100P_0402_50V8J
PR77
62K_0402_1%
2
1
PQ22
DTC115EUA_SC70-3
(17)
PR71
1
100K_0402_1%
1
1
3
PC61
2N7002W-T/R7_SOT323-3
1
2
<BOM Structure>
0.01U_0402_25V7K
PC69
0.01U_0402_25V7K
2
1
PACIN
PR75
22K_0402_5%
PACIN 1
2
(25)
PC54
2200P_0402_25V7K
2
1
1
2
PR66
150K_0402_1%
PQ20
2
G
PQ14
DTC115EUA_SC70-3
PR63
6251VDD
2
PC56
.1U_0402_16V7K
PC60
1
DCIN
PD11
10_0603_5%
(17) FSTCHG
PQ17
2N7002W-T/R7_SOT323-3
PC165
0.1U_0603_25V7K
2
1
PR65
10K_0402_5%
2
1
2
G
S
CSIN
JUMP_43X118
PR221
PQ15
DTC115EUA_SC70-3
CSIP
PD12
1SS355TE-17_SOD323-2
1
PQ13 TP0610K-T1-E3_SOT23-3
P3
SI7121DN-T1-GE3_POWERPAK8-5
PQ11
1
2
3
5
PJ8
2
PR60
200K_0402_1%
CHG_B+
PR57 0.05_1206_1%
4
4
PR59
47K_0402_1%
PC51
0.1U_0603_25V7K
2
1
PQ12
DTA144EUA_SC70-3
PC55
2.2U_0603_6.3V6K
2
1
B340A_SMA2
1
B+
P3
SI7121DN-T1-GE3_POWERPAK8-5
PQ10
1
2
3
5
100K_0402_1%
PR61
100K_0402_1%
2
1
PC52
5600P_0402_25V7K
1
2
P2
PD9
VIN
ISL6251AHAZ-T_QSOP24
VMB
CP = 85%*Iada ; CP = 1.343A
PR83
15.4K_0402_1%
1
2
VS
BATT-OVP=0.1112*VMB
6
PR88
105K_0402_1%
VADJ-->VREF-->4.41V
CV mode
VADJ--->Ground--->3.99V
Charging Voltage
(0x15)
Vcell=(0.175*VADJ+3.99)
tm
12.60V
2008/09/20
Title
Date:
in
Deciphered Date
SCHEMATICS MB A5651
xa
2007/09/20
Rev
he
Issued Date
Compal Secret Data
f@
ho
12600mV
ai
Normal 3S LI-ON Cells
BATT Type
l.c
om
PC72
0.01U_0402_25V7K
PU1B
LM358DT_SO8
7 0
PR87
10K_0402_1%
1
2
(17) BATT_OVP
PR86
499K_0402_1%
2
Per cell=3.5V
CC=0.3~1.76A
IREF=1.62*Icharge
IREF=0.486V~2.85V
3.24V==>2A
PR84
340K_0402_1%
LI-3S :13.5V----BATT-OVP=1.5012V
2
PR85
31.6K_0402_1%
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)
where Vaclm=0.8199V, Iinput=1.343A
(17) CALIBRATE#
PC71
0.01U_0402_25V7K
CP mode
Vaclim=2.39*(20K/(20K+38.3K))=0.8199V
Iada=0~1.58A(30W)
401793
D
Sheet

D
25
of
32
ISL6237_B+
ISL6237_B+
16
LX5
DL3
23
LGATE1
18
DL5
LGATE2
PGND
22
OUT1
10
FB1
11
BYP
SKIP
29
1
PQ8
IRFH3707TRPBF_PQFN8-3
FB3
@ PR43
10K_0402_1%
VL
30
OUT2
32
REFIN2
2VREF_ISL6237
1
PC33
4.7U_0805_25V6-K
2
1
PC164
0.1U_0603_25V7K
2
1
1
+
2
C
PC44
150U_B2_6.3VM_R45M
PHASE1
PHASE2
PR42
@ 61.9K_0402_1%
1
2
25
PR44
0_0402_5%
2
LX3
PR38
4.7_1206_5%
PC41
0.1U_0603_25V7K
PC40
0.1U_0603_25V7K
DH5
PR40 0_0603_5%
BST5A 2
1
17
15
BOOT1
PC43
680P_0402_50V7K
UGATE1
PC38
1U_0402_6.3V6K
1
2
1
1
1
PC42
680P_0402_50V7K
PC32
4.7U_0805_25V6-K
2
1
3
2
1
19
PR41
0_0402_5%
PC34
2200P_0402_50V7K
2
1
PC37
4.7U_0603_6.3V6M
2
1
PVCC
+5VALWP
PL4
4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%
2
1
BOOT2
VCC
UGATE2
24
6
VIN
26
PQ6
TP
DH3
PR39 0_0603_5%
2
1 BST3A
PQ7
PR37
4.7_1206_5%
PC39
150U_B2_6.3VM_R45M
PU4
33
LDO
1
1
2
3
PL3
8.2UH_FDV0630-8R2M=P3_3.7A_20%
1
2
PC35
0.1U_0402_25V6
PC36
1U_0402_6.3V6K
1
2
PQ5
+3VALWP
VL
PC30
4.7U_0805_25V6-K
2
1
PC31
2200P_0402_50V7K
2
1
PR36
0_0805_5%
1
2
PC29
4.7U_0805_25V6-K
2
1
PL11
HCB2012KF-121T50_0805
1
2
PC163
0.1U_0603_25V7K
2
1
B+
FB5
REF
PC45 0.22U_0402_6.3V6K
LDOREFIN
@ PR45 0_0402_5%
2
1
VL
PR46 0_0402_5%
1
2
MAINPWON
POK1
13
GND
21
EN2
TON
EN1
27
2VREF_ISL6237 2
14
SPOK
ILIM1
12
ILM1
ILIM2
31
ILIM2
SN0806081RHBR QFN 32P
PR49
309K_0402_1%
2
1
PR50
249K_0402_1%
+5VALWP
Ipeak=7.0A Imax=4.9A Iocp=8.4A
Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)
Vlimit=(5E-06 * 309K)/10=154.5mV
Ilimit=154.5mV/17.9m ~154.5mV/14.5m x 1.2
=8.631A ~ 8.879A
Iocp=Ilimit+Delta I/2
=9.611A ~ 9.859A
Delta I=1.960A (Freq=400KHz)
Compal Secret Data
2007/09/20
Issued Date
Deciphered Date
2008/09/20
Title
SCHEMATICS MB A5651
Custom
Date:
(26)
PQ9
TP0610K-T1-E3_SOT23-3
EN_LDO
PC48
0.047U_0402_16V7K
PR55
0_0402_5%
2
1
+3.3VALWP Ipeak=5.731A Imax=4.012A Iocp=6.877A

Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)
Vlimit=(5E-06 * 249K)/10=124.5mV
Ilimit=124.5mV/17.9m ~124.5mV/14.5m x 1.2
=6.955A ~ 7.155A
Iocp=Ilimit+Delta I/2
=7.922A ~ 8.122A
Delta I=1.934A (Freq=300KHz)
28
PC47
1U_0402_6.3V6K
5
1
2
2VREF_ISL6237
2
2
PR53
806K_0603_1%
(26)
POK2
NC
PC46
0.22U_0402_6.3V6K
VL
PD7
1SS355TE-17_SOD323-2
NC
PR48
200K_0402_1%
1
2
20
PR47
100K_0402_1%
1
2
VS
PD6
GLZ5.1B_LL34-2
1
2
Rev
401793
Sheet
26
of
32
PL12
HCB2012KF-121T50_0805
1
2
PC166
0.1U_0603_25V7K
2
1
4
1
PR91
0_0603_5%
BST_1.8V 1
2
PQ23
3
2
1
SYSON
B+
<Vo=1.8V> VFB=0.75V
Vo=VFB*(1+PR96/PR97)=0.75*(1+28.7K/20.5K)=1.8V
Fsw=328KHz
1
+
2
PR96
28.7K_0402_1%
1
2
Cout ESR=15m ohm Rdson(max)=17.9m Rdson(typical)=14.5m

Ipeak=4.97A, Imax=3.479A, Iocp=5.964A
Delta I=((19-1.8)*(1.8/19))/(2.2u*328K)=2.259A
=>1/2DeltaI=1.129A
Vtrip=Rtrip*10uA=8.66K*10uA=0.0866V
Iocpmin=Vtrip/(Rdsonmax)+1.129
=0.0866/(0.0179)+1.129=5.967A
Iocpmax=(0.0866/(0.0145*1.2))+1.129A=6.106A
Iocp=5.967A~6.106A
PR97
20.5K_0402_1%
PL13
HCB2012KF-121T50_0805
1
2
PR98
300K_0402_5%
1
2
PC167
0.1U_0603_25V7K
2
1
PC85
4.7U_0805_25V6-K
2
1
B+
PR100
0_0603_5%
BST_1.05V1
2
PQ25
3
2
1
PR99
2K_0402_1%
1
2
PC84
4.7U_0805_25V6-K
2
1
PC83
2200P_0402_50V7K
2
1
+VCCP_B+
DL_1.05V
1
PGND
RT8209BGQW_WQFN14_3P5X3P5
2
GND
7
PC92
4.7U_0805_10V6K
1
+
2
PC88
330U_B2_2.5VM_R15M
LGATE
PGOOD
PC89
4.7U_0603_6.3V6K
+5VALW
PR102
4.7_1206_5%
10
PC90
680P_0603_50V7K
VDDP
2
PR104
14K_0402_1%
15
14
11
+VCCPP
FB
12
CS
LX_1.05V
PHASE
VDD
DH_1.05V
13
PQ26
VOUT
BOOT
UGATE
PL7
1UH_FDV0630-1R0M-P3_10.3A_20%
1
2
PR103
100_0603_1%
1
2
TON
PC87
0.1U_0603_25V7K
BST_1.05V-1 1
2
+5VALW
NC
PU7
EN/DEM
PC86
1U_0402_6.3V6K
PR101
30K_0402_5%
(17,24,27,30) SUSP#
PC82
4.7U_0805_10V6K
1
2
DL_1.8V
LGATE
PGND
PGOOD
GND
PC79
4.7U_0603_6.3V6K
+5VALW
PC78
220U_B2_2.5VM
10
2
PR95
8.66K_0402_1%
VDDP
LX_1.8V
1
PR93
4.7_1206_5%
14
11
FB
12
CS
PHASE
+1.8VP
PC80
680P_0603_50V7K
VDD
0.1U_0603_25V7K
PQ24
VOUT
DH_1.8V
13
UGATE
BOOT
TON
PR94
100_0603_1%
1
2
PL6
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2
PC76
1
2
BST_1.8V-1
+5VALW
NC
PU6
EN/DEM
PC77
1U_0402_6.3V6K
PR92
30K_0402_5%
15
(17,24)
PR90
1K_0402_1%
1
2
PC75
4.7U_0805_25V6-K
2
1
PC73
2200P_0402_50V7K
2
1
5
PR89
300K_0402_5%
1
2
PC74
4.7U_0805_25V6-K
2
1
1.8V_B+
PR105
8.2K_0402_1%
1
2
2008/09/20
Title
SCHEMATICS MB A5651
Custom
Date:
in
Deciphered Date
Rev
xa
2007/09/20
f@
Compal Secret Data
Issued Date
ho
tm
ai
l.c
om

Delta I=((19-1.05)*(1.05/19))/(1.5u*280K)=3.549A
=>1/2DeltaI=1.774A
Vtrip=Rtrip*10uA=14K*10uA=0.14V
=0.14/(0.0179)+1.774=9.596A
Iocpmax=(0.14/(0.0145*1.2))+1.774A=9.820A
Iocp=9.596A~9.820A
401793
he
PR106
20.5K_0402_1%
<Vo=1.05V> VFB=0.75V
Vo=VFB*(1+PR105/PR106)=0.75*(1+8.2K/20.5K)=1.05V
Fsw=280KHz
Sheet
27
of
32
PR107
300K_0402_5%
1
2
(17,24,27,29)
PR108
2K_0402_1%
SUSP#
2
PC168
0.1U_0603_25V7K
2
1
<Vo=0.89V> VFB=0.75V
Vo=VFB*(1+PR114/PR115)=0.75*(1+28.7K/20.5K)=0.89V
Fsw=263KHz
2
PR113
8.66K_0402_1%
DL_0.89V
FB
PR114
3.74K_0402_1%
1
2
LGATE
2
1
PGND
PC102
4.7U_0805_10V6K
2
PGOOD
GND
+0.89V_PG
PR215
10K_0402_5%
2
1
(17)
2
PC99
4.7U_0603_6.3V6K
+5VALW

Delta I=((19-1.8)*(1.8/19))/(2.2u*263K)=1.467A
=>1/2DeltaI=0.7335A
Vtrip=Rtrip*10uA=8.66K*10uA=0.0866V
=0.0866/(0.0179)+0.7335=5.572A
Iocpmax=(0.0866/(0.0145*1.2))+0.7335A=5.711A
Iocp=5.572A~5.711A
+0.89VP
1
+
2
PC98
220U_B2_2.5VM
VDDP
10
11
CS
0.1U_0603_25V7K
LX_0.89V
PR111
4.7_1206_5%
14
DH_0.89V
12
VDD
13
PHASE
PC100
680P_0603_50V7K
UGATE
PQ28
VOUT
TON
BOOT
PL8
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2
PC97
1
2
BST_0.89V-1
+5VALW
PR112
100_0603_1%
1
2
NC
PU8
EN/DEM
PC96
1U_0402_6.3V6K
PR110
30K_0402_5%
15
PR109
0_0603_5%
BST_0.89V1
2
3
2
1
PC95
4.7U_0805_25V6-K
2
1
PC94
4.7U_0805_25V6-K
2
1
PC93
2200P_0402_50V7K
2
1
0.89V_B+
PQ27
PL14
HCB2012KF-121T50_0805
1
2
B+
+3VALW
PR115
20.5K_0402_1%
Ipeak=1.48A, Imax=1.036A
+1.8V
PC105
1U_0402_6.3V6K
1
2
+1.5VS
+1.8V
PC198
.1U_0402_16V7K
1.54K_0402_1%
PC108
22U_0805_6.3V6M
PC107
0.01U_0402_25V7K
ADJ
G9731F11U_SO8
PR118
3
4
VEN
POK
VO
VO
<BOM Structure>
PC109
.1U_0402_16V7K
8
7
PR119
@ 47K_0402_5%
VPP
VIN
TP
GND
(17,24,27,29) SUSP#
B
PR117
10K_0402_5%
1
2
PU10
6
5
9
PC106
4.7U_0805_6.3V6K
+5VALW
PR120
1.74K_0402_1%
6
NC
VREF
NC
VOUT
NC
TP
+3VALW
1
VCNTL
GND
PC111
1U_0603_6.3V6M
PR121
1K_0402_1%
PC110
4.7U_0805_6.3V6K
VIN
2
1
PU11
1
+0.9VS
PC199
.1U_0402_16V7K
1
2
PC114
10U_0805_6.3V6M
PR123
1K_0402_1%
S
2N7002W-T/R7_SOT323-3
PC112
.1U_0402_16V7K
2
1
PC113
.1U_0402_16V7K
PQ29
2
G
PR122
0_0402_5%
1
2
1
(24) SUSP
APL5336KAI-TRL SOP
Ipeak=1A, Imax=0.7A
2007/09/20
Issued Date
Compal Secret Data
Deciphered Date
2008/09/20
Title
Date:
SCHEMATICS MB A5651
Rev
401793
Sheet
1
28
of
32
(5)
(5)
(5)
(5)
(5)
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
VR_ON (17)
CPU_VID0
(5)
(5)
0_0402_5%
1
2
PVCC
20
PL10
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2
+CPU_COREP
+CPU_CORE
3211_SW
3
2
1
21
17
AGND
33
PR124
4.7_1206_5%
PC186
2.2U_0603_10V6K
4
LL=5.9m ohm
OCP=7.85A
VID:0.75V~1.1V
Io(max)=6.04A
PQ31
AON7702L_DFN8-5
PC115
680P_0603_50V7K
3
2
1
CSCOMP
18
AGND
3211_DRVL
PGND
+5VS
DRVL
19
B+
PC148
0.1U_0402_25V6
1
2
PC147
2200P_0402_50V7K
1
2
PC116
4.7U_0805_25V6-K
1
2
5
16
CSFB
15
CSREF
14
PH4
100K_0402_1%_NCP15WF104F03RC
1
2
3
Place RTH1 close to inductor

on the same layer
1
1
PC189
1000P_0402_50V7K
PC190
220P_0402_50V7K
PR217
75K_0402_1%
2
1
2
LLINE
13
3211_VCC
26
VID5
27
VID4
25
22
SW
PR213
35.7K_0402_1%
2
1
PR214
499K_0402_1%
RAMP
12
3211_RAMP
1
2
PR218
309K_0402_1%
PC191
1000P_0402_50V7K
PC121
4.7U_0805_25V6-K
2
1
1
VID6
PR204
0_0402_5%
1
VID5
PR203
0_0402_5%
1
VID4
PR202
0_0402_5%
PR201
1
VID3
28
VID3
VID6
DRVH
3211_DRVH
PR206
PC183
0_0603_5%
0.22U_0603_25V7K
2CPU_BOOST-1
1
2
(6)VCCSENSE
0_0402_5%
2
29
VID2
30
VID1
11
PR211
200K_0402_1%
1
2 3211_RPM
PR210
80.6K_0402_1%
3211_IREF
1
2
3211_CSCOMP 1
2
1
1
(6) VSSSENSE
BST
23 CPU_BOOST 1
3211_RAMP-1
Connect to input caps
PL9
HCB2012KF-121T50_0805
PQ30
24
3211_CSCOMP
+CPU_B+
PR219
1K_0402_1%
2
1
3211_CSFB
PR158
0_0402_5%
3211_CSCOMP
RT
ILIM
PC182
1U_0805_25V6K
VCC
GPU
PR207
28K_0402_1%
Avoid high dV/dt
PR150
0_0402_5%
PR200
10_0603_1%
COMP
3211_ILIM 8
PR209
2.37K_0402_1%
+CPU_B+
FB
3211_RT
ADP3211AMNR2G_QFN32_5X5
RPM
PC188
470P_0402_50V8J
3211_COMP 6
23211_COMP-1
1
FBRTN
PR208
1K_0402_1%
PC187
47P_0402_50V8J
1
PR199
1
VID2
CLKEN#
IREF
0_0402_5%
1
VID1
IMON
10
3211_FB
PC185
390P_0402_50V7K
0_0402_5%
VID0
31
32
EN
PWRGD
VID0
1
2
1
2
(8) CLK_ENABLE#
4
1
+5VS
PU12
PR205
10K_0402_1%
PC184
1000P_0402_50V7K
PR198
+3VS
3211_EN
PR212
274K_0402_1%
1
2
(5,8,13,17) VGATE
PR196
PR195
0_0402_5%
2
13211_PWRGD
PR197
PR194
4.7K_0402_1%
0_0402_5%
+3VS
PC192
1000P_0402_50V7K
l.c
om
Shortest the
net trace
2008/09/20
Size
C
Date:
in
Title
SCHEMATICS MB A5651
Document Number
xa
Deciphered Date
he
2007/09/20
Issued Date
Compal Secret Data
f@
ho
tm
ai
Rev
401793
Sheet
29
H
of
32
Version change list (P.I.R. List)

Item
D
Page 1 of 1 for PWR
Fixed Issue
Reason for change
Rev.
PG#
Modify List
Date
Phase
add PC200
For design change
0.1
24
2009.5.15
EVT
add PC193,PC194
For design change
0.1
26
2009.5.15
EVT
add PC195,PC196
For design change
0.1
27
2009.5.15
EVT
add PC197,PC198,PC199
For design change
0.1
28
2009.5.15
EVT
change PL3,PL4
For design change
0.1
26
change PL3,PL4 to 4.7uH
2009.5.15
EVT
change PQ10,PQ11
For design change
0.1
25
change PQ10,PQ11 to P-Chanel
2009.6.5
EVT
add PC165
Solution for 3G noise reduce
0.1
25
2009.6.5
EVT
add PC163,PC164
0.1
26
2009.6.5
EVT
add PC166,PC167
0.1
27
2009.6.5
EVT
10
add PC168
0.1
28
2009.6.5
EVT
11
delete PC103,PC1120
For design change
0.1
29
2009.6.5
12
change PR94,PR102
For design change
0.1
27
change PR94,PR102 to 100ohm
2009.6.5
13
change PC79,PC89
For design change
0.1
27
change PC79,PC89 to 4.7uF
2009.6.5
14
change PR112
For design change
0.1
28
change PR112 to 100ohm
2009.6.5
15
change PC99
For design change
0.1
28
change PC99 to 4.7uF
2009.6.5
16
change +5VALW/+3VALW OCP
For design change
0.1
26
change PR49 to 309ohm & PR50 to 249ohm
2009.6.5
17
add PJ1,PJ2,PJ3,PJ4,PJ5,PJ6,PJ7
For design change
0.1
25
2009.6.15
18
add PJ9,PJ10
For design change
0.1
28
2009.6.15
19
Change net name
For design change
0.1
25
Change net name +1.05V to +VCCP
2009.6.15
20
Change PJP2
For design change
0.1
24
Change PJP2 to DC040903020
2009.6.15
21
Change PBJ1
For design change
0.1
23
Change PBJ1 to SP020008Y00
2009.6.15
22
delete PJ6,PJ7,PJ9,PJ10
For design change
0.1
28
23
Change net name
For design change
0.1
29
2009.6.18
A
2009.6.18
Compal Secret Data
Issued Date
Change net name GND_SIGNAL to GND
2007/09/20
Deciphered Date
2008/09/20
Title
Custom
Date:
SCHEMATICS MB A5651
Rev
401793
D
Sheet
1
30
of
32
Version change list (P.I.R. List)

Item
D
Page 1 of 1 for PWR
Fixed Issue
Reason for change
Rev.
PG#
For design change
0.1
29
Change
add PR221
For design change
0.1
25
Change
PR4
For design change
0.1
23
Change
PJP3 to PBJ1
For design change
0.1
Change
PH1 & PH4
For design change
Change
PL10
Change
Modify List
Date
Phase
2009.6.30
EVT
2009.6.30
EVT
change PR4 to 0 ohm
2009.7.2
EVT
23
change SP020008Y00 to SP093MX000
2009.8.4
EVT
0.1
24
change SL210031F00 to SL200000V00
2009.8.12
EVT
For design change
0.1
29
change SH000006I80 to SH000000700
2009.8.12
EVT
PR99 & PR108
Modify power sequence
0.1
27
change SD028000080(0 ohm) to SD034200280(20K ohm)
2009.8.12
EVT
Change
PR90
0.1
27
2009.8.12
EVT
Change
PR83
Modify ISL6251 Charger KV
0.1
25
2009.8.24
EVT
10
Change
PR117
0.1
28
2009.8.24
EVT
11
Change
PR99 & PR108
0.1
27
change SD034200280(20K ohm) to SD034200180(2K ohm)
2009.8.24
EVT
12
Change
PR90
0.1
27
change SD034100280(10K ohm) to SD034100180 (1K ohm)
2009.8.24
EVT
2009.8.24
EVT
13
Change
14
PR194
PC77 & PC86 & PC96
change PR194 to 4.7K ohm
change SD034182280(18.2 ohm) to SD034154280(15.4K ohm)
Change
PC77 & PC86 & PC96 to pop
0.1
27
Change PC109
Change part number
0.1
27
change SE076104KM8(0.1uf) to SE076104K80(0.1uf)
2009.8.24
EVT
15
Change PL3.PL4
To slove high frequency noise
0.1
26
change SH00000BU00(4.7uH) to SH00000BS00(8.2uH)
2009.8.27
EVT
16
Change PL9
For design change
0.1
29
change SM01000BY00 to SM01000C000
2009.9.4
DVT
17
Change PL4
To improve +5VALWP efficiency
0.1
26
change SH00000BS00(8.2uH) to SH00000F900(4.7uH)
2009.9.10
DVT
18
Change
Modify CPU CORE OCP
0.1
29
change SD028180180(1.8K ohm) to SD034237180 (2.37K ohm)
2009.9.30
PVT
change SE076104KM8(0.1uf) to SE000000K80 (1uf)
PR209
19
20
21
l.c
om
22
2008/09/20
Title
Custom
Date:
SCHEMATICS MB A5651
in
Deciphered Date
401793
Rev
xa
2007/09/20
f@
Compal Secret Data
Issued Date
ho
tm
ai
23
he
Sheet
1
D
31
of
32
<2009/4/28>
Update new power schematic,
release first version NAV50 schematic
<2009/04/29>
. Add R1182 R1183 L3 on page 9
. Change J3 to R1184 on page 13
<2009/06/12>
. Page4 Add C314 C313 C1150 D19 on +VCC_FAN1
. Page8 Add C1145 C1146 C1147
. Page10 Move CRT_DET# from Page13 to Page10
. Page13 Add +RTCVCC circuit
<2009/07/08>
. Page5 Add 470pf on H_SMI# for known issue.
<2009/06/15>
. Update New Power schematic (change PBJ1 to PJP3)
. Page 10 modify C310 C308 C303 C307 C306 C304 Bom Structure
. Page 22 Modify Hole location by (ME drawing 06/12)
<2009/06/16>
. Page7 Modify DDR Command Control Pin pull-high Resister location
. Page9 Change R577 to 0402 type
<2009/06/17>
. Update New Power schematic 06/17
. Page9 modify LVDS Conn. Pin define
. Page9 Del C1110
. Page4 Add EMI solution D38 D39 D40
<2009/05/12>
. Follow Intel Layout Checklist, Add C141 on VDDSPD on page 7
. Modify SRC CLK PORT LIST on page 8
. Del CLKREQ_LAN# on page 8
. Change PCIE Port list on page 13
. Change USB Port list on page 13
. Add W/L 3G SW on page 16
. Del R103 on page 18
<DVT START>
<2009/08/04>
. Page5 CLK_CPU_HPLCLK CLK_CPU_HPLCLK# exchange
. Page9 Change JLVDS1 to P/N ACES 88341-3001 30P
. Page17 del PM_1.8V(U6.82) ,Del R1310 R1311
. Page18 Del D41
<2009/09/08>
Update Power schematic 0904
. Page18 Change R1388 to 100 ohm 0402
. Page18 Change LED1 to SC591NB5A00
<2009/06/19>
. Page4 Add new signal CPU_ITP , CPU_ITP#
. Page5 ADD R1378
. Page6 ADD C1152,C1153,C1154 C1160,C1161,C1162
. Page7 DDR_A_D8DDR_A_D9
. Page8 ADD R1379,R1380,U77,R1381,C1157,R1382,R1383,R1384,C1157
, Page8 DEL C390
. Page9 ADD C1156
. Page11 DEL R1322, R1154
. Page13 DEL U77, ADD C1158
. Page17 ADD C1159
<2009/05/14>
. Update New Power schematic
. Del R376 R377 on page 8
. Del D5 D7 D8 on page 4
. Change JLVDS1 to SP010006810 on page 9
. Add D6 for EMI on page 9
. Change C1106 to C_0603 type on page 9
. Change USB_OC# on page 13
. Add USB Port2 on page 20
. Change JP11 Pin define & Add D22 on page 19
. Change C512 to 1u_0402 on page 15
. Add U29 (MEDIA_LED#)) on page 16
<2009/09/03>
. Page7 Change C112 to 0402 type
. Page8 Add T6 on CLK_48M_CR
. Page16 Modify JP18 Pin define change +5VALW +5VS to +3VALW +3VS
. Page20 Change Pin 18, 23 to +1.5VS change Pin7 , 9 to USB20_P7 N7
. Page21 Del H12
<2009/06/18>
. Page8 modify U4 Pin define and Q31
. Page13 Add R1376, R1377
. Page15 Modify C403
. Page23 Modify H11
<2009/05/13>
. Change JMINI1 to PCIE Port 3 on page 15
<2009/05/14>
. Page8 Change C174 C175 to 10U_0603
<2009/07/03>
. Page18 Add D41.2 to PWR_PWM_LED#
. Page8 Change co-lay net name to +1.5VM_CK505
. Page20 Change JP2 Pin42 to +5VS
<2009/07/06>
. Page18 Add pwr switch for NAV50
<2009/04/30>
. Change JDIM1 to SP07F001720 on page 7
. Del SATA1 Port on page 12
. Change R51 R57 R70 R63 R317 R314 R190 to 0402 Size on page 21
<2009/05/04>
. Add WWAN_CLKREQ# and R107 pull-high to +3VS on page 8
. Add CRT_DET# on page 10
. Add CRT_DET# circuit on page 13
. Add 3 LEDS on page 16
. Add BT/BTN Board CONN. on page 16
. Update TP/B CONN. to SP01000LB00 on page 19
<2009/05/11>
. Add INVT_PWM on Page 5
. Del R323 on page 5
. C74 change to 2.2U_0603 on page 6
. C267 change to 22U on page 6
. C391 change to 0.1U on page 6
. Del C67 C35 C33 C36 on page 6
. Del +LGI_VID and U71.A21 direct connect to +VCCP on page 6
. Follow Intel checklist, add R52 on FSB on page 8
. Add D5 D7 D8 on page 4
. Add R174 on page 9
. Add PCI_RST# on page 11
. Add C1115 C1114 C1116 C1117 C1118 on page 15
<2009/06/10>
. Page 7- Add C116 @
. Page 22- Modify USB_OC#1_2 to USB_OC#2
. Page 17- Modify PLTRST# to PCI_RST#
. Page 17- Add @ on R1311
<2009/06/22>
. Page22 change IO Conn. pin34 from 48M to USB_ON#
. Page10 change JCRT1 P/N to SP010906182
<2009/09/10>
Update Power schematic 0910
. Page22 unmount Q6 Q8
<2009/10/07>
. Page4 U71 Change to SA00003M800
. Page6 R26 Change to SHI00009C00
. Page13 R152 Change to SD034200A80
. Page18 R1388 Change to SD028510A80
<2010/04/29>
update new bom
<2009/06/23>
. Page15 Add C1163 C1164 C1165 C1166
. Page18 change PWR/B Conn. P/N to SP01000H300
. Page22 change JUSB1 JUSB2 P/N
<2009/06/24>
. Page8 Change C1350 C1351 to 0402 type
. Page10 Add R1385 R1386 on JVGA_HS JVGA_VS
<2009/05/19>
.Update new clock GEN co-lay schematic on page 8
<2009/06/25>
. Page22 move some parts to I/O Board , Add the
.
<2009/06/05>
.Update new clock GEN co-lay schematic on page 8
.Follow Intel check list change C161 C165 to 27P on page 8
.Follow Intel check list change C56 to 22uF on page 6
MONO_IN_R on M/B
<2009/06/29>
. Page16 Change JP24 to ACES_88266_05001
. Page15 Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T
<2009/06/08>
.Update New Power schematic 06/06 version
Page 13- a.Del R203 (pull-up GPIO6 Resister)
b.Change R1184 NU
Page 17- a. Add VGATE
b. Del R1294
c. Change D30 NU
d. Change R1295 to 0 ohm
e. Add R1309 0 ohm on EC_RSMRST#
f. Pull-up LAN_WAKE# +3VALW
g. ICH_POK change to PCH_POK
h. Pull-up KB_RST# to +3VS
Page 10- a. Add R1283 R1284 ,Change R247 R249 to 10 ohm
b. Add @ on U10 U11 C301 C298
c. Del C302 C300 R1281 R1287
<2009/06/30>
. Page18 Change PWR_LED# to PWR_PWM_LED#
. Page17 Add PWR LED DETECT PIN on Pin97
<2009/07/02>
. Page9 Add C1167 C1168 for RF request.
. Page13 Change R223 to 100K
. Page16 change JP24 to ACES_85201-0505N
. Page17 Del R1387 R1388 on EC Pin97
. Page17 Add New Board ID to separate NAV50 NAV60
. Page17 Change IC to SA00003J400 (New)
. Page18 Add D41 for ESD
Compal,Electronics,lnc
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL,INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF COMPETENT DIVISION OF R&D DEPARTMENT
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR
DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SCHEMATICS MB A5651
Size
Document Number
Custom
Date:
Rev
401793
D
Sheet
1
32
of
32

Acer Aspire La5651p

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A

NAV70 Schematics Document

Compal Electronics, Inc.

Compal Secret Data

1.8V DDRII 667

Conn. to I/O Board

AMP & INT

Compal Electronics, Inc.

Compal Secret Data

Friday, May 21, 2010

External PCI Devices

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

Graphic core power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

SLP_S3# SLP_S4# SLP_S5#

ICH7M SM Bus address

BOARD ID Table(Page 17)

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Must be placed within 500 mils from Pineview-M pins

Modify follow KAV60 schematic 06/12

Modify D38 D39 D40 Pin define

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Friday, May 21, 2010

Add 470PF on H_SMI# for known issue 07/08

Del R323 05/11

Place closed to chipset

H_THERMDA, H_THERMDC routing together.

EMC1402-1-ACZL-TR MSOP 8P SENSOR

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placed within 0.5"

placed within 0.5"

Friday, May 21, 2010

CPU THERMAL SENSOR

GFX supply current: 1.38A

DDR supply current 2.27A

22UF 6.3V M X5R 0805

22UF 6.3V M X5R 0805

Display PLL SFR and CRT DAC supply

22UF 6.3V M X5R 0805

DDR analog supply current: 1.32A

22UF 6.3V M X5R 0805

GIO supply current: 0.006A T31

LVDS supply current: 0.06A

DAC, GIO, LVDS, & LGIO, DPLL, HMPLL

DMI analog supply current: 0.48A

SFR & DMIHMPLL supply current: 0.104A

Follow Intel check list change to 22uF 06/06

Close Chipset pin

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