1

EDA SIMULATION

Proceso de Diseo de un Sist. Dig. g

2

Design Idea Behavioral Design Flow Graph, Pseudo Code Data Path Design Bus & Register Structure Logic Design Gate Wirelist, Netlist Physical Design Transistor List, Layout Manufacturing Chip or Board
M.R. Barbacci, The ISPS Computer Description Language, Carnegie-Mellon University, 1981, p.70

Manejo del Quartus II y la tarjeta DE2 de Altera

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Instalacin s a ac
Qsim

del so wa e Quartus II de software Qua us Instalacin de los simuladores

Modelsim

Introduccin Instalacin Manual

a la tarjeta de desarrollo DE2

DE2_introduction.pdf

de la tarjeta DE2

t t i iti lDE2 df tut_initialDE2.pdf

del Usuario

DE2 UserManual pdf DE2_UserManual.pdf

Manejo del Quartus II y la tarjeta DE2 de Altera

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Tutorial 1:
Realice

el siguiente tutorial
II Introduction Using Verilog Design g g g

Quartus

Documento: tut_quartus_intro_verilog.pdf Se localiza en el disco que viene con la tarjeta DE2-115 Notas importantes: 1.- Detenerse en la seccin de simulacin y usar el documento: Quartus_II_Simulation.pdf 2 No realizar la seccin de Active Serial Mode 2.Active Programming

Testbench HDL in Quartus II ModelSim Altera

Realice la simulacin del tutorial utilizando ModelSim-Altera STEPS:

Verifique la ruta de la licencia de ModelSim-Altera (Tools->License Setup -> EDA Tool Options), C:\altera\11.0\modelsim_ase\win32aloem Analyze and Synthesize the device (design) under test:

-> Compilation Tool Use HDL simulation syntax. Utilice el mdulo t proporcionado en el tutorial anterior (: tut_quartus_intro_verilog.pdf) Save the file in the path (uncheck add file to current project) p p j

Create a Testbench (nameTB.vhd):

/projname/simulation/modelsim Si no existe el folder simulation/modelsim, es necesario crearlo. /p j /projname indica el nombre del proyecto en el que se est trabajando p y q j

Testbench HDL in Quartus II ModelSim Altera

Link testbench to DUT.

->Assigments->Settings->EDA Tool Settings->Simulation>NativeLink settings->Testbenches button->New Complete the form: Create new test bench settings according to the DUT selected.

S Simulate

Choice the test bench: ->Assigments->Settings->EDA Tool Settings>Simulation->NativeLink settings->Compile test bench Note: You can modify the test bench file and then Run the simulation again, just pressing the up arrow key followed by the enter key, in the ModelSim text Console.

Testbench HDL in Quartus II ModelSim Altera

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Continuacin

Start simulation:

->Tools ->EDA Simulation tool ->Run EDA RTL simulation

Analyze the results showed by ModelSim Altera. Note: You can modify the test bench file and then Run the simulation

Tarea
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Concluir las simulaciones en modo:

Manualmente

(manipular las seales): Qsim Combinado: ModelSim-Altera ModelSim Altera Standalone: ModelSim

Estudiar el captulo 1 del libro:

Advanced

Digital Design with the Verilog HDL, Ciletti (referencia 1 del programa analtico)