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Abbreviated Title: L.C. L-Amp

Corresponding Author: Vivek Singh, Morgan State University Clarence M. Mitchell, Jr. School of Engineering, Baltimore, MD, 21251 Tel: (301) 825-6905 Email: vevekat@yahoo.com

Word Count: 1895

Figures : 7

Last Date of Revision: April 25, 2011

Singh 2011 L.C. L-Amp

1. Introduction. 2 2. Objective 3 3. Proposed Work. 3 4. High Level Design 4 5. Verilog HDL Design.... 5 6. NIOS II Design. 6 7. Results. 8 8. Conclusion 9 9. Acknowledgement................................................................................................................................................10 10. Appendices. 10 11. References...10

Singh 2011 L.C. L-Amp

A low cost lock-in amplifier has been designed and built on the Altera Cyclone II DE2 FPGA board and tested. The design parameters were considered such that the frequency of weak signal was ensured while testing. It was able to measure the phase shift of the detected weak signal due to the delay.


Lock in Amplifier is a device that provides a DC output proportional to the AC signal. It detects the very low signal of a particular frequency rejecting all other frequencies from a noisy environment. This device is very useful in measuring the phase shift of large signals with high signal to noise ratio. Initially, the signal is multiplied by a reference function, mixing through a frequency mixer and the result is filtered using a low-pass filter. For a signal Y (t) containing two frequencies when multiplied by the reference function R (t) the result is obtained X (t) is as follows:

Y (t ) = A1 sin(1t + ) + A2 sin( 2 t ) R(t ) = sin( r t )

X (t ) = Y (t ) R (t )

= A1[{cos(1 r )t + } {cos(1 r )t + ]} / 2 + A2 [{cos( 2 r )t + } {cos(2 r )t + ]} / 2


The reference frequency r selects the frequency to be passed into the lock-in. If the r is close to

1 , the difference 1 r is a low frequency which will pass though the low pass filter rejecting all other frequencies. If 1 = r then = 0 i.e. it only measures the amplitude of 1 . Similarly, if both
are every close to each other it will only measure the beat between the two frequencies. Lock-in Amplifier is very useful in detecting very small signals in presence of large background noise. However, it is very costly to obtain and perform the analysis on the lab. Considering a preferred design choice it can be easily build using microchips or even better using the programmable FPGA board to use it in a PC. Due to the high cost of microchips the FPGA logic for the Lock-in is build and tested.

Singh 2011 L.C. L-Amp

The primary objective of this research was to build all digital lock-in amplifier on a FPGA (Field Programmable Gates Array) board (Altera Cyclone DE II). Also, to design the digital components using Verilog HDL and interconnect the modules by building a system, using the SOPC (System on a Programmable Chip) builder on Quartus II software. Finally, to design the VGA software user interface using C programming language and embedded it on the NIOS II processor using NIOS II IDE software


The main objective of this research is to build all digital lock-in amplifier using FPGA board. It would be performed using the steps shown on Fig 1. Each of the physical components used on signal processing would be designed individually as VHDL modules. The rough algorithm is shown on Fig 2. The other task would be to design a C programming module for the user interface. Once the amplifier is successfully built, the measurements have to be performed. It would be tested to measure the fluorescence lifetime and would be compared with the MATLAB simulation. The raw data acquired from the oscilloscope would be saved and loaded into MATLAB and secondly to filter the raw data using the digital low pass filter using cheby1 with normalized passband edge frequency. Then the filtered data would be processed using FFT and the phase of each individual wave would be calculated using angle and unwrap.

Fig. 1. Block diagram of lock-in amplifier

Singh 2011 L.C. L-Amp


The high level design for the lock-in amplifer is shown in fig.2. This design was made for the Altera Cyclone II DE2 board from Terasic. The snapshot of the board is shown in fig 2a. The major advantage of DE2 board was it supports the hardware components needed, such as the basic FPGA support circuity(power supply, programming, etc), as well switches and buttons for user input along with a VGA output port. However, for the purpose of lockin the only disadvantage was that there is the absence of high speed A/D converters. It also contains two ports of 100MS/s 14 bit DAC outputs and 2 port of 65MS/s 14 bit A/D input which was sufficient for a design goal of 1MHz input bandwidth. For the purpose of the design, the input signal is first fed into the A/D which is then multiplied in a multiplier and passed though the low pass filter. It is then processed by NIOS II processor and sends the signal to output port A. Similarly, the reference signal is passed thought the A/D to the PLL (Phase Locked Loop), which is then mixed into the mixer and passed thorough the low pass filter. It is then processed by NIOS II processor into the output port B.

Fig. 2a. Altera Cyclone II DE2 FPGA board

Singh 2011 L.C. L-Amp

Input Signal


Input Reference


0 crossing detect


Internal Reference

Fig. 2b. High level Schematic of lock-in amplifier


In order to build the system using the SOPC builder on Quartus II software all the verilog modules had to be separately constructed and compiled together. The top level verilog module was the main amplifier lockin_amp.v which defined all other supporting verilog modules. The supporting verilog modules are character_generator.v, DDS_signal_generator.v, zero_crossing_detector.v, ntsc_display_generator.v, ref_digital_PLL.v, and exponential_decay_filter.v. These modules are discussed below: Zero crossing detector: This module simply took the digitized reference input, and waited for zero crossing. For the prevention of noise on the signal receptively triggering the crossing detects both positive and negative hysteresis was added. To prevent any phase shift the output was always triggered at the zero crossing. ADPLL: Phase locked loop (PLL) was needed for an externally generated reference signal. Since, the goal was to digitized all the components, it was implemented as an all digital phase locked loop(ADPLL) which as input took a digitized data stream of the reference signal and as output gave a pair of locked quadrature sine waves. Low Pass Filter: Low pass filters was designed to emulate the simple RC circuit with adjustable time constant. The quadrature mixers were implemented by a simple single pole IIR filter. It was done using two multipliers to multiply the two filter parameters against the input and previous output signal, respectively. The outputs were then summed, and stored in an output register which also previous output to the filter. NTSC Video Output: The video output was needed for the purpose of user interface from the VGA DAC. An accurate timing sync timing system along with the actual video signal output during the correct portions of the video scan had to be designed to generate the signal. However, for the lockin output only the text information was required hence a luminosity encoded output (Black and white) was sufficient. The timing information and luminosity signals were generated with straightforward timing and comparator logic. 5

Singh 2011 L.C. L-Amp Each individual verilog module was created to function it as the physical digital component that would be programmed into the DE2 board. At this level all the verilog modules couldnt be fully understood and debugged hence, the compilation was performed, which showed no errors.

Using the SOPC builder of Quartus II software a system had to be built on the chip that would interconnect all the verilog modules as physical components on the FPGA board driven by the NIOS II processor clocked at 50 MHz. The SOPC design is shown in fig.3, which was compiled without any errors.

Fig.3 SOPC design using SOPC builder

After successful compilation of SOPC builder the files that were required to program the DE2 board were obtained. It was then programmed using the Quartus II programmer. All the verilog modules were successfully programmed into the board. Now, the NIOS II had to be programmed to embed the c user interface. Using the NIOS II IDE the c file lockin.c was compiled as shown is fig.4. The ptf file obtained by the SOPC builder was used to detect the CPU used for the system. The file could be compiled successfully without any errors but the elf file which was required for programming the NIOS II processor couldnt be build successfully and the NIOS II hardware simulation couldnt be performed. Hence, the NIOS II processor couldnt be programmed and the c interface couldnt be used on the board. The possible issue would be the licence for the Quartus II software. It may have 6

Singh 2011 L.C. L-Amp certain limitation of use. Also, to debug all the verilog modules for any uncertain errors required more time, which couldnt be performed due to the limitation of time for this research.

Fig.4 Compilation of c user interface lockin.c on NIOS II IDE

Singh 2011 L.C. L-Amp

Due to the error encountered on NIOS II IDE the VGA interface couldnt be programmed into the board. However, the c program was run on the DEV C++ just to display the actual user interface on pc that would have been displayed using the DE2 board. It is shown in fig.5.

Fig.5 C user interface displayed on pc

The lock-in measurements would have been very stable and it would have look something like fig.6, which is the sine wave plot displayed on the TMS (Tektronic Multisignal oscilloscope) using the ideal lock-in amplifier. This plot was just the reference plot for the verification of this research. However, the physical lock-in amplifier couldnt have been used to obtain the plot, but due to the clearance issue for the lab I was unable to do so.

Singh 2011 L.C. L-Amp

Fig.6 Waveform of the PLL locked to an irregular input function TMO

From fig.6 it can be clearly observed that the PLL output is very steady and smooth that the irregular input signal. The PLL reliably locked within ~<1s for any frequency between the lowest operating frequency of 100 KHz and 1 MHz. Above 1MHz the PLL could still lock till ~5 MHz, but occasionally had trouble locking in a timely fashion.


Building a full functioning lock-in amplifier is pretty complicated task which cost both time and money. However, using the programmable FPGA board logics, most of the analog components can be easily implemented to design and build a fully functioning low cost lock-in amplifier. Although there were several errors encountered, which were difficult to debug the goal of building the system using SOPC builder and programming the FPGA board was successfully achieved.

Singh 2011 L.C. L-Amp

Everyone taking EEGR-451 class- for supporting me Dr. James Whitney- for providing me the DE2 board and giving me the opportunity to do this project Altera forum moderators- for helping me with issues on Quartus II Gods I worship.

C source code- http://fpgalockinamp.blogspot.com/ Verilog HDL source code- http://fpgalockinamp.blogspot.com/

1. J.O Hamblen, T.S Hall and M.D Furman, Rapid prototyping of digital systems, SOPC edition , Springer 2008 2. P.P Chu FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience (February 4, 2008) 3. http://www.princeton.edu/~romalis/PHYS312/Lock-in%20amplifier.pdf 4. http://www.thinksrs.com/downloads/PDFs/ApplicationNotes/AboutLIAs.pdf 5. http://courses.cit.cornell.edu/ece576/FinalProjects/f2008/tor2/main.html 6. http://www.design-reuse.com/articles/7330/fpga-programming-step-by-step.html 7. http://www.altera.com/ 8. http://courses.cit.cornell.edu/ece576/FinalProjects/f2008/tor2/main.html