Recent Patents on Nanotechnology 2009, 3, 61-72

61

Low Energy, Low Latency and High Speed Array Divider Circuit Using a Shannon Theorem Based Adder Cell
Chinnaiyan Senthilpari*, Krishnamoorthy Diwakar and Ajay K. Singh
Faculty of Engineering &Technology, Multimedia University, Jalan Ayer Keroh lama, 75450 Melaka, Malaysia
Received: September 3, 2008; Accepted: September 26, 2008; Revised: October 6, 2008

Abstract: The paper discuses the design of 1-bit full adder circuit using Shannon theorem. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring and Restoring divider circuits. The proposed adder and divider schematics are designed by using DSCH2 CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The divider circuits are designed by using standard CMOS 0.35 m feature size and corresponding power supply 3.5 V. The parameters analyses are carried out by BSIM 4 analysis. We have compared the simulated results of the Shannon based divider circuit with CPL and CMOS adder cell based divider circuits. We have further compared the results with published results and observed that the proposed adder cell based divider circuit dissipates lower power, gives faster response, lower latency, low EPI and high throughput.

Keywords: Shannon theorem, Divider, Power dissipation, Propagation delay, BSIM 4, Latency, EPI and Throughput. 1. INTRODUCTION Digital dividers generally can be categorized as employing arithmetic operations to execute a division operation. Arithmetic dividers receive an input that combines the numerator and denominator. Look-up table implementations often require large look-up tables to be accurate for highspeed division, which is generally requiring significant processing time and chip space [1]. Many look-up table implementations also require multiple iterations to improve accuracy, which increases latency associated with the division operation. One consideration in the design of digital dividers is the throughput of the division process [2]. The throughput of the process determines the rate at which a new value can be initiated into the process and also refers as the initiation interval. The throughput of the division process generally depends on the desired precision and the algorithm used. Another consideration is the processing time required to perform the digital division operation, which corresponds to the amount of time required to perform the division process and referred as latency [2, 3]. In many conventional digital divider designs, the latency determines the overall speed of the division process. As a result, most calculationtype dividers typically provide only a few bits of precision for real-time operation. There are two kinds of array divider such as NonRestoring Array Divider (NRAD) and Restoring Array Divider (RAD) [3]. This paper deals with Non-Restoring and Restoring array divider. The Non-Restoring array divider is guessing the quotient at each stage and when it is wrong it will not correct the remainder in this stage, instead of that it would continue to go to next stage. It has some extra remainder correction circuit after the last stage to correct the last remainder output by the divider. The Non-Restoring divider is much more efficient and faster than regular
*Address correspondence to tthis author at the Faculty of Engineering &Technology, Multimedia University, Jalan Ayer Keroh lama, 75450 Melaka, Malaysia; Tel(o): +606-252 3558; Fax: +606 231 6552; E-mail: c.senthilpari@mmu.edu.my 1872-2105/09 $100.00+.00

Restoring array divider. Since the array divider has many stages, it can be efficiently pipelined [4]. More importantly, the Non-Restoring divider uses a very regular structure and each cell only needs to connect to the nearest neighbour cells, which makes it very efficient for VLSI design. The Restoring array divider circuit has controlled subtract cell which is used as the cell component of the divider circuit [3], [4]. Conventional twos complement binary subtractor is implemented using carry-propagate subtractor cell. These carry-propagate subtractors cell propagate the carry signal from the least significant bit to the most significant bit position. In this present paper, we have designed a full adder circuit by using Shannon theorem, as well as show the recent patents related to the BSIM4. This proposed adder cell is used in the Non-restoring array divider (NRAD) and Restoring array divider (RAD) circuits. The Non- Restoring and Restoring array dividers may use in DSP application circuits [5]. By using BSIM 4 parameters, the power dissipation, propagation delay, area of the 7x4 bit Nonrestoring and Restoring array divider circuits are analysed which are implemented by CPL, CMOS, Mixed Shannon and proposed Shannon. The parameter analyse of power dissipation, propagation delay, area of the divider circuit are calculated from layout simulations. The BSIM 4 parameter analyses are helpful to measure the total power dissipation of chip, Maximum quiescent current for various capacitances values and Maximum quiescent current for the various supply voltages. 2. RELATED PATENTS In the integrated circuit, the layout simulation plays important role. The vertical geomentry layouts are creating noise as well as power dissipation. This kind of errors are minimized using by BSIM 4 analyser. The inventors Checka, Nisha (Cambridge, MA, US), chandrakasan, Anantha (Belmont, MA, US) , Reif, Rafael (Newton, MA, US) are invented the substrate noise tool which is analyzing substrate noise is disclosed and capable of accepting inputs of
2009 Bentham Science Publishers Ltd.

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(a) Fig. (1). (a) Logic OR, (b) AND gate and (c) 2:1 mux.

(b)

(c)

increasing complexity and granularity. During this kind of operations, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating substrate models based on estimated die size, which is allowing the designer to have an early indication of potential substrate noise and power issues [6]. Our proposed adder based divider circuits is reduced the noise using by BSIM 4 analyzer. 3. ADDER DIVIDER ARCHITECUTE FOR THE ARRAY

output [11]. The Fig. (1) shows a basic AND, OR and 2:1 Mux circuit, that are designed using by Multiplexing Control Input Technique (MCIT). This logic gate design by MCIT technique is reduced number of transistor than conventional CMOS circuit. The elaboration of this technique is gives the proposed Shannon full adder cell. 3.1. Shannon Theorem The Shannon Theorem states that any logic expression can be expanded into two terms, the first with a particular variable setting a variable to 1, then multiplying it by the variable and then setting the variable to 0 and multiplying by the inverse. By repeating Shannon's Theorem for each variable in the expression the fullest reduction can be achieved [12]. The method lends itself to automation which is particularly useful in multiplexer and pass transistor circuit design. Shannon's Theorem can be stated in a generalized form as: A function of many variables, f(a 0, a1, a2, ..., ai, ..., an) can be written as the sum of two terms, one with a particular variable (say ai) set to 0, and other with it set to 1. f(a0, a1, a2, ..., ai, ..., an) = ai' f(a0, a1, a2, ..., 0, ..., an) + ai f(a0, a1, a2, ..., 1, ..., an) (1) Shannon's Theorem is applied to the logical function using n-1 variables as control inputs and three data lines set to a logical 1. These source inputs are then connected to the VDD lines and logical 0 connected the ground. The remaining nth variable is connected from the data input to the source input. The control signals flow vertically and the data flows horizontally. N-type transistors are placed at the intersections to satisfy the expanded Shannon function. We remove pairs of transistors where they cancel each other. The Shannon theorem output expression depends upon the pass logic 1 or logic 0. If it has 0 logic, the connection input is given by 0 and by 1 for the connection input 1. 3.1.1. Architecture of the Proposed Adder Cell Our proposed full adder circuit is designed by using Shannon theorem. The full adder sum and carry circuits are designed based on standard adder circuit equations [7]. An input B and its complement are used as the control signal of the sum circuit which is shown in Fig. (2). The two-input XOR gate is developed using the multiplexer method. The output node of the two-input multiplexer circuit is the differential node. According to standard full adder equation

The Non-Restoring and Restoring array dividers circuits are implemented by using Shannon based adder cell and compared with CPL, CMOS and mixed Shannon adder cell based divider circuits. The main concept behind CPL is the use of an NMOSFET network for the implementation of logic functions [7, 8]. The complementary principle of the CPL adder circuit topology, with inverted pass signals, produces the complementary logic function in CPL. The pass variables are directly passed from the inputs to the outputs; therefore, inversion of the pass variables yields the complementary function. The CPL circuit also uses the lowest power per gate during the logic transition which makes it suitable for memory circuit. A CPL circuit can be designed using any number of tool; this flexibility contributes to a low design cost and encourages regular and easily automated layout styles [9]. The CPL circuit has some drawbacks due to body effects, source follower action, high leakage power when not crosscoupled, lower performance at large stage counts and limited fan-out capability. Passtransistor logic consists of complementary inputs and outputs and an NMOS pass transistor network. Since, simply by exchanging the input nodes, two inputs AND, OR and multiplexers circuits can be constructed [7], therefore, by using duality method the adder trees are implemented [9]. According to Reto Zimmermann [10] CMOS full adder circuit depicts a two-input multiplexer gate (MUX2) in pure CMOS and CMOS with pass-gates respectively [10]. The design of 2:1 MUX needs two data inputs A and B, as shown in Fig. (1c). The data inputs are given through the source input of the transistor and control inputs are given through gate of the pass transistors. The multiplexer circuit have two possible inputs, and basically the idea is to label these two choices with as few bits as possible. When control input c = 0, B is directed to the output. When control input c = 1, A is directed to the output. Here, we the control input c to specify the subscript of the input which we want to direct to the

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is represented by all zeros. The relationship between a number and its signed 2's complement equivalent is formalized in the equation (2);
(b b k k b 1 k 2 k 1 b ....b b b ) = (( 1) k (b + (b 2 1 0 2 k k i=0 b )2i ) i 10

C S C

(2) 3.2. Non-Restoring Divider Binary division is basically a procedure to determine how many times the divisor D divides the dividend A thus resulting in the quotient Q [1, 3]. At each step in the process the divisor D either divides A into a group of bits or it does not. The divisor divides a group of bits when the divisor has a value less than or equal to the value of those bits. Therefore, the quotient is either 1 or 0. A basic Nonrestoring divider cell consists of a full adder and a XOR gate. It will read the practical remainder from the previous stage and depending on the quotient of the last stage it will add the divisor to obtain the remainder for next stage. In this paper the gate level schematic of full adder cells are used to obtain the FET level schematic, which pertains our proposed adder cells. After the design of one divider cell, we can tile them in two dimensions to form a matrix, depending on the number of the bits in divisor and dividend. The Non-restoring array divider cell consists of full adder, and 2 inputs X-OR cells. The divider circuit can be roughly divided into two halves. The upper half consists of the four stages of cascaded full adders in the top half of the Fig. (3), in which the number of stages is dependent on the number of dividend bits and the number of cascaded full adders being dependent on the number of divisor bits. In this 7 x 4 bit divider circuit, there are four stages for the seven dividend bits and four cascaded full adders for the four divisor bits. The four most significant bits of the dividend are used in the first stage of the cascaded full adders and then each succeeding stage uses one more dividend bit, plus three bit from the preceding stage (hence four stages). If additional dividend bits and/or divisor bits are desired, then each additional dividend bit would correspond to one stage of cascaded full adders and each additional divisor bit would correspond to another cascaded full adder in each stage [10, 12]. 3.3. Restoring Array Divider The Restoring array division circuits produce one digit of the final quotient per iteration as shown in Fig. (4). The Restoring array division methods start with a close approximation to the final quotient and produce twice as many digits of the final quotient on each iteration [2]. All division methods are based on the form Q=N/D where Q =Quotient N= numerator (Dividend), D= Denominator (divisor). Restoring division operates on fixed-point fractional numbers and depends on the following assumptions: N<D, D<1 the quotient digits q are formed from the digit set {0, 1}. 4. RESULTS AND DISCUSSION The Non-Restoring and a Restoring array divider circuit are designed using adder cell and subtractor cell respectively. In Non-restoring array divider to get a rough estimate of the propagation delay, Microwind 3 simulation was performed

Cout

Fig. (2). Proposed Shannon adder.

[8], the sum circuit needs three inputs. In order to avoid increasing the number of transistors due to the addition of a third input, the following arrangement is made; the CPL XOR gate is multiply with Cs complement input and EXNOR gate is multiplied with input C and this reduces the number of transistors in the sum circuit. Compared with our previous paper [13], this kind of arrangement cause an increase in the number of transistors but this arrangement avoids the critical path delay. The C and C output node is called the differential node of the circuit [12]. The differential node output is a summing output, as given in Standard full adder equation [10]. The full adder carry circuit is designed by using fundamental Shannon equation. The source inputs are connected with logic 1, which results always ON condition for the transistor. The actual inputs AB, BC and CA are connected in parallel to give the output C=AB +BC+ CA. Two complementary ( C and B ) inputs are used in the full adder carry circuit for the balancing the circuit and to avoid the floating wire concept. The circuit works according to the standard carry equation [10]. In this circuit, all of the pass inputs are connected at V DD line so that the pass gates are always on. The control input terminals are connected the function inputs. 3.1.2. Complement Subtractor To find the value (A-B), if assume that the input A is greater than B, we can use only 2s complement method, which is clearly shown in Fig. (1). In this method, 2s comple-ment of B is to be added to A and the end around carry is to be ignored. All the bits of B is complemented to get 1s complement of B and then to the least significant bit B0 is added with 1to get 2s complement of B. the right most full adder adds A0, B0 and 1. The immediate left full adder circuit adds A1, B1, and C0 and so on. The end carry is ignored. The results A-B is given by DN.D1D0. Signed 2's complement is a modification of the sign-magnitude form in which addition and subtraction of the full adder circuit performed. The high order bit is still the sign bit and logical 1 still indicates a negative number [14]. Furthermore, zero

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d0
0

d1

d2

d3

d0
CAS CAS CAS CAS
4

q0

q1

CAS

CAS

CAS

CAS
5

q2

CAS

CAS

CAS

CAS
6

q3

CAS

CAS

CAS

CAS

T0

T1

T2

T3

Fig. (3). Non-restoring Divider architecture.

Z1 D1 Z2 D2 Z3 D3 Z4 D4 Z5

Q1

FS Cell

FS Cell

FS Cell

FS Cell

D1 Q2

FS Cell

D2

FS Cell

D3

FS Cell

D4

FS Cell

0
Z7

D1 Q3

FS Cell

D2

FS Cell

D3

FS Cell

D4

FS Cell

0 Z8

D1 Q4

FS Cell

D2

FS Cell

D3

D4

FS Cell

FS Cell

S3

S4

S5

S6

Fig. (4). Restoring Array Divider (RAD).

for the full adders. The propagation delay for each of these components was then used in estimating the propagation delay for the entire circuit. The worst-case scenario for the delay was determined to be the one in which all inputs was set to logic high. The speed of the divider circuit can be determined by the maximum delay along with critical path. A propagation delay of divider circuit for conserving power on a semiconductor chip is provided. The circuit includes a delay chain responsive to a input signal for generating an output signal having a selectively adjustable delay at an output circuit. The delay chain techniques have been developed to reduce the energy dissipation of CMOS design systems. The minimization of power can be carried out by reducing the supply voltage, the capacitance, the number of transitions (e.g. the activity in the circuit) and by optimizing the timing of the signals. A large impact on energy is made

by the supply voltage. By reducing VDD the energy dissipation decreases quadratically but the delay increases and the performance is degraded. A possible solution is that of using different supply voltages in different parts of the circuit. The parts not in the critical path are supplied by lower voltages, while the critical one by the higher voltage [15]. Another technique is to compensate the loss of performance by replicating the hardware (parallelism) to keep the throughput. Table I shows the simulation results of MCIT AND gate, OR gate and 2:1 Mux circuit for various feature size. The corresponding power supply is also mentioned in the Table I. The Designed MCIT logic gates are compared with conventional CMOS AND, OR and 2:1 Mux circuit. From the simulated results it is observed that MCIT based circuits

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Table I. Power Dissipation, Propagation Delay, Area Throughput, Latency, EPI and Number of Transistor of the and, or and 2:1 Mux Circuits
0.5V [50nm] gates Parameter Our PD ( W) AND Delay (ps) Area ( m)2 PD ( W) OR Delay (ps) Area ( m)2 PD ( W) 2:1 MUX Delay (ps) Area ( m)2 0.014 7 28 0.044 8 28 0.021 5 28 Conv 0.062 120 70 0.072 165 80 0.091 70 40 Our 0.049 9 32 0.055 12 32 0.038 6 32 Conv 0.072 130 96 0.169 124 96 0.118 96 66 Our 0.110 12 50 0.416 18 50 0.165 8 50 Conv 0.318 159 144 1.242 160 144 0.456 104 90 Our 0.386 18 66 0.942 20 66 0.293 14 66 Conv 0.462 174 180 1.57 218 180 0.786 110 126 Our 0.755 20 220 0.997 24 220 0.782 16 220 Conv 0.645 180 462 2.662 130 462 1.342 116 300 Our 3.85 26 350 1.799 30 350 1.293 22 350 Conv 1.238 200 729 4.239 236 729 1.675 132 450 Our 4.157 47 880 6.6 54 880 1.586 26 880 Conv 7.04 208 1680 8.6 419 1680 3.564 148 1680 0.7V [70nm] 1.0V [90nm] 1.2V [120nm] 2V [180nm] 2.5V [0.25m] 3.5V [ 0.35m]

(Our=proposed MCIT circuit Conv = conventional circuit (CMOS))

gives better performance than conventional CMOS circuit. Table II shows the simulated results in terms of power dissipation, delay and area of 1 bit full adder cell designed by using Shannon based adder, CPL and CMOS and mixed Shannon based adder for different feature size. It is observed that for any feature size, the proposed adder cell dissipates lower power and gives faster response than the other techniques. A tremendous improvement in performance is observed in our proposed cell compared to CPL based adder cell and CMOS based adder cells. Table III gives the comparison results of our proposed design with other published 1 bit cell. All the circuits are simulated by using Microwind VLSI CAD tool. Our proposed circuit is dominating in terms of the propagation delay, PDP and power consumption than ref [15,16]. This 2s complement subtractor circuit is used for the array cell of the Restoring array divider circuit. The 2s complement subtractor circuit are designed using proposed Shannon based adder, mixed Shannon based adder, CPL adder and CMOS adder. The parameters like power dissipation, propagation delay and area are given in Table IV for various feature size and correspondingly supply voltage. Our Shannon theorem based subtractor circuit gives less power dissipation and lower delay than other circuits. The proposed 4-bit Shannon based subtractor circuit is passing the signal to execute fast shifting. Table V compares the proposed subtractor circuit with Adiseno [17], S.Nikolaidis [18], A.Chatzigeorgiou [19] and mixed Shannon subtractor [5] in terms of propagation delay, load capacitance and speed. Our proposed circuit is faster than other reported circuit [6, 17-19]. In our circuit, the fast shifter of logical input has speed approximately 0.52GHz. The proposed circuit signal is operated at 100MHz/107.5mV without any loss of power. Timing analysis of a proposed subtractor circuit can be performed either by calculating the output voltage at each time step or by simply calculating the propagation delay and the slope of the output at the half-VDD point in order to define an equivalent signal for the output

waveform, that can be fed as input to the next stage. The contribution of the program complexity in terms of region boundaries and branching between them on the total execution time is more intense when only the propagation delay is calculated rather than the full output waveform [18, 19]. Our proposed Shannon adder cell consists of 16 transistors and mixed Shannon based adder cell consists of 12 transistors compare to CPL-18 transistor and CMOS -28 transistors. The two different (Non-Restoring and Restoring array) 7x4 bit divider circuits are simulated by using Microwind 3 VLSI CAD tool. All the outputs checked from 1111111 1000 to 111111 1111. Various parameters such as area, propagation delay, dissipated power, throughput, latency and EPI are determined from array dividers layout of feature size 0.35 m. The divider circuits are analyzed using BSIM 4 parameter analyzer and results are given in Table VI. Our proposed Shannon adder based Non-Restoring array divider circuit gives less power dissipation, lower delay, low EPI, low latency and high throughput compared with mixed Shannon, CPL and CMOS based array divider circuits due to lower critical path in our proposed adder cell. Similarly, dominance reflects in the restoring array divider circuit in terms of power, delay, EPI, latency and throughput. Our Shannon based Non-restoring array divider circuit shows an improvement of 12.16% in propagation delay, 2% in EPI, 81.87% in latency and 65.32% in throughput compared to Shannon based Restoring array divider circuit. The Restoring and Non-restoring divider circuits implemented by using our proposed Shannon based adder cell dissipates lower power than CPL, CMOS and mixed Shannon based adder cell divider circuits irrespective of power supply as seen from Fig. (5). The power dissipation, supply voltage versus total quiescent current (IDD), capacitance versus dynamic power dissipation and capacitance versus quiescent current (IDDQ) are measured using BSIM4 layout parameter. The

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Table 2.

Comparison of Power Dissipation, Propagation Delay and Area for 1-bit Adder Cell Designed with Different Technique
Supply Voltage Power W 0.5V [50nm] 0.042 2 15x7 0.309 6 16x7 0.817 14 43x8 1.49 654 25x7 0.7V [70nm] 0.371 4 22x10 0.437 12 16x9 2.247 23 19x10 3.76 854 53x10 1.0V [90nm] 0.442 6 23x11 0.513 18 17x10 3.249 31 20x12 7.06 971 67x14 1.2V [120nm] 0.569 13 28x14 0.658 22 20x9 4.907 81 24x14 10.69 995 74x11 2V [180nm] 1.984 23 37x26 2.529 25 19x12 9.936 87 49x28 14.04 1000 93x26 2.5V [0.25 m] 12.04 29 62x32 14.8 49 52x30 14.782 205 62x35 25.34 1401 117x32 3.5V [0.35m] 24.88 54 84x52 31.13 70 82x48 29.69 324 98x56 29.10 1602 186x52

Adder Type

5V [0.6m] 58.6 114 142x80 84.05 105 124x74 48.75 640 148x86 32.25 1995 280x80

Shannon

Delay (ps) Area (m )

2

Mixed Shannon [13]

Power W Delay (ps) Area (m ) Power W

2

CPL

Delay (ps) Area (m ) Power W

2

CMOS

Delay (ps) Area (m2)

Table 3. Comparision Table of 1-bit Proposed Shannon Based, CPL and CMOS Adder Cells in Terms of Power Dissipation, Propagation Delay, PDP and Area
Supply Voltage 2V 2.5V Mixed Shannon Proposed [13] Chang et al. [15] Hybrid Chang et al. [15] CCMOS 2V 2.5V 2V 2.4V 2V 2.4V 2V 2.4V Chang et al. [15] TFA 2V 2.4V 2V 2.4V Chang et al. [15] 14-T 2V 2.4V Chang et al. [15] 10T Alito et al. [16] CMOS 2V 2.4V 1.8V Power Watt 1.984 12.04 2.529 14.8 8.71 15.9 8.77 15.9 11.2 17.7 10.6 17.6 10.0 16.8 18.8 31.0 56.5 86.4 5.472 % Reduction ------21.55 16.21 77.21 24.27 77.267 24.27 82.28 31.97 81.28 31.59 80.16 28.33 89.44 61.16 96.48 86.06 63.74 Delay ns 23 29 0.025 0.049 0.256 0.231 0.269 0.244 0.179 0.173 0.274 0.252 0.274 0.250 0.303 0.268 1.85 0.584 1.46 % Reduction ------8 40.8 91.01 87.44 91.44 88.114 87.50 83.23 91.6 88.49 91.6 88.4 92.40 89.17 98.75 95.03 98.42 0.0632 0.725 2.230 3.673 2.359 3.880 2.005 3.062 2.862 4.435 2.740 4.125 5.94 7.94 104.5 50.5 7.99 PDP fJ Area m2 962 ---228 ---78.76 ---100.05 ---136.64 ---96.57 ---134.88 ---68.24 ---70.56 -------

Adder Type

% Reduction ------27.84 51.86 97.95 90.49 98.06 91.00 97.72 88.60 98.4 92.13 98.33 91.53 99.23 95.60 99.56 99.3 99.42

% Reduction -------76.29 ----91.81 ----89.59 ----85.79 ----89.96 ----85.97 ----85.97 ----92.66 -------

Shannon Proposed

Chang et al. [15] CPL

Chang et al. [15] TGA

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Adder type

Supply Voltage 2.5V

Power Watt 11.45 5.29 11.04 9.62 18.93 5.79 11.69 4.72 10.09 4.655 9.23 7.641 15.39

% Reduction -4.9 62.49 -8.3 79.37 36.39 65.73 -2.9 57.96 -16.19 57.37 -23.33 74.03 21.76

Delay ns 0.870 1.49 0.890 1.060 0.671 1.720 0.753 0.564 0.244 0.471 0.200 1.490 0.860

% Reduction 96.66 98.45 96.74 97.83 95.67 98.66 96.14 95.92 88.11 95.11 85.5 98.45 96.62

PDP fJ 9.96 7.88 9.83 10.2 12.70 9.96 8.81 2.66 2.46 2.19 1.85 11.39 13.24

% Reduction 99.49 99.42 96.44 99.55 97.25 96.49 96.03 98.28 85.81 97.91 81.13 99.59 97.36

Area m2 595 ---528 ---1091 ---471 ---252.5 ---494 ---659

% Reduction -38.14 ----45.11 ----11.82 ----51.03 ----73.80 ----48.64 ----31.49

Alito et al. [16] Mirror Alito et al. [16] CPL

1.8V 2.5V 1.8V 2.5V 1.8V 2.5V 1.8V 2.5V 1.8V 2.5V

Alito et al. [16] LEAP

Alito et al. [16] LP

Alito et al. [16] TG

Alito et al. [16] TG drivecap

1.8V 2.5V

Table 4. Power Dissipation, Propagation Delay and Area for 1bit Proposed Shannon Based, CPL and CMOS 2S Complement Based Subtractor Cells
Subtractor Type 0.5V [50nm] 0.102 10 15x7 0.134 23 16x7 0.144 11 13x8 0.186 13 41x7 0.7V [70nm] 0.140 14 22x10 0.224 36 16x9 0.455 19 19x10 0.484 15 60x10 1.0V [90nm] 0.233 27 23x12 0.373 42 17x10 1.766 35 20x12 1.205 28 83x12 1.2V [120nm] 0.487 34 28x14 3.168 53 20x13 2.315 77 24x14 1.256 31 75x14 2V [180nm] 1.7 48 57x27 4.769 62 41x24 10.894 95 49x28 6.493 72 105x26 2.5V [0.25m] 4.45 54 72x34 14.50 68 52x30 24.369 191 62x35 14.117 82 132x32 3.5V [0.35m] 21.574 68 114x54 16.648 71 82x48 70.476 290 98x56 26.8 113 210x52 5V [0.6m] 33.161 144 172x83 44.74 314 124x74 141.06 369 148x86 38.645 261 316x80

Supply Voltage Power W

Shannon

Delay (ps) Area (m ) Power W

2

Mixed Shannon

Delay ps Area (m2) Power W

CPL

Delay ps Area (m ) Power W

2

CMOS

Delay ns Area (m )
2

Table 5.

Subtractor Compariosn in Terms of Propagation Delay, Load Capacitance (CL) and Speed
Proposed Shannon 84.671 0.35 100 12.180GHz Mixed Shannon [5] 92.134 0.35 100 11.098GHz Reference (6) 110 0.35 100 9.0859GHz Reference [17] 0.35 100 2.5GHz Reference [18] 252 0.35 100 Reference [19] 132 0.35 100 -

Parameters Propagation delay (ps) Feature CL Speed

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Table 6. Non-Restoring Array Divider and Restoring Array Divider of Feature Size 0.35V: Comparision in Terms of Power Dissipation, Propagation Delay, Area, EPI, Latency and Throughput
Delay (ps) 260 295 2264 522 296 446 3226 664 EPI (Watts/IPS) 0.794 x10
-9

Feature Size

Type of Adder Shannon

Power (mW) 0.617 1.231 1.977 2.7930 0.5773 0.5933 0.3108 0.669

Area m2 1512x76 1562x89 1818x105 1858x141 2012x125 1542x93 1798x99 2010x147

Latency n 2.308 8.72 20.112 16.176 12.736 18.624 59.616 21.776

Throughput GHz 3.623 1.8848 0.3977 1.259 1.2562 0.859106 0.268384 0.7347

Non-Restoring Array Divider

Mixed Shannon CPL CMOS Shannon

0.7604 x10-9 0.788 x10

-9

0.7028 x10

-9

0.7788x10-9 0.7626x10 0.6981x10

-9

Restoring Array Divider

Mixed Shannon CPL CMOS

-9

0.7154x10-9

90
Shannon (NRAD)

80

MixedShannon (NRAD) CPL (NRAD) CMOS (NRAD) Shannon (RAD) Mixed Shannon (RAD) CPL (RAD) CMOS (RAD)

Power dissipation(mW)

70 60

50 40 30 0 0.5 1 1.5 2 SupplyVoltage 2.5 3 3.5

Fig. (5). Supply Voltage Versus power dissipation.

parameters are calculated from total transistors of the circuit, wires, and input/output pads. Power in modern digital CMOS integrated circuits has traditionally been dominated by dynamic switching power. However, as technology scales leakage currents become increasingly large and must be taken into account to minimize total power consumption [20]. Once the magnitude and general shape of the curve has been examined, the measurements can be done using a linear scale for current. The 7x4 bit divider layout is placed in the state where the electrical failure mode is active [20, 21]. The supply voltage versus maximum IDD current (mA) of NonRestoring and Restoring array divider circuit is shown in Fig.

(6). As seen from Fig. (6), the maximum operating current of divider circuit increases as the supply voltage increases, irrespective of design technique. Other important observation is that the proposed divider circuits show less increase in IDD max compared to CPL, Mixed Shannon and CMOS adder based divider circuits. The circuit layout total capacitance versus total power dissipation and maximum IDD of the divider circuits are shown in Fig. (7) and Fig. (8). Our Shannon adder based divider circuits give lower operating current at any

Functional Polymeric Nanofibers from Electrospinning

Recent Patents on Nanotechnology 2009, Vol. 3, No. 1

69

80

Shannon (NRAD) Mixed Shannon (NRAD) CPL (NRAD) CMOS (NRAD) Shannon (RAD)

100
Shannon (NRAD)

70

90 80
Quiscent Current (mA)

MixedShannon (NRAD) CPL (NRAD) CMOS (NRAD) Shannon (RAD) Mixed Shannon (RAD) CPL (RAD) CMOS (RAD)

Quiescent Current(mA)

60

50

Mixed Shannon (RAD) CPL (RAD) CMOS(RAD)

70 60 50 40 30 20

40

30

20 0 0.5 1 1.5 2 Voltage 2.5 3 3.5

20

40 60 Capacitance (pF)

80

100

Fig. (6). Supply Voltage versus quiescent IDD current (mA).

Fig. (8). Capacitance Versus Power Dissipation (mW).

100 90 80
Shannon (NRAD) Mixed Shannon (NRAD) CPL (NRAD)
CMOS (NRAD)

Power Dissioation (mW)

70 60 50 40 30 20

Shannon (RAD) Mixed Shannon (RAD) CPL (RAD) CMOS (RAD)

Maximum Drain current is dependent on the duration of the simultaneous on-times of the pull-up and pull-down networks, the transistor sizes, and the supply voltage level. The magnitude of drain current depends on the area of the drain diffusion and the leakage current density, which determines the operating current of the proposed circuit. Our proposed circuit designed by using NMOSFET tree structure, gives balanced path [3, 21]. The dynamic leakage current can be determined by varying load capacitance value (CL). In Table VII we are showing the comparison with other existing simulated results. As seen, there is significant improvement in delay, EPI and throughput but we get reduction in power and Latency in our proposed circuit. Our proposed Shannon adder based divider circuit is giving better performance than mixed Shannon based divider circuit [5], Schwarzbcher [22], Scott [23], Anders [24] and Tung [25] circuits in terms of power dissipation, propagation delay and area. The Shannon adder based circuit is compared with Schwarzbacher et.al [22] in terms propagation delay and observed a improvement than 99.4 to 99.8%. The Scott [23] NCL and NCL (opt) circuits gives higher propagation delay which are approximately 99.96% and 100.11% respectively. The Shannon theorem based dividers circuits are compared with Tung et al. [25] Radix 4 SRT (0.7V) NVT and NVT+HVT and NVT+HVT+LVT circuits in terms power dissipation, propagation delay and area. Our proposed circuit gives better performance. The power improvement in our proposed circuit is varying from 94.09% to 94.97% and propagation delay improvement varies from 98.55% to 98.63%. We also compared the simulated results of our circuits with Ray et al. [26] and Tung et al. [25] circuits in terms of EPI and latency. Our divider circuit gives tremendous improvement in energy. The energy per instruction reduced

20

40 60 Capacitance (pF)

80

100

Fig. (7). Capacitance versus Maximum IDD Current.

capacitance values as seen in Fig. (6) and also gives lower power dissipation than CPL, Mixed Shannon and CMOS adder cell based divider circuits. So our proposed adder based divider circuits can be used in lower power operating circuits. The load capacitance (CL) represents the power dissipated during a switching event, i.e., when the output node voltage of our divider circuit makes a power consuming transition. Generally, in digital CMOS circuits dynamic power is dissipated when energy is drawn from the power supply voltage to charge up [21].

70 Recent Patents on Nanotechnology 2009, Vol. 3, No. 1

Senthilpari et al.

Table 7.

Power, Delay and Area Comparsion with Published Results

Author Types CAS (5V) CAS (3.5V) CAS (2.5V) CAS (2V) Power mW 2.686 0.671 0.434 0.1349 3.3414 1.231 0.4610 0.1729 ---------------------27 4.8 2.93 % ------------19.61 45.49 15.08 21.19 ---------------------95.44 96.39 94.09 Delay 414ps 392ps 295ps 210ps 628ps 240ps 161ps 108ps 21.43n 13.03n 16.36n 64.5n 22.79n 75.92n 64.33n ------1.90ns % ------------34.07 38.77 45.42 48.57 99.87 99.80 99.84 99.95 99.88 99.96 100.11 ------98.63 Area(m2) 2011x239 2010x137 1297x61 1037x49 2014x218 1562x89 977x56 581x25 ---------------------------15235 % -------------8.65 -49.51 -30.84 -71.41 ---------------------------4.6

Our Proposed Shannon adder cell (NRAD)

Mixed Shannon adder cell [13]

CAS (5V) CAS (3.5V) CAS (2.5V) CAS (2V)

A. Th. Schwarzbacher et al. [22] 2000

Petry(2.5V) LUT(2.5V) RNS(2.5V) SBD(2.5V) SBD(opt) (2.5V)

Scott C. Smith et al. [23] 2004 Anders et al. [24] 2003 Tung N. Pham et al. [25] 2006

NCL (2.5V) NCL(opt) (2.5V) SRT(3.3V) SRT (2V) Radix 4 SRT (0.7V) NVT NVT +HVT NVT+HVT+LVT

3.23 3.44

94.64 94.97

1.90ns 1.80ns

98.63 98.55

15471 15803

6.11 8.08

Table 8.

Comparsion of EPI, Latency and Throughput with Published Results

Types Shannon adder (NRAD) EPI x10-9 0.7604 0.77883 ---------78 86 87 ---------------99.02 99.11 99.12 ---------------% ------Latency 8.72 18.624 63 57.25 55 14 14 14 18 22 16 25 14 % ------86.15 84.76 84.14 37.71 37.71 37.71 51.55 60.36 45.5 65.12 37.17

Author Our Proposed

Shannon adder (RAD) Arbitrary Random # F3 RayC.C.Cheung et al. [26] 2007 Arbitrary Random # F2 Arbitrary Random # F1 NVT Tung N.Pham et al. [25] 2006 NVT +HVT NVT+HVT+LVT SRT (8) Newton-Raphson (tmul=3) i=8 Stuart F. Oberman et al. [27] 1997 Newton-Raphson (tmul=3) i=16 Series Expansion (tmul=3) PL Series Expansion (tmul=3) NPL

Functional Polymeric Nanofibers from Electrospinning (Table 8) Contd. Author Types A Quotient App (tmul=3) i=8 A Quotient App (tmul=3) i=16 Short Reciprocal (tmul=2) i=8 Short Reciprocal (tmul=2) i=16 Round/Prescale (tmul=3)PL Round/Prescale (tmul=3) NPL EPI x10-9 ------------------[8]

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% -------------------

Latency 24 15 29 17 28 26

% 63.66 41.86 69.93 48.70 68.85 66.46

to 78% to 87% compared with Tung et al. [25] SRT divider circuit. The Shannon adder based divider circuits latency is compared with Tung et al. [25], and observed lower latency in proposed circuits. The Ray et al. [26] circuit is compared with our Shannon adder based divider circuit, our circuit latency is reduced about 84.14% to 86.15% from Ray et al. [26] circuits. Our proposed divider circuits are compared with Stuart et al. [27] SRT 8-bit, Newton Raphson 8th bit, 16th bit, Series expansions pipeline method, non pipeline method, 8th bit quotient approximation, 16th quotient approximation, short reciprocal 8th, 16th Round/prescale pipeline and round/prescale non pipeline method. Our divider circuit gives better latency than Stuart et al. [27] circuits, which is shown in Table VIII. CURRENT & FUTURE DEVELOPMENT The 7x4 bits Non-restoring array divider and Restoring array divider circuit are designed using Shannon based adder cell technique. The proposed Shannon based adder cell dominates CMOS and CPL design technique in terms of power dissipation, propagation delay, area, EPI, throughput and latency. The Shannon based adder cell gives better performance in terms of power dissipation, propagation delay, area, throughput and latency due to less critical path compared to other published circuits. Our circuit may be used in DSP circuits due to its low delay, lower power dissipation, lower energy per instruction and high throughput. REFERENCES
[1] Jen-Shiun C, Eugene L, a Jun-Yao L. A radix-2 non-restoring 32b/32-b ring divider with asynchronous control scheme. Tamkang J Sci Eng 1999; 2(1): 37-43. Bhat M, Crawford J, Morin R, Shiv K. performance characterization of decimal arithmetic in commercial java workloads. Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on 25-27 April 2007. pp. 54 - 61. Digital Object Identifier 10.1109/ISPASS. 2007.363736. Behrooz P. Computer arithmetic algorithms and hardware designs. Oxford University Press 2000; 19: 512583-512585 Koren K. Computer arithmetic Algorithms. 2nd Edition Library of congress cataloging-in-publication 2002; 1:56881:160-168. Senthilpari C, Diwakar K, Prabhu CMR, Ajay K S. Power deduction in digital signal processing circuit using inventive cpl subtractor circuit. ICSE '06. IEEE International Conference Publication 2006; 820-824. Checka, N., Chandrakasan, A., Reif, R.: US20070067747 (2007). Markovi D, Nikoli B, Oklobdija VG. A general method in synthesis of pass-transistor circuits. Microelectr J 2000; 31: 991-998.

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