Print Vlsi

EC 2357 VLSI DESIGN LAB
MAAMALLAN INSTITUTE OF TECHNOLOGY

SRIPERUMPUDHUR-602105
DEPARTMENT OF ECE
LABORATORY RECORD NOTE BOOK

NAME REG NO CLASS SUBJECT : ____________________________________________________ : ____________________________________________________ : ____________________________________________________ : ____________________________________________________
MAAMALLAN INSTITUTE OF TECHNOLOGY

SRIPERUMPUDHUR-602105
CERTIFICATE
Certified to be the bonafide record of work done by __________________________________of ___________________________ in _____________________________ laboratory during the academic year 2011-12 .
Faculty Incharge
Submitted for the exam held on ____________
INTERNAL EXAMINER
EXTERNAL EXAMINER
EC 2357 VLSI DESIGN LAB INDEX

EX.NO DATE NAME OF THE EXPERIMENT PAGE NO. SIGN
1. COMBINATIONAL CIRCUIT DESIGN

1.1 ADDERS 1.1.a 1.1.b 1.1.c RIPPLE CARRY ADDER CARRY SAVE ADDER CARRY SELECT ADDER 1.2 MUX AND DEMUX 1.2.a 1.2.b DEMULTIPLEXER MULTIPLEXER 1.3 ENCODER AND DECODER 1.3.a 1.3.b 1.3.c ENCODER DECODER PRIORITY ENCODER 1.4 MULTIPLIER 1.4.a ARRAY MULTIPLIER 1.5 CODE CONVERTERS 1.5.a 1.5.b BCD TO GRAY CODE CONVERTER EXCESS 3 TO BCD CODE CONVERTER 50 54 43 29 34 39 19 24 5 10 15
2. SEQUENTIAL CIRCUIT DESIGN

2.1 2.2 2.3 ACCUMULATOR PSEUDO RANDOM SEQUENCE GENERATOR BINARY COUNTER 58 63 68

2.4 MOD-10 COUNTER 73
3. DESIGN IMPLEMENTATION IN FPGA

3.1 3.2 ALU FULL ADDER 78 82
4. LAYOUT DESIGN USING MICROWIND

4.1 4.2 4.3 CMOS INVERTER LAYOUT DESIGN LOGIC GATES LAYOUT DESIGN DIFFERENTIAL AMPLIFIER LAYOUT DESIGN 85 91 98
EXP NO: 1.1 a RIPPLE CARRY ADDER AIM: To write a verilog HDL program for ripple carry adder and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module RCA(s,cout,a,b,cin); output [7:0] s; output cout; input [7:0] a,b; input cin; wire c1,c2,c3,c4,c5,c6,c7; fulladd fa0 (s[0],c1,a[0],b[0],cin), fa1 (s[1],c2,a[1],b[1],c1), fa2 (s[2],c3,a[2],b[2],c2), fa3 (s[3],c4,a[3],b[3],c3), fa4 (s[4],c5,a[4],b[4],c4),
DATE:

fa5 (s[5],c6,a[5],b[5],c5), fa6 (s[6],c7,a[6],b[6],c6), fa7 (s[7],cout,a[7],b[7],c7); endmodule SUB PROGRAM: module fulladd(s,cout,a,b,cin); output s; output cout; input a,b; input cin; wire e,f,g; assign e=(a^b),f=(e&cin),g=(a&b); assign s=(e^cin),cout=(f|g); endmodule TEST BENCH(VERILOG): module RSATB_v; // Inputs reg [7:0] a; reg [7:0] b; reg cin; // Outputs wire [7:0] s; wire cout; // Instantiate the Unit Under Test (UUT) RSA uut ( .s(s), .cout(cout), .a(a),

.b(b), .cin(cin) ); initial begin // Initialize Inputs a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule RTL SCHEMATIC:
SYNTHESIS REPORT: ======================================================================== * Final Report *
======================================================================== Final Results RTL Top Level Output File Name : RCA.ngr

Top Level Output File Name Output Format Optimization Goal Keep Hierarchy : RCA
: NGC : Speed : NO
Design Statistics # IOs Cell Usage : # BELS # LUT3 : 16 : 16 : 26 : 17 :9 : 26
# IO Buffers # # IBUF OBUF
======================================================================== Device utilization summary: --------------------------Selected Device : 3s100etq144-4 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 26 26 out of 108 24% 9 out of 960 0% 0%
16 out of 1920
SIMULATION OUTPUT:
RESULT:

Thus a verilog HDL program was written for ripple carry adder and its output was verified. EXP NO: 1.1 b CARRY SAVE ADDER AIM: To write a verilog HDL program for carry save adder and verify its output. SOFTWARE REQUIRED: Xilinx ISE10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module CSA(d,a,b,e); output [4:0] d; input [3:0] a,b; input e; wire s1,s2,s3,c0,c1,c2,c3,c4,c5,c6,c7; fulladd fa1(d[0],c7,a[0],b[0],e), fa2(s3,c6,a[1],b[1],e), fa3(s2,c5,a[2],b[2],e), fa4(s1,c4,a[3],b[3],e), fa5(d[1],c3,c7,s3,e), fa6(d[2],c2,c6,c3,s2), DATE:
10

fa7(d[3],c1,c5,s1,c2), fa8(d[4],c0,c4,c1,e); endmodule SUB PROGRAM: modulefulladd(s,cout,a,b,cin); output s; outputcout; inputa,b; inputcin; wiree,f,g; assign e=(a^b),f=(e&cin),g=(a&b); assign s=(e^cin),cout=(f|g); endmodule TEST BENCH(VERILOG): moduleCSATB_v; // Inputs reg [3:0] a; reg [3:0] b; reg e; // Outputs wire [4:0] d; // Instantiate the Unit Under Test (UUT) CSA uut ( .d(d), .a(a), .b(b), .e(e) );
11

initial begin // Initialize Inputs a = 0; b = 0; e = 0; // Wait 100 ns for global reset to finish #100;
// Add stimulus here end endmodule
RTL SCHEMATIC:
======================================================================== Final Results RTL Top Level Output File Name : CSA.ngr 12

Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # # LUT2 LUT3 LUT4 MUXF5 : 17 :1 :2 : 12 :2 : 14 :9 :5 : 14 : CSA
: NGC : Speed : NO
======================================================================== Device utilization summary: --------------------------Selected Device : 3s100etq144-4
Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs:
8 out of
960
0% 0%
15 out of 1920 14 14 out of 108
12%
13
SIMULATION OUTPUT:
RESULT:
14

Thus a verilog HDL program was written for carry save adder and its output was verified.
EXP NO: 1.1 c CARRY SELECT ADDER AIM: To write a verilog HDL program for carry select adder and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module csa(s,cout,a,b,cin); output [7:0]s; outputcout; input [7:0]a,b; inputcin; wire c0,x,y,ctop,cbot; wire [7:4] stop,sbot; assign x=0,y=1; 4ripple rca1([3:0]s,c0,[3:0]a,[3:0]b,cin); rca2([7:4]sbot,cbot,[7:4]a,[7:4]b,x); rca3([7:4]stop,ctop,[7:4]a,[7:4]b,y); 15
DATE:

MUX mux1(s4,stop[4],sbot[4]c0); mux2(s5,stop[5],sbot[5]c0); mux3(s6,stop[6],sbot[6]c0); mux4(s7,stop[7],sbot[7]c0); mux5(cout,ctop,cbot,c0); endmodule TEST BENCH(VERILOG): moduleCARRY_SEL_ADD_TB_v; // Inputs reg [11:0] x; reg [11:0] y; reg z; // Outputs wire [3:0] s; wire [5:1] m; // Instantiate the Unit Under Test (UUT) CARRY_SELECT_ADD uut ( .s(s), .m(m), .x(x), .y(y), .z(z) ); initial begin // Initialize Inputs x = 0; y = 0; z = 0;
16

// Wait 100 ns for global reset to finish #100 // Add stimulus here end endmodule RTL SCHEMATIC:
SYNTHESIS REPORT: ==================================================================== * Final Report *
==================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS : 31 17 : 34 : CARRY_SELECT_ADD.ngr : CARRY_SELECT_ADD : NGC : Speed : NO

# # # # # # LUT3 LUT4 MUXF5 IO Buffers IBUF OBUF : 16 :8 :7 : 34 : 25 :9
======================================================================== Device utilization summary: --------------------------Selected Device Number of Slices Number of 4 input LUTs Number of IOs Number of bonded IOBs : : : : : 3s100etq144-4 13 out of 960 1% 1%
24 out of 1920 34 34 out of 108
31%
SIMULATION OUTPUT:
RESULT: Thus a verilog HDL program was written for carry select adder and its output was verified. 18
EXP NO: 1.2 a DEMULTIPLEXER AIM: To write a verilog HDL program for demultiplexer and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module DEMUX(y,s,din); output [0:3]y; input [0:1]s; input din; wire a,b; not n1(a,s0); not n2(b,s1); and (y0,din,a,b); and (y1,din,a,s0); and (y2,din,s0,b); and (y3,din,s0,s1); 19
DATE:

endmodule
TEST BENCH(VERILOG): moduleDEMUX_TB_v; // Inputs reg in; reg s0; reg s1; // Outputs wire out0; wire out1; wire out2; wire out3; // Instantiate the Unit Under Test (UUT) DEMUX uut ( .out0(out0), .out1(out1), .out2(out2), .out3(out3), .in(in), .s0(s0), .s1(s1) ); initial begin // Initialize Inputs in = 0; s0 = 0; s1 = 0;
20
// Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT: ======================================================================= * Final Report *
======================================================================= Final Results RTL Top Level Output File Name Top Level Output File Name : DEMUX.ngr : DEMUX 21

Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # # # # # BELS LUT3 IO Buffers IBUF OBUF :4 :4 :7 :3 :4 :7 : NGC : Speed : NO
======================================================================== Device utilization summary: --------------------------Selected Device : 3s100etq144-4 Number of Slices Number of 4 input LUTs Number of IOs Number of bonded IOBs : : : : 2 out of 960 0% 0%
4 out of 1920 7 7 out of 108
6%
22
SIMULATION OUTPUT:
RESULT: 23

Thus a verilog HDL program was written for demultiplexer and its output was verified
EXP NO: 1.2 b MULTIPLEXER AIM:
DATE:
To write a verilog HDL program for multiplexer and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module MUX4_1(out,i0,i1,i2,i3,s0,s1); output out; input i0,i1,i2,i3,s0,s1; wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1); not (s0n,s0); and (y0,i0,s1n,s0n); and (y1,i1,s1n,s0); and (y2,i2,s1,s0n); and (y3,i3,s1,s0); 24

or (out,y0,y1,y2,y3); endmodule TEST BENCH(VERILOG): module MUX4TO1_v; // Inputs reg i0; reg i1; reg i2; reg i3; reg s0; reg s1; // Outputs wire out; // Instantiate the Unit Under Test (UUT) MUX4_1 uut ( .out(out), .i0(i0), .i1(i1), .i2(i2), .i3(i3), .s0(s0), .s1(s1) ); initial begin
25

// Initialize Inputs i0 = 0; i1 = 0; i2 = 0; i3 = 0; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule RTL SCHEMATIC:
26
======================================================================= Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy : MUX4_1.ngr : MUX4_1 : NGC : Speed : NO
Design Statistics # IOs :7
Cell Usage : # # # # # # BELS LUT3 MUXF5 IO Buffers IBUF OBUF :3 :2 :1 :7 :6 :1
======================================================================== Device utilization summary: ---------------------------
Selected Device : 3s100etq144-4
27
Number of Slices Number of 4 input LUTs Number of IOs Number of bonded IOBs
: : : :
1 out of
960
0% 0%
2 out of 1920 7 7 out of 108
6%
SIMULATION OUTPUT:
28

RESULT: Thus a verilog HDL program was written for multiplexer and its output was verified. EXP NO: 1.3 a ENCODER AIM: To write a verilog HDL program for encoder and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module encoder(d,x,y,z); input [7:0]d; output x,y,z; or r1(x,d[4],d[5],d[6],d[7]); or r2(y,d[2],d[3],d[6],d[7]); or r3(z,d[1],d[3],d[5],d[7]); endmodule TEST BENCH(VERILOG): DATE:
module test; // Inputs reg [7:0] d;

29

// Outputs wire x; wire y; wire z; // Instantiate the Unit Under Test (UUT) encoder uut ( .d(d), .x(x), .y(y), .z(z) ); initial begin // Initialize Inputs d = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end
endmodule
30
RTL SCHEMATIC:
SYNTHESIS REPORT:
================================================================== * Final Report *
================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage :
31
: encoder.ngr : encoder
: NGC : Speed : NO
: 11

# BELS # LUT4 :3 :3 : 10 :7 :3
================================================================== Device utilization summary: ---------------------------
Selected Device : 3s500efg320-5
2 out of 4656
0% 0%
3 out of 9312 11 10 out of 232
4%
32
SIMULATION OUTPUT:
RESULT: Thus a verilog HDL program was written for encoder and its output was verified. 33
EXP NO: 1.3 b DECODER AIM:
DATE:
To write a verilog HDL program for decoder and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5: Verify the output by simulating the source code. VERILOG SOURCE CODE: module decoder(z,a,b,e); input a,b,e; output [3:0]z; wire x,y; not x1(x,a); not x2(y,b); and a1(z[0],x,y,e); and a2(z[1],x,b,e); and a3(z[2],a,y,e); and a4(z[3],a,b,e); endmodule
34
TEST BENCH(VERILOG): moduleDECODER_TB_v; // Inputs reg a,b.e; // Outputs wire [3:0] z; // Instantiate the Unit Under Test (UUT) DECODER uut ( .z(z), .a(a), .b(b), .e(e) ); initial begin // Initialize Inputs a = 0; b= 0; e= 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end
35

endmodule RTL SCHEMATIC:
======================================================================= Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Target Technology Macro Preserve : YES 36 : decoder.ngr : decoder : NGC : Speed : YES : Automotive CoolRunner2

XOR Preserve Clock Enable wysiwyg : YES : YES : NO
Design Statistics # IOs :7
Cell Usage : # # # # # # # BELS AND2 AND3 INV IO Buffers IBUF OBUF : 10 :4 :2 :4 :7 :3 :4
========================================================================
Total REAL time to Xst completion: 7.00 secs Total CPU time to Xst completion: 7.14 secs Device utilization summary: --------------------------Selected Device : 3s100etq144-4 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 4 out of 960 0% 0%
8 out of 1920 12 12 out of 108
11%
37
SIMULATION OUTPUT:
RESULT: Thus a verilog HDL program was written for decoder and its output was verified. 38
EXP NO: 1.3 c PRIORITY ENCODER AIM:
DATE:
To write a verilog HDL program for priority encoder and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5: Verify the output by simulating the source code. VERILOG SOURCE CODE: module priority(encode0,encode1,valid,d0,d1,d2,d3); output encode0,encode1,valid; input d0,d1,d2,d3; wire y1,y2; not g1(y1,d2); and g2(y2,y1,d1); or g3(encode1,d3,y2); or g4(encode0,d3,d2); or g5(valid,encode0,d1,d0); endmodule
39
TEST BENCH: modulepriorityencode; // Inputs reg d0; reg d1; reg d2; reg d3; // Outputs wire encode0; wire encode1; wire valid; // Instantiate the Unit Under Test (UUT) priorityuut ( .encode0(encode0), .encode1(encode1), .valid(valid), .d0(d0), .d1(d1), .d2(d2), .d3(d3) ); initial begin // Initialize Inputs d0 = 0; d1 = 0; d2 = 0; d3 = 0;
40

// Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule RTL SCHEMATIC:
SYNTHESIS REPORT: * Final Report *
======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : :7 : priority.ngr : priority : NGC : Speed : NO
41

# # # # # # # BELS LUT2 LUT3 LUT4 IO Buffers IBUF OBUF :3 :1 :1 :1 :7 :4 :3
======================================================================== Device utilization summary: --------------------------Selected Device : 3s100evq100-4 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: SIMULATION OUTPUT: 2 out of 960 0% 0%
3 out of 1920 7 7 out of 66
10%
RESULT: Thus a verilog HDL program was written for priority encoder and its output was verified.
42
EXP NO: 1.4 a ARRAY MULTIPLIER
DATE:
AIM: To write a verilog HDL program for array multiplier and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module ARRAY_MUL(m,a,b); output [7:0]m; input [3:0] a,b; wire [15:0] p; wire [12:1] s; wire [12:1] c; and(p[0],a[0],b[0]); and(p[1],a[1],b[0]); and(p[2],a[0],b[1]); and(p[3],a[2],b[0]); and(p[4],a[1],b[1]); and(p[5],a[0],b[2]); 43

and(p[6],a[3],b[0]); and(p[7],a[2],b[1]); and(p[8],a[1],b[2]); and(p[9],a[0],b[3]); and(p[10],a[3],b[1]); and(p[11],a[2],b[2]); and(p[12],a[1],b[3]); and(p[13],a[3],b[2]); and(p[14],a[2],b[3]); and(p[15],a[3],b[3]); halfadd ha1(s[1],c[1],p[1],p[2]); halfadd ha2(s[2],c[2],p[4],p[3]); halfadd ha3(s[3],c[3],p[7],p[6]);
fulladd fa4(s[4],c[4],p[11],p[10],c[3]), fa5(s[5],c[5],p[14],p[13],c[4]), fa6(s[6],c[6],p[5],s[2],c[1]), fa7(s[7],c[7],p[8],s[3],c[2]), fa8(s[8],c[8],p[12],s[4],c[7]), fa9(s[9],c[9],p[9],s[7],c[6]);
halfadd ha10(s[10],c[10],s[8],c[9]); fulladd fa11(s[11],c[11],s[5],c[8],c[10]); fulladd fa12(s[12],c[12],p[15],s[5],c[11]); buf(m[0],p[0]); buf(m[1],s[1]); buf(m[2],s[6]);
44

buf(m[3],s[9]); buf(m[4],s[10]); buf(m[5],s[11]); buf(m[6],s[12]); buf(m[7],c[12]); endmodule
SUB PROGRAM: modulehalfadd(s,c,a,b); outputs,c; inputa,b; xor(s,a,b); and (c,a,b); endmodule
modulefulladd(s,cout,a,b,cin); output s; outputcout; inputa,b; inputcin; wiree,f,g; assign e=(a^b),f=(e&cin),g=(a&b); assign s=(e^cin),cout=(f|g); endmodule
45
TEST BENCH(VERILOG):
moduleARRAY_MUXTB_v; // Inputs reg [3:0] a; reg [3:0] b; // Outputs wire [7:0] m; // Instantiate the Unit Under Test (UUT) ARRAY_MUL uut ( .m(m), .a(a), .b(b) ); initial begin // Initialize Inputs a = 0; b = 0; // Wait 100 ns for global reset to finish #100;
// Add stimulus here end
46

endmodule
RTL SCHEMATIC:
SYNTHESIS REPORT:
======================================================================== * Final Report *
======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal : ARRAY_MUL.ngr : ARRAY_MUL : NGC : Speed 47

Keep Hierarchy : NO
Design Statistics # IOs Cell Usage : : 16
# BELS # # # LUT2 LUT3 LUT4
: 30 : 11 :1 : 18 : 16 :8 :8
========================================================================
Device utilization summary: ---------------------------
Selected Device : 3s100etq144-4
17 out of
960
1% 1%
30 out of 1920 16 16 out of 108
14%
48
SIMULATION OUTPUT:
RESULT: Thus a verilog HDL program was written for array multiplier and its output was verified. 49
EXP NO: 1.5 a BCD TO GRAY CODE CONVERTER AIM:
DATE:
To write a verilog HDL program for BCD to gray code converter and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE:
module sss(g,d); output [3:0]g; input [3:0]d; assign g[3]=d[3]; assign g[2]=d[3]|d[2]; assign g[1]=d[2]^d[1]; assign g[0]=d[1]^d[0]; endmodule
TEST BENCH: module test; // Inputs

50

reg [3:0] d;
// Outputs wire [3:0] g; // Instantiate the Unit Under Test (UUT) sss uut ( .g(g), .d(d) ); initial begin // Initialize Inputs d = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule
RTL SCHEMATIC:
51
SYN THESIS REPORT:
Final Report
================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # LUT2 :3 :3 :8 :4 :4 :8 : sss.ngr : sss
: NGC : Speed : NO
================================================================== Device utilization summary:

52

--------------------------Selected Device : 3s500efg320-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 8 8 out of 232 3% 2 out of 4656 0% 0%
3 out of 9312
SIMULATION OUTPUT:
53
RESULT: Thus a verilog HDL program was written for BCD to gray code converter and its output was verified. EXP NO: 1.5 b EXCESS 3 TO BCD CODE CONVERTER AIM: To write a verilog HDL program for excess 3 to BCD code converter and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code VERILOG SOURCE CODE: Module excessbcd( output [3:0] b, input [3:0] e ); assign b[0]=~e[0]; 54 DATE:

assign b[1]=e[1]^e[0]; assign b[2]=~e[2]&~e[0]|~e[2]&~e[1]|e[2]&e[1]&e[0]; assign b[3]=e[3]&e[2]|e[2]&e[1]&e[0]; endmodule TEST BENCH: modulecodeconv; // Inputs reg [3:0] e; // Outputs wire [3:0] b; // Instantiate the Unit Under Test (UUT) excessbcduut ( .b(b), .e(e) ); initial begin // Initialize Inputs e = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule
RTL SCHEMATIC:
55
======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # INV LUT2 LUT3 :4 :1 :1 :1 56 :8 : excessbcd.ngr : excessbcd : NGC : Speed : NO

# LUT4 :1 :8 :4 :4
========================================================================
Device utilization summary: --------------------------Selected Device : 3s100etq144-5
2 out of
960
0% 0%
4 out of 1920 8 8 out of 108
7%
SIMULATION OUTPUT:
57
RESULT: Thus a verilog HDL program was written for excess 3 to BCD code converter and its output was verified. EXP NO: 2.1 ACCUMULATOR AIM: To write a verilog HDL program for accumulator and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module ACCUMULATOR(c,clr,d,q); input c,clr; 58 DATE:

input [3:0]d; output [3:0]q; reg [3:0]tmp; always@(posedge c or posedgeclr) begin if(clr) tmp=4'b0000; else tmp=tmp+d; end assign q=tmp; endmodule
TEST BENCH(VERILOG): moduleACCUMULATOR_TB_v; // Inputs reg c; regclr; reg [3:0] d; // Outputs wire [3:0] q; // Instantiate the Unit Under Test (UUT) ACCUMULATOR uut ( .c(c), .clr(clr), .d(d),
59

.q(q) ); initial begin // Initialize Inputs c = 0; clr = 0; d = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule RTL SCHEMATIC:
======================================================================== Final Results RTL Top Level Output File Name : ACCUMULATOR.ngr 60

Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # # # LUT2 LUT2_L LUT3 LUT4 LUT4_D :6 :1 :1 :1 :2 :1 :4 :4 :1 :1 :9 :5 :4 : 10 : ACCUMULATOR : NGC : Speed : NO
# FlipFlops/Latches # FDC
# Clock Buffers # BUFGP
======================================================================== Device utilization summary: --------------------------Selected Device : 3s100etq144-4
Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs:
3 out of
960
0% 0% 0%
4 out of 1920 6 out of 1920
61

Number of IOs: Number of bonded IOBs: Number of GCLKs: 10 10 out of 1 out of 108 24 9% 4%
SIMULATION OUTPUT:
62
RESULT: Thus a verilog HDL program was written for accumulator and its output was verified. EXP NO: 2.2 PSEUDO RANDOM SEQUENCE GENERATOR AIM: To write a verilog HDL program for pseudo random sequence generator and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: module prbs(y,clk); output y; DATE:
63

input clk; wire [1:0]q; wire[2:0]x; wire rst,a; dff d1(q[0],x[0],a,clk,rst), d2(q[1],x[1],q[0],clk,rst), d3(y,x[2],q[1],clk,rst); xor x1(a,q[0],y); endmodule
module dff(q,qbar,d,clk,rst); output q,qbar; input d,clk,rst; reg q,qbar; initial q=1'b1; always @(posedge clk) begin if (rst==1'b1) begin q=1'b0; qbar=~q; end else if(d==1'b0) begin q=1'b0; qbar=~q;
64

end else if(d==1'b1) begin q=1'b1; qbar=1'b0; end end endmodule
TESTBENCH: module sha; // Inputs reg clk; // Outputs wire y; // Instantiate the Unit Under Test (UUT) prbs uut ( .y(y), .clk(clk) ); initial begin // Initialize Inputs clk = 0; // Wait 100 ns for global reset to finish #100;
65

// Add stimulus here
end endmodule
RTL SCHEMATIC:
======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs :2 66 : prbs.ngr : prbs : NGC : Speed : NO

Cell Usage : # BELS # # # INV LUT2 VCC :4 :2 :1 :1 :3 :3 :1 :1 :1 :1
# FlipFlops/Latches # FDR
# IO Buffers # OBUF
========================================================================
Device utilization summary: --------------------------Selected Device : 3s500efg320-5
Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs:
2 out of 4656 3 out of 9312 3 out of 9312 2 2 out of 1 out of 232 24
0% 0% 0%
0% 4%
SIMULATION OUTPUT:
67
RESULT: Thus a verilog HDL program was written for pseudo random sequence generator and its output was verified. EXP NO: 2.3 BINARY COUNTER AIM: To write a verilog HDL program for binary counter and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code. VERILOG SOURCE CODE: DATE:
68

module count1(clk,rst,count); input clk; input rst; output [3:0] count; reg [3:0]count; always @ (posedge clk) if(rst) count=4'b0000; else begin if(count==4'b1111) count=4'b0000; else
count=count+1; end endmodule
TESTBENCH:
module test; // Inputs reg clk; reg rst; // Outputs wire [3:0] count; // Instantiate the Unit Under Test (UUT) count1 uut ( .clk(clk), .rst(rst), .count(count) 69

); initial begin // Initialize Inputs clk = 0; rst = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule
RTL SCHEMATIC:
================================================================ Final Results

70

RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # # # INV LUT2 LUT2_L LUT3 LUT4 :6 :1 :1 :1 :1 :2 :4 :4 :1 :1 :5 :1 :4 :6 : count1.ngr : count1 : NGC : Speed : NO
# FlipFlops/Latches # FDR
==================================================================== ===== Device utilization summary: --------------------------Selected Device : Number of Slices: 3s100evq100-4 3 out of 960 0%
71

Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs: 4 out of 1920 6 out of 1920 6 6 out of 1 out of 66 24 9% 4% 0% 0%
SIMULATION OUTPUT:
72
RESULT: Thus a verilog HDL program was written for binary counter and its output was verified. EXP NO: 2.4 MOD-10 COUNTER AIM: To write a verilog HDL program for mod-10 counter and verify its output. SOFTWARE REQUIRED: Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write different combinations of input using the test bench. Step5:Verify the output by simulating the source code DATE:
73

VERILOG SOURCE CODE: Module modten(c,a0,a1,a2,a3); output a0,a1,a2,a3; input c; wire r; ff f0(a0,c,r); ff f1(a1,a0,r); ff f2(a2,a1,r); ff f3(a3,a2,r); nand(r,a1,a3); endmodule module ff(q,cl,r); output q; input cl,r; reg q=1'b0; always@(negedge cl or negedge r) if(~r) q=1'b0; else q=(~q); endmodule TEST BENCH(VERILOG): module MOD10_TB_v; // Inputs reg t; regclk; regrst;
74

// Outputs wire [9:0] dout; // Instantiate the Unit Under Test (UUT) MOD10 uut ( .dout(dout), .t(t), .clk(clk), .rst(rst) ); initial begin // Initialize Inputs t = 0; clk = 0; rst = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule RTL SCHEMATIC:
75
======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Target Technology Macro Preserve XOR Preserve Clock Enable wysiwyg Design Statistics # IOs Cell Usage : :5 : modten.ngr : modten : NGC : Speed : YES : Automotive CoolRunner2 : YES : YES : YES : NO
76

# BELS # # INV OR2 : 15 : 14 :1 :4 :4 :5 :1 :4
# FlipFlops/Latches # FDC
Total REAL time to Xst completion: 9.00 secs Total CPU time to Xst completion: 9.22 secs
Device utilization summary: --------------------------Selected Device : Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs: 3s100etq144-4 2 out of 960 0% 0% 0%
4 out of 1920 4 out of 1920 13 6 out of 1 out of 108 24
5% 4%
SIMULATION OUTPUT:
77
RESULT: Thus a verilog HDL program was written for mod-10 counter and its output was verified.
EXP NO: 3.1 ARITHMETIC AND LOGICAL UNIT AIM:
DATE:
To write a verilog HDL program for ALU and verify its output in FPGA. HARDWARE AND SOFTWARE REQUIRED: FPGA kit , JTAG cable, Power supply Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. 78

Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write all possible combinations of input using the test bench. Step5:Verify the output by simulating the source code. Step6:Download the program to the FPGA kit and check its output. VERILOG SOURCE CODE: Module gere(a,b,sel,y); inputa,b; input [1:0] sel; output y; reg y; always@(a or b or sel) begin case(sel) 2'b00:y=a&b; 2'b01:y=a|b; 2'b10:y=a+1; 2'b11:y=b-1; endcase end endmodule
RTL SCHEMATIC:
79
======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # LUT4 :1 :1 :5 :4 :1 :5 : gere.ngr : gere : NGC : Speed : NO
========================================================================
Device utilization summary: 80

---------------------------
Selected Device : 3s500efg320-5
1 out of 4656 1 out of 9312 5 5 out of 232
0% 0%
2%
SIMULATION OUTPUT:
PIN ASSIGNMENT #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "l13" ; NET "b" LOC = "l14" ; NET "sel[0]" LOC = "h18" ; 81

NET "sel[1]" LOC = "n17" ; NET "y" LOC = "f12" ;
RESULT: Thus a verilog HDL program was written for ALU and its output was verified in FPGA. EXP NO: 3.2 FULL ADDER AIM: To write a verilog HDL program for full adder and verify its output in FPGA. HARDWARE AND SOFTWARE REQUIRED: FPGA kit , JTAG cable, Power supply 82 DATE:

Xilinx ISE 10.1 ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and perform synthesis . Step4: Write all possible combinations of input using the test bench. Step5:Verify the output by simulating the source code. Step6:Download the program to the FPGA kit and check its output. VERILOG SOURCE CODE: module fulladder(sum,cout,a,b,cin); output sum,cout; input a,b,cin; assign {cout,sum}=a+b+cin; endmodule RTL SCHEMATIC:
83

======================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # LUT3 :2 :2 :5 :3 :2 :5 : fulladder.ngr : fulladder : NGC : Speed : NO
Device utilization summary: Selected Device : 3s500efg320-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 1 out of 4656 2 out of 9312 5 5 out of 232 2% 0% 0%
SIMULATION OUTPUT:
84
PIN ASSIGNMENT #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "l13" ; NET "b" LOC = "l14" ; NET "cin" LOC = "h18" ; NET "cout" LOC = "f12" ; NET "sum" LOC = "e12" ;
RESULT: Thus a verilog HDL program was written for full adder and its output was verified in FPGA. EX.NO: 4.1 CMOS INVERTER LAYOUT DESIGN AIM To design and verify the basic logic gates using Microwind layout design tool and to determine the power consumed by analyzing the simulation results. DATE:
SOFTWARE REQUIRED 85

MICROWIND 2.7 a STUDY OF MICROWIND LAYOUT DESIGN TOOL USES: In all design processes, a logical and systematic approach is essential. This is particularly so in the case of a VLSI system which could otherwise take so long as to render the whole system obsolete before it is off the drawing board. Design processes are aided by simple concepts such as stick and symbolic diagrams, design rules are the communication link between the designer specifying requirements and the fabricator who materializes them. Microwind layout design tool are used to produce workable mask layouts from which the various layers in silicon will be formed or patterned. Applications: i. In design implementation, this converts the logical design into a physical file format that can be downloaded to the selected target device such as Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD). ii. In design of combinational and sequential logic circuits of VLSI system.
About the software: MICROWIND 2.7 a by Etienne Sicard released in Dec 14-2003
Purpose of Lambda() based design rules The object of a set of design rules is to allow a ready translation of circuit design concepts, usually in stick diagram or symbolic form, into actual geometry in silicon. In general, design rules and layout methodology based on the concept of provide a process and feature size-independent way of setting out mask dimensions to scale. CMOS design Rules The CMOS fabrication process is much more complex than nMOS fabrication, which in turn has bee simplified using the set of CMOS design rules, also called as micron () based rules. The goal of any set of design rules should be to optimize yield while keeping the geometry as small as possible without compromising the reliability of the finished finished circuit. STEPS TO BE FOLLOWED IN CMOS INVERTER LAYOUT DESIGN i. Open the Grid window in Microwind2.7
86
ii.
The complete grid window is considered as p-well
87

iii. Now we need to place n-well over p-well(rectangular box)
iv. Next we need to place the P-diffusion over n-well (width of p-diffusion equals 4)
88
89

v. Metal contacts can be drawn by selecting 4X4 square in p-diffusion
vi. The same steps can be followed for nMOS. The grid itself is p-well and we can directly start with n-diffusion layer. There should be minimum of 6 spacing between pMOS and nMOS transistor.
90
vii. The pMOS and nMOS should be connected by using a poly layer (poly width=2). The polylayer should be extended to 3 length between p and n layer. Also leave 1 space on both sides of polysilicon.
91

viii. The source of pMOS to drain of nMOS connection is made using a metal of width 3. The input is given as a pulse to polysilicon and the output is taken by assigning the node at themetal.
FINAL LAYOUT DESIGN
92
SIMULATION OUTPUT
93

OBSERVTION
Transistors used Power consumption Device pMOS transistors nMOS transistors
CMOS Inverter
1 1.236w
Total transistors
RESULT: Thus the layout design of CMOS inverter was studied, designed and verified using Microwind2.7a.
EX.NO: 4.2 LOGIC GATES LAYOUT DESIGN AIM:
DATE:
To design and verify the basic logic gates using Microwind layout design tool and to determine the power consumed by analyzing the simulation results.
SOFTWARE REQUIRED MICROWIND 2.7 a
ALGORITHM: Step1: Define the specifications and initialize the design.
94

Step2: Declare the name of the layout using Microwind2.7. Step3: Zoom in and out to select the 1 value. Step4: After placing each and every component apply DRC (Design rule checker). Step5: Analyse the output using the run simulation command. Step6: Check all possible combinations of input using the simulation output. Tabulate the results and determine the power consumption.
LAYOUT DESIGN: AND GATE
95
SIMULATION OUTPUT:
OR GATE
96
SIMULATION OUTPUT:
NAND GATE
97
SIMULATION OUTPUT:
NOR GATE
98
SIMULATION OUTPUT:
OBSERVATION AND GATE
99

Transistors used Power consumption Device CMOS Inverter 2-I/P Nand gate Total transistors pMOS transistors 1 2 3 nMOS transistors 1 2 3 3.438w
OR GATE
Transistors used Power consumption Device CMOS Inverter 2-I/P NOR gate Total transistors pMOS transistors 1 2 3 nMOS transistors 1 2 3 2.924w
NAND GATE
Transistors used Power consumption Device 2-I/P NAND gate pMOS transistors 2 2 nMOS transistors 2 1.316w Total transistors 2
NOR GATE
Transistors used Power consumption Device 2-I/P NOR gate Total transistors pMOS transistors 2 2 nMOS transistors 2 1.058w 2
100
RESULT: Thus the basic logic gates were designed using Microwind layout design tool and the simulation results were verified and tabulated. EX.NO: 4.3 DIFFERENTIAL AMPLIFIER LAYOUT DESIGN AIM: DATE:
101

To design and verify the basic differential amplifier using Microwind layout design tool and to determine the power consumed by analyzing the simulation results.
SOFTWARE REQUIRED MICROWIND 2.7 a
ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the layout using Microwind2.7. Step3: Zoom in and out to select the 1 value. Step4: After placing each and every component apply DRC (Design rule checker). Step5: Analyse the output using the run simulation command. Step6: Check all possible combinations of input using the simulation output. Tabulate the results and determine the power consumption.
LAYOUT DIAGRAM:
102
SIMULATION OUTPUT:
103
OBSERVATION:
Transistors used Device Differential amplifier Total transistors pMOS transistors 2 2 nMOS transistors 3 3
Power consumption
15.154w
RESULT: Thus the differential amplifier was designed using Microwind layout design tool and the simulation results were verified and tabulated.
104

Print Vlsi

Загружено:

Сведения о документе

Исходное описание:

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Print Vlsi

Загружено:

Авторское право:

Доступные форматы

EC 2357 VLSI DESIGN LAB

MAAMALLAN INSTITUTE OF TECHNOLOGY

LABORATORY RECORD NOTE BOOK

EC 2357 VLSI DESIGN LAB

MAAMALLAN INSTITUTE OF TECHNOLOGY

Submitted for the exam held on ____________

EC 2357 VLSI DESIGN LAB INDEX

1. COMBINATIONAL CIRCUIT DESIGN

2. SEQUENTIAL CIRCUIT DESIGN

EC 2357 VLSI DESIGN LAB

3. DESIGN IMPLEMENTATION IN FPGA

4. LAYOUT DESIGN USING MICROWIND

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

SYNTHESIS REPORT: ======================================================================== * Final Report *

EC 2357 VLSI DESIGN LAB

Design Statistics # IOs Cell Usage : # BELS # LUT3 : 16 : 16 : 26 : 17 :9 : 26

# IO Buffers # # IBUF OBUF

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

// Add stimulus here end endmodule

SYNTHESIS REPORT: ======================================================================== * Final Report *

EC 2357 VLSI DESIGN LAB

# IO Buffers # # IBUF OBUF

======================================================================== Device utilization summary: --------------------------Selected Device : 3s100etq144-4

15 out of 1920 14 14 out of 108

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

SYNTHESIS REPORT: ==================================================================== * Final Report *

EC 2357 VLSI DESIGN LAB

24 out of 1920 34 34 out of 108

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

SYNTHESIS REPORT: ======================================================================= * Final Report *

EC 2357 VLSI DESIGN LAB

4 out of 1920 7 7 out of 108

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EXP NO: 1.2 b MULTIPLEXER AIM:

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

SYNTHESIS REPORT: ======================================================================= * Final Report *

Design Statistics # IOs :7

Cell Usage : # # # # # # BELS LUT3 MUXF5 IO Buffers IBUF OBUF :3 :2 :1 :7 :6 :1

======================================================================== Device utilization summary: ---------------------------

Selected Device : 3s100etq144-4

EC 2357 VLSI DESIGN LAB

2 out of 1920 7 7 out of 108

EC 2357 VLSI DESIGN LAB

module test; // Inputs reg [7:0] d;

EC 2357 VLSI DESIGN LAB

EC 2357 VLSI DESIGN LAB

================================================================== * Final Report *

EC 2357 VLSI DESIGN LAB

# IO Buffers # # IBUF OBUF