OBJECTIVES Objective of this experiment is to recast word problems into design specification.

Besides, to design combinational circuit in a structured way, derived truth table from design specifications and obtain minimized Boolean Expression using minimization techniques. Others objective is to design and simulate circuits using TTL components from software design tools and to build digital circuits in the lab using difference type of TTL components and interconnecting them. Lastly, to learn techniques of troubleshooting if the circuit does not functioning.

BRIEFLY INTRODUCTION The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic "0" or logic "1", at any given instant in time as they have no feedback, and any changes to the signals being applied to their inputs will immediately have an effect at the output. In other words, in a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs and if one of its inputs condition changes state so does the output as combinational circuits have "no memory", "timing" or "feedback loops".

EQUIPMENT 1. IDL800 digital experimenter 2. 74 series ICs 3. Wire 22AWG DESIGN PROBLEM Design a 2-bits multiplier circuit (A x B = M) that will multiply two bits number (A = and B = ) in binary code. For example: A= 0 B=0 => => =00 =00 =0000

So the output of A x B = 0 x 0 will be M = 0 =>

A B

Combinational Circuit Multiplier

PROCEDURE 1. Firstly, the block diagram of combinational circuit multiplier in design problem is redraw showing the inputs and outputs to actually represent multiplier circuit.

Combinational Circuit Multiplier

2. From the diagram, the truth table is derived describing the operation of the combinational circuit multiplier that has 4 inputs and 4 outputs.

INPUT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

OUTPUT 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1

3. From the truth table, a Boolean expression for each output is obtained by using minimization techniques.

M3 00 00 01 11 10 M2 00 00 01 11 10 M1 00 00 01 11 10 M0 0 0 0 0 01 0 0 1 1 11 0 1 0 1 10 0 1 1 0 = = 0 0 0 0 01 0 0 0 0 11 0 0 0 1 10 0 0 1 1 = = = + 0 0 0 0 01 0 0 0 0 11 0 0 1 0 10 0 0 0 0 =

00 00 01 11 10 0 0 0 0

01 0 1 1 0

11 0 1 1 0

10 0 0 0 0

4. The multiplier circuit using logic gate is draw and the pin is assign at each logic gate.

5. The multiplier circuit design is simulated and compiled by using Quartus II and waveform diagram of the design which contains all outputs for all possible input combinations is produced by using ModelSim-Altera. 6. The schematic and waveform diagram is printed. 7. The multiplier circuit is constructed using digital experimenter and TTL components available in the lab. 8. The circuit is tested to verify its functionality. 9. All observations are recorded in log book. 10. Finally, the circuit is demonstrated to the lab instructor for getting approval that the circuit functioning accordingly.

RESULT SCHEMATIC DIAGRAM FROM QUARTUS II

WAVEFORM DIAGRAM FROM MODELSIM-ALTERA

OBSERVATION FROM HARDWARE DESIGN INPUT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OUTPUT 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1

DISCUSSION Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that are combined or connected together to produce more complicated switching circuits. These logic gates are the building blocks of combinational logic circuits. Combinational logic circuits can be very simple or very complicated and any combinational circuit can be implemented with only NAND and NOR gates as these are classed as universal gates. The three main ways of specifying the function of a combinational logic circuit are:

Truth Table. Truth tables provide a concise list that shows the output values in tabular form for each possible combination of input variables. For this experiment, the possible input combination = = = 16, where n = number of input variables. Example: 0 1 0 1 1 1 1 1 1 (input (input ) )

X + 0 0 0

(output

A Karnaugh Map provides a systematic method for simplifying Boolean Expressions. If properly used, will produce the simplest SOP or POS expression possible, known as the minimum expression. The effectiveness of algebraic simplification depends on the familiarity with all the laws, rules and theorems of Boolean Algebra. For this experiment, we used SOP. So, Boolean Algebra form an output expression for each input variable that represents a logic "1". Example:

M2 00 00 01 11 10 0 0 0 0 01 0 0 0 0 11 0 0 0 1 10 0 0 1 1 = = = +

Logic Diagram Shows the wiring and connections of each individual logic gate that implements the circuit.

From the Boolean Expression that has been simplified for each output, we able to construct the circuit combination with the minimum number of logic gates.

CONCLUSION The minimized Boolean Expression can be obtain by using some minimization techniques which is Karnaugh Map. Besides, the circuit is designed and simulated by using TTL components from software design tools (Quartus II and ModelsimAltera). Lastly, the combinational circuit can be designed in a structured way.