Lancelot

VGA video controller for the Altera Nios II processor. V4.0 December 16th, 2005 http://www.microtronix.com

1. Description
Lancelot is a VGA video controller for the Altera Nios (II) processor. The peripheral consists of two parts; the Lancelot core and the Lancelot VGA Board. This a add-on daughter board, which fits on the expansion interface of various Altera (and Altera partner) development boards, like the Altera Cyclone Nios Development Board, Altera Stratix Nios development board and the Altera EPXA1 Development board. The board holds the Video DAC and the VGA, PS2 and audio connectors. The Lancelot core is written in VHDL and can be used for Altera APEX 20KE/C, APEX II, Cyclone and Stratix devices.

Master Registers

Line Buffer Colour Table Line Buffer Video DAC R G B

State Machine

Slave Registers

Local Registers

State Machine

HS VS

Core

Board

The Lancelot core reads out the line buffers, drives the external video DAC and generates the sync signals. After the processor initialises and starts Lancelot, the VGA state machine requests new video data. The bus wrapper state machine reads one horizontal video line from the SDRAM and stores it in the line buffer. While one (empty) line buffer is filled by the bus wrapper DMA controller, the other (full) line buffer is readout by the VGA state machine. When the video line buffer is empty and the other line buffer is full, the line buffers are swapped and the process starts again. The colour table converts the 256 colour data to 24-bits colour pixels. The VGA state machine is also responsible for generating VGA timing and video DAC control signals.

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2. Lancelot Signals
Table 2.1. shows the Lancelot core signals for the Nios processor. The master port connects to the S(D)RAM controller and reads video data from the S(D)RAM using DMA. The processor can access the Lancelot register through the slave port.
Signal Size avalon_clk 1 video_clk 1 reset_n 1 master_addr 32 master_rddata 32 master_rd 1 master_waitreq 1 slave_cs 1 slave_addr 3 slave_rddata 32 slave_wrdata 32 slave_rd 1 slave_wr 1 R 7 G 7 B 7 HS 1 VS 1 M1 1 M2 1 Blank_n 1 Sync_n 1 Sync_t 1 Table 2.1. Lancelot Core signals Direction In In in out in out in in in out in in in out out out out out out out out out out Description System clock Video clock Reset Avalon master address Avalon master read data Avalon master read select Avalon master wait request Avalon slave chip select Avalon slave address Avalon slave read data Avalon slave write data Avalon slave read select Avalon slave write select Red output to video DAC Green output to video DAC Blue output to video DAC Hsync to VGA Vsync to VGA Mode select video DAC Mode select video DAC Control signal to video DAC Control signal to video DAC Control signal to video DAC

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3. Lancelot Registers
The Lancelot core has 7 registers, which are all 32-bits wide.
Register Map Offset Register 0 Control 0 Status 1 Colour Table 2 3 Reset 4 Resolution 5 Horizontal Timing 6 Vertical Timing 7 DMA Control Register Bit Name 5 VS Polarity 4 HS Polarity 3 Set DAC Mode 2 Start Video 0 Reset Status Register Bit Name 31 16 Signature 9 New Frame

Mode W R W W R/W R/W R/W R/W

Description Writing a logic 1 inverts the VS output. Writing a logic 1 inverts the HS output. A logic 1 sets the Video DAC in RGB mode. Writing 1 to this bit starts the internal video state machine. The Lancelot Core is automatic reseted during power-up.

8 7 6 5 4 3 2 1 0

Frame Missed Line Buffer Video Full Line Buffer Video Empty Line Buffer DMA Full Line Buffer DMA Empty Blank VS Blank HS VS HS

Description MG (5247) This bit is 1 when the next frame is the first frame of the screen. The bit is set when the line buffer isnt filled with a new line after an dma request or writing the line buffer data took longer than maximum line time (32 s). This bit is 1 when the video line buffer is full. This bit is 1 when the video line buffer is empty. This bit is 1 when the DMA line buffer is full. This bit is 1 when the DMA line buffer is empty. This bit indicates the vertical blank status (1 = vertical blank). This bit indicates the horizontal blank status (1 = horizontal blank). Internal vsync signal. Internal hsync signal.

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Colour Table Register Bit Description 31 - 24 Colour index 23 - 16 Red value 15 8 Green value 70 Blue value Resolution Register Bit Description 25 - 16 Horizontal Resolution 15 0 Vertical Resolution Horizontal Timing Register Bit Description 23 16 Pulse Width 15 8 Back Porch Width 70 Front Porch Width Vertical Timing Register Bit Description 13 16 Pulse Width 15 8 Back Porch Width 70 Front Porch Width DMA Register Bit Description 31 - 0 DMA start address

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4. Video Timing
The two figures below show the timing of a video line and video frame. According to the resolution a line consists of 640, 800 or 1024 pixels. A frame is divided into 480, 600 or 768 lines. If the BLANKn signal is asserted the output of the video DAC is forced to zero. When the horizontal sync signal (HS) is low indicates a new line. A new frame is indicated by a low pulse on the vertical sync signal (VS).
Active Line

BLANKn

RGB

HS

A B C D E

Figure 4.1. Horizontal Video Timing (Line)

Active Line

BLANKn

RGB

VS

F G H I J

Figure 4.2. Vertical Video Timing (Frame)

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Resolution A Line Period B Hsync Sync Period C Hsync Back Porch D Active Video E Hsync Front Porch F Frame Period G Vsync Sync Period H Vsync Back Porch I Active Frame J Vsync Front Porch Table 4.1. Video Timing

640 x 480 32.8 s 3.8 s 1.9 s 25.4 s 0.6 s 16.7 ms 0.05 ms 1 ms 15.3 ms 0.3 ms

800 x 600 26.4 s 3.2 s 2.2 s 20 s 1 s 16.58 ms 0.1 ms 0.6 ms 15.84 ms 0.02 ms

1024 x 768 20.7 s 2.1 s 2.5 s 15.7 s 0.4 s 16.67 ms 0.12 ms 0.6 ms 15.88 ms 0.06 ms

Table 4.2. shows the video settings, which can be used to set the Lancelot horizontal and vertical timings registers.
Resolution Video Clock Horizontal Resoltution Vertical Resolution Hsync Pulse Width Hsync Back Porch Width Hsync Front Porch Width Vsync Pulse Width Vsync Back Porch Width Vsync Front Porch Width Table 4.2. Video Settings 640 x 480 25.2 Mhz 640 480 95 40 25 2 22 10 800 x 600 40 Mhz 800 600 128 88 40 4 23 1 1024 x 768* 65 Mhz 1024 768 136 160 24 6 29 3

* Note; This video mode is only supported by the Excalibur ARM reference design.

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5. Reference Designs
Perform the following steps to run the Lancelot reference design on your Altera Nios Development Board. Unplug the power cable from the development board. Mount the Lancelot VGA Card on the Santa Cruz proto header as shown in figure 5.1 (Altera Stratix Nios Board or Altera Cyclone Nios Board). Connect the VGA output to a monitor. Connect an Altera programming cable to the JTAG header. Power the development board. Open de Nios II SDK Shell and browse to the flash_image directory in the Nios II reference design installation. Type the command ./lancelot_flash_image to load the Nios II configuration into the development board flash device. Press the Reset Config button to run the Lancelot reference design.

JTAG Connector

Reset Config

Figure 5.1. Altera Cyclone / Stratix Nios Development Board

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