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VLSI PROJECT LIST (VHDL/Verilog) M.

TECH
S.No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PROJECT TITLES Design and Implementation of APB Bridge based on AMBA 4.0 RISC-Based Architecture for Computer Hardware Introduction DDR SDRAM Memory Controller for Digital TV Decoders Design and Implementation of High Performance AHB Reconfigurable Arbiter for Onchip Bus Architecture. Design of FPGA based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor A design of the PLB to AHB bus bridge Building an AMBA AHB compliant Memory Controller VLSI Implementation of Synchronizer and Pipelined CORDIC in OFDM Receiver for Fourth Generation Wireless LAN Applications Cost efficient design and fixed point analysis of IFFT/FFT processor chip for OFDM systems. The Design of an 8-bit CISC CPU Based on FPGA FPGA Implementation of AES Algorithm Design of Control Module for ADC Based on FPGA Design and Simulation of UART Serial Communication Module Based on VHDL Design of three-lift controller based on FPGA Analysis of Low power Open Core Protocol Compliant Interface using VHDL Hardware Implementation of FIR Filter FPGA Implementation of Dynamic Key Management for DES Encryption Algorithm Implementation of Convolution Encoder and Viterbi Decoder using Verilog HDL A Processor-DMA-Based Memory Copy Hardware Accelerator An Area Reduced, Speed Optimized Implementation of Viterbi Decoder Design of On-Chip Bus with OCP Interface. (Verilog) Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix. (Verilog) Low Power Design Techniques Applied to Pipelined Parallel and Iterative CORDIC Design Design Method of Viterbi Decoding of Convolutional Code Based on VHDL IEEE 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011
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Contact: newvlsiprojects@gmail.com

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Efficient implementation and evaluation of wavelet packet for 3D Medical Image Segmentation Robust Multiple Watermarks for Volume Data Based on 3D-DWT and 3D-DFT A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix-2 Modified Booth Algorithm. (Verilog) Optimized Design of UART IP Soft Core based on DMA Mode A Design of Embedded Gigabit Ethernet Interface An Efficient Architecture for 3-D Discrete Wavelet Transform. (Verilog) The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation. (Verilog) QPSK Modulator on FPGA An Efficient Distributed Arithmetic based VLSI Architecture for DCT Design and implementation of packet switching capabilities on 10GB EMAC core AXI Compliant DDR3 Controller

2011 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010

Contact: newvlsiprojects@gmail.com

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