RITS-ICAEM 2012: RITS-International Conference On Advancement In Engineering And Management

28&29th Feb 2012

A High Performance CMOS Band Gap Reference Circuit Design

Mohammed Noorullah Khan Assistant Professor, ECE Dept, MJ College Engineering & technology, Banjara Hills, Hyderabad, AP,India. mdnoorece@mjcollege.ac.in Khaja Mujeebuddin Quadry Dr.Syed Abdul Sattar Professor, ECE Dept, Member IEEE Professor & Dean Royal Institute of Technology &science, Royal Institute of Technology &science Hyderabad, A.P., India. Hyderabad, A.P., India. mujeebqd@yahoo.com syed49in@yahoo.com stages two gain stages and one unity gain output stage. The output buffer is normally present only when resistive loads need to be driven. If the load is purely capacitive, then it is seldom included. The first gain stage is a differential input single ended output diffamp stage. The second gain stage is normally a common source gain stage that has an active load. Capacitor is included to ensure stability when the op-amp is used with feedback. Because is between the input and the output of the high gain second stage, it is often called a Miller capacitance since its effective capacitance load on the first stage is larger than its physical value. It should be noted that the first stage has a pchannel differential input pair with an n-channel current mirror active load.

Abstract This paper presents a CMOS band gap reference design, Thus it is suitable for the application of a wide range of frequency and power input. In order to reduce thermal noise and to provide the output reference voltage that is resistant to power supply variations, the design incorporates an RC filter into conventional reference structure. The CMOS op-amp which is the basic building block for this band gap reference is designed. A 2.5 volt high swing op amp is designed to achieve a DC gain of 60 dB with a unity gain frequency of 7 MHz. The phase margin achieved is 60 degrees that is sufficient to provide stable operation for which the band gap reference gives constant output voltage of 1.25 v for the temperature range of -50 to 150 c Keywords: Band gap Reference, Two Stage CMOS op amp, Multi fingering, Common Centroid layout. I. INTRODUCTION With the development of modern electronic systems, high performance analogue devices have been becoming increasingly important for system integration. As one of the most basic components in analogue VLSI, band-gap voltage reference circuit has been widely used in many applications that require highly accurate voltage reference, such as high precision comparators, D/A and A/D converters etc. In this paper, a CMOS band-gap voltage reference circuit that incorporates an RC filter is presented

Figure 2: Block diagram of Two stage CMOS op amp. The second stage needs to have a negative gain because of the feedback capacitor. With a positive gain an oscillator or unstable system will be implemented instead. The last stage is a buffer to convert the high output impedance of the inverter stage to low output impedance. This is needed in developing a good op amp. Ideal op amp requires rin = and ro=0. The paper is organized as follows - Section II describes the fundamentals of Band gap reference along with op amp. In section III, a systematic design of Band gap reference along with op amp design op amp design is given. In section IV, improved Band gap reference is proposed. In section V, layout aspects like common centroid algorithm and multifingering principle is described. Finally section VI summarizes the results of the paper. The conclusion and future work is discussed in section VII. II. CMOS BAND GAP REFERENCE AND OP AMP FUNDAMENTALS A. CMOS Band Gap Reference CMOS band-gap structures are frequently used to generate the reference voltage with desired accuracy performance. Since the key factors that affect the reference accuracy are power supply, temperature, and output noise etc, various methods and techniques have been adopted to

Figure:1 Block diagram of Band gap reference Figure 1 shows a band gap reference block diagram which gives constant reference voltage irrespective of change in temperature A block diagram of the typical two stage op-amp which is used by this band gap reference is shown in the Figure 1. The design is called two stages as it refers to the number of gain stages in the op-amp. Figure 2 actually shows three

RITS-ICAEM 2012: RITS-International Conference On Advancement In Engineering And Management

28&29th Feb 2012

improve PSRR, minimize temperature coefficient and reduce noise. Figure 3 shows a typical circuit of CMOS band-gap reference.

B. Unity Gain Frequency of op amp Due to Miller effect, the load of the first stage is effectively the compensation capacitance Cc magnified by (1+A2) or approximately the gain of the second stage A2 as show in figure 4.

Figure 3: Typical structure of CMOS band-gap reference In this circuit, through the feedback from reference output, the input voltages ( Vx and Vy) of op-amp tend to be equal, therefore the voltage across the resistor R3 is

Figure 4: Miller effect on gain of first stage

The gain of the first stage is Where,

Where Vt = KT/q is thermal voltage, J1 and J2 are the emitter current densities of the transistors Q1 and Q2, respectively, and their ratio is

The voltage gain of the op amp, assuming the output buffer has unity gain (A3=1),

The unity gain bandwidth, wGB is the radian frequency when the gain is 1. That is, Where N is the ratio of the emitter area (AE2) of Q2 to the emitter area (AE1) of Q1. Combining the equations (1) and (2) gives

Solving for

, we get

Thus,

C. Slew Rate Determination

The output reference voltage VREF can be derived as

The principle to achieve temperature performance is that the thermal voltage VT with a positive temperature coefficient compensates the emitter-to-base voltage VBE2, which has a negative temperature coefficient. Therefore, theoretically, by choosing appropriate parameters of resistors and transistors, the reference output can display a zero temperature coefficient . In terms of the effect of power supply ripple on accuracy of the reference, since VT is irrelevant to power supply and such ripple has very limited influence on VEB2, the output reference VREF can effectively resist power supply variation.

Figure 5: Effect of Cap on Slew Rate

Slew rate is the maximum rate at which the output changes when input signals are large. The affect on slew rate is seen in Figure 5. When vin+ >>0 (vin-<<0) is large positive (negative), M1 is on and M2 is off. Hence ISD1=ISD5, since ISD2=0. The current flows through M3 which is then mirrored to M4, therefore ISD1=IDS3=IDS4=ISD5. The current in the compensation capacitor can only flows through M4,

RITS-ICAEM 2012: RITS-International Conference On Advancement In Engineering And Management

28&29th Feb 2012

since M2 is off and the input impedance of the second stage A2 is . That is ICc=IDS4=ISD5. On the other hand, when vin+<<0 (vin->>0) is large negative (positive), M1 is off and M2 is on. Hence, ISD1=0 which flows through M3 and mirrored to M4, therefore IDS3=IDS4=0. That is, current source ISD5 flows through M2, then to Cc directly, since M4 is off. In both cases, the maximum current that flows through Cc is ISD5.

parameters like Vg Pmos, Vg Nmos, , Vtp, Kp,Kn , Lambda from technology library file of 0.25 micron the following design steps are presented. Design here means finding value of W/L ( for ease of representation in equation aspect ratio is given as a ) of all transistors. In the design process the Unity gain bandwidth and slew rate determine the size of Transistors M1, M2 and M5. The negative CMR influences the size of M3 ad M4. Phase Margin and Gain are key parameters that ascertain the sizes of M6 ad M7 transistors that form the CSA. Finally the output impedance decides the size of M8 and M9[6]. 1. Determine Isd5 from slew rate and Cc SR = ISD5 / Cc Determine Find a5 from Vsd5 and Isd5, use Kp Determine Isd2 and Isd1 which is half of Isd5 Calculate gm1 using gm1=Cc * Wgb from gm1 using standard Determine a1 Calculate a5 again from positive CMR (max Vg1) and applying KVL to M1 and M5 we get find Vsd1 (sat) and ultimately find a1. Select the maximum value from step6 and step7 for a1. Now for symmetry in design a2= a1 Determine a3 from negative CMR specs (min VG1 given) using the equation

III. SYSTEMATIC OP AMP DESIGN A. Design Specifications The op amp to be designed is considered with the following specifications such that it can be used in the design of audio sigma delta ADC. The Design specifications are as follows. Supply Voltages: VDD = + 2.5V, VSS = - 2.5V Open-loop gain: 15000 (84db) Unity Gain Frequency (wGB) = 5 MHz= 25 Slew Rate, SR = 10 V/Sec Output Resistance, Ro 1.5K Common Mode input Range(CMR): -2V to 1.5V Phase Margin = 60

2. 3. 4. 5. 6. 7.

8.

9. Now for symmetry in design a3= a4 10. Determine gm6 using Phase Margin formula PM = 90 2
Figure 6: Transistor level diagram of CMOS Op Amp

and from gm6 calculate a6

B. Design Process For the Band Gap reference we have the equation

11. Determine Isd6 using Isd6= [a6 / a3 ]* Isd3 once obtained Isd7=Isd6. Using Isd7 and Isd5 calculate a7 as a7 = [Isd5/Isd7]*a5 Note: we know a1,a2,a3,a4(Diff amp),a5,a6,a7(CSA) and overall gain of opamp is decided by these two stages 12. Overall Gain is given as = = = use

To get optimal temperature coefficient the following parameters have been assumed VEB2 = 0.67, R1 = 4.37K, R2 = 30K, R3 = 7.42K, N = 10 For which aconstant voltage of 1.25v is obtained A standard design procedure for high Swing Two stage CMOS Op Amp is presented in [3]. Using the given specifications like Slew Rate(SR), Supply Voltages (Vdd, Vss), Unity Gain Frequency (Wgb), Gain, Phase Margin(PM), Output Impedence (Ro) and technology

value of Lambda. Check whether the obtained gain is same as required gain. It should be close if not equal otherwise, redesign. 13. Consider that current flowing through M10 (bias transistor) which is same as current flowing through M8 and M9 and five times Ids5. I,e, Ids10=50uA

RITS-ICAEM 2012: RITS-International Conference On Advancement In Engineering And Management

28&29th Feb 2012

14. Calculate a8 from Ro using the formula

Figure 9: Improved band gap reference with RC filter Hence with the addition of filter circuit power supply noise and other noises are filtered out. V. ASPECTS OF LAYOUT DESIGN

15. We know Isd10, find Vsg10 and calculate a10 using

16. a9 = a10 as same current flows through them. 17. Tabulate all the values as follows

The layout design of analog devices needs to incorporate specialized techniques to make sure that the device doesnt suffer any mismatches, since mismatch in a device could lead to offset errors in differential amplifier stage. Further to optimize space usage on the die, very high aspect ratios are desired for the devices used in the common-drain amplifier stage [4]. The most commonly used techniques are Multifingering and Common centroid layout A. MULTIFINGER TRANSISTORS For transistors that require very large W/L ratio, a folded layout like figure 10.1(a) maybe not enough to reduce high gate resistance instead, a layout like figure 10.1(b) is an improved version of figure 10.1(a) using multifinger transistor. The width of the transistor is reduced to half and the gate resistance is reduced by a factor of 4. While multifinger transistor reduces gate resistance, it raises source and drain capacitance, which introduces a trade-off [5].

Figure 7 Design summary of Op-amp

IV IMPROVED BAND-GAP REFERENCE In order to improve the stability of output reference voltage in resisting power supply ripples and reducing output noise, an improved CMOS band-gap reference structure is proposed in this paper by connecting an RC filter to the output of the reference, as shown in Figure 3

Figure 8 Improved Band gap reference With this circuit a pole of frequency f = 1/ 2 r c is introduced, hence the noise with frequency that is equal to or higher than f can be effectively filtered out, If we choose R= 200k and C = 10f then f is about 30Hz in figure 9 we get better response

Fig 10.1 Transistor with (a) 2 fingers (b) 4 Fingers The transistor M8 used in CDA stage of the Opamp is shown in the fig 4.2. The transistor with W=57m and L=0.8m is designed using 10 fingers of W=5.7m and L=0.8m. The sources of the fingers are connected together to form source(S) of the resultant transistor. Similarly, the drain and gate regions are connected together to form the resultant drain (D) and gate (G). Thereby, the so formed device occupies one tenth the width occupied by its predecessors without fingering.

RITS-ICAEM 2012: RITS-International Conference On Advancement In Engineering And Management

28&29th Feb 2012

Fig 13 Complete Layout of Band Gap refernce

VI. RESULTS AC analysis is performed on the above op amp. Frequency domain plots describe the response of the Op-Amp. Wherein, the gain of the Op-Amp becomes 0 dB much before the -180 degrees point. The compensation was designed for a Phase Margin of 60 degrees but a practical Phase Margin of 50 degrees is achieved. Results also show a gain of 69 dB and Unity gain frequency = 7MHz.

Fig 11 Transistor of CDA with 10 fingers B. COMMON CENTROID LAYOUT Symmetry becomes more difficult to establish for large transistors. In the differential pair the two transistors have a large width so as to achieve a small input offset voltage, but gradients along the x-axis rise to appreciable mismatches. To reduce the error, a common centroid configuration is used such that the effect of first-order gradients along both the axes is cancelled [2]. Illustrated in fig 4.3, the idea is to decompose each transistor into two halves that are placed diagonally opposite of each other and connected in parallel. The differential pair used in the op-amp module is designed using this technique as shown in fig 4.4 Here, as discussed above the transistors M1,M2 are divided into two and are placed diagonally opposite to each other and connected in parallel. The two transistors M1and M2 have common source (S), and drain regions as D1 and D2 [7].

Figure 14 AC analysis of Op amp The above band gap reference is simulated for wide range of temperature from -50 to 150 deg c for which a constant ouput of 1.25 volts is obtained with slight variation in microvolts shown in figure 15

Fig 12 Common Centroid layout of two transistors M1 and M2 used in diff-amp pair The final layout design of Band gap reference with all layout improvement techniques and compensating capacitance is shown in fig 13

Figure 15 Temperature simulation of band gap refernce Also by the introduction of RC filter the noise can be

RITS-ICAEM 2012: RITS-International Conference On Advancement In Engineering And Management

28&29th Feb 2012

[4] Yonghui Tang; Geiger, R.L A 0.6 V ultra low voltage operational amplifier, IEEE International Symposium on Circuits and Systems , page(s): 611 614, 2002

[5] Mohamed Dessouky et al Layout-oriented synthesis

of high performance analog circuits ACM conference on Design, automation and test in Europe, New York, USA, 2000 Figure 16 Noise analysis of Band gap reference reduced for which the noise analysis is as shown in figure16
VII. CONCLUSION AND FUTURE WORK

[6] Ta-Lee Yu et al Multifinger MOS transistor Element US Patent No: 5831316, 1998 [7] Cadence Lab Manual of Wayne state university, USA
D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, New York, 1997. [8] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill, Edition 2002

By introducing an RC filter into traditional CMOS band-gap reference structure a CMOS band-gap reference circuit with high power supply rejection capability, low output noise has been designed for reference voltage of 1.25v for modern analogue VLSI applications. The circuit analysis and simulation results show that the circuit resists power supply variations and significantly reduces high frequency noise level, Therefore the circuit is able to operate in a wide range of frequency and power supply conditions. A two stage CMOS op amp with high voltage rail to rail swing of is designed with a gain of 69dB and unity gain frequency of 7 MHz. The various design challenges in layout design are addressed with the use of advance design techniques like multi fingering and common centroid. The Future work of the op amp design process includes compensation techniques to improve the phase margin of the op amp by introducing an extra transistor in series with compensating capacitor which will improve the performance of the op amp and enables stable operation for the op amp such that it can be applied in various applications like Band gap reference Circuits. With the introduction of RC filter the turn on time of the Band Gap reference circuit will be increased, hence with the help of special circuitry it can be minimized.

References
[1] M Gunawan, GCM Meijerand , J Fonderie, A curvature corrected Low voltage Band Gap reference, IEEE journal of solid state circuits, vol 28,no 6 pp 667670, june 1993 [2] Mahattanakul, J.; Chutichatuporn, J. Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme Regular Papers, IEEE Transactions on Circuits and Systems I , Volume: 52 Issue: 8 page(s): 1508 1514, Aug. 2005 [3] Di Long; Xianlong Hong; Sheqin Dong; Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit IEEE International Symposium on Circuits and Systems, Vol. 3, Page 2999 - 3002, 2005