Extraction & Pos-layout Simulation

As you know, the device you have layout has resistive and capacitive parasitic elements. Thus we need the most accurate model of our inverter device as possible. Then, use this model to carry out pos-simulation in order to check that whether the layout inverter satisfy the specification or not. 1. Open the layout cell view of the inverter that you drawn and passed DRC and LVS Check in previous labs.

2. Set up RCX rule by go to Assura -> Setup -> Rcx Setup In Setup tab, choose gpdk090 in Technology field.

In Extraction tab, choose RC in Set As Default field.

Leave other tabs options as default. Click on OK, then YES from pop up window. 3. To extract, in the layout window go to Assura > Run RCX... and click OK. After doing this a setup window should pop up. Go to the setup tab of the RCX window as shown below:

4. Here you should make sure the output is the "Extracted View". Now, go to the Extraction Tab:

In this screen, you should type the name of your ground node pin into the "Ref Node " box. Then click on "OK". If this is not the first time you are running RCX, you will be prompted to overwrite the cell view, click on Yes. In addition, you may get a file locking failure and log window. IMPORTANT NOTE: It is highly recommended that you choose the coupled mode for the capacitor extraction (not decoupled like in the figure). Coupled mode will display all individual node capacitors to other note, while decoupled mode will lump all these capacitors to the reference node. Coupled is slower, but much more accurate. 6. Note that RCX creates a new view called av_extracted. Open this new view using Library Manager.

5.

Hit Shift-f to flatten. You should get a layout as in figure below.

7.

To make the view even more interesting, enable Nets in Options, Display, Display Controls shown in this view will be used to simulate the performance of the device.

Full Simulation With Extracted Parasitic of Inverter

Having completed the layout of the inverter the next stage of the design process is to simulate the operation and investigate rise and fall times of the inverter. To simulate with the extracted view, the setup is fairly simple. 1. Open test-benchs schematic cell view of the inverter. Change the input of the inverter to vpulse which have properties as below:

2.

Go to Launch -> ADE L, then Setup -> Environment this will pop up a window:

In this window, type av_extracted view at the first one in the list of views. This means the simulator will try and use this model first if available.

Run simulation with conditions as below:

You should soon get a log file and simulation window. First, review the log file. You will get a few warnings about inline components, which can be ignored for our exercise. There should be a few notices. These are because we are simulating such a small device and some of the parameters seem very small to the simulator. Compare this result with the pre-layout simulation to see the difference.

Your task is now to determine rise time tr, fall time tf, propagation delay time tpHL and tpLH. You should already be familiar with which points to measure these between on the simulation output curves. There are several ways to do this using the Cadence simulation results window. Click Trace then Trace Cursor to manually compute the four results needed. Trace then Delta Cursor can be used as well. Additionally, you can use Maker, Place, then Trace Marker (or just hit t then click where you want a label). Assignments: carry out pos-layout simulation with your drawed NOR gate layout. References 1. http://personal.ee.surrey.ac.uk/Personal/T.Vladimirova/Teaching/E1_VLSI_Lab_Manual_v1.pdf