Release Notes For ModelSim SE/PE 5.

7f Copyright Model Technology, a Mentor Graphics Corporation company, 2003 - All rights reserved.

Sep 17 2003 ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file on the Model Technology web site. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation, supported platforms, and licensing, see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp How to Get Support For information on how to obtain technical support visit the support page at: [3]http://www.model.com/support/default.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [4]http://www.model.com/support/default.asp or find them in the installed modeltech tree in <path to modeltech installation>/docs/rlsnotes ______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 5.7f [7]Verilog Defects Repaired in 5.7f [8]PLI Defects Repaired in 5.7f [9]VHDL Defects Repaired in 5.7f [10]FLI Defects Repaired in 5.7f [11]VITAL Defects Repaired in 5.7f [12]Mixed Language Defects Repaired in 5.7f [13]General Defects Repaired in 5.7f [14]Mentor Graphics DRs Repaired in 5.7f [15]Known Defects in 5.7f [16]Product Changes to 5.7f

[17]New Features Added to 5.7f ______________________________________________________________________ Key Information * The following platform will be discontinued as of the ModelSim 5.8 release: + AIX 4.2 * You must recompile or refresh your models if you are moving forward from 5.7 Betas or 5.6x or earlier release versions. See "Regenerating your Libraries" in the ModelSim Start Here Guide for more information on refreshing your models. * Acrobat reader version 4.0 or greater must be used to read any .pdf file contained in ModelSim version 5.5c or greater. * Product changes and new features mentioned here are introduced in the 5.7f release. If you are migrating to the 5.7f release from 5.6x or earlier releases, please also consult version 5.7x release notes for product changes and new features introduced during the 5.7 patch releases. The previous version release notes can be found in your modeltech installation directory at docs/rlsnotes. * The HP-UX 10.20 platform is no longer supported as of the ModelSim 5.7 release. The hp700 platform executables are built on HP-UX 11.0. Please note that in order for FLI/PLI shared libraries to be loaded and executed correctly by the hp700 version of vsim, they must be compiled and lin ed on HP-UX 11.0. * Beginning with the 5.6 release (on Windows platforms only), attempts to lin in libvsim.lib or t 83.lib using the Microsoft Visual C++ lin er version 5.0 will fail with a message similar to "Invalid file or dis full: cannot see to 0xaa77b00". Microsoft Visual C++ version 6.0 should be used. * In the next major release, the linux platform executables will be built on RedHat Enterprise Wor station 2.1. This version is compatible with RedHat 7.2 and higher. RedHat 6.0 through 7.1 will be supported for one release with a new platform vco. ______________________________________________________________________ User Interface Defects Repaired in 5.7f * The virtual save command did not include the -delay option in the generated .do file and it incorrectly generated the list of signals included in delayed virtual signals. * In Modelsim PE, the Main window Tools > Options menu did not wor . For example, if you tried to change the VSIM prompt or Transcript File parameters, it did not wor . * When using the Find dialog in the Source window, the matching item did not highlight unless the dialog box was closed. * The List window failed to update if a gating expression was applied in a macro file specified on the command line. The window updated properly if the macro file was executed at the VSIM prompt. * The performance of ModelSim's user interface was degraded for each selection of the 'Compile Selected', 'Compile All', or 'Compile Out-Of-Date' menu items in a project containing a large number of files. ______________________________________________________________________ Verilog Defects Repaired in 5.7f * $fscanf can now write to a memory element. * $setuphold did not report all the timing violations that were reported by the equivalent $setup and $hold timing chec s. A similar situation existed with $recrem and the equivalent $recovery and $removal timing chec s. Also, some $setup and

$removal errors were not reported if the reference event occurred multiple times in the violation window. * Pulse filtering problems caused events to be scheduled in the past. This occurred when pulses appeared at a path input without a path delay specified, and the path output was included in other paths with specified delays. * vlog allowed inout ports declared using the new ANSI-style syntax to be re-declared. This now reports an error. * The options +nowarnFOFIR and +nowarnFOFIA for suppressing warnings from the $fopen() system tas had no effect. * Path pulse errors were not detected on transitions to X while a previous pulse error was pending for a transition from X to another value. This behavior occurred only when not compiling with -fast. * In some cases sign-extension was not being performed in expressions involving elements of signed arrays. * A force statement involving feedbac did not behave as expected. * The simulator crashed when externally referencing net arrays. * Unconnected ports with $width or $period timing chec s in some cases caused a crash during SDF annotation. * The -optcells option of the add wave command did not wor under some conditions. * An optimized cell with multisource interconnect delays, where at least one of the delays was not annotated, in some cases selected the wrong delay or crashed. * Mixed designs containing Verilog generate constructs crashed in some cases. * Localparams could be overridden with ordered inherited parameter instantiation. Now localparams will be ignored by ordered parameters. * When using the -fast or +opt switch, VHDL configurations could not be referenced from Verilog design units. * Compiling a design that contained unreferenced functions with -fast resulted in an internal compiler error in some cases. * A design containing system function calls that was compiled with -fast produced incorrect results in some cases depending on the optimizations that were applied. * A design using the "list of instances" syntax hung the compiler if a parameter value was passed down in the instantiations and if compiled with -fast. * Compiling a design containing an array of vector nets resulted in an internal compiler error if compiled with -fast and if the net had no drivers. * Optimization interactions when compiling a design with -fast could result in incorrect evaluation of ternary and bitwise infix expressions in some unusual cases if the operand widths did not match each other. * If a Verilog design failed to elaborate with unresolved hierarchical references and the design was elaborated again and it still had unresolved hierarchical references, the simulator could crash. * $fwrite() wrote all zeroes for %u and %z formats when compiled with -fast. * $fwrite ignored multi-channel descriptors when formatting with %u and %z. * Some output path delays with transitions to/from X were being scheduled with the wrong delay value for an optimized cell containing tristate gate primitives. ______________________________________________________________________

PLI Defects Repaired in 5.7f * When comparing a handle to an object obtained from an iterator to a handle to the same object obtained from a system tas /function argument, vpi_compare_objects() always returned FALSE. * vpi_put_value() now supports strength values. * The ability to return handles to VHDL architectures from vpi_handle_by_name() had accidentally been turned off. ______________________________________________________________________ VHDL Defects Repaired in 5.7f * vcom previously allowed a generate statement without a BEGIN eyword between the declarative items and the concurrent statements. Now a warning message is issued, since this is technically illegal VHDL. * When a VHDL entity with an unconstrained port was instantiated with a conversion function connecting the actual to the formal port, the simulation crashed. * There was a problem with vcom label expression parsing. * In some cases the simulator generated bad code and crashed when merging processes together. This occurred when a record or array signal was partially assigned to and some of the assignments occurred within a FOR or WHILE loop. * SDF Interconnect Delays from an indexed bus port to another indexed bus port would give an incorrect error message about expecting a negative generic array size. ______________________________________________________________________ FLI Defects Repaired in 5.7f ______________________________________________________________________ VITAL Defects Repaired in 5.7f ______________________________________________________________________ Mixed Language Defects Repaired in 5.7f * When setting a VHDL generic of type time from Verilog, the value wasn't scaled to the current timescale. ______________________________________________________________________ General Defects Repaired in 5.7f * v2 _int_delays functionality did not correctly handle unconnected ports. ______________________________________________________________________ Mentor Graphics DRs Repaired in 5.7f * DR 00141151 - Added information to error message to advise user that most li ely cause is incorrectly set licensing environment variable. * DR 00140556 - VPI: bug with vpi_compare_objects function. * DR 00146869 - The VHDL procedure modelsim_lib.util.signal_force sometimes failed or crashed when called multiple times with a string literal actual for the second argument (formal "force_value"). * DR 00141981 - Incorrect handling of tri-state buffer bufif0 with -fast. * DR 00141412 - Running vsim using +multisource_int_delays option aborts when loading design and sdf file. * DR 00140217 - Location map variables in library mappings not wor ing. * DR 00139846 - `timescale not considered for generic on VHDL instances.

* DR 00139494 - Invalid error on Verilog 2001 re-definition of ports. ______________________________________________________________________ Known Defects in 5.7f * Designs compiled under ModelSim 5.7e containing indexed part selects of net arrays (eg. net_array[1+:4]) in some cases produce an error when simulated under ModelSim 5.7f: # ** Fatal: (vsim-3377) Invalid part-select expression: 'net_array'. In this case a re-compile under ModelSim 5.7f will be necessary to resolve the error(s). ______________________________________________________________________ Product Changes to 5.7f ______________________________________________________________________ New Features Added to 5.7f * Verilog cells containing bufif0, bufif1, notif0, and notif1 output drivers now optimize.