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Project synopsis

2010

PROJECT SYNOPSIS Project title:


DESIGN AND VERIFICATION OF SOC BUS BRIDGE

AIM:

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Project synopsis

2010

To Design and verify an SOC(system on chip) bus bridge between OCP to AXI protocol using VHDL and Verify the design using VHDL Test bench and System Verilog Assertions (SVA).

INTRODUCTION:
System on Chip (SoC) are built by integrating many Intellectual Property (IP) cores, Reuse of Intellectual Property (IP) modules has become common practice in chip design. Aimed at accelerating the design phase and increasing system reliability, pre-designed and pre-verified modules are integrated into a single chip. As the integrated modules are often designed by different groups and for different purposes, they typically comply with different interface protocols. For such modules to communicate correctly there is a need for a Bus Bridge that mediates between them. A general SoC architecture, including Bus Bridge for modules is illustrated in Figure 1.

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Project synopsis

2010

System on Chips (SOC) uses many complex bus protocols for data transfer because of the merits of shared resources, low cost of implementation and high performance. Bus bridges are used for conversion and communication among these protocols. The Open Core Protocol (OCP) defines a high performance, bus independent, interface between IP cores that reduces design time, design risk, and manufacturing costs for SOC designs. The AMBA Advanced eXtensible Interface (AXI) protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for a high speed submicron interconnects. Nowadays these protocols common in SOC designs so communication between protocols is indeed and achieved using bus bridge. This project implements the Bus-Bridge to achieve a communication between master subsystems that uses the protocol OCPv3.0 to slave subsystem that uses AXIv2.0. Bus Bridge converts the OCP signals to AXI signals and vice-versa. The implementation of Bus Bridge includes designing the FSMs for OCPv3.0 and AMBA AXIv2.0. These FSMs are implemented using for VHDL. The design will be verified using VHDL test bench and System Verilog Assertions (SVA).

OBJECTIVES:
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Project synopsis

2010

1. To Perform the Literature Survey on OCP Protocols and AXI Protocols (Difference between various profiles) and the need for a Bus Bridge. 2. To Prepare a Design Document for AXI to OCP Bus Bridge, detailing the following: - Requirements - Eg. The design should be Spyglass clean (Linting). - This design must be synthesizable. - Top level block diagram of the design. - Top level interface signals. - Design of Finite State Machines (FSM) if any. - Limitations. 3. Implement the design document using VHDL. 4. To prepare a Verification Plan to verify the Design, detailing the following: - Verification Strategy with Top Level diagrams - Usage of BFM/Transactors. - SVA VIP usage (AXI). - Functional Claims of the Design. - Testcase description. - Coverage goals. - Functional Claims vs. Testcase Table (Requirement Matrix).
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Project synopsis

2010

5. Implement the Verification Plan using VHDL and SVA. 6. Demo & Presentation.

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