INTRODUCTION

In Sequential circuits output is a function of present inputs and pat output. These circuits have a feedback element or memory element which stores the output of the circuit and makes it available at the input. The following is the general diagram of sequential circuits:

The binary information stored in the memory element that is fed back into the circuit defines the state of the circuit. Sequential circuits are of two types: Synchronous circuits: In these types of circuit, output is defined only on the basis of values of inputs at discrete instants of time. In these circuits we use flip-flops as memory devices and a common clock is used to control the working of the circuit. A clock is a periodic wave which continuously changes its state from 1 to 0 and 0 to 1 as

When-ever pulse goes from high to low, it is called FALLING or TRAILING EDGE and when pulse goes from low to high, it is called RISING EDGE. Asynchronous circuits: In these types of circuit every change in the inputs affects output and output depends on values at every instant of the inputs. All the circuits which dont have any flip-flops or clock are called Asynchronous circuits. Hence all the combinational circuits are Asynchronous circuits.

CLOCK

A clock signal is defined by clock period or clock frequency. The clock period is defined as time interval after which clock repeats it self or we can define it as time gap between two consecutive falling edges or two consecutive rising edges and clock frequency is defined as number of clock pulses in a second. Clock freq = 1/ clock period Duty Cycle: of a periodic wave is defined as percentage of the clock period we have a HIGH pulse. i.e. Duty cycle = (time for which pulse is 1)*100 / Clock period

If width of HIGH pulse = width of LOW pulse = t as shown above. Then Duty cycle = t/ 2t *100 = 50% If we are given duty cycle = 33%, then it means 100/3 = (time for which pulse is 1)*100 / Clock period Hence width of HIGH pulse = (1/3) * clock period as shown below:

BISTABLE MULTIVIBRATOR
FLIP-FLOP is another name of Bi-stable Multi-vibrator. A flip-flop is the basic element of sequential circuit. It has the capability of storing 1 bit. The circuit of the Bistable Multi- vibrator using transistors is as follow:

The two transistors are used to store a single bit and they can hold data without external assistance as far as power is supplied to the circuit. If Q is high we get high as an input to the transistor T1 and hence Q bar is low and as Q bar is low we get LOW as input to transistor T2 and hence Q is HIGH. We can see how output is maintained by the circuit itself. So we dont need t refresh the circuit again and again. DERIVING THE CIRCUIT OF FLIPFLOP (from digital

components):
To understand the logic lets consider a basic circuit of an inverter with a feedback as below:

Now what would be the output of the circuit? We know what ever is at input, well get inverse of that at output and as output is fed back to input so again it would be inverted and this way well have a pulse oscillating between 0 and 1. Hence the output is as follow:

And width of the pulse (either LOW or HIGH) would be equal to the total delay of the gate and wires. Hence we have the clock period equal to 2*(gate delay + wire delay).

But basic function of a sequential element is to hold the value but in the above circuit we have an oscillating value and hence no permanent value is stored.

To store a value what we can do is use 2 inverters and hence only one value would be stored in the value as net effect of 2 inverters is same output as input. So we are able to store one bit in the cell.

But even there is a problem associated with this circuit as we dont know the value stored in the circuit, as soon as we complete this circuit a value is stored immediately and circuit becomes stable. Let the stable value is 0 in the circuit as shown:

Now if we try to input a 1 to the circuit from the input as:

It would be of no use as providing a +5v (high) and a 0v (low) would result in sinking the whole voltage and hence net input as zero voltage. Well not be able to change the value stored as input would still be zero and hence value stored would be zero. And hence there is no provision that we can set a value in the circuit. To make this provision we make a change in the circuit as follow:

We have place an OR gate with one input as S and the other input being the feed back input. So in this circuit initial value stored is 0.

Role of S: what ever is the value of S, that value is stored in the circuit. Now if we make S=1 then well get a 1 as output of OR gate and hence 1 is stored in the circuit. Now the situation of the circuit is as follow:

Another problem in the circuit

How to make it zero now: now 1 is stored in the circuit and if we want to store a 0 again in the circuit then we make S=0. But when we make S=0, we are not able to change the value from 1 to 0. So we find that there is another problem with this circuit that we are not able change value to 0. What now..? Now we make another change in the circuit as follow so that we can change the value to 0 or 1 as we want: As we have seen that we can put a 1 on the line using OR gate but we need to put a 0 at the input of first inverter to store a 0 in the circuit. So what do we do now? Lets see values at different points in the circuit if a 0 is stored.

And we see that if we can place a 1 in the middle of two inverters we can change the value stored to 0 and hence we include an OR gate in the middle of inverters as follow:

We can represent the above circuit as follow (replacing OR & NOT with NOR):

In the middle of two NOR gates we have the invert of what we have at the output. hence we can represent the middle point with Q bar.

And with little adjustments we can represent the above circuit as given on the next page:

This circuit is called RS latch and we can store either a 0 or a 1 in this circuit depending upon the value of R & S as discussed on next page.

RS FLIPFLOP
When R=0, S=0 we dont have a change in the output in the circuit. When R=0, S=1 we have output as Q=1 and Q bar = 0 When R=1, S=0 we have the output as Q=0 and Q bar = 1 But when we have R=1, S=1, both R and S make outputs of their NOR gates 0. Hence we have Q=0, Q bar = 0 which is not a valid case as Q & Q bar should be compliment of each other and hence we dont consider this case. This is calledRACE CONDITION. All these cases can be collectively represented in a table as follow:

Lets draw the timing diagram of the RS latch: t is the delay for a NOR gate.

Initially we have R=0, S=0 and Q=0. When value of S changes to 1, we see in the circuit of RS latch, output of NOR gate (which is Q) becomes 0 after delay of t ns. Hence both Q & Q are 0.Now inputs of other NOR gate become R=0 & Q=0 and hence we get Q as 1 after another delay of t ns which is shown in the timing diagram. Similarly other outputs are shown. We can also represent the above circuit using NAND gates as: Lets convert to NAND circuit step by step.

Now we replace R by R (bar) and S by S (bar) and eliminating the 2 circles and hence final circuit.

The characteristics of the FF are as given in table:

Clocking RS latch:

We can control RS Latch with clock by ANDing both inputs with clock separately as:

Hence when we have CLK (OR E) = 1, R & S gets passed to the RS latch circuit and hence the output is affected by the inputs only when CLK (OR E) = 1 and when CLK (OR E)=0, inputs are not passed to the circuit and hence whole circuit is isolated from R & S. As this circuit is enabled only when Level of the CLK (OR E) is HIGH and disabled when level of CLK (OR E) is LOW, this is called LEVEL SENSITIVE (LATCH). So when ever CLK (OR E) is high all the changes in the input are transmitted to the output as shown in the waveforms below:

D Latch:
As we have already discussed that when ever we have both R & S equal to 1 we witness an ambiguous state. Hence to avoid this we have made an arrangement in which well never have both R & S equal. We connect the two inputs with an inverter between them as shown below:

This is the flip-flop which is most widely used in real world applications. This is also called delay Latch. The following table would show the overall functioning of the Dlatch:

JK LATCH:
This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow:

Lets now try to understand this circuit. We can see that in the circuit above we have ANDed Q bar with J & CLK (OR E) and Q with K & CLK(OR E). Hence when we have previous Q=1, Q bar=0 then J would not be passed further and K would be passed which means latch can be cleared if we have previous Q=1. When we have Q=0, Q bar=1 then only K would not be passed and J would be passed and we see that Latch can be set if previous output is 0.

We discuss all the cases below: When J=1.K=1 If previous Q=0, then we need to get output as Q=1(compliment of previous output), Q bar=0 hence we need to have inputs reaching the basic flip-flop are J=1, K=0. Hence we AND input K with the previous output Q and J with Q bar, due to which only upper AND is activated and only J is passed and hence we get the output=1. If previous Q=1, then we need to get output as Q=0 (compliment of previous output), Q bar=1. Hence we need inputs to the basic flip-flop as J=0, K=1 to clear the output. As we have ANDed J with previous Q bar and K with Q, lower AND gate is activated and K=1 is passed to clear the output. When J=1, K=0 As J is ANDed with Q so J=1 would be passed only when we have we have Q=1. Hence when we have Q=0 & Q=1, upper AND gate is activated and J would be passed further and hence output would be set to 1. And if we have previous outputs as Q=1 & Q=0, we need not pass J as output would be same even if we pass it.

When J=0, K=1

As K is ANDed with Q, so K=1 would be passed further if we have previous Q=1 & Q=0 (lower AND gate is activated) and hence output would be cleared but if previous Q=0, Q=1 then we need not pass the inputs J=0, K=1 (which would clear the output) as theyll not affect the output independent of whether inputs are passed or not. When J=0, K=0 As both the inputs are zero, output is not affected. The following table summarizes all the functioning:

Waveforms representing the behavior of JK latch are as:

T Latch:
This latch is obtained from JK by connecting both the inputs. This is also known asToggle latch as output is toggled if T=1. The truth table is:

The circuit diagram of T latch is as follow:

TIMING PROBLEM IN LATCHES:

Well in sequential circuits, paths exit between latches through combinational circuits from one latch to other or from output of latch to input of same latch. When we give a feed back to input of same latch then we face a timing problem as shown: Suppose we have the following circuit:

In this circuit when ever we have E=1, output Q of latch is complimenting again and again as we have connect the Q-bar to D input. We represent the above in waveforms as:

But ideal is that we have only one transition in the output per clock. Hence to avoid this problem we use edge triggered flip-flops. PROBLEM IN JK & T LATCH: When we have J=1, K=1 or T=1 then output is complimented and if CLK (OR E) is still HIGH, then when the new output is fed back,

output is complimented again and this way output is continuously complimented. This problem is called RACE AROUND PROBLEM. We can observe this as: Let Q=1,Q=0 with J=1, K=1 or T=1, then lower AND gate is enabled and hence J=0, K=1 is passed and output is cleared and we have Q=0, Q=1. If CLK (OR E) is still HIGH and now as Q=0, Q=1, then upper AND gate is activated and J=1, K=0 is passed, hence output is now set i.e. Q=1,Q=0 and so on.

To avoid this RACE AROUND PROBLEM we can make sure that pulse width of the clock is less than the propagation delay of the Latch. Due to this restriction JK & T latches are generally not used in this form but as edge triggered flip-flops which are discussed later.

ASYNCHRONOUS INPUTS:
There are two special inputs which are used to clear and preset the value of the flipflop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal dont wait for the clock to come but can affect the output independent of the clock. These inputs can be of two types: Active LOW: This means when the input is LOW, it would affect the output otherwise if input is HIGH then it causes no change. Active HIGH: This means when input is HIGH then it can change the output otherwise if input is LOW, it doesnt cause any change in the output. These inputs can be adjusted in the circuit diagram of the flip-flop with Active HIGH DIRECT

INPUTS as:

Red colored line defines the boundary of the flip-flop. The following table shows the output for various combinations of inputs with Active HIGH direct inputs:

Similarly we can have the circuit for Active LOW direct inputs

Waveforms illustrating the functions of CLEAR & PRESET inputs for T Flip-flop are as:

Note: When we have both PRESET & CLEAR equal to 1 (in Active high inputs) we have RACE CONDITION as PRESET tries to make output equal to 1 and CLEAR tries to make output equal to 0 simultaneously which is not possible.. Similarly we have RACE CONDITION when both PRESET & CLEAR are equal to 0 in Active low inputs.

Different parameters of clock pulses:

Note that we need the width of PRESET pulse, CLEAR pulse etc to be greater than some minimum values for proper operation of every flip-flop. This width is measured between 50% transition points of rising and trailing edges of the given signal.

Setup and Hold time are measured w.r.t the activating clock edge. The Setup time is the difference between the 50% transition point of DATA input before clock edge and 50% transition point of activating clock edge while Hold time is measured between 50% transition point of activating clock edge and 50% transition point of the DATA after clock edge as shown below:

Propagation time is measured between 50% transition point of activating clock edge and the 50% transition point of output for the corresponding edge but it is generally different when output changes from 1 to 0 or 0 to 1. Hence we define propagation time TpHL as difference between 50% transition point of activating clock edge and 50% transition point of the output change from HIGH to LOW

while propagation time TpLH as difference between 50% transition point of activating clock edge and 50% transition point of the output change from LOW to HIGH.

And we take average of both TpHL and TpLH to specify the propagation time

QUESTIONS:
Q-What is the difference between LATCH & FLIP-Flop? Ans: We can easily find the answer after going through the theory given:

1. Latches are level sensitive while flip-flops are edge sensitive devices 2. Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops. 3. As we can see from different circuits given earlier, we need more gates to implement flip-flops than latches.
Q- Implement the function of D latch using MUX? Ans: We know D-LATCH can be triggered when CLK is 1 (positive level triggered) or when CLK is 0 (negative level triggered). Hence we can implement both of these as follow:

And we can make a truth table for each of these as: Those are actually the truth tables for D-LATCH. Hence we get the D-latch using MUX.

Q- Implement the function of T latch using MUX & a NAND gate? Ans: We can achieve the above as follow:

EDGE SENSITIVE LATCH (i.e. FLIP-FLOP):

Latches which are activated by the edge of the clock are called Flip-flops. If it is apositive edged flip-flop then inputs are accepted only when a LOW to HIGH transition occurs in the clock and if it is a negative edged flip-flop then inputs are accepted only when there is a HIGH to LOW transition in the clock signal.

When we use a pulse triggered latches in the circuit then every fluctuation in the input is visible in output. Hence we use edge triggered flip-flop and output is generated only depending upon the value of input at the clock edge. We represent the flip-flop similar to latch but in flip-flops we place a triangle near CLK terminal as shown: And to represent a negative edged flip-flop we place a circle before the triangle (as we do in case of inverter) shown below:

One way to make flip-flop respond to edge of the clock only, we use a RC circuit to produce a edged clock rather than a pulsed clock. This RC circuit generates spikes in response to the transitions in the clock pulse as shown below and we use either positive or negative spikes and neglecting the other spike.

We can get only positive spike using following circuit:

We can also achieve edge triggering by other methods as explained next.

Master slave flip-flop- PART I:

We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level.

Diagram of the RS master-slave flip-flop is as:

First latch acts as a master and 2nd latch acts as a slave. Master latch is enabled on positive level and slave latch is enabled on negative level. Hence when ever CLK goes positive, master latch starts accepting the inputs and generates the outputs correspondingly. But as slave latch is disabled it accepts none of the generated outputs but when CLK goes LOW, 2nd latch starts accepting inputs and inputs are actually the final output of the master latch (which is the output corresponding to the inputs at last moments of HIGH pulse to master latch just before falling edge) . Hence slave latch just passes that final output of the master latch to the output terminals or we can say as a whole, output is produced only corresponding to the inputs which are just before the falling edge and the whole circuit acts as anegative edged flip-flop. Circuit diagram of RS master-slave is as:

Similarly we can achieve a positive edged flip-flop by triggering master flip-flop on negative level and slave flip-flop on positive level of the pulse. Well use inverter to master flip-flop instead of slave flip-flop.

MASTER SLAVE FF - PART II

We can have a Master-Slave JK flip-flop as following diagram:

And while drawing the circuit diagram we instead of giving two feed backs (one for each flip-flop), well draw only a single feedback from the final output of the whole circuit to the input of the circuit and implement the JK flip-flop. We can analyze the circuit as we did in case JK latch and see that JK flip-flop is implemented by following circuit:

-: Master Slave JK flip-flop:-

Following waveforms for positive edge triggered flip-flop would further illustrate the working of an edge triggered flip-flops:

PROBLEM IN MASTER SLAVE:

We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and following waveforms are the expected output of RS flip-flop

While when we actually give the above inputs to RS master-slave flip-flop, we get the following outputs

And we see that at the 4th and 5th edge we have the wrong transitions. Why so? Before the 4th negative edge, there is small R pulse which resets the output of Master RS flip-flop and after resetting the output of master RS flip-flop R goes low. Now we have S=0 & R=0 and output of master stays low and hence when transition of CLK occurs from 1 to 0, we have S=0 & R=1 (instead of S=1 & R=0) at the slave FF and hence final output is reset. So we notice that a high pulse at R has affected output even when pulse occurred much before the negative edge. Before the 5th negative edge, a short high pulse occurs at S input of master due to which output of master is set to 1 and after some time S resets and we have S=0 & R=0 and hence output of master stays high and when CLK goes from 1 to 0, we have inputs of slave as S=1 & R=0 (instead of S=0 & R=1) and hence final output is set to 1. We again notice a pulse which occurs much before the edge and still affects the final output. So we find a situation when a master-slave flip-flop doesnt work as edge-triggered FF. Similar problem well face in JK flip-flop as we have a no change condition in both FFs. But we can realize a edge-triggered FF with D Flip-flop without this problem as:

D-Flip-flop using MUX

Q- Can we implement the D-Flip-flop using MUX?

Ans: Yes, we can. As we can derive a D FF from D latch by following circuit:

So we implement the above circuit to get D ff from MUX as: The following D FF is a falling edged or negative edged Flip-flop.

And we can implement the rising edge or positive edged flip-flop using negative level triggered D-LATCH as:

TIMING PARAMETERS OF A FLIP-FLOP:

There are basically 3 types of factors which affect the working of a flip-flop: 1. SETUP TIME 2. HOLD TIME

3. PROPAGATION TIME

SETUP TIME & HOLD TIME

Setup Time: This is defined as minimum amount of time required for which an input should be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-flop and setup time is t= 1ns seconds. If clock pulse with period 5 ns is going from 0 to 1 i.e. first positive edge is coming at time t=1 ns then both inputs J & K should be stable for 1 ns from time t=0ns to t=1ns & t=5ns to t=6 ns & t=10 ns to t= 11 ns i.e. J & K should not change during this period as shown:

Hold Time: This is defined as minimum amount of time required for which an input should be stable just after the clock transition occurs. Suppose we have a positive edged JK flip-flop and Hold time is t= 1ns seconds. If clock pulse with period 5 ns is going from 0 to 1 i.e. first positive edge is coming at time t=1 ns then both inputs J & K should be stable for 1 ns from time t=1ns to t=2ns & t=5ns to t=6 ns & t=11 ns to t= 12 ns i.e. J & K should not change during this period as shown:

And both conditions can be represented as follow and inputs should be stable for at least 2 ns:

Well there are some special timing requirements which must be fulfilled by the input signal to get a valid output at the output terminal. If any of the above requirements is not followed and inputs change their value within any of setup time window or hold time window, then output of the flip-flop can not be predicted and flipflop is said to enter in METASTABLE STATE and output can be either zero or one. This whole process is called METASTABILITY.

PROPAGATION TIME:
It is defined as the time after the clock transition, required for a flip-flop to generate output. This is also called CLOCK TO Q delay T clock-to-q. e.g. Lets draw the wave forms of inputs and outputs for D FLIP-FLOP which would illustrate the above discussed:

Maximum Frequency of the clock signal:

To achieve the maximum frequency of the clock signal we can assume to start SETUP time immediately after the CLK to Q delay is finished.

This would mean that we can have the next positive edge (CLK to Q delay + SETUP time) after the previous positive edge. And with 50% duty cycle, falling edge would be right in the middle of positive edges. Hence we get the total minimum time period and maximum frequency of the clock signal as

Tmin = CLK to Q delay + SETUP time Fmax= 1/ Tmin = 1/( TCLK-to-Q + TSETUP)

Q- We are given a D FF which is used as a divide by 2 circuit and specifications of the flip-flop are as: T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and circuit is as:

Ans: Ill recommend drawing the 1st edge of clock and then to mark the various delays which we require for proper input to reach the flip-flops before the 2nd edge of the clock as: We know that we have to obey following conditions of setup & propagation time:

To get the minimum delay (maximum frequency of the circuit) , we eliminate the time between end of propagation time and starting of setup time and we get the clock

waveform as: minimum time period as:

Hence we get to know that

T = T (setup) + T (CLK to Q) = 5 + 9 = 14 ns = 14 * 10-9 s And the maximum frequency we get is 1/ T = 1 / 14 = 109 / 14 = 71.4 MHz Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns

Ans: As input to first flip-flop is directly available and hence this doesnt affect clock frequency but input to 2nd flip-flop reaches after various delays from the previous edge of the clock. We the above as follow:

And the complete clock can be represented as follow: c-delay is combinational delay

Hence clock time period = T CLK to Q + c-delay + Setup time = 9 + 13 + 5 = 27 ns And maximum frequency of the circuit is F max = 1 / 27 = 3.7 MHz Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns.

Ans: There is a change in the circuit from the previous questions that we have an extra buffer in the way of clock signal to 2nd flip-flop. Due to this buffer, clock edge reaching 2nd flip-flop delays by 2 ns. Note that we calculate the various delays for input of 2nd FF wrt the clock edge of 1st flip-flop. And input going through all the delays should reach before clock edge reaches the 2nd flip-flop. Let me represent the above in a diagram as follow: We firstly represent the delays wrt edge of 1st FF as

And the delayed input must reach before the edge reaches 2nd flip-flop

And we know that for 1st FF clock edge can reach anytime as there is direct input available. Hence we get that Clock time period is T = T CLK to Q + cdelay + Setup time clock delay for 2nd FF = 9 + 13 + 5 2 = 25 ns And maximum frequency of the circuit is F max = 1 / 25 = 4.0 MHz

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit.

Ans: Now we to take care of following conditions while calculating maximum frequency of the circuit:

Inputs of FF1 come directly hence only setup time of FF1 should be satisfied Various delays would matter for Inputs of FF2 wrt to the previous edge of FF1 Various delays would matter for Inputs of FF3 wrt to the previous edge of FF2

Lets represent all delays with the different clock edges:

Hence we get to know that If we calculate minimum clock period (Tmin) considering conditions to be fulfilled for edge of FF1 then Tmin= T1 (setup) = 5 ns Considering conditions to be fulfilled for edge of FF2 then Q) + cdelay1 + setup2 = 9 + 13 + 4 = 26 ns Considering conditions to be fulfilled for edge of FF3 then Q) + cdelay2 + setup3 = 7 + 4 +16 = 27 ns Tmin= T1 (CLK to

Tmin= T2 (CLK to

Now if we take clock period as 5 ns then well not be able to satisfy the condition at clock edge of FF2 & FF3 (As clock is common for all) If we take clock period as 26 ns, then well be satisfying the condition at FF1 & FF2 but conditions of FF3 would not be satisfied & hence we cannot take this as clock period. But if we take clock period as 27 ns then we satisfy the condition at every clock edge. Hence minimum clock period to satisfy every condition is Tmin = 27 and maximum clock frequency we get is 1/ 27 = 3.7 MHz

CHARACTERISTIC EQUATION OF RS FLIP-FLOP:

The truth table for RS Flip-flop is as follow:

Now lets draw the K-map and get the equation for output Q. As the Qp and Qp bar are compliment of each other so well consider only one of those in K-MAP

CHARACTERISTIC EQUATION OF D FLIP-FLOP:

Truth table is as:

The equation we get is

CHARACTERISTIC EQUATION OF JK FLIP-FLOP: The truth table for RS Flip-flop is as follow:

The equation we get is

CHARACTERISTIC EQUATION OF T FLIP-FLOP:

THE TRUTH TABLE IS AS

And the equation we get is as:

EXCITATION TABLE OF FLIP-FLOPS

Excitation of a flip-flop is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change. E.g. As in truth table we say for T flip-flop if input T is 1 and previous Q is 0 then we have output as 1 while in excitation table we are given that present output Q is 0 and new Q is 1 then input T is 1.

Next we write truth table of various flip-flops and then we write their excitation flipflops.

EXCITATION TABLE OF RS Flip-flop:

The truth table of the RS flip-flops is as:

Now to write the excitation table of this flip-flop we first write the various output changes possible as:

Now we can see from that truth table that to change output from 0 to 0, we can keep inputs S, R as 0, 0 or 0, 1 and we can write both the combinations as 0, X which means we just need to keep S=0 and R can have either of two possible values. Similarly we can note that for output change from 0 to 1, we keep inputs at S=1, R=0.Similarly we can find the other cases and we get the table as:

Similarly we can find out the excitation tables for other kind of flip-flops as shown next:

EXCITATION TABLE OF OTHER FFs

D Flip-flop: The excitation table of D flip-flop is as:

JK Flip-flop: The excitation table of JK flip-flop is as:

For output change from 0 to 1 we can either keep inputs J, K as 1, 0 or we can make use of toggle input combination J=1, K=1 to get compliment of the output. Similarly the other case T Flip-flop: The excitation table of T flip-flop is as:

CONVERSION OF ONE FLIP-FLOP TO OTHER:

As we have already seen from the way we derived D flip-flop from RS flip-flop or the way we derived T flip-flop from JK flip-flop or the way we derived JK flip-flop from RS flip-flop by feeding back outputs that to derive a flip-flop from the other flip-flop we

need to design a combinational arrangement before the given flip-flop to convert the given to work as required flip-flop. Hence the general diagram to obtain a flip-flop from the given flip-flop is as:

RS flip-flop to D flip-flop:
Lets first now derive the D flip-flop from RS flip-flop which we have already done: We first write the truth table for required D flip-flop as

Now we write the excitation table of given FF SR flip-flop as

Now we need to make a arrangement so that we manipulate input D to inputs R, S such that we get the same output with RS FF as that of D FF. So we combine the two tables given above with same outputs in the same row:

Now we design the combinational circuit to convert D input to SR inputs using K-map as:

K-map for S input:

K-map for R input:

Hence we convert the SR FF to D FF as:

RS flip-flop to JK flip-flop:
We first write the truth table for required Flip-flop i.e. JK FF

Now we write the excitation table of given FF SR flip-flop as

Now we combine two tables to get the combinational circuit as:

Now we design the combinational circuit to convert J, K to corresponding R, S K-map for S input:

K-map for R input:

So we get the circuit to convert RS FF to JK FF:

D Flip-flop to RS flip-flop:
We first write the truth table for required Flip-flop i.e. RS FF

Now we write the excitation table of given FF i.e. D flip-flop as

Now we combine two tables to get the combinational circuit as:

Now we design the combinational circuit to convert J, K to corresponding R, S

K-map for D input:

And we get the circuit to convert D to SR FF:

D to T & T to D FF
Similarly we get the circuits as follow: D FF to T FF:

T FF to D FF:

Note: We have not shown the clock but we can attach the clock signal to the given FF.

Similarly we can obtain other conversions.

MEMORY
1-bit Memory Cell: We know that flip-flop can store either zero or one permanently until a change is made in the inputs. Hence flip-flop would work as 1-bit memory cell.

Registers:
A register is a group of 1- bit memory cells. To make a N-bit register we need N 1-bit memory cells. Register with parallel load: We can represent a simple 4-bit register as: We can give the values to be stored at input and we get that value stored at the next clock pulse.

But in this circuit we have to maintain the inputs to keep the outputs unchanged as we dont have the input condition in D Flip-flop for unchanged output. Hence we modify the above circuit with an extra

input LOAD which when 1 would mean there is a new input data to be stored and LOAD=0 would mean we have keep the stored data same. The modified circuit is as:

Shift register:
In this type of register value stored in the register can be either shifted to left or right depending upon the circuit as: PARALLEL IN PARALLEL OUT: This type of shift registers is already discussed above. SERIAL IN SERIAL OUT: Right shift: Here data is shifted by one bit from left to right with every clock tick.

Left shift: Here data is shifted by one bit from right to left with every clock tick

SERIAL IN PARALLEL OUT: In this type of register we firstly load data serially in the register. For a 4-it register well need 4 clock cycles to load data and then output comes out in parallel mode.

PARALLEL IN SERIAL OUT: In this type of shift registers we first input the Parallel data by using LOAD=1 and then data is shifted and data comes out serially.