Chapter 1 INTRODUCTION

1.1 Background
The function of the Acoustic Emission Sensor Network is to locate faults based on the acoustic signatures captured by a network of nodes. Each node is a processor based system equipped with an acoustic sensor, signal conditioning and data acquisition hardware, memory for local data storage, a processor for computation of parameters based on the acquired digital data which would characterize the acoustic signal captured, a wireless radio for transmitting the acquired and computed data to a server. The node was based on the popular low power MSP processor from Texas Instruments. The ADC used in this network generates samples at a rate of 40 million samples per second. The MSP processor cannot read data with such a high sampling rate. This was achieved by using a CPLD that controls the functioning of ADC and stores the samples into SRAM. The MSP processor reads sensor data on receipt of acquisition complete signal from the CPLD. ZigBee, a low power wireless technology working in the unlicensed 2.4 GHz ISM band was the technology chosen for wireless communication.

Fig. No.1.1 Hardware block schematic of AES node

1.2 Aim of this Project

The main objective of the project is to design and implement CPLD based subsystem that interacts with ADC and stores digital data into SRAM directly and transfer the same data from SRAM to microcontroller (MSP430 based) sub-system for further processing.

1.3 Methodology
Depending on the area of the object in which structural defects are to be detected, AES nodes are distributed on the surface of the object. Reception of burst of data is done by CPLD, CY62167 and calculation of different parameters is performed by microcontroller, MSP430F2418.The results are analyzed by simulating the code using Xilinx ISE 9.1i Project Navigator tool and Xilinx Chip Scope.

1.4 Significance of this Work

The main application of the Acoustics Emission Sensing Network is to locate the structural defects which are supposed to be found before they occur. Mainly this application is used to find the defects in 1) Bridges 2) Containers

1.5 Outline of this Report

Chapter 1 gives introduction to Acoustic Emission Sensing Network along with block diagram showing various components used in the process. Chapter 2 gives the detailed description of all the blocks used in the AES node. It also explains the operation of the node. Chapter 3 explains about CPLD in general and also about the difference between CPLD and FPGA. It gives the functional block diagram of Xc2c256 CPLD from Xilinx and its features. Chapter 4 details the operation of SRAM in general and about CY62167, SRAM from Cypress Semiconductors in particular. Chapter 5 shows the schematics of CPLD card and also about the components used in schematics. Chapter 6 explains about the language used to develop the code and the tools that are used to simulate the code to analyze the results. Chapter 7 gives the conclusion of the project and its applications and future scope.
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1.6 Conclusion
This chapter gives the overview of the project i.e., the block diagram of the AESN node which shows different blocks used and the interconnections between them and tools used, applications of AESN node and about the contents of the remaining chapters.

Chapter 2 DESCRIPTION OF AES NODE

The AES nodes acquire acoustic data, compute derived parameters and transmit them using ZigBee wireless technology to the Zigbee-WiFi Converter. The AES nodes can also receive configuration data and change their configuration parameter settings. The hardware block schematic of the AES node is given in Fig. No.1.1. The Zigbee-WiFi Converter will connect the AES nodes which are in a ZigBee network and the main server which is Wi-Fi enabled. The Bridge is two-way; from the ZigBee to Wi-Fi networks and vice-versa. The explanation of each block involved is as follows.

2.1 Acoustic Emission Sensor

The acoustic emission sensor will sense the acoustics from structures and feeds to the amplifier for further processing. Three types of acoustic sensors can be used. However in a node there will be only one type of sensor. The sensor types are as follows:

Table 2.1 Types of sensors S.No. 1 2 3 Sensor Type TYPE-I TYPE-II TYPE-III Maximum Frequency Of Output Signal 175KHZ 375KHZ 500KHZ

2.2 Preamplifier
The sensor output is fed to a pre-amplifier with a fixed gain. The preamplifier used is AD8632 from Analog Devices. The AD8632 brings precision and bandwidth to the SOT-23-5 package at single supply voltages as low as 1.8 V and low supply current. The small package makes it possible to place the AD8631 next to sensors, reducing external noise pickup. The AD8632 are rail-to-rail input and output bipolar amplifiers with a gain bandwidth of 4 MHz and typical voltage offset of 0.8 mV from a 1.8 V supply. The low supply current and the low supply voltage make these parts ideal for battery-powered applications. The 3 V/s slew rate makes the AD8632 a good match for driving ASIC inputs, such as voice codecs. The AD8632 is specified over the extended industrial ( 40_C to +125_C) temperature range. The dual AD8632 is available in 8-lead SOIC and SOIC packages.

Fig. No.2.1 Pin configuration of AD 8632

2.3 Variable Gain Amplifier

A variable-gain or voltage-controlled amplifier is an electronic amplifier that varies its gain depending on a control voltage (often abbreviated CV).Variable gain amplifiers is used to amplify or attenuate incoming signals to properly drive an associated analog-to-digital converter (A/D). Based upon the gain signal, the variable gain amplifier will accordingly amplify an input signal by an amount corresponding to the gain signal, to obtain an amplifier output signal. Gain in the node is a configurable parameter. The microcontroller controls the gain of this amplifier based on the configured gain. The gain can be set with a resolution of 2 db over a 40 db range. The VGA used here is AD 8639. The AD8638/AD8639 are single and dual wide bandwidth, auto-zero amplifiers featuring rail-to-rail output swing and low noise. These amplifiers have very low offset, drift, and bias current. Operation is fully specified from 5 V to 16 V single supply (2.5 V to 8 V dual supply). The AD8638/AD8639 provides benefits previously found only in expensive zerodrift or chopper-stabilized amplifiers. Using the Analog Devices, Inc., topology, these auto-zero amplifiers combine low cost with high accuracy and low noise. No external capacitors are required. In addition, the AD8638/AD8639 greatly reduces the digital switching noise found in most chopper- stabilized amplifiers. The AD8638/AD8639 is specified for the extended industrial temperature range (40C to +125C). The single AD8638 is available in tiny 5-lead SOT-23 and 8-lead SOIC packages. The dual AD8639 is available in 8-lead MSOP, 8-lead SOIC and 8-lead LFCSP packages. The AD8638/AD8639 is members of a growing series of auto- zero op amps offered by Analog Devices

Fig. No.2.2 Pin configuration of AD 8639

Applications Pressure and position sensors Strain gage amplifiers Medical instrumentation Thermocouple amplifiers automotive sensors Precision references Precision current sensing

2.4 ADC
An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device which converts continuous signals to discrete digital numbers. Typically an ADC is an electronic device that converts an input analog voltage (or current) to a digital number proportional to the magnitude of the voltage or current. The digital output may use different coding schemes such as binary, Gray code or two's complement binary. The resolution of the converter indicates the number of discrete values it can produce over the range of analog values. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or "levels", is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels, since pow(2,8)= 256. Resolution can also be defined electrically, and expressed in volts. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of discrete intervals as in the formula: The ADC used here is AD9235. The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters (ADCs). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound.

Fig. No.2.3 Functional block diagram of ADC, AD 9235

2.5 CPLD
Programmable logic devices are very standard ICs which are available in standard configurations. CPLD means Complex Programmable Logic Device defined as a single chip used for implementation of circuits which require more inputs and outputs, either multiple PLAs or PALs can be employed. CPLD used in this project interacts with ADC and stores digital data into SRAM directly without intervention of the MSP processor. The CPLD used is XC2C256 which belongs to the Cool Runner II family of Xilinx. The functions of the CPLD are: Control of the functioning of the ADC Storage of digital data into SRAM directly without intervention of the microcontroller Communication with microcontroller for reading of digital data after the data in a burst is acquired Reading of stored data by the microcontroller and data acquisition by ADC are not done simultaneously

2.6 SRAM
SRAM is a memory that used to store the instructions that tell CPU how to work with its parts. These instructions are called drivers. Static Random Access Memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit and random access means that locations in the memory can be written to or read from in any order, regardless of the last memory location that was last accessed.. SRAM exhibits data remainder, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The SRAM used is CY62167DV30 which belongs to Cypress Semiconductors. The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling.

2.7 Microcontroller
A microcontroller is a small computer on a single integrated circuit consisting internally of a relatively simple CPU, clock, timers, I/O ports, and memory. The Program memory is in the form of NOR flash or one-time programmable. ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for small or dedicated applications. By reducing the size and cost compared to a design that uses a separate microprocessor, memory, and input/output devices, microcontrollers make it economical to digitally control even more devices and processes. The microcontroller selected is from the MSP430 family of microcontrollers from Texas Instruments. The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator allows wake-up from low-power modes to active mode in less than 6s. The MSP430x11x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another area of application.

Fig. No.2.4 Pin Configuration of MSP 430

Fig. No.2.5 Functional block diagram of MSP430F 2418

2.8 Local display

A low powered LCD will be used local display of parameters at each individual node. Timed scrolling will be used to display all the parameters. No user switches will be provided to control the LCD display. The display that is used here is Nokia 3315 graphical display because of its low power consumption and also as a future requirement, if it is used in standalone mode.

2.9 EEPROM
An EEPROM of xx KB will be provide to provide non-volatile memory storage for parametric data. The configuration parameters for the node will be stored in the EEPROM. Interface to microcontroller is serial interface.

2.10 Wireless Communication

The node is provided wireless communication capability using a ZigBee transceiver. The ZigBee transceiver selected is the XBee module from MaxStream. The ZigBee is connected to the microcontroller on a serial interface. The node transmits information to server using ZigBee and the client receives it on wifi, which uses protocol translation.

2.11 Power
The unit will be battery powered. Four 1.2V NiMH rechargeable batteries will be used to power up the system. These batteries will serve as input power to a Power Management unit which will derive the voltages required for the operation of the different devices.

2.12 Operation of Node

When the powers on all the nodes of the AES Network are switched on and counters initialized. The MSP microcontroller after getting input from the comparator it will send signal to the CPLD to read the burst data from the ADC and to store data in SRAM. And whenever the MSP microcontroller requires the data then it will send signal to CPLD then CPLD will read data from SRAM and sends it to the MSP microcontroller.

2.13 Conclusion
This chapter gives the detailed description of each block present in the AES node such as preamplifier, variable gain amplifier, and analog to digital converter, CPLD, SRAM etc. and also about the operation of each node and key components used.

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Chapter 3 COOL RUNNER II CPLD

3.1 Introduction
Programmable logic devices are very standard ICs which are available in standard configurations. CPLD means Complex Programmable Logic Device defined as a single chip used for implementation of circuits which require more inputs and outputs, either multiple PLAs and PALs can be employed. CPLD used in this project interacts with ADC and stores digital data into SRAM directly without intervention of the MSP processor. A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.

3.2 Features of CPLD

Features of CPLD in common with PALs Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up. For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families. Features of CPLD in common with FPGAs Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million. Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic. The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.

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The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs, and PALs. These in turn were preceded by standard logic products that offered no programmability and were "programmed" by wiring several standard logic chips together. The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on Look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (e.g. sum of products).

3.3 Features of Cool Runner-II CPLD

a) Optimized for 1.8V systems As fast as 5.7 ns pin-to-pin delays As low as 13 A quiescent current b) Industrys best 0.18 micron CMOS CPLD Optimized architecture for effective logic synthesis. Multi-voltage I/O operation 1.5V to 3.3V c) Available in multiple package options d) Advanced system features Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface IEEE1149.1 JTAG Boundary Scan Test Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset Advanced design security PLA architecture 100% product term routability across function block Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels

3.4 Architecture of Cool Runner-II CPLD

Cool Runner-II CPLD is a highly uniform family of fast, low power CPLDs. The underlying architecture is a traditional CPLD architecture combining macro cells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The FBs use a Programmable Logic Array (PLA) configuration which allows all product terms to be routed and shared among any of the macro cells of the FB.

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Design software can efficiently synthesize and optimize logic that is subsequently fit to the FBs and connected with the ability to utilize a very high percentage of device resources. Design changes are easily and automatically managed by the software, which exploits the 100% routability of the Programmable Logic Array within each FB. This extremely robust building block delivers the industrys highest pin out retention, under very broad design conditions. The architecture is explained in more detail with the discussion of the underlying FBs, logic and interconnects. The design software automatically manages these device resources so that users can express their designs using completely generic constructs without knowledge of these architectural details. More advanced users can take advantage of these details to more thoroughly understand the softwares choices and direct its results.

Fig. No.3.1 Cool Runner II CPLD architecture 3.4.1 Macrocell The Cool Runner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum of product logic expressions that comprise up to 40 inputs and span 56 product terms within a single function block. The macrocell can further combine the SOP expression into an XOR gate with another single p-term expression. The resulting logic expressions polarity is also selectable. As well, the logic function can be pure combinatorial or registered, with the storage element operating selectable as a D or T flip-flop, or transparent latch.

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Available at each macrocell are independent selections of global, function block level or local p-term derived clocks, sets, resets, and output enables. Each macrocell flipflop is configurable for either single edge or Dual EDGE clocking, providing either double data rate capability or the ability to distribute a slower clock (thereby saving power). For single edge clocking or latching, either clock polarity can be selected per macrocell. Cool Runner-II CPLD macrocell details are shown in Figure 3.2. Note that in Figure 3.3, standard logic symbols are used except the trapezoidal multiplexers have input selection from statically programmed configuration select lines (not shown).

Fig. No.3.2 Cool Runner II CPLD macrocell There are many models in Cool Runner-II CPLD family and in this project we are using XC2C256 model. And the features and description of XC2C256 CPLD is given below

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3.5 Description of CPLD Xc2c256:

The Cool Runner-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A Dual EDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. These yields divide by even and odd clock frequencies.

Fig. No.3.3 Pin Configuration ofXC2C256 Cool Runner II CPLD

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3.6 CPLD Interface Flow

System Power Up

32 Bit Counter initialization is done through CPLD3 Pin from Low- to - High

RTC Initialization

Check uC Interface Signals

CPLD1 =1

Check for CPLD1, CPLD2, CPLDCLK

CPLD2 =1

Capture Data from ADC

Check for CPLDCLK

Store Data in SRAM

Acquire Data From SRAM And place that on Data Bus

Fig. No.3.4 Flow chart for CPLD flow

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Interface Details:

Fig. No.3.5 Interface details of CPLD Clock CPLD1 : 20MHz external Crystal Oscillator provided on board. : Signal from microcontroller (Micro Controller Board) requesting CPLD to capture the data available on ADC Data bus (ADC on analog card) whenever CPLD1 is made high (CPLD1 = 1). : Signal from microcontroller requesting CPLD to check the CPLDCLK, Read each 16- bit word from SRAM on every Positive edge of CPLDCLK. : Signal from an external switch for Initialization of 32-Bit counter in CPLD. : Signal from microcontroller to CPLD to read each word for every positive edge when CPLD2 is high. : 12-bit Data from ADC from Analog Card. : Addressing the SRAM in order to write /read each 16-bit word at a particular location. : Bi-Directional data Bus between SRAM and CPLD, which is also connected, to microcontroller for data writing and reading.

CPLD2

CPLD

CPLDCLK

ADC Data Address

Data_io

Write_Enable: Write Enable Signal output from CPLD to control the write/read operation of SRAM. ADC CLK : Output signal from CPLD to provide Sampling clock for ADC.

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Table 3.1 Absolute Maximum Ratings

Symbol VCC VCCIO VJTAG VAUX VIN VTS TSTG 3.7 Conclusion:

Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input relative to ground Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient)

Value Units -0.5 to 2.0 V -0.5 to 4.0 V -0.5 to 4.0 V -0.5 to 4.0 V -0.5 to 4.0 V -0.5 to 4.0 V -65 to +150 C

This chapter explains the features of CPLD and Cool Runner II CPLD, architecture of CPLD Xc2c256 and macrocell and also functional description of CPLD in general and about the Xilinx CPLD Xc2c256 in particular.

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Chapter 4 SRAM
4.1 Introduction
SRAM is a memory that used to store the instructions that tell CPU how to work with its parts. These instructions are called drivers. Static Random Access Memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit and random access means that locations in the memory can be written to or read from in any order, regardless of the last memory location that was last accessed.. SRAM exhibits data remainder, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. An SRAM cell has three different states it can be in: standby where the circuit is idle, reading when the data has been requested and writing when updating the contents. The SRAM used in this process is having 20-bit address lines and 2^20 Address locations and each address location is capable of storing 16-bit data. The SRAM is interfaced with CPLD. And the CPLD collects the burst data from ADC card and writes the data into SRAM in successive address locations. The interfacing between the SRAM and CPLD includes Data bus, Address bus, read enable and write enable connections. The Logic diagram and portfolios of SRAM used in this block is shown below. The used in this project is CY62167DV.

4.2 Functional Description of CY62167 SRAM

The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).

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Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15.

Fig. No.4.1 Logical block diagram of SRAM CY62167

4.3 SRAM Portfolio

Table 4.1 Portfolio of CY62167

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Fig. No.4.2 Top view of SRAM CY62167

4.4 Features of SRAM CY62167

TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM Very high speed: 45 ns Wide voltage range: 2.2V 3.6V Ultra-low active power i. Typical active current: 2 mA at f = 1 MHz ii. Typical active current: 18.5 mA at f = fMax (45 ns speed) Ultra-low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected CMOS for optimum speed/power Available in Pb-free and non Pb-free 48-ball VFBGA and 48-pin TSOP I package

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4.5 Conclusion
This chapter explains the introduction to SRAM and features of SRAM, the functional description of SRAM, CY62167 which is from Cypress Semiconductors Limited and logic block diagram of CY62167 SRAM which shows the internal architecture. The portfolio of SRAM is shown in a table which shows the minimum, maximum and typical ranges of supply voltages, its operating frequency, speed etc.

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Chapter 5 SCHEMATICS
The schematics diagram of CPLD card is as shown below:

Fig. No.5.1 Schematics of CPLD card

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The schematics are developed using Eagle 4.1 software. Various components other than CPLD, ADC, Microcontroller, and SRAM are used. The brief explanation of those components such as ferrite beads, JTAG etc. is given below.

5.1 Ferrite Beads:

A ferrite bead is a passive electric component used to suppress high frequency noise in electronic circuits. It is a specific type of electronic choke. Ferrite beads employ the mechanism of high dissipation of high frequency currents in a ferrite to build high frequency noise suppression devices. Ferrite beads may also be called ferrite blocks, ferrite cores, ferrite rings, ferrite EMI filters, a ferrite choke or mistakenly as ferrous beads.

Fig. No.5.2 Ferrite beads Ferrite beads are used (in a way similar to inductors) as a passive low-pass filter. The geometry and electromagnetic properties of coiled wire over the ferrite bead result in a high impedance (resistance) for high-frequency signals, attenuating high frequency EMI/RFI electronic noise. The absorbed energy is converted to heat and dissipated by the ferrite, but only in extreme cases will the heat be noticeable. Ferrite beads are one of the simplest and least expensive types of interference filters to install on preexisting electronic cabling. For a simple ferrite ring, the wire is simply wrapped around the core through the center typically 5 or 7 times. Clamp-on cores are also available, which can be attached without wrapping the wire at all.

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5.2 JTAG (Joint Test Action Group)

JTAG, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the same time. The JTAG connector used here is a 14-pin Xilinx JTAG connector. The pin configuration of 14-pin Xilinx JTAG connector is as shown below:

VGND GND GND GND GND GND GND

1 3 5 7 9 11 13

2 4 6 8 10 12 14

VREF TMS TCK TDO TDI -----

Fig. No.5.3 Pin configuration of Xilinx jtag connector 5.2.1 Features of Xilinx JTAG connector Download speed of up to 5 Megabits per second (Mb/s) Chip Scope Pro Analyzer compatible In-system configures the following Xilinx devices: Virtex series FPGAs Spartan series FPGAs XC9500/XC9500XL/XC9500XV CPLDs Cool Runner (XPLA3)/Cool Runner-II CPLDs LED status indicator. Automatically senses and adapts to correct I/O voltage. Interfaces to devices operating at 5V (TTL), 3.3V (LVTTL), 2.5V, 1.8V, and 1.5V. In-system programs serial-access flash PROMs via the serial peripheral interface (SPI). Externally powered using keyboard/mouse splitter cable or AC power brick.

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Fig. No.5.4 Xilinx parallel cable IV

The description of signals used in the JTAG connector is as given below: Test Clock (TCK): Synchronizes the internal state machine operations. Test Mode State (TMS): Sampled at the rising edge of TCK to determine the next state. Test Data In (TDI): Represents the data shifted into the devices TDI test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state. Test Data Out (TDO): Represents the data shifted out of the devices TDI test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state. Test Reset (TRST): An optional pin which, when available, can reset the TAP controllers state machine.

5.3 Conclusion
This chapter gives the schematics of CPLD card and details of different components such as ferrite beads, JTAG etc. used in the schematics

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Chapter 6 Software & Tools

The language used to develop code for this project is VHDL and the tool used to simulate the output is Xilinx ISE 9.1. The brief introduction of language and tools is given below.

6.1 Introduction to VHDL:

VHDL (VHSIC hardware description language; VHSIC: very-highspeed integrated circuit) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

6.2 VHDL: Origin and development

VHDL is a language which is permanently extended and revised. The original standard itself needed more than 16 years from the initial concept to the final, official IEEE standard. When document passed the committee it was agreed that the standard should be revised every 5 years. The first revision phase resulted in the updated standard of the year 1993. Independently of this revision agreement, additional effort is made to standardize extensions of the pure language reference. These extensions cover for examples packages (std_logic_1165, numeric_bit, numeric_std,) containing widely needed data types and subprograms, or the definition of special VHDL subsets like the synthesis subset IEEE 1076.6. The latest extension is the addition of analogue description mechanisms to the standard which results in a VHDL superset called VHDL-AMS. VHDL development was initiated originally from the American Department of Defense (DoD). They requested a language for description a hardware, which had to be readable for machines and the humans at the same time and strictly forces the developer to write structured and comprehensible code. So that the source code itself can serve as a kind of specification document. Most important was the concept of concurrency to cope with the parallelism of digital hardware. Sequential statements to model very complex functions in a compact from were also allowed. In 1987, VHDL was standardized by the American Institute of Electrical and Electronics Engineers (IEEE) for the first time with the first official update in 1993. Apart from the file handling procedures these two versions of the standard are compatible. The standard of the language is described in the Language Reference Manual (LRM).

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A new and difficult stage was entered with the effort to upgrade VHDL with analog and mixed-signal language elements. The upgrade is called VHDL-AMS (Analog Mixed Signal) and it is super of VHDL. The digital mechanisms and methods have not been altered by the extension. For the time being, only simulation is feasible for the analog part because analog synthesis is a very complex problem affected by many boundary conditions. The mixed signal simulation has to deal with the problem of synchronizing the digital and analog simulators, which has not been solved adequately.

6.3 Modeling Techniques:

VHDL features also three important modeling techniques: 1) Behavioral Modeling 2) Dataflow Modeling 3) Structural Modeling

6.4 Data Objects:

A data object holds a value of a specified type. It is created by means of an object description. An example is Variable COUNT: INTEGER; This result in the creation of a data object called COUNT, which can hold integer values. The object COUNT is also declared to be of variable class. Every data object belongs to one of the following four classes: 1) Constant 2) Variable 3) Signal 4) File

6.5 VHDL Structural Elements

The main units in VHDL are entity, architectures, configurations, packages and library. Entity : Interface Architecture : Implementation, behavior, function Configuration: Model Chaining, Structural, hierarchy Process : Concurrency, event controlled Package : Modular design, Standard solutions, data types and constants Library : Compilation, object code

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6.6 Applications of VHDL

VHDL is used mainly for the development of Application Specific Integrated Circuits (ASICs). Tools for the automatic transformation of VHDL code into a gate-level netlist were developed already at an early point of time. This transformation is called synthesis and is an integral part of current design flows. While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices (PLDs). VHDL can be applied to model system behavior independently from the target technology. This is either useful to provide standard solutions, e.g. for microcontrollers, error correction (de-) coders, etc, or behavior models of microprocessor and RAM devices are used to simulate a new device in its target environment

6.7 Xilinx ISE 9.1i:

Starting the ISE Software To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting: Start All Programs Xilinx ISE 9.1i Project Navigator Accessing Help At any time during the tutorial, you can access online help for additional information about the ISE software and related tools. To open Help, do either of the following: Press F1 to view Help for the specific tool or function that you have selected or highlighted. Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

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Fig. No.6. 1 ISE Help Topics Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: Verilog (or VHDL) Verify that Enable Enhanced Design Summary is selected. Leave the default values in the remaining fields. When the table is complete, project properties will look like the following:

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Fig. No.6.2 Project device properties 7. Click Next to proceed to the Create New Source window in the New Project Wizard. at the end of the next section, your new project will be complete. Creating a VHDL Source Create a VHDL source file for the project as follows: a. Click the New Source button in the New Project Wizard. b. Select VHDL Module as the source type. c. Type in the file name counter. d. Verify that the Add to project checkbox is selected. e. Click Next. f. Declare the ports for the counter design by filling in the port information as shown below: g. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template. h. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

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Fig. No.6.3 Define module i. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template. j. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

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Fig. No. 6.4 New project in ISE

6.8 Design procedure of XILINX 9.1i

The Xilinx 9.1i provides PLD designers with the basic design process using ISE (Integrated Simulation Environment). The designing procedure has the following steps Getting Started Creating a new project Creating an HDL source Design simulation Creating timing constraints Implementing design and verifying constraints Assigning pin location constraints Downloading design to the Demo Board

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6.9 Xilinx platform cable USB II: Features

High-performance FPGA and PROM programming and configuration Includes innovative FPGA-based acceleration firmware encapsulated in a small form factor pod attached to the cable Leverages high-speed Slave Serial mode programming interface Recommended for prototyping use only Easy to use Fully integrated and optimized for use with Xilinx iMPACT software Intuitive multiple cable management from a single application Supported on the following operating systems: - Microsoft Windows XP Professional - Microsoft Windows Vista - Red Hat Enterprise Linux - SUSE Linux Enterprise Automatically senses and adapts to target I/O voltage Interfaces to devices operating at 5V (TTL), 3.3V (LVCMOS), 2.5V, 1.8V and 1.5V Intuitive fly leads-to-cable interface labeling

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Chapter 7 Source code

7.1 Source code
--------------------------------------------------------------------------------------------- Company: GRIET -- Engineer: Chaitanya.D.L -- Design Name: AES_CPLD_C_Analog card Interface -- Module Name: SRAM_interface - Behavioral -- Project Name: AES Nodal Units -- Target Devices: CPLD XC2C256 -- Tool versions: Xilinx ISE 9.1 -- Description: Specified in CPLD Interface Flow -----------------------------------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity SRAM_interface is Port ( clock: in std_logic; CPLD1: in std_logic; CPLD2: in std_logic; CPLD_clk: in std_logic; Write_enable: out std_logic; CPLD3: in std_logic; ADCdata: in std_logic_vector (11 downto 0); Address: out std_logic_vector (19 downto 0); Data_io : inout std_logic_vector (15 downto 0); ADCCLK: out std_logic); End SRAM_interface;

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Architecture Behavioral of SRAM_interface is type write is (idle,Wraddress_state,Rdaddress_state,write_state,read_state,read_end,data_state,write_e nd); Signal state: write: =idle; type Real_count is (switch1, switch2); Signal Switch_count :Real_count:=switch1; type check_count is (check1, check2); Signal check_cpld1:check_count:=check1; Signal data_reg: std_logic_vector (15 downto 0); Signal reset: std_logic:='1'; Signal cnt: integer: =0; Signal d1, d11, d2, d22, d3, d33, d4, d44: std_logic:='0'; Signal CPLD_RD:std_logic:='0'; Signal CPLD_2:std_logic:='0'; Signal write_address_enable, read_address_enable:std_logic:='0'; Signal write_address, read_address: std_logic_vector (19 downto 0) :=( others =>'0'); Signal read_reset, write_reset:std_logic:='1'; Signal counter_32bit, count_value:std_logic_vector (31 downto 0) :=( others =>'0'); Signal count_edge:std_logic:='0'; Signal AD, ADC_DATA1:std_logic_vector (11 downto 0) :=( others =>'0'); Signal ADC_DATA:std_logic_vector (15 downto 0) :=( others =>'0'); Signal clock_1MHz: std_logic; Signal count_1MHz: integer; begin ------------------------------------------------------------------------------------To detect CPLD1 and to Store Counter value in SRAM----------------------------------------------------------------------------------Process (clock, reset, CPLD1, counter_32bit) begin if reset = '1' then check_cpld1 <= check1; count_value <= (others => '0'); elsif clock'event and clock = '1' then Case check_cpld1 is When check1 => if CPLD1 = '1' then count_value <= counter_32bit; check_cpld1 <= check2; else count_value <= count_value; check_cpld1 <= check1; end if;
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when check2 => if CPLD1 = '0' then check_cpld1 <= check1; else check_cpld1 <= check2; end if; when others => check_cpld1 <= check1; end case; end if; end process; ------------------------------------------------------ Internal reset for process -----------------------------------------------------Process (reset) begin if reset = '1' then reset <= '0'; end if; end process; -------------------------------------------------------- Clock for ADC -------------------------------------------------------ADCCLK <= clock; --------------------------------------------------------------------1MHz Clock for 32-bit Counter Running -------------------------------------------------------------------Process (clock, reset) begin if reset = '1' then count_1MHz <= 0; clock_1MHz <= '0'; elsif clock'event and clock = '1' then if count_1MHz = 9 then count_1MHz <= 0; clock_1MHz <= not clock_1MHz; else count_1MHz <= count_1MHz + 1; end if; end if; end process;

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--------------------------------------------------------------32-Bit Counter Running / Initialization -------------------------------------------------------------Process (clock_1MHz, reset, count_edge) begin if reset = '1' then counter_32bit <= (others => '0'); switch_count <= switch1; elsif clock_1MHz'event and clock_1MHz = '1' then case switch_count is when switch1 => if count_edge = '1' then switch_count <= switch2; else switch_count <= switch1; end if; when switch2 => if (count_edge = '1' or counter_32bit = X"FFFFFFFF) then counter_32bit <= (others => '0'); else counter_32bit <= counter_32bit + 1; end if; switch_count <= switch2; when others => switch_count <= switch1; end case; end if; end process; ------------------------------------------------------------------------ Generating Address for writing data to SRAM -----------------------------------------------------------------------Process (clock, write_reset, write_address_enable) begin if write_reset = '1' then write_address <= (others =>'0'); elsif clock'event and clock = '1' then if write_address_enable = '1' then if write_address = "00011000011010100000" then write_address <= (others =>'0'); else write_address <= write_address + 1; end if; end if; end if;

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-------------------------------------------------------------------------- Generating Address for reading data from SRAM -------------------------------------------------------------------------Process (clock, read_reset, read_address_enable) begin if read_reset = '1' then read_address <= X"00000"; elsif clock'event and clock = '1' then if read_address_enable = '1' then if read_address = "00011000011010100000" then read_address <= X"00000"; else read_address <= read_address + 1; end if; end if; end if; end process; --------------------------------------------------------------------- Flow to Write and Read Data to for/ from SRAM --------------------------------------------------------------------Process (clock, reset, CPLD1, CPLD_2, read_address, write_address, count_value, ADCDATA) begin if reset = '1' then data_reg <= (others =>'Z'); address <= (others =>'Z'); data_io <= (others =>'Z'); Write_Enable <='1'; cnt <= 0; state <= idle; read_reset <='1'; write_reset <='1'; elsif clock'event and clock ='1' then case state is when idle => data_reg <= (others =>'Z'); address <=(others =>'Z'); data_io <=(others =>'Z'); write_address_enable <= '0'; read_address_enable <= '0'; read_reset <='0'; Write_Enable <='1';

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if (CPLD1 = '1' and CPLD_2 ='0') then write_reset <='0'; state <= Wraddress_state; elsif (CPLD_2 ='1' and CPLD1 ='0')then write_reset <='0'; state <= Rdaddress_state; else write_reset <='1'; state <= idle; end if; when Wraddress_state => read_reset <='1'; address <= write_address; if write_address = "00000000000000000000" then data_io <= count_value (31 downto 16); elsif write_address = "00000000000000000001" then data_io <= count_value (15 downto 0); else data_io <= ("0000" & ADCDATA); end if; Write_enable <='0'; state <= write_state; when Rdaddress_state => write_reset <='1'; address <= read_address; state <= read_state; when read_state => data_reg <= data_io; read_address_enable <= '1'; state <= idle; when read_end => state <= idle; when write_state => Write_enable <='0'; state <= write_end; when data_state => data_io <= X"1234; state <= write_end; when write_end => write_address_enable <= '1'; state <= idle; when others => state <= idle; end case;

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end if; end process; ------------------------------------------------- Edge Trigger for Read Clock-------------------------------------------------Process (clock, CPLD_clk) begin if clock'event and clock ='1' then d1 <= CPLD_clk; end if; end process; process (clock, d1) begin if clock'event and clock ='1' then d2 <=d1; end if; end process; process (clock,d2) begin if clock'event and clock ='1' then d3 <=d2; end if; end process; d4 <= not d3; CPLD_RD <= d4 and d2; CPLD_2 <= CPLD_RD when CPLD2 = '1' else '0'; ----------------------------------------------------------------------------- COUNTER Edge Trigger for Counter Initialization----------------------------------------------------------------------------Process (clock_1MHz, CPLD3) begin if clock_1MHz'event and clock_1MHz ='1' then d11 <=CPLD3; end if; end process; process (clock_1MHz,d11) begin if clock_1MHz'event and clock_1MHz ='1' then d22 <=d11; end if; end process;

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process (clock_1MHz,d22) begin if clock_1MHz'event and clock_1MHz ='1' then d33 <=d22; end if; end process; d44 <= not d33; count_edge <= d44 and d22; end Behavioral;

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Chapter 8 Results
8.1 Screen Shots:
The clients side used software is LABVIEW software developed by National Instruments Limited. The screen shots shown below are from LABVIEW software. And the simulation results are from XILINX ISE 9.1i with Modelsim simulator.

8.1.1 Simulation Results 1. Initialization of variables

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2. Generation of 1MHZ clock

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3. Generation of address

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4. Initialization of counter

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5. Final result

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8.1.2 Assembled AES node

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8.1.3 Default settings

8.1.4 Received signal

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8.1.5 Analysis of the signal

8.2 Conclusion
This chapter gives a little introduction about the hardware description language, VHDL used to develop the source code of the project and the design procedure of Xilinx ISE 9.1i software used to simulate the code to analyze the results. It also shows the screen shot of simulation results.

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Chapter 9 Conclusions
Conclusion:
The function of the Acoustic Emission Sensor Network is to locate faults based on the acoustic signatures captured by a network of nodes. The ADC used in this network generates samples at a rate of 40 million samples per second. The MSP processor cannot read data with such a high sampling rate. This was achieved by using a CPLD that controls the functioning of ADC and stores the samples into SRAM. The MSP processor reads sensor data on receipt of acquisition complete signal from the CPLD. ZigBee, a low power wireless technology working in the unlicensed 2.4 GHz ISM band was the technology chosen for wireless communication. This project designed and implemented CPLD based sub-system that interacts with ADC and stores digital data into SRAM directly and transfer the same data from SRAM to microcontroller (MSP430 based) sub-system for further processing.

Future scope
Process that is being implemented in the microcontroller can also be implemented in CPLD i.e., CPLD can be used for both storing data into SRAM and as well as to do the required parameter calculations. So that CPLD can be used in a more efficient way. But because of clients requirements, CPLD is used only to store data into SRAM and microcontroller is used to do the computations. And also instead of the CPLD, FPGA can be used for both storing the data and for doing all the processing because FPGA is more advantageous than CPLD. That is FPGA can be used to do both storing of samples that are received from ADC and also to do the computation of parameters such as Cumulative counts Cumulative events Count rate Event rate Peak amplitude Rise time RMS value But according to the clients requirements IGCAR (Indira Gandhi Centre for Atomic Research), instead of FPGA CPLD is chosen to store data and microcontroller is chosen to do the parameter computation.

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So, this project when implemented in future, CPLD can be used to do both the tasks of storing data and to do the computations. Otherwise FPGA can be used in place of CPLD for storing the data and also for doing the processing.

Applications:
The main Application of the Acoustics Emission Sensing Network is to locate the structural defects before the incident occurs and take the necessary measures to prevent the damage to the structures. The Acoustics Emission Sensing Network is used to locate the structural defects in Bridges Containers Large vessels etc.

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CHRONOLOGICAL BIBLIOGRAPHY

[1]Zainalabedin Navabi, VHDL Analysis and Modeling of Digital Systems, 2nd Ed., Tata McGraw-Hill, New Delhi, 1998. [2]Morris Mano.M, Digital Logic and computer Design, Prentice Hall of India, New Delhi, 1998 [3]Bhaskar.J, A VHDL primer, 2nd Ed., BS Publications, Hyderabad, 2001 [4]Robert K. Dueck, Digital Design with CPLD Applications and VHDL, Thomas Delmar Learning, Singapore, 2001 [5]John F Wakerly, Digital Design Principles and Practices, 4th Ed., Pearson Education, New Delhi, 2001 [6]Douglas L. Perry, VHDL Programming by Example, Tata McGraw-Hill, New Delhi, 2002

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ALPHABETICAL BIBLIOGRAPHY

Bhaskar.J, A VHDL primer, 2nd Ed., BS Publications, Hyderabad, 2001. Douglas L. Perry, VHDL Programming by Example, Tata McGraw-Hill, New Delhi, 2002. John F Wakerly, Digital Design Principles and Practices, 4th Ed., Pearson Education, New Delhi, 2001. Morris Mano.M, Digital Logic and computer Design, Prentice Hall of India, New Delhi, 1998. Robert K. Dueck, Digital Design with CPLD Applications and VHDL, Thomas Delmar Learning, Singapore, 2001. Zainalabedin Navabi, VHDL Analysis and Modeling of Digital Systems, 2nd Ed., Tata McGraw-Hill, New Delhi, 1998.

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