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2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009)

High Speed LVDS Driver for SERDES


Hari Shanker Gupta, RM Parmar and RK Dave
SPACE APPLICATIONS CENTRE, ISRO, JODHPUR TEKRA (P.O), AHMEDABAD-380015 E-mail: hari@sac.isro.gov.in, rmparmar@sac.isro.gov.in, rkdave@sac.isro.gov.in critical when used with SERDES for high transmission rate. LVDS has become an attractive alternative as a standalone driver or as I/O pad for high-speed devices like SerDes. The low power and low voltage operation are the added advantages. A modified LVDS driver design technique is proposed and its performance is compared with the conventional type in the following sections. It is envisaged that LVDS driver would be low power and high speed (400 Mbps) device based on 0.8 CMOS technology and shall also be fully compatible to IEEE STD 1596.3-1996[3]. Sections 2 and 3 respectively discuss LVDS driver topologies and typical design along with the issues related to achieving required performance. The expected performance and conclusions are addressed in the last section. VDD

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Keywords: LVDS, CMFB, CMOS, IEEE STD 1596.3-1996,

1. INTRODUCTION: Typical Low-Voltage Differential Signaling (LVDS) Interface shown in Fig-1.1 consists of a current source (nominal 3.5 mA), which drives the differential lines terminated with 100 load. The LVDS receivers have high input impedance and the drive current mainly flows through the terminating resistor generating about 350 mV across the receiver inputs. When the driver switches, it changes the direction of current flow through the resistor, thereby creating a valid one or zero logic state. The Serializer De-serializer devices popularly known as SerDes are used for high speed data transmission. They utilize LVDS interface leading to lower power, better noise immunity and reliable clock recovery. They also exhibit large bandwidth for high speed data transmission. A bottleneck in the digital transmission of signals via long wire is the I/O cells, which have to drive load at the required rate, meeting the stringent voltage levels as per applicable standards throughout the operating temperature range. The I/O cells/pads are designed to supply sufficient current to drive load which results in large pad size and higher power restricting the speed of operation, at larger loads. Most of the conventional CMOS I/O cells utilized very large area to accommodate large driving transistors and associated large passive elements [2]. This becomes more

Driver
VSS Fig 1.1: Typical LVDS Interface 2. LVDS DRIVERS TOPOLOGIES: Table-1: Comparisons of LVDS driver topologies
Topology Parameter Bridge Driver Double current source Switchable current source

Static power Control on O/P LV Operation Size I/P Capacitance Circuit complexity Buffer requirement Speed

Low More No Small Small low No High

High Less Yes Large Large low No Low

Receive r

Abstract: - Low Voltage Differential Signaling (LVDS) is a method used for high-speed transmission of binary data over copper cable. In the earlier remote sensing payload camera electronics, the multi-port parallel data were provided to spacecraft base-band system, requiring large number of I/O connectors and associated harnesses. This multi-port parallel data can be multiplexed, serialized and transmitted to other subsystems using LVDS interface thereby reducing the number of I/Os, cabling and associated weight of interface hardware. This work presents the design, simulation and analysis of I/O interface circuits for high speed operation which is fully compliant with the IEEE STD 1596.3 (LVDS). A common mode feedback (CMFB) circuitry is utilized in the LVDS transmitter to stabilize the common mode voltage in a pre-defined range. In most of the previous designs [1] output cells utilize voltage divider circuit composed of two large resistors (M) between output pads and center is taped as feedback. These resistors may be off-chip discrete components (due to stringent stability and large die area requirement). The modified common mode feedback circuit has been designed and analyzed with appropriate transistor geometry and evaluated. Its performance is also compared with conventional CMFB design.

D Vob

D Voa

Out

Low Less Yes Small Small high Yes Low

The merits and demerits of popular LVDS driver topologies viz. Bridge driver, double current source and Switchable current source are compared in Table-1.

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2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009)
V 1 25 V 1.00 DRIVER D Dout (+) Dout ()

VOLTAGE REFERENCE TTL LEVEL


LEVEL SHIFTE R
5.00 2.40 1.42 1.08 0.00 Q

CMOS LEVEL PHASE SPLITTE R

Q
BUFF BUFF

Dout(

< 300 ps

<200 < 2 ns

< 500 ps

< 1 ns

Fig 2.1: Detailed block diagram of LVDS Driver Most of the constituent blocks of LVDS such as Level shifter, voltage reference, current sources feedback network and the buffer circuits and the differential driver are mixed signal designs. Fig- 2.1 shows detailed block diagram of a typical LVDS device. In order to have stable common mode and differential output voltage over the entire temperature range from -55oC to 125oC for space use, the design of current sources, type of feedback and temperature compensation are required to be critically addressed. Bridge type topology uses less external components, has precision feedback loop control and small input capacitances. It meets all our requirements and hence is discussed further. 3. LVDS DRIVER CIRCUIT DESIGN: The bridge type LVDS driver circuit shown in Fig-3.1 behaves as a current source with switched polarity. The current switch constituted by M1, M2, M3, and M4 is controlled by D and D. The transmitter output Vob and Voa are the outputs coupled to the transmission lines. When D = 1, M2 and M3 are turned on, while M1 and M4 are turned off. Thus, Vob is pulled high and Voa is pulled down to LOW. In other case, when D = 0, M2 and M3 are turned off, while M1 and M4 are turned on. Thus, Vob is pull-down, Voa is pulled high, generating logic 1 and logic 0 conditions. A stable common mode voltage (VOCM) is required as per LVDS standards [3]. To meet this requirement, a voltage divider composed of two large value resistors between Vob and Voa is generally used. The reason for the large value resistors, Ra and Rb is to minimize quiescent currents though feedback. VOCM = VDD Volt) M
U

However, the large value resistors demand large die area or use of off-chip discrete components. The proposed driver circuit uses a modified common mode feedback (CMFB) circuit scheme to resolve this problem. The CMFB implemented in [4] for maintaining stable common mode voltage of differential amplifier is employed in the proposed LVDS design. The modified CMFB circuit does not require high value resistors. Also, it occupies lesser area and has minimum parasitics in the feedback circuit, thereby improving the speed of operation and reduction in silicon area. Additionally this arrangement can be made less sensitive to temperature and process variations. The functional diagram of the modified CMFB concept is given in Fig-3.2. Here M7 to M10 are matched transistors. The source coupled pairs M7-M8 and M9-M10, together sense the common mode output voltage. Feedback proportional to the difference between common mode voltage and VOCM is appropriately fed back to generate stable common mode voltage.

Id 8 =

(V VOCM ) ------------ (3.2) Ia + gm8 * oa 2 2

Id10 =

Ia (V VOCM ) ----- (3.3) + gm10 * ob 2 2

Where Id8, Id10 are drain currents and gm8, gm10 are transconductance of M8 and M10 transistors respectively as shown in Fig-3.2. These currents are summed in diode connected current source I, to give common mode sensor output current. At steady state I, reach the current Ia when the common mode voltage approaches VOCM.
V + V ob I = Ia + gm 10 * oa 2 ----- (3.4) V OCM

VDD

VDD

VDD

VDD
I

(Voa + Vob ) ------- (3.1) 2 (5/3.3


M10

D Vob D

D Voa D

VOCM

Voa

M7

M8

M10

M9

Vob

V
M8

Ia

Ia

M7
VOC
M

IB

D V D

M1

M2

D Vob M5
M6

Fig-3.2: Modified CMFB Approach for LVDS Driver Transistorized circuit simulated is shown in Fig-3.3. The operation of the feedback loop is as follows. As soon as Voa and Vob drops to cause common mode voltage to be smaller than VOCM, the current via M8 and M10 are reduced which in turn decreases the source current of LVDS driver pair, causing common mode voltage to increase. Similarly, when Voa and Vob increases to cause common mode voltage to be higher than

Ra
M3

Rb
M4

D M9

I VSS

ML IB

VSS VSS Fig- 3.1: Bridge driver circuit

VSS

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2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009)

VOCM, the current via M8 and M10 is increased, which in turn increases the source current of LVDS driver pair.
VDD (5/3.3 Volt) VDD(5/3.3 V l) M11

M M I VOCM

IB D

D
Vob

M1

M2

D
Voa

M3 ML IB VSS

M4

Voa

M7

M8 M13

M10 M9

Vob

M12 VSS

Vbias

Vbias

M14

All the parameters are met with worst case conditions such as VDD (nominal 10%), total Mil temperature range and all process corners. The proposed option though consumes slightly more power compared to that of conventional design [1], but it offers significant advantages like 40% less area and 20-30% higher speed. The eye opening of serial data at maximum rate (800 Mbps) is reasonably good with horizontal eye opening more than 0.95UI and vertical opening meeting LVDS threshold limits. The same driver core will be used for SERDES design planned for future mixed signal ASIC.
VDD = 5.0 V, VIN = TTL Clock, Load = 100 ,, CL =5 pF

Fig-3.3: LVDS driver with Modified CMFB circuit The targeted process of the proposed design is 0.8 CMOS with 5V operation. The VOCM is to be derived from VREF along with other biases. As the feedback is in the form of current, suitable current gain of 20 is chosen to mirror 3.5 mA driver current and accordingly current through the feed back circuit is fixed as 172.5A for minimum power dissipation. The geometry of all the transistors in the driver has been computed based on following relations and listed in Table-2. 1. (W/L)Mu = f ( IB, A) 2. (W/L)ML = f ( IB, A) 3. (W/L)M1 = (W/L)M2 = f ( IB, fall time) 4. (W/L)M3 = (W/L)M4 = f ( IB, rise time) 5. (W/L)M5 = (W/L)M6 = f ( I, A,) 6. (W/L)M7,M8,M9,M10 = f ( I, A) 7. (W/L)M11,M12,M13,M14 = f ( I) Where A = is Current gain for mirroring, and IB is driver current. Table 2: Transistor dimensions of driver Circuit
Transistor MU ML M1,M2 M3, M4 M5,M6,M11 M7, M8,M9,M10 M12 M13,M14 (W/L) ratio 112.1 69.9 461.1 528 5.6 182 3.5 5.6 Length (m) (L) 3.2 3.2 0.8 0.8 3.2 3.2 3.2 3.2 Width (m) (W) 358.7 223.7 Voltage Level 368.9 422.4 17.9 581.8 11.2 17.9 Vdiff Vert : 1V/Div Hor : 20nS/Div Vob Voa Vin

Time (ns)

Vert : 40mV / Div Hor : 0.1 nS/Div

Fig-4.1: EYE Pattern of Output Data

VDD = 5.0 V VIN = TTL Clock, Load = 100 , CL =5 pF

4. RESULTS AND DISCUSSION: Based on the targeted goals, geometries are computed for all the transistors and circuit design and simulations are carried out. Optimization is also carried out after studying the sensitivities. Circuit is characterized with load RL = 100 and CL = 5 pF and the results are shown in figures 4.1 to 4.4. With the recommended load, the performance is satisfactory up to 650 Mbps data rate and with higher capacitive load of around 15 pF, it meets required specs up to 450 Mbps data rate.

Time (ns)

Figt-4.2: LVDS Outputs Voltage @ 20 Mbps

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UI = 0.95

240 mV

2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009)

16 14

Power Supply Current (mA)

12 10 8 6 4 2 0
1.E+03

Power Supply Current Vs Frequency

1.E+05

1.E+06

1.E+07

Frequency (Hz)

3.E+07

5.E+07

1.E+08

2.E+08

4.E+08

Fig 4.3: Current Vs Device Operating Frequency

1.285 1.28

Sensitivity Of VOCM

Common mode O/P (VOCM )

1.275 1.27 1.265 1.26 1.255 1.25 1.245 1.24 1.235

-100

-50

Temp(oC)

50

100

150

Fig-4.4: O/P common mode voltage with temperature 5. ACKNOWLEDGEMENT The authors acknowledge the constant encouragement and guidance received from Shri DRM Samudraiah, Deputy Director, SEDA, Shri AS Kiran Kumar Associate Director, Space Applications Centre, and Dr. R.R. Navalgund, Director, Space Applications Centre. The authors also wish to thank Mr. Sanjeev Metha for fruitful discussions on design, analysis aspects and Mr. Nilesh Desai for providing valued suggestions on manuscript.
6. REFERENCES: [1] A. Boni, A. Pierazzi, and D. Vecchi, LVDS 1/0 interface for Gb/s-per-pin operation in 0.35-pm CMOS,IEEE J. of SolidState Circuits, vol. 36, no. 4, pp. 706-711, Apr - 2001. [2] Mingdeng Chen, Jose Silva-Martinez, Michael Nix and Moises E. Robinson, Low- Voltage Low-Power LVDS Drivers IEEE J. Solid State Circuits, Vol. 40, no. 2 pp. 472-479, Feb - 2005. [3] IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std. 1596.3-1996, 1994. [4] P-W. Li, M.J. Chin, P. R. Gray, and R. Castello, RatioIndependent algorithmic analog-to-digital conversion technique, IEEE J. SSC, Vol. SC-19, no. 6 pp. 828836, Dec - 1984.

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