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Page 1
Motivation
Analysis of a few simple circuits Generalizes to Synchronous Sequential Circuits (SSC)
Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic
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Overview
Concept of the Synchronous Sequential Circuits
Partitioning into Datapath and Control When Inputs are Sampled and Outputs Asserted
Word Problems
Case Studies
Dr. Ehab A. H. AL-Hialy Page 3
Status
Registers Combinational Functional Units (e.g., ALU) Busses SSC generating sequences of control signals Instructs datapath what to do next
Control
Control
State Status Inputs
The Supervisor
Control Outputs
The worker
Datapath
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State T ime
Immediate Outputs:
affect datapath immediately could cause inputs from datapath to change
Clock
Delayed Outputs:
take effect on next clock edge propagation delays must exceed hold times
Inputs
Outputs
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State diagram can have different forms depending on the type of sequential circuit output.
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Block Diagram
N Coin Sensor D Reset Clk Vending Machine SSC Open Gum Release Mechanism
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Reset S0 N S1 D S2
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Present State 0
Inputs D N 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X
Next State 0 5 10 X 5 10 15 X 10 15 15 X 15
Output Open 0 0 0 X 0 0 0 X 0 0 0 X 1
N 5 D
5
N 10 D N, D 15 [open]
10
15
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Output Open 0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X
NOTE! For D-FFs the next state will be what is at the D input. So each FFs next state values in the state table must be the D inputs for that FF.
5
1 0
10
1 1
15
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D FF easiest to use
Q1 Q0 00 DN Q1 01 11 10
00
01 11 D 10
0
0
0
1
1
1
1
1 X
N
00
01 11 D 10
0
1
1
0
1
1
0
1
N
00
01 11 D 10
0
0 X
0
0
1
1
0
0
N
X X X
X X X X
X X X
1
Q0
1
Q0
1
Q0
Q1 D Q0 N N \ Q0 Q0 \N Q1 N Q1 D
D1 D CLK R \reset
Q1
Q \ Q1
D1 = Q1 + D + Q0 N
OPEN
D0 = N Q0 + Q0 N + Q1 N + Q1 D
D0 CLK R \reset D Q Q0 Q \ Q0
OPEN = Q1 Q0 8 Gates
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JK Characteristic Table
JK Excitation Table
Q+
Q 0 0 1 1
Q+ 0 1 0 1
J 0 1 X X
K X X 1 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 0 0 1 1 1 0
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Q Q+ 0 0 1 1 0 1 0 1
J K 0 1 X X X X 1 0
S R 0 1 0 X X 0 1 0
T 0 1 1 0
D 0 1 0 1
You can use any FF type for your implementation FF types can be mixed; I.e. in vending machinge you could use a JK FF for Q1 and a T FF for Q0
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J-K FF
JK Excitation Table
Present State Q1 Q0 0 0
Inputs D N
Next State Q+ Q+ 1 0 0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X
J1 0 0 1 X 0 1 1 X X X X X X X X X
K1 X X X X X X X X 0 0 0 X 0 0 0 X
J0 K 0 0 1 0 X X X X X 0 1 1 X X X X X X X X X 0 1 0 X X X X X 0 0 0 X
Q 0 0 1 1
Q+ 0 1 0 1
J 0 1 X X
0
X X 1 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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J1 = D + Q0 N
K1 = 0
N
00
01 11 D 10
0
0 1
0
1 1
X X
X X X X
Q0 Q1 N
00
01 11 D 10
X X
X X X X X X
0
0 0
Q0
0
0 0
Q1
N Q0 D \ Q0
X X X X
X X
J0 = N + Q1 D K0 = Q1 N
Q1 Q0 00 DN 00 01 11 D 10
01
11
10
Q1 Q0 00 DN 00 01 N 11 D 10
J CLK
Q1 \ Q1
01
11
10
K RQ
0 1 0
X X X X X X
Q0
0 1 1
X X X
0 1 0
0 0 0
Q0
X X X
N
X X X X
X X
X X
K Q R
7 Gates
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Outputs are function solely of the current state Outputs change synchronously with state changes
X Inputs
Mealy only; no connection for Moore
Outputs depend on state AND inputs Input change causes an immediate (asynchronous) output change
State Register
Combinational Logic for Next State (FF Inputs)
Z Outputs
State Feedback
Clock
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Moore Machine
N/0
5
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0 1
1 0
0/0
1
1/0
Different # of states
[0] 1 2 1/1
[1]
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State Register
Combinational Logic for Next State (FF Inputs) Comb. Logic for Outputs)
Output Register
Z Outputs
State Feedback
Clock
Clock
Latched state AND outputs Avoids glitchy outputs! Outputs are delayed by up to 1 clock period Usually equivalent to the Moore form
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X: 00101010010 Z: 00010101000
X: 11011010010 Z: 00000001000
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0 S1 /0
1 S2 /0 0
S4 /0
0 S5 /0 0 S6 /0 0,1
Outputs 1
S3 /1
Loops in State
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0 S1 /0
1
1 S4 /0
0
S2 /0
1 0 S3 /1
S5 /0
0 0,1
Outputs 1
S6 /0
Loops in State
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0 S5 /0
0 0,1
Outputs 1
S6 /0
Loops in State
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1 S2 /0
1 0 S3 /1
1 1
0 S5 /0
0 0,1
Outputs 1
S6 /0
Loops in State
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Write down sample inputs and outputs to understand specification Write down sequences of states and transitions for the sequences to be recognized
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Binary: 000, 001, 010, 011, 100, 101, 110, 111 Gray: 000, 001, 011, 010, 110, 111, 101, 100
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S4 /100
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A busy highway is intersected by a little used farmroad. Detectors C sense the presence of cars waiting on the farmroad. With no car on farmroad, light remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green. Assume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights. Note: The interval timer is just another sequential circuit!
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Farmroad C FL HL Highway
Highway HL FL C Farmroad
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Input Signal
reset C TS TL
Description
place SSC in initial state detect vehicle on farmroad short time interval expired long time interval expired
Output Signal
HG, HY, HR FG, FY, FR ST
Description
assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval
State
S0 S1 S2 S3
Description
Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red)
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TS
S1 TS/ST S2
TL + C/ST
S3: FY, HR
TL C
Note: This sequential circuit has both Mealy and Moore outputs!
Page 39
how do you set the internal combination? exactly when is the ERROR light asserted?
hardwired into next state logic vs. stored in internal register assert as soon as error is detected vs. wait until full combination has been entered
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Operator Data
UNLOCK
ERROR
Internal Combination
L0 L1 L2
Inputs:
Reset Enter Key-In L0, L1, L2
Outputs:
Unlock Error
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Si Enter=1
Enter=0
Sj
KI /= Li KI = Li Check next key To error sequence
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State Diagram
KI = L0
Enter Idle0 Enter Comp1 KI = L1 Enter Idle1 Enter Comp2 KI = L2 Reset Done [Unlock] Reset
KI L0
Enter
Enter
Reset
Reset
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