JITTER BASICS PART 1

By Javier Solorzano High Bandwidth Applications Engineer, Micrel, Inc.

In todays high-speed digital communications industry, timing variations in a signal have become more of an issue due to a need to maximize signal bandwidth while maintaining signal integrity. These timing variations are called jitter. Jitter can also be defined as the deviation of a timing event from its ideal location in time. Because large systems contain many high-speed products, a jitter budget must be maintained in order to minimize the probability of incurring a bit error. Bit errors are commonly referred to in terms of a bit error ratio (BER), where the bit error ratio is defined as the ratio of bad bits incurred to the number of valid bits in the data pattern. Controlling jitter in the digital signal path plays a very important role in minimizing BER and thereby increasing system reliability. These systems transfer data at various rates based upon industry standards such as Fibre-Channel, Gigabit Ethernet, and SONET. As the demand for these higher frequencies and data rates increase, so does the demand for lower jitter. As a result, it is important for both circuit and board designers to understand jitter, its sources, and its effects on a system. In Part I of this two part article, we will take a look at the basics of jitter and how it affects data and clock signals. Part I will also cover the actual types of jitter. The two major components of Total Jitter in a system are Deterministic Jitter and Random Jitter. Deterministic Jitter can be broken down into subtypes, which include Intersymbol Interference (ISI), Periodic jitter and Duty Cycle Distortion (DCD). Additionally, the second component of total jitter, Random Jitter (RJ), will be covered. RJ is normally due to thermal noise and shot noise in semiconductors. This will lead into how one can minimize the detrimental effects its causes.

Figure 1. Waveform With Jitter1.

To understand the general idea of what a waveform looks like with jitter, refer to Figure 1. In this diagram, there is an ideal signal shown as a square wave. Along with this signal, the jitter of the signal is depicted at the signal edges by use of dotted lines. As shown by the arrows, when jitter is present, a transition can occur slightly early or slightly late. Hence, this can cause bit errors at the receiving end of a system where a data signal may be sampled by a clock signal. By reviewing Figure 2, one can see that errors can occur due to a reduction in the sampling window that the clock signal uses to decipher whether the data is at a one or a zero. In the expanded region shown, one can see how jitter has reduced this window, which can lead to a reading of a zero instead of one.

Figure 2. Data Sampling Window Reduction1.

As the frequency of the data signals increase, jitter consumes more and more of the sampling window. As shown in Figure 3, a 50Mbps data signal will have a 20ns sampling window. However, if one has a 500Mbps data signal, then one will have a 2ns sampling window. If one had a 50ps of jitter, this would amount to 0.5 percent of the sampling window for the 50Mbps signal while the same amount of jitter on a 500Mbps signal will amount to 5 percent of the sampling window and 10 percent on a 1Gbps sampling window. Because of the ongoing demand for higher frequencies, which are pushing deeper into the gigabit range, it is vital to consider the effects of jitter.

Figure 3. 50Mbps and 500Mbps Sampling Window Comparison.

One should now take a closer look at what jitter is composed of. Total jitter is composed of two components; deterministic jitter and random jitter. If one considers Figure 4, one can see how deterministic jitter and random jitter can be divided further into its subcomponents.

Figure 4. Breakdown of Jitter Components2.

Deterministic jitter is considered bounded and as a result, it is measured in terms of a peak-to-peak value. When one says bounded, one is referring to the ability to predict the causes and characteristics of the different components of this type of jitter. In contrast, random jitter is unbounded and therefore, it does not have a finite peak-topeak value. As a result, an RMS value is used to account for it. Random jitter can be predicted by considering its Gaussian distribution function, which is how we can acquire its RMS value from one standard deviation or 1 from the mean of the Gaussian distribution function. Once this value is acquired, a peak-to-peak value can be calculated, which can then be used in conjunction with the deterministic peak-to-peak jitter to generate our total jitter value. Refer to Jitter Basics Part 2 newsletter for more information on this.

In particular, the following are examples of sources that can cause deterministic jitter: Power supply switching o Electromagnetic Interference source Crosstalk o Due to adjacent traces on a printed circuit board Transmitter threshold offset/differences in rise and fall time o Imperfections in transmitter circuit and signal o Capacitive loading Impedance mismatch o Incorrect termination of transmitted logic type( LVPECL, CML, LVDS etc) o Standing waves and reflections Transmitter bandwidth limitations o Rise and fall time/frequency limitations in transmitter or receiver circuitry

In turn, these effects can lead to the following types of jitter: Periodic Jitter Duty Cycle Distortion( DCD) Intersymbol Interference/Data dependent jitter( ISI)

Engineers dealing with circuit design or PCB board design are very concerned about what they can do to minimize the effects of jitter. Hence, it is important to consider what the options are. Since multiple data signals are being transmitted simultaneously on a PCB board, a data signal (victim signal) may be affected by adjacent signals (driver signals) that are being transmitted at high speeds. This is considered crosstalk. If a signal is adjacent to the signal in question, this coupling can occur as shown in Figure 5.

Figure 5. Crosstalk Coupling Between Adjacent Signals3

In order to minimize these effects, one needs to create space between the traces that carry these signals. Furthermore, by placing low frequency and energy carrying signals such as a select trace to a multiplexer or an equalizer level select trace next to the signal in question will help to minimize any coupling. Today, data transmission is done through the use of differential signals. Hence, this also provides shielding from external coupling since both the true and the complement signals are coupled the same way. The interference is masked because noise coupled to these lines is common mode to the differential pair. Furthermore, electromagnetic interference can affect a signal through nearby power pins or power supplies. Consider Figure 6. When a power supply signal switches, a significant amount of energy from a magnetic field can be coupled into the signal path. This magnetic field can, in turn, create an unwanted current that can alter a signals bias point as well as its amplitude.

Figure 6. Power Supply Switching Interference4

To minimize this, it is important to make sure that all power pins are placed as far as possible from the data signals. In addition, all power supplies must be properly bypassed with a capacitor or through other means of shielding. As mentioned before, differential data paths also reduce the effects of power supply switching since the effect is common mode to both differential lines simultaneously. Another source of data degradation is reflections or standing waves due to the improper termination of the signal line. Since reflections are due to the signal itself, it can be considered a

DJ contribution to jitter. Refer to Figure 7. Signals suffering from reflections often have spikes or humps throughout the waveform that can alter its rise and fall times and thus, can contribute to incorrect sampling of the data bits.

Figure 7. Signal Integrity Affected By Improper Line Termination2.

To minimize this, it is important to terminate all data signals with their appropriate termination schemes. Since different logic types such as LVDS, LVPECL, and CML exist, it is important to understand what the proper termination requirements are for each. Some schemes are more appropriate than others; hence, one must determine what this is based on the specific application requirements. Please refer to Micrels Interfacing Different Logic Levels (Part 1 and Part 2) Newsletters for more information: http://www.micrel.com/page.do?page=applications/hbw_tutorials.jsp As speeds and the desire for improved performance increase, the amount of jitter in a system or product will become more of a concern than it is today. Hence, by understanding jitter, its sources, and how to minimize its effects, better choices will be made in design. However, because of the important role jitter plays in a system, jitter testing is becoming commonplace due to the tight jitter budget customers have and will continue to have as speeds increase. Thus, understanding how to identify and measure Deterministic and Random Jitter components will allow circuit and board designers to take action and diminish those jitter components that are causing the problem and thus, reduce the total jitter in a system. Please refer to Jitter Basics Part 2 for more information.

Notes 1. Nehring, Dan, Oscillator Jitter FAQ, www.spvvius.ru/jitter_faq2.pdf 2. Hancock, Johnnie, Jitter- Understanding it, measuring it, eliminating it; Part 3: Causes of Jitter, Copyright 2004, Summit Technical Media, LLC, 3. Wavecrest Corp, Understanding Jitter, Copyright 2001, www.wavecrest.com.cn/technical/VISI_6_Getting_Started_Guides/6understanding.P DF 4. Wavecrest Corp, Jitter Fundamentals, SMPB-00019 Rev.1, www.wavecrestkk.co.jp/jittfun_hires_sngls.pdf References [1] Wavecrest Corp, Jitter Fundamentals, SMPB-00019 Rev.1, www.wavecrestkk.co.jp/jittfun_hires_sngls.pdf [2] Hancock, Johnnie, Jitter- Understanding it, measuring it, eliminating it; Part 3: Causes of Jitter, Copyright 2004, Summit Technical Media, LLC, www.highfrequencyelectronics.com/Archives/Jun04/HFE0604_Hancock3.pdf [3] [4] DF Nehring, Dan, Oscillator Jitter FAQ, www.spvvius.ru/jitter_faq2.pdf Wavecrest Corp, Understanding Jitter, Copyright 2001, www.wavecrest.com.cn/technical/VISI_6_Getting_Started_Guides/6understanding.P