Operating System Requirements(8.

5)
Provide protection to shared I/O resources

ECE468 Computer Organization and Architecture OSs Responsibilities

Guarantees that a users program can only access the portions of an I/O device to which the user has rights Provides abstraction for accessing devices: Supply routines that handle low-level device operation Handles the interrupts generated by I/O devices Provide equitable access to the shared I/O resources All user programs must have equal access to the I/O resources Schedule accesses in order to enhance system throughput

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Recap: Summary of Bus Options:

Option Bus width Data width Transfer size Bus masters Clocking High performance Separate address & data lines Wider is faster (e.g., 32 bits) Multiple words has less bus overhead Multiple (requires arbitration) Synchronous Low cost Multiplex address & data lines Narrower is cheaper (e.g., 8 bits) Single-word transfer is simpler Single master (no arbitration) Asynchronous

OS and I/O Systems Communication Requirements

The Operating System must be able to prevent: The user program from communicating with the I/O device directly If user programs could perform I/O directly: Protection to the shared I/O resources could not be provided Three types of communication are required: The OS must be able to give commands to the I/O devices The I/O device must be able to notify the OS when the I/O device has completed an operation or has encountered an error Data must be transferred between memory and an I/O device

Protocol

pipelined

Serial

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I/O System Design Issues

Giving Commands to I/O Devices

Two methods are used to address the device: Special I/O instructions Memory-mapped I/O

Processor

interrupts

Cache

Special I/O instructions specify: Both the device number and the command word Memory - I/O Bus Device number: the processor communicates this via a set of wires normally included as part of the I/O bus Command word: this is usually send on the buss data lines

Main Memory

I/O Controller Disk Disk

I/O Controller Graphics

I/O Controller Network

Memory-mapped I/O: Portions of the address space are assigned to I/O device Read and writes to those addresses are interpreted as commands to the I/O devices User programs are prevented from issuing I/O operations directly: The I/O address space is protected by the address translation
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I/O Device Notifying the OS

The OS needs to know when: The I/O device has completed an operation The I/O operation has encountered an error This can be accomplished in two different ways: Polling: - The I/O device put information in a status register - The OS periodically check the status register I/O Interrupt: Whenever an I/O device needs attention from the processor, it interrupts the processor from what it is currently doing.

Interrupt Driven Data Transfer

CPU (1) I/O interrupt (2) save PC Memory IOC (3) interrupt service addr read store ... : rti memory interrupt service routine add sub and or nop user program

device (4) Advantage:

User program progress is only halted during actual transfer Disadvantage, special hardware is needed to: Cause an interrupt (I/O device) Detect an interrupt (processor) Save the proper states to resume after the interrupt (processor)

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Polling: Programmed I/O

CPU Is the data ready? Memory IOC no yes read data

I/O Interrupt(page 678)

An I/O interrupt is just like the exceptions except: busy wait loop not an efficient way to use the CPU unless the device is very fast! but checks for I/O completion can be dispersed among computation intensive code no An I/O interrupt is asynchronous Further information needs to be conveyed An I/O interrupt is asynchronous with respect to instruction execution: I/O interrupt is not associated with any instruction I/O interrupt does not prevent any instruction from completion You can pick your own convenient point to take an interrupt

device store data done?

I/O interrupt is more complicated than exception: Needs to convey the identity of the device generating the interrupt Interrupt requests can have different urgencies: Interrupt request needs to be prioritized

yes Advantage: Simple: the processor is totally in control and does all the work Disadvantage: Polling overhead can consume a lot of CPU time
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Example 1: Overhead of polling(page 676)

Assume that the number of clock cycles for a polling operation, including transferring to the polling routine, accessing the device, and restarting the user program, is 400 and that the processor executes with a 500MHz clock Determine the fraction of CPU time consumed for the following three cases, assuming that you poll often enough so that no data is ever lost and assuming that the devices are potentially always busy: mouse must be polled 30 times per second floppy disk transfers data to CPU in 16-bit units and has a data rate of 50 KB/sec. hard disk transfers data four-word chunks and can transfer at 4MB/sec.
For mouse, fraction = 30400500MHz = 0.002% For floppy disk, polling rate = 50KB/s 2=25K/s, fraction = 25k 400500MHz =2% For hard disk, polling rate = 4MB/s 16=250K/s, fraction = 250k 400500MHz =20% So for quicker I/O devices, polling wastes more CUP time. What is worse, even when I/O is not busy. CPU still keeps polling.
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Interrupt Logic
Detect and synchronize interrupt requests Ignore interrupts that are disabled (masked off) Rank the pending interrupt requests Create interrupt microsequence address Provide select signals for interrupt microsequence

uSeq. addr & select logic

Interrupt Priority Network

:
Interrupt Mask Reg Sync. Inputs Q

Synchronizer Circuits

Async interrupt requests

Async. D Inputs

Clk
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Clk
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Program Interrupt/Exception Hardware

Hardware interrupt services: Save the PC (or PCs in a pipelined machine) Inhibit the interrupt that is being handled Branch to interrupt service routine Options: Save status, save registers, save interrupt information Change status, change operating modes, get interrupt info.

Delegating I/O Responsibility from the CPU: DMA

CPU sends a starting address, direction, and length count to DMAC. Then issues "start". Direct Memory Access (DMA): External to the CPU Act as a maser on the bus Transfer blocks of data to or from memory without CPU intervention Memory DMAC IOC CPU

A good thing about interrupt: Asynchronous: not associated with a particular instruction Pick the most convenient place in the pipeline to handle it

device DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory.

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Programmers View
main program Add Div Sub interrupts request (e.g., from keyboard) (1) (2) Save PC and branch to interrupt target address Save processor status/state Service the (keyboard) interrupt Restore processor status/state (3) get PC

Example 3: Overhead of DMA(page 681)

Consider the same hard disk and processor in Examples 1 and 2: hard disk transfers at 4MB/sec. the processor executes with a 500MHz clock Assume the initial setup of a DMA transfer takes 1000 clock cycles the handling of the interrupt at DMA completion requires 500 cycles Determine the fraction of CPU time consumed if the hard disk is actively transferring 100% of the time and the average transfer from the disk is 8KB

DMA rate is = 4MB/s 8kB= 500/s

Interrupt target address options: General: Branch to a common address for all interrupts Software then decode the cause and figure out what to do Specific: Automatically branch to different addresses based on interrupt type and/or level--vectored interrupt
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fraction when 100% busy = (1000+500) 500500MHz =0.2% So MDA is even better than interrupt-driven. Reason?

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Example 2: Overhead of Interrupt (page 679)

Consider the same hard disk and processor in Example 1: hard disk transfers data four-word chunks and can transfer at 4MB/sec. the processor executes with a 500MHz clock Assume that the overhead for each transfer, including the interrupt, is 500 clock cycles Determine the fraction of CPU time consumed if the hard disk is only transferring data 5% of the time.

Delegating I/O Responsibility from the CPU: IOP

CPU IOP main memory bus I/O bus (1) Issues instruction to IOP CPU IOP (3) (4) IOP interrupts CPU when done (2) memory what to do where to put data how much D1 D2 . . . Dn target device where cmnds are OP Device Address IOP looks in memory for commands OP Addr Cnt Other special requests

Mem

Interrupt rate is the same as polling rate = 4MB/s 16=250K/s,

fraction when 100% busy = 250k 500500MHz =25% fraction when 5% busy = 25%5% = 1.25% So interrupt-driven is much better than polling. Reason?

Device to/from memory transfers are controlled by the IOP directly. IOP steals memory cycles.

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Summary:
Three types of buses: Processor-memory buses I/O buses Backplane buses Bus arbitration schemes: Daisy chain arbitration: it cannot assure fairness

Where are we visited?

Input Multiplicand
32

Input Multiplier

Performance evaluation

Multiplicand Register
32=>34 signE x <<1 34 32=>34 signEx
1 0

Load Mp

32
34

ENC[2]

HI register (16x2 bits)

Cl earHI
LoadHI

LO register (16x2 bits)

LoadLO

ENC[1]
ENC[0]

2 LO[1:0]

32

32

Result[HI]

Result[LO]

"L O[

Single/multicycle Datapaths

34x2 MUX

Multi x2/x1

Arithmetic
Control Log ic
0]"

34

34

34-bi t ALU 34 32

Su b/Add

32

ShiftAll

LO[1]

Booth Encoder

Performance

Centralized parallel arbitration: requires a central arbiter I/O device notifying the operating system: Polling: it can waste a lot of processor time I/O interrupt: similar to exception except it is asynchronous Delegating I/O responsibility from the CPU Direct memory access (DMA) I/O processor (IOP)
IFetch cd Exec Mem WB D IFetch cd Exec Mem WB D

IFetch cd Exec Mem WB D IFetch cd Exec Mem WB D

198 1 0 98 198 1 198 2 198 3 1 4 98 1 98 5 1 6 98 198 7 1 8 98 199 9 1 0 99 199 1 1 99 2 199 3 1 4 99 1 5 99 1 99 6 199 7 1 8 99 200 9 0 Time

ECE4680 Winter 2003

Extra 2 bi ts

Prev

1000 Moores Law

Proc CPU 60%/yr. (2X/ 1.5 yr) Proce ssor-Memory Performance Gap: (grow s 50% / year)

100

10 DRA M 9%/yr. (2X/ 10 DRA M yrs)

Pipelining I/O Memory Systems

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ECE4680: Objectives and Assessment

Beyond ECE4680

In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary.

Application Operating System Instruction Set Architecture

Insight into fast/slow operations that are easy/hard to implementation hardware

Experience with the design process in the context of a large complex (hardware) design.

Compiler

Instr. Set Proc. I/O system Digital Design Circuit Design

Functional Spec Control & Datapath Physical implementation

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The Big Picture

Processor Input Control Memory Datapath

Output

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