Department of Electrical Engineering

The University of Faisalabad

Experiment No. 2
To design a multiplexer (4 to 1) in VHDL using CPLD development platform or FPGA circuit
board.

=============================================================================
-- It is a 4 input multiplexer with the function as:
-sel
Input => output
-MSB LSB
-0
0
in0 => output
-0
1
in1 => output
-1
0
in2 => output
-1
1
in3 => output
-----------------------------------------------------------------------------IF
and CASE can only be used inside a process.
-WHEN and WITH can only be used outside a process.
--IF
corresponds to WHEN
-CASE corresponds to WITH
-=============================================================================

VLSI Lab Work taught By: Ubaid Umar

Department of Electrical Engineering

The University of Faisalabad

=============================================================================

USING CASE
=============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer_4to1_case is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
e : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC);
end multiplexer_4to1_case;
architecture Behavioral of multiplexer_4to1_case is
begin
process (a, b, c, d, e, Sel) is
begin
case Sel is
when "00" => Output <= a;
when "01" => Output <= b;
when "10" => Output <= c;
when "11" => Output <= d;
when others => Output <= e;
end case;
end process;

end Behavioral;

VLSI Lab Work taught By: Ubaid Umar

Department of Electrical Engineering

The University of Faisalabad

=============================================================================

USING IF
=============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer_4to1_if is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
sel0 : in STD_LOGIC;
sel1 : in STD_LOGIC;
output : out STD_LOGIC);
end multiplexer_4to1_if;
architecture Behavioral of multiplexer_4to1_if is
begin
PROCESS(sel0, sel1, a, b, c, d)
BEGIN
IF

(sel0='0' AND sel1='0') THEN

output <= a;
ELSIF (sel0='1' AND sel1='0') THEN
output <= b;
ELSIF (sel0='0' AND sel1='1') THEN
output <= c;
ELSIF (sel0='1' AND sel1='1') THEN
output <= d;
ELSE
-- (sel0 or sel1 are not 0 or 1)
output <= 'X';
END IF;
END PROCESS;

end Behavioral;

VLSI Lab Work taught By: Ubaid Umar

Department of Electrical Engineering

The University of Faisalabad

=============================================================================

USING WITH
=============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer_4to1_with is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
sel0 : in STD_LOGIC;
sel1 : in STD_LOGIC;
output : out STD_LOGIC);
end multiplexer_4to1_with;
architecture Behavioral of multiplexer_4to1_with is
SIGNAL

sel

STD_LOGIC_VECTOR(1 DOWNTO 0);

begin
sel <= sel1 & sel0; -- concatenate s1 and s0
WITH sel SELECT
output <= a WHEN "00",
b WHEN "01",
c WHEN "10",
d WHEN "11",
'X' WHEN OTHERS;
end Behavioral;

VLSI Lab Work taught By: Ubaid Umar

Department of Electrical Engineering

The University of Faisalabad

=============================================================================

USING WHEN
=============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer_4to1_when is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
sel0 : in STD_LOGIC;
sel1 : in STD_LOGIC;
output : out STD_LOGIC);
end multiplexer_4to1_when;
architecture Behavioral of multiplexer_4to1_when is
begin
output <= a WHEN
b WHEN
c WHEN
d WHEN
'X';

(sel1
(sel1
(sel1
(sel1

&
&
&
&

sel0)="00"
sel0)="01"
sel0)="10"
sel0)="11"

ELSE
ELSE
ELSE
ELSE

end Behavioral;

VLSI Lab Work taught By: Ubaid Umar