A 14-TRANSISTOR CMOS FULL ADDER WITH FULL VOLTAGE-SWING NODES

Mark Vesterbacka Department of Electrical Engineering Linkoping University Linkoping, Sweden

Abstract We explain how exclusive OR and NOR circuits (XORKNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 pm process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evallated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder.

INTRODUCTION
CMOS full adder circuits
CMOS full adder circuits based on pass transistors can often be realized using fewer transistors compared to other solutions. For example, a direct realization using static CMOS logic requires 28 MOSFETs [l]. On the other hand, a transmission gate full adder has been reported that only needs 16 MOSFETs for its realization [2]. However, the saving in device count does not come entirely for free, since the pass transistor adders generally lack in driving capability. Nevertheless, they are area efficient design alternatives in places where the loads are small, or where additional drivers can be afforded. Attempts have been made to lower the device count further. In [3] and [4], pass transistor full adders are designed using only 14 MOSFETs, but with a cost of a poor voltage-swing in some of the circuit nodes. Other recently proposed adders aim at improving the performance of the pass transistor adder in terms of energy [ 5 ] , [6] or speed [7] at a cost in device count of 17, 18, and 18 MOSFETs, respectively. In this paper, we present a new full adder circuit that needs only 14 MOSFETs for its realization while having full voltage-swing in all nodes.

0-7803-5650~0/99/$10.00 1999 IEEE Q

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The general structure of a pass transistor adder is shown in Fig. 1. It consists of one exclusive ORMOR function (XOR/XNOR) shown to the left, two transmission gates shown in the middle, and one XOR gate shown to the right in the figure. As indicated in the figure, the complementary outputs of the XOIUXNOR gate are used to control the transmission gates which together realizes a multiplexer circuit producing the carry. The complementary outputs are also used to simplify the XOR gate that produces the sum.

Figure 1 General structure of a pass transistor full adder. .

CMOS XOR circuits

Some pass transistor XOR circuits are shown in Fig. 2 that have been used in the realization of the pass transistor adders in [ 11-[7] (the corresponding complementary XNOR circuits were used in some of the adders). The circuit in Fig. 2 (a) uses only four MOSFETs to realize an XOR function. However, it is not suitable in all applications due to a threshold voltage drop at the output for A = B = 0. A full-swing output is achieved by the circuits in Fig. 2 (b) and (c). However, they use four and five MOSFETs respectively and do also need a complementary input, which may require additional MOSFETs in an adder realization, depending on the availability of this signal.

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A@B

Figure 2. Pass transistor XOR circuits.

NEW FULL ADDER

Reference adder
In the pass transistor adder structure in Fig. 1, one XOR/XNOR function is used. To realize this function, either one of the XOR circuits can be used along with a complementary XNOR structure, or one CMOS inverter can be added to produce the XNOR output. Also, assuming that no complementary inputs are available, a CMOS inverter is needed to create the complement of A for the circuits in Fig. 2 (a) and (b). This yields a minimum device count of eight to implement the XOR/XNOR function using any of the gates in Fig. 2. The two transmission gates require another four MOSFETs, while the rightmost XOR gate can be implemented using four MOSFETs. The pass transistor full adder presented in [2] has this structure; yielding a device count of 16 MOSFEiTs. The XOR/XNOR function and the XOR gate were realized with the XOR circuit in Fig. 2 (b) and

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two CMOS inverters according to the realization shown in Fig. 3. Since this circuit has a low device count, and also has full voltage-swing in all nodes, it will be used as a reference circuit in the following.

Figure 3. 16-transistor full adder circuit.

Proposed adder
To further decrease the device count, we use the recently proposed
XOR/XNOR circuit shown in Fig. 4 [SI. It is based on the same cross coupled

pMOSFET structure as in Fig. 2 (a), but it also uses the complementary cross coupled nMOSFET structure to produce the complement. These structures do not provide an output for A = B = 0 and A = B = 1, respectively, which instead is provided by the feedback nMOSFEiT and pMOSFJZT marked with asterisks (*) in Fig. 4. The feedback also eliminates the threshold voltage loss associated with the structure in Fig. 2 (a).

=-i
Figure 4. Six-transistor XOR/XNOR circuit.
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Only six transistors are needed to realize this circuit, which should be compared with the minimum of eight MOSFETs needed in realizations with the XOR gates in Fig. 2. However, the lower device count does not come entirely for free. Compared to the other XOR gates, the feedback will lower the maximal operating frequency and require the MOSFETs to be ratioed. To properly ratio the MOSFETs, the design effort increases. The strength of the driving circuits must thereby be considered, taking worst case process parameters into account. A new full adder circuit that uses the six-transistor XORRNOR gate is shown in Fig. 5. Here, the XOR gate in Fig. 2 (b) has been used to produce the sum. The total device count becomes 14 for this circuit.

Figure 5. New 14-transistorfull adder circuit.

SIMULATION RESULTS
Simulation settings
A layout was made for the new full adder circuit in a MIETEC 0.35 pprocess. Another layout was made for the reference full adder in Fig. 3. The layouts are shown in Fig. 6, with the reference adder in a) and the new adder in b). Two metal layers out of five have been used within the adder cells. To yield more realistic rise and fall times in the simulations, CMOS inverters were added to all inputs. CMOS inverters were also added to load the output. The energy consumed in the input drivers was included in the simulations, while the energy consumption in the load was excluded. The complete simulation setup is shown in Fig. 7. The simulations were performed with HSPICE [9] using a power supply voltage of 3 V. The feedback pMOSFET marked with an asterisk in Fig. 5 had an aspect ratio of (1.6 pd0.35 pn),and the feedback nMOSFET also marked with an asterisk had an aspect ratio of (0.5 pd0.35 pn). All other pMOSFETs in CMOS inverters and both full adders had the aspect ratio (3.2 pnd0.35 pn) and all nMOSFETs (0.8 pd0.35 pm). Simulation results for the reference full adder are

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shown in Fig. 8 a) and simulation results for the new full adder are shown in Fig. 8 b). The full adder input voltages (X, Y, Z are shown in order from the top in the ) figures, followed by the cany and the sum output voltages.

(b)
Figure 6. Layout of a) the reference full adder, b) the new full adder.

Figure 7 Simulation setup. .

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Simulated input and output voltages for the XOIUXNOR circuit in the new full adder are shown in Fig. 9. The shown voltages are, in order from top to bottom, ) the the input voltages (Y,Z , XOR and the XNOR output. In this simulation, it can be seen that although the input X is not directly connected to the XOR circuit, it still causes glitches to appear at the XOR and XNOR output due to switching of the transistors connected to the output. Note that the circuit does not work if the feedback pMOSFETs are given the that were aspect ratio (3.2 p d O . 3 5 pm) and the nMOSFET (0.8 pd0.35 p) used for the other MOSFETs. This experiment shows the importance of ratioing the MOSFETs properly.

Results
The results have been compiled into table 1. The power consumption and power delay product are approximately equal for both circuits. The propagation delay from the X input to the carry output are very low for both circuits, which suggests that this input is good for use in carry chains. Comparing the other propagation delays that are tabulated on the form input+output, the propagation delay to the carry is halved, and the propagation delay to the sum is increased by 40% for the new circuit. The device count has been lowered from 16 to 14 MOSFETs, and the area is approximately scaled with the same factor.

CONCLUSION
A new full adder circuit was proposed that is realized using only 14 MOSFETs. Although the device count is very low, the circuit has full voltageswing in all nodes. This is achieved through the use of a recently proposed CMOS XOR circuit that only needs six MOSFETs to produce both an exclusive OR and an exclusive NOR function, saving two MOSFETs over other known solutions. However, there is an increased cost associated with this XOR circuit in terms of design time. This is due to that the XOR circuit is realized using a feedback structure containing two MOSFETs that need to be ratioed properly. To estimate the performance, the proposed circuit was compared to another pass transistor full adder with a low device count, i.e. 16 MOSFETs. A layout were made in a 0.35 pn process for both adders, and the corresponding netlists were simulated in HSPICE. A comparison between the two adders yielded similar performance in terms of power consumption and power delay product. Regarding the input yielding the shortest propagation delays from the input to the outputs, the respective propagation delays were also similar for both adders.

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Figure 8. Simulation of a) the reference full adder, b) the new full adder.

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Figure 9. Simulation of the XORKNOR gate in the new full adder.

Circuit Power consumption @ 500 MHz [mW] Power delay product [pJ]
'

ReferenceFA
0.30
0.11

New FA
0.28
0.12

Propagation delay X+C [ns] Propagation delay Y+C [ns] Propagation delay Z+C [ns] Propagation delay X+C [ns] Propagation delay Y+C [ns] Propagation delay Z+C [ns] Device count [I Area [urn']

0.04
0.37 0.20 0.16 0.30

0.05
0.18 0.18 0.15 0.37 0.42 14
150

0.29
16 170

Table 1. A simple comparison of the two full adder circuits.

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References
[I]

N. Weste and K. Eshragian, Principles of CMOS VLSI Design-A Systems Perspective, 2nd ed., Reading, MA: Addison-Wesley, 1993.

[2] N. Zhuang and H. Wu, A New Design of the CMOS Full Adder, IEEE J. o Solid-state Circuits, vol. 27, no. 5, pp. 840-844, May 1992. f [3] E. Abu-Shama, A. Elchouemi, S. Sayed, and M. Bayoumi, An Efficient Low Power Basic Cell for Adders, Proc. 38th Midwest Symp. on Circuits and Systems, vol. 1, pp. 306-309, 1995. [4] E. Abu-Shama, and M. Bayoumi, A New Cell for Low Power Adders, Proc. Int. Symp. on Circuits and Systems, vol. 4, pp. 49-52, 1996. [5] A. M. Shams and M. A. Bayoumi, A New Full Adder Cell for Low-Power Applications, Proc. IEEE Great Lakes Symp. on VLSl 98,pp. 45-49, 1998. [6] H. Lee and G. E. Sobelman, A New Low-Voltage Full Adder Circuit, Proc. IEEE Great Lakes Symp. on VLSI 97,pp. 88-92, 1997. [7] A. T. M. Khalid, A Fast Optimal CMOS Full Adder, Proc. 39th Midwest Symp. on Circuits and Systems, vol. 1, pp. 91-93, 1996. [8] M. Vesterbacka, A New Six-Transistor CMOS XOR Circuit with Complementary Output, To appear in Proc. 42nd Midwest Symp. on Circuits and Systems, Las Cruces, NM, Aug. 8-1 1, 1999. [9] HSPICE Users Manual, Meta-Software, Campbell CA, 1992.

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