051-7455 K36 DVT

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
K36 MLB SCHEMATIC
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
DATE
REFERENCED FROM M70
8/9/2007
D
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
1
2
3
4
5
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7
8
9
10
11
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13
14
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26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Date
Contents
Sync
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
37
Ethernet (Yukon)
Yukon Power Control
ETHERNET CONNECTOR
FIREWIRE CONTROLLER
FIREWIRE PORT
PATA CONNECTOR
SATA CONNECTOR
USB EXTERNAL CONNECTORS
CONNECTOR MISC
IR CONTROLLER & BT INTERFACE
SMC
SMC SUPPORT
38
39
40
43
44
45
46
47
48
49
50
Page
09/05/2006
Table of Contents
System Block Diagram
Power Block Diagram
CONFIGURATION OPTIONS
Revision History
FUNC TEST 1 OF 2
Power Aliases
SIGNAL ALIAS /RESET
CPU FSB
CPU Power & Ground
CPU Decoupling & VID
CPU ITP700FLEX DEBUG
NB CPU Interface
NB PEG / Video Interfaces
NB Misc Interfaces
NB DDR2 Interfaces
NB Power 1
NB Power 2
NB Grounds
NB Standard Decoupling
NB Graphics Decoupling
SB Enet, Disk, FSB, LPC
SB PCI, PCIe, DMI, USB
SB Pwr Mgt, GPIO, Clink
SB Power & Ground
SB Decoupling
SB Misc
Clock (CK505)
Clock Termination
DDR2 SO-DIMM Connector A
DDR2 SO-DIMM Connector B
Memory Active Termination
(.csa)
RX
RX
MK
RX
RX
RX
MK
RX
RX
RX
RX
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
RX
RX
RX
RX
RX
RX
DK
DK
LD
LD
LD
LT
LT
LT
LT
LT
LT
DK
RX
LT
LT
LT
LD
LD
TABLE_TABLEOFCONTENTS_HEAD
USB
05/11/2006
WFERRY-WF
06/30/2005
POWER
07/18/2005
SMC
N/A
N/A
07/25/2005
TP
06/15/2006
WFERRY
07/17/2006
GPU
11/12/2006
T9_MLB_NOME
11/12/2006
T9_MLB_NOME
04/26/2006
MSARWAR
5/23/05
MASTER
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
06/15/2006
WFERRY
06/15/2006
WFERRY
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
10/30/2006
T9_MLB
06/01/2006
WFERRY
07/26/2005
NB
06/06/2006
DSIMON
06/06/2006
DSIMON-WF
06/20/2005
MEMORY
06/20/2005
MEMORY
06/20/2005
MEMORY
08/19/2005
ENET
10/07/2006
USB
10/07/2006
USB
09/14/2006
USB
08/30/2005
ENET
07/17/2006
GPU
07/17/2006
GPU
07/17/2006
GPU
06/30/2006
USB
06/29/2006
USB
09/05/2006
USB
10/30/2006
T9_MLB
07/17/2006
GPU
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
51
52
53
55
56
59
61
62
66
67
68
69
70
71
72
73
75
76
77
78
79
90
92
94
100
101
102
103
104
105
106
LPC+ Debug Connector

SMBUS CONNECTIONS
CPU Current & Voltage Sense
TEMPERATURE SENSE
Fan
SMS
SPI ROMs
AUDIO: CODEC
AUDI0: SPEAKER AMP
AUDIO: JACK
AUDIO: JACK TRANSLATORS
DC-In & Battery Connectors
S0 FETS & Power Sequencing
IMVP6 CPU VCore Regulator
Render VCore Supplies
1.5V / 1.05V Supplies
1.8V/0.9V Supplies
5V/3.3V Supplies
3.42V/1.25V Switcher
S3 FET & S3/S5 Control
PBUS Supply/Battery Charger
INVERTER,LVDS,TMDS
EXTERNAL TMDS
MINI-DVI CONNECTOR
CPU/FSB Constraints
NB Constraints
Memory Constraints
SB Constraints (1 of 2)
Clock Constraints
FireWire & SMC Constraints
Date
Contents
Sync
06/01/2006
LD
LD
ES
ES
LD
MK
RX
RX
RX
RX
RX
RX
MK
MK
MK
MK
MK
MK
MK
MK
MK
MK
ES
ES
ES
RX
ES
LD
RX
RX
DK
DVT BUILD
A
WFERRY
06/01/2006
WFERRY
07/17/2006
GPU
06/21/2006
GPU
11/10/2005
ENET
08/23/2005
SMC
04/26/2006
WFERRY
03/12/2007
M70AUDIO
03/12/2007
M70AUDIO
03/12/2007
M70AUDIO
03/12/2007
M70AUDIO
07/13/2005
POWER
05/31/2006
DSIMON-WF
07/13/2005
POWER
06/29/2006
GPU
07/13/2005
POWER
07/13/2005
POWER
07/13/2005
POWER
12/06/2005
ENET
06/12/2006
DSIMON-WF
08/19/2005
SMC
06/23/2006
GPU
06/06/2005
GRAPHIC
05/21/05
EUGENE
06/08/2006
WFERRY
06/12/2006
WFERRY
06/08/2006
WFERRY
06/12/2006
WFERRY
06/12/2006
WFERRY
06/12/2006
WFERRY
06/12/2006
WFERRY
K36 EE DRIS:
RX-RAYMOND XU
DK-DINESH KUMAR
RC-RAY CHANG
MK-MARC KLINGELHOFER
LT-LAWRENCE TAN
LD-LINDA DUNN
MM-MARY(YUAN) MA
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #s
PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-7455
SCHEM,MLB,K36
SCH
CRITICAL
820-2279
PCBF,MLB,K36
PCB
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
BOM OPTION
TITLE
DO NOT SCALE DRAWING
SCHEM,MLB,K36
NONE
SIZE
THIRD ANGLE PROJECTION
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
051-7455
REV.
SHT
01
OF
76
U1000
CPU
U2900
CK 505
2.? GHz
Core ~1.2V
Pg 10
J1302
Pg 9
Clocks
TERMS
Pg 28
Pg 29
ITP CONN
PG 12
FSB
NB-GMCH
Core
1.05 - 1.25V
Pg 14
TV
Out
PG 68
RGB
MUX
PG 57
PG 57-67
DIMM
DDR2 - Dual Channel
Parallel
Term
Temp Sense
Pg 32
1.8V - 64 Bits
533/667/800? MHz
Pg 14
DMI
CLnk 0
Pg 15
Pg 15
U5520
PG 49
HEAT-PIPE/FIN
U5500
PG 49
U5920 SUDDEN MOTION DETECT PG 51
POWER SENSE
PG 69
J9001
PG 48
J5601
U6100/50
FAN CONN PG 50
SPI
Boot ROM
Int Disp
Conn
CPU
Pg30,31
Pg 15
Pg 17,18,19
LVDS
DVI-I
Power
Supply
Misc
GPIO
J9401
Pg 15/16
PCI-E
SDVO
TMDS
DC/Batt
Conn
J3101
J3201
Main Memory
Pg 13
U1400
U9200
J6900/50
64-Bit
800/1066? MHz
x4 DMI
PG 54
2.5 GHz
PG 67
B,0
BSA BSB ADC
SMC
Fan Ser
Prt
J5100
LPC Conn
Pg 23
J4600
UATA
SB-ICH8
Pg 24
GPIOs
U4800
SATA-2
J4401
SPI
Pg 24
SATA
SATA-1
PG 40
CLnk 0
U2300
Pg 22
SATA
Conn
DMI
Pg 23
PG 46
PG 44
Pg 22
SATA-0
J4501
LPC
U4900
J4850
IR
CONTROLLER
PG 44
Core 1.05V
J4700
J4810
3G
Geyser
CONNECTOR
PG 43
Trackpad/Keyboard
PG 42
Bluetooth
PG 43
J4601
USB
Connectors
PG 41
USB
PCI-E
CAMERA
Ln5 Ln6
Core
Pg 25
Pg 24
B
SMB
Pg 23
Ln1 Ln2 Ln3 Ln4
Pg 23
UATA
Pg 22
PG 39
1 2 3 4 5 6 7 8 9
Conn
E-NET
CLnk 1
PCI
AZALIA
Pg 22
Pg 24
Pg 23
Pg 22
DIMMs
Clk Gen
J3101
U2900
J3201
UC500
33 MHz
32-Bit
U6200
U4000
Audio
Codec
FW32306
Pg 53
Pg 37
System Block Diagram
U6600/10/20
JACK
TRANSLATORS
U3700
NINEVEH
PG 56
Speaker
Amps
SYNC_MASTER=WFERRY-WF
SYNC_DATE=05/11/2006
PG 54
E-NET

Pg 34

J3400
J4300
J3900
Mini PCI-E
AirPort
E-NET
Conn
FireWire
Conn
Pg 33
Pg 36
PG 38
J6701 INTERNAL MIC

J6702/03 INTERNAL SPEAKER
J6750/00 LINE IN/OUT

SIZE
Audio
Conns
PG 55
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
76
01
K36 POWER SYSTEM ARCHITECTURE

D6901
02
PPDCIN_G3H
VIN
SMC_ENRGYSTR_LDO_EN
MAX8719
U7950
SHGN*
D7950
7A FUSE
PPVBAT_G3H_CHGR_REG
VOUT
SMC PWRGD
RN5VD30A-F
U5000
(PAGE 45)
ENABLE
Q5350
PPBUS_G3H
D
CLOCK
VIN
01
AC
ADAPTER
IN
CHGR_EN
(S5)
U7970
6A FUSE
DCIN
ENABLES
VIN
ENA1
17 1V5S0_RUNSS
(S0)
ENA2
PGOOD1
ISL6257HRZ
U7900
(PAGE 66)
U5300
01
02
VOUT
ISL9504
3S2P
IMVP_VR_ON
PGOOD2
19
U7100
(PAGE 59)
RC
DELAY
P3V3S3_EN_L
(S3)
12
RESET*
U6201
ENA
PP4V5_AUDIO_ANALOG
VOUT
(PAGE 53)
PP5V_S3
P25
LOGIC
U4900
(PAGE 45)
17
CHGR_EN
02
Q7859
06
P60
07
Q7860
SMC_PM_G2_EN
(S5)
VIN
5VS5_RUNSS
(S5)
3V3S5_RUNSS
(S5)
Q7859
ENA1
ENA2
07
5V
VOUT1
PP1V2_ENET_REG
MAX8516
PM_ENET_EN_L
VIN
PP5V_S5
(7.5A MAX CURRENT)

08
PP3V3_S5_REG
VOUT
ENA (PAGE 35)
CRESTLINE
P3V3S3_EN_L
12
18
16
MCH DPLL
VIN
P1V8S0_EN
ENA
TPS731125
U2265
(PAGE 21)
18
TPS3808-1.25V
MR* U7200
RESET*
SENSE
(PAGE 58)
ADAPTER IN
RUNSS_GATE_D
15
S5
S3
VLDOIN
1.8V
VOUT1
0.9V VOUT2
R7502
13
PP1V8_S3_REG
(10.75A MAX CURRENT)
PP0V9_S0_REG
TPS51116
U7500
(PAGE 62)
UVLO_A
GATE A P5VS0_EN
15
PP5V_S0_FET
UVLO_B
GATE B P3V3S0_EN
15
PP3V3_S0_FET
PP1V8_S0_FET
14
02
1V25S0_RUNSS
17
(S0)
GFX_VR_EN
PM_SLP_S3_L
20
GPU_VCORE
U7200
PM_PWRBTN_L
SMC_RESET_L
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
(PAGE 44)
Power Block Diagram

SYNC_MASTER=POWER
UVLO_C
UVLO_D
ENA*
GATE C P1V8S0_EN
15
GATE D RUNSS_GATE_D

15

SIZE
PPVCORE_S0_NB_GFX_IMVP
(7.7A MAX CURRENT)
ISL6130IRZA
U7000
(PAGE 58)
VIN ISL6263
ENA
VOUT
(PAGE 60)
21
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
23
RST*
PGOOD_1V8S3
Q7006
SOFT
START
PP1V8_S3_REG_R
18
14
1V05S0_RUNSS
17
(S0)
IMVP_VR_ON(P16)
RSMRST_IN(P13)
PLT_RST*
PWR_BUTTON(P90)
P17(BTN_OUT)
IMVP_VR_ON
SLP_S5_L(P95)
PGOOD_1V5S0
PGOOD_1V05S0
Q7007
SOFT
START
99ms DLY
PGOOD_SEQUENCER
VIN
17
PWRGD(P12)
10-1
SLP_S4_L
19
12
Q7007
1V5S0_RUNSS
(S0)
SLP_S3_L
PM_SLP_S3_L
05
04-1
1V8S3_RUNSS
SOFT
START
09 RSMRST_PWRGD
SLP_S5_L
PM3V3ENET_SS
02
Q7006
ALL_SYS_PWRGD
PM_RSMRST_L
RST*
16
PP1V5_S0_REG
15
RSMRST_OUT(P15)
SMC_ONOFF_L
PM_ENET_EN_L
U7870
10
SMC
22
P1V25_S0_NB_DPLL
WOL_EN
SMC_ADAPTER_EN
30
FSB_CPURST_L
U1400
(PAGE 13)
BATTERY ONLY:
VOUT
15
Q3802
16
P3V3S0_EN 15
Q3810
P3V3_ENET_FET
17
U3820
PP1V9_ENET_REG
ENA
VOUT
(PAGE 35)
PP1V25_S0_FET
Q7001
HCPURST*
1.9V S3
TPS79501DRB
VIN
PP3V3_ENET_FET
PP3V3_S0_FET
P1V8_S0_FET
PWROK
13
PP3V3_S3
Q7004
PP1V25_S0_REG
PP3V3_S5
14 Q3801
15
VOUT
(PAGE 64)
Q7866
09
18
ENA
VREG3
RSMRST_PWRGD
17-1
PP5V_S5_REG
1.25V S0
TPS62510
1V25S0_RUNSS
12
U7720
08
TPS51120
U7600
(PAGE 63)
1.2V YUKON
VIN U3830
P5VS3_EN_L
3.3V VOUT2 (5A MAX CURRENT)
PGOOD1,2
PP3V3ENET_SS
U1000
(PAGE 9)
17-1
VIN
13
SMC
PM_S4_STATE_L
PM_SLP_S4_L
PWRGOOD
16
4.5V AUDIO
TPS79501
15
Q7865
PM_SLP_S3_L
CPU
Q7000
12
P5VS3_EN_L
(S3)
28
U2300
(PAGE 22)
25
U2801
P5VS0_EN
RC
DELAY
CPU_PWRGD
PWROK
CPUPWRGD(GPIO49)
24
29
RSMRST*
26 VR_PWRGOOD_DELAY
PPBUS_G3H
11 Q7860
PLT_RST_L
PM_SB_PWROK
PP5V_S0_FET
ICH
06-1
PWRBTN*
VRMPWRGD
27
SMC_CPU_VSENSE
VR_PWRGOOD_DELAY
PGOOD
CK_PWRGD
PLTRST*
19
VR_ON
23
BATT_POS_F
18
VR_PWRGD_CK505_L
CLKEN#
SLG8LP537V
U2900
(PAGE 28)
U2803
VR_PWRGD_CK505
A SMC_CPU_ISENSE PPVCORE_CPU_S0
(36A MAX CURRENT)
CPUVCORE
VIN
PWRGD
CLK_PWRGD
PP1V05_S0_REG_R
ICH8M
PGOOD_1V5S0
PGOOD_1V05S0
SMC_DCIN_ISENSE
1.5VVOUT2
18
R7302
PP1V05_S0_REG
(8A MAX CURRENT)
PP1V5_S0_REG
(4A MAX CURRENT)
VOUT1
TPS51124
U7300
(PAGE 61)
SMC_BATT_ISENSE
PBUS CONVERTER/
BATTERY CHARGER
BATTERY
1.05V
17 1V05S0_RUNSS
(S0)
U7975
VOUT
04
SMC_RESET_L
02
(PAGE 66)
03
3.425V G3HOT
PP3V42_G3H_REG
LT3470
U7790
(PAGE 64)
PBUSB_VSENSE
ENRGYSTR LDO
OF
76
01
PAGE_BORDER=TRUE
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM OPTION
BOM options provided by this page:

(NONE)
BOMOPTION
K36 GOOD
630-9104
EVT
IC,MDC,SR,E1,2.0G,800FSB,4M,BGA
U1000
CRITICAL
GOOD
337S3500
IC,MDC,SR,G0,2.2G,800FSB,4M,BGA
U1000
CRITICAL
BETTER
337S3500
IC,MDC,SR,G0,2.2G,800FSB,4M,BGA
U1000
CRITICAL
BEST
TABLE_5_ITEM
TABLE_5_ITEM
BOM OPTION REMOVED BOM OPTION REMOVED
---
0.031
---
0.031
BOM TABLE FOR HF POSCAPS
0.07
L7-L8
L8
BOM OPTION REMOVED BOM OPTION REMOVED
REMOVED
0.076
POWER
TABLE_5_ITEM
337S3463
REMOVED
>
L7
>>
BOM OPTION
>>
L6-L7
CRITICAL
---
>
POWER
>
L6
0.014
0.07
>
L5-L6
>>>
0.076
GND
>> >
L5
0.079
0.014
>
L4-L5
>>
Speed)
Speed)
SIGNAL
>>
REFERENCE DESIGNATOR(S)
0.156
L3-L4
L4
0.079
0.014
>
DESCRIPTION
SIGNAL
>>
QTY
0.076
>>
L3
---
0.014
>
L2-L3
TABLE_5_HEAD
PART#
0.07
GROUND
>>
L2
0.1
>
L1-L2
0.018
0.047
>>
CONFORMAL_COAT
L1
SIGNAL(TOP)
TRACE WIDTH
(MM)
BOM OPTION REMOVED
>
Speed)
Speed)
THICKNESS
(MM)
BOM OPTION REMOVED
BOM OPTION REMOVED
>
MLB STACKUP
LAYER
BOM OPTION REMOVED
REMOVED
>
SIGNAL
GROUND
SIGNAL(High
SIGNAL(High
GROUND
POWER
POWER
GROUND
SIGNAL(High
SIGNAL(High
GROUND
SIGNAL
REMOVED
>
Top
2
3
4
5
6
7
8
9
10
11
BOTTOM
M70 GOOD
630-7935
CONCEPT
>>
>>
>>
BOARD STACK-UP AND CONSTRUCTION
K36 BEST
630-9106
EVT
>>
>>
>>
COMMON
ALTERNATE
ARB_ONLY
K36
LPCPLUS
INVERTER_BUF
BOM OPTION
INVERTER_UNBUF
BOM OPTION
ITP
NO_REBOOT_MODE
NBCFG_DMI_REVERSE
NBCFG_DMI_X2
NBCFG_DYN_ODT_DISABLE
NBCFG_PEG_REVERSE
NBCFG_SDVO_AND_PCIE
GOOD
BETTER
BEST
K36_PGM
YUKON_EC
YUKON_ULTRA
NORMAL
FANCY
STANDOFF
ODD_PWR_CORE
ODD_PWR_RESUME
ISL6126
BOM OPTION
BOM OPTION
ISL6130
K36 BETTER
630-9105
EVT
GROUND
---
0.014
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
L8-L9
B
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
CRITICAL
K36
TABLE_5_ITEM
343S0448
IC,CRESTLINE,GM965,667
U1400
L9
0.076
SIGNAL
L9-L10
HF VERSION OF 128S0057
C4610,C4611,C6830,C6831
CRITICAL
K36
128S0164
C2130,C2716,C7543
CRITICAL
K36
128S0148
C6605
CRITICAL
K36
128S0169
C7220,C7352,C7542
CRITICAL
K36
128S0160
C2173,C2700
CRITICAL
K36
128S0150
CRITICAL
K36
128S0157
C2220
CRITICAL
K36
128S0162
C2140
CRITICAL
K36
128S0135
C6601,C6603
CRITICAL
K36
TABLE_5_ITEM
0.156
TABLE_5_ITEM
TABLE_5_ITEM
338S0434
IC,ICH8,BGA
U2300
CRITICAL
K36
TABLE_5_ITEM
516-0162
IN-LINE SODIMM CONNECTOR
J3101,J3201
CRITICAL
TABLE_5_ITEM
L10
SIGNAL
0.1
0.014
TABLE_5_ITEM
K36
L10-L11
L11
GROUND
0.076
TABLE_5_ITEM
0.1
0.014
C6204,C6205,C7651,C7652,C7691,C7692
TABLE_5_ITEM
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
341S2196
IC,16MBIT 8PIN SPI SERIAL FLASH,SOIC8
U6100
CRITICAL
K36_PGM
341S2060
IC,EEPROM,SERIAL IIC,8KBIT,SO8
U3780
CRITICAL
K36_PGM
TABLE_5_ITEM
TABLE_5_ITEM
341S2198
IC,SMC,HS8/2116
U4900
CRITICAL
K36_PGM
341S2093
IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR
U4800
CRITICAL
K36_PGM
TABLE_5_ITEM
0.1
0.014
128S0147
TABLE_5_ITEM
L11-L12
0.07
L12 SIGNAL(BOTTOM)0.047
0.018
CONFORMAL_COAT
0.1
TABLE_5_ITEM
TOTAL
LOCKED BOOTROM PN 341S2197
1.276
---
TABLE_5_HEAD
CRITICAL
BOM OPTION
826-4393
PART#
QTY
DESCRIPTION
LBL,P/N LABEL,PCB,28MMX6MM
EEE:Z55
CRITICAL
GOOD
826-4393
EEE:Z56
CRITICAL
BETTER
TABLE_5_ITEM
CONFIGURATION OPTIONS
TABLE_5_ITEM
TABLE_5_ITEM
826-4393
EEE:Z57
CRITICAL
SYNC_MASTER=SMC SYNC_DATE=07/18/2005
BEST

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
76
01
Revision History
- WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357
- ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD DRAG CIRCUIT TO
PROPERLY DISCHARGE ODD POWER WHEN ITS TURNED OFF - RADAR: 4923903
- ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755
- LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD
- HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500
- FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858
- FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888
- NO STUFF 3G CONNECTOR CIRCUITRY
- CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252)
- CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING
MICROPHONE THROUGH LVDS CABLE
- CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT
- CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553
- MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913
- MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB
- TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481
M70 EVT TO DVT CHANGES
3/8/2007
CSA PAGE 22:
- 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603).
CSA PAGE 25:
- 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5.
CSA PAGE 77:
- 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0,
C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF,
AND REVERT REFERENCE DESIGNATORS. (CHANGE FROM TPS62510 TO LTC3412A)
3/12/2007
CSA PAGE 25:
- 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP.
CSA PAGE 45:
- UPDATE SYMBOL FOR J4501.
CSA PAGE 62,66,67,68:
- SYNC FROM AUDIO TEAM.
CSA PAGE 94:
- 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K.
7/17/2007
CSA PAGE 59:
- UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150.
6/29/2007
CSA PAGE 4:
- CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G).
- CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G).
- CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G).
- CHANGE NB FROM 338S0426(500M) TO 343S0448(667M).
- CHANGE SB FROM 338S0427 TO 338S0434.
CSA PAGE 16:
- DISCONNECT GFX_VID<0> TO GND.
- CONNECT GFX_VID<0:3> TO GFX_VID0:3 ON NB.
- ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID<4> TO GND.
CSA PAGE 22:
- 5282756 ADD C2207 (0.1UF, 0402).
- SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT.
- CHANGE GFX_VID<1:4> TO GFX_VID<0:3>.
- CHANGE STRAPPING FROM 0010 ON GFX_VID<1:4> TO 0001 ON GFX_VID<0:3>.
CSA PAGE 39:
- CHANGE J3900 FROM 514S0143 TO 514-0443.
- EDIT BOM OPTION TABLE.
CSA PAGE 46:
- CHANGE U4600 FROM 353S1245 TO 353S1728.
- REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B.
- ADD NOSTUFF R4660 AND R4661.
CSA PAGE 47:
- CHANGE J4700 FROM 516S0251 TO 516S0588.
CSA PAGE 69:
- REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR.
CSA PAGE 94:
- 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348.
7/5/2006
CSA PAGE 4:
- REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS).
CSA PAGE 21:
- CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE.
CSA PAGE 27:
- CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE.
CSA PAGE 28:
CSA PAGE 46:
- REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS).
CSA PAGE 48:
CSA PAGE 55:
- CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT.
- J5550 CHANGES FROM 2PIN TO 4PIN.
CSA PAGE 56:
CSA PAGE 67:
CSA PAGE 90:
7/6/2006
CSA PAGE 8:
- REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS.
- REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN.
- ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N.
- ADD FUNC_TEST=TRUE FOR PP1V05_S0_R.
CSA PAGE 9:
- REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN.
- REMOVE ALIAS FOR =FWPWR_PWRON.
- ADD SPN ALIASES FOR TP_CK505_SRC7_N/P.
- ADD SPN ALIASES FOR CK505_PCI2/4_CLK.
CSA PAGE 12:
- REMOVE R1290 TO R1296 ON CPU_VID<0:6>.
CSA PAGE 13:
- DELETE TEXT NOTE AND WITH RESET BUTTON.
CSA PAGE 15:
- RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L.
CSA PAGE 25:
- ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L).
- CHANGE R2514 TO 100K.
CSA PAGE 29:
- CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907.
- NOSTUFF C2907, C2910, C2916, C2911, C2914.
- CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM.
- CHANGE R2902 FROM 1OHM TO 0OHM.
CSA PAGE 44:
- REMOVE TEXT NOTE WILL CHANGE TO 606P.
CSA PAGE 53:
- RE-DRAW CPU VOLTAGE SENSE RC FILTERING.
CSA PAGE 62:
- RE-CONNECTED /SHDN INPUT OF U6801 SO THAT ITS CONTROLLED BY U6200 PORTA VREF. - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN.
- ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1.
- ADDED SMALL 15PF COMPENSATION CAP. TO U6201 FEEDBACK NETWORK (C6224).
CSA PAGE 67:
- CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES).
- ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER.
- REMOVED DZ6772.
- ADDED R6740 NO STUFF.
CSA PAGE 68:
- CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854.
- ADDED R6856 NO STUFF.
CSA PAGE 71:
- RENAME CPU_VID_R<6:0> TO CPU_VID<6:0>.
7/13/2007
CSA PAGE 4:
- CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ).
CSA PAGE 38:
- CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DONT NEED LOW-PROFILE PARTS).
M70 DVT TO K36 CHANGES
7/12/2007
CSA PAGE 43:
- CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC).
- UPDATE BOM OPTION TABLE FOR J4300.
- NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476.
CSA PAGE 46:
- CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN).
- UPDATE BOM OPTION TABLE FOR J4600 AND J4601.
CSA PAGE 62:
- ADD PAGE_TITLE AUDIO: CODEC.
CSA PAGE 67:
- CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN).
- CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN).
CSA PAGE 79:
- CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL.
CSA PAGE 94:
3/14/2007
CSA PAGE 47:
- ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY.
CSA PAGE 69:
- ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY.
CSA PAGE 90:
- DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH.
CSA PAGE 94:
- ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY.
7/11/2007
CSA PAGE 9:
- CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED).
CSA PAGE 31:
- STUFF C3110 AND C3111.
CSA PAGE 32:
- STUFF C3210 AND C3211.
CSA PAGE 39:
- UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475.
CSA PAGE 50:
- REMOVE R5077 (BECOMES R5931).
CSA PAGE 59:
- ADD R5930, 10K PU ON SMC_SMS_INT.
- ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT.
- STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT.
3/5/2007
CSA PAGE 8:
- 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS.
CSA PAGE 34:
- 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN.
- 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL.
CSA PAGE 49:
- 5040728 STUFF C9421 FOR EMI.
CSA PAGE 62,66,67,68:
- SYNC FROM AUDIO TEAM.
CSA PAGE 67:
- 4999533 SWAP PIN 2 AND PIN 3 OF MIC CONNECTOR, BACK TO M42 PIN OUT.
CSA PAGE 79:
- 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558.
7/10/2007
CSA PAGE 4:
- BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196.
- SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198.
- UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST.
CSA PAGE 8:
- ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3.
CSA PAGE 29:
- ADD CRITICAL TO U2900.
CSA PAGE 44:
- ADD CRITICAL TO U4401.
CSA PAGE 46:
- CHANGE U4675 FROM APN 353S1505 TO APN 353S1742. (SMALL PACKAGE)
- ADD R4670 & R4671. (USB BYPASS ROUTING).
CSA PAGE 49:
- REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT.
CSA PAGE 50:
- CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT.
CSA PAGE 52:
- ICH8-M ME SMBUS:
- SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.B
- THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE.
- SMC MANAGEMENT SMBUS CONNECTION:
- ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.B
- THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER.
CSA PAGE 59:
-ADD 2ND SMS (U5930).
CSA PAGE 62:
- CHANGED C6210 FROM A CASE-R 10UF TANT. CAP. TO A SMA-LF 3.3UF TANT. CAP.
- MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200.
CSA PAGE 67:
- REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732. ALSO REMOVED L6774.
- STUFFED R6740.
- MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771B CRITICAL.
CSA PAGE 68:
- NO STUFFED R6854
CSA PAGE 72:
- CHANGE R7208 FROM 8.66K TO 15.8K.
M70 PROTO TO EVT CHANGES
7/24/2007
CSA PAGE 4:
- CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500).
CSA PAGE 22:
- STUFF R2242 AND NOSTUFF R2247.
CSA PAGE 92:
- CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K.
- CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K.
M70 EVT TO DVT CHANGES

8/9/2007
PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS.
- ALL 128S0057 BECOME 128S0147.
- ALL 128S0073 BECOME 128S0164.
- ALL 128S0085 BECOME 128S0148.
- ALL 128S0111 BECOME 128S0169.
- ALL 128S0113 BECOME 128S0160.
- ALL 128S0115 BECOME 128S0150.
- ALL 128S0122 BECOME 128S0157.
- ALL 128S0123 BECOME 128S0162.
- ALL 128S0129 BECOME 128S0135.
- ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER.
CSA PAGE 4:
- ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS.
Revision History
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
76
01
Functional Test Points

Power Supply NO_TESTs
Fan Connectors
NO_TEST
IMVP6_RBIAS
IMVP6_COMP
5VS5_RUNSS
1V5S0_RUNSS
I93
I94
I95
I96
59A4 59B7
59A4 59B7
I12
I15
63B5 65C5
I16
58B1 61B5
I157
I158
I159
FUNC_TEST
=PP5V_S0_FAN_RT
TRUE
FAN_RT_PWM
TRUE
FAN_RT_TACH
TRUE
=PP3V3_S0_FAN_RT
TRUE
SMC_FAN_1_CTL
TRUE
SMC_FAN_1_TACH
TRUE
Battery Digital Connector

7A7 50C4
I1
50B3
I3
50C3
I4
CLOCK NO_TESTS
I111
I112
I113
I115
I114
I116
I117
I118
I119
I120
I122
NO_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I19
I18
CK505_CPU0_N
CK505_CPU0_P
CK505_CPU1_N
CK505_CPU1_P
CK505_CPU2_ITP_SRC10_N
CK505_CPU2_ITP_SRC10_P
CK505_DOT96_27M_N
CK505_DOT96_27M_P
CK505_LVDS_N
CK505_LVDS_P
I17
28C4 29D6 75D3
I71
28C4 29D6 75D3
I72
28C4 29D6 75D3
I73
28C4 29D6 75D3
I74
28C4 29D6 75D3
I75
28C4 29D6 75D3
I76
28A4 29B6 75D3
I77
28A4 29B6 75D3
I78
28B4 29C6 75C3
I79
28B4 29C6 75D3
CK505_PCIF1_CLK
I80
I81
28B6 29B6 75D3
I82
I83
I125
I183
TRUE
TRUE
CK505_SRC2_N
CK505_SRC2_P
I84
28B4 29C6 75C3
I85
28B4 29C6 75C3
I86
I87
I186
I187
I188
I189
I190
I191
I194
I195
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
CK505_SRC4_N
CK505_SRC4_P
CK505_SRC5_N
CK505_SRC5_P
CK505_SRC6_N
CK505_SRC6_P
CK505_SRC8_N
CK505_SRC8_P
I88
28B4 29C6 75C3
I89
28B4 29C6 75C3
I91
28B4 29C6 75C3
I90
44A8 50B4
I177
44A8 50C4
I180
28B4 29C6 75C3
28A4 29B6 75C3
I201
I202
I203
I204
I205
I206
I207
I208
FW_B_TPA_N_SPN
FW_B_TPA_P_SPN
FW_B_TPBIAS_SPN
FW_B_TPB_N_SPN
FW_B_TPB_P_SPN
FW_C_TPA_N_SPN
FW_C_TPA_P_SPN
FW_C_TPBIAS_SPN
FW_C_TPB_N_SPN
FW_C_TPB_P_SPN
I92
I152
8D1
I155
8D1
8D1
8D1
I153
8D1
I154
8D1
I156
8D1
8D1
8D1
I160
8D1
I161
LVDS NO_TESTS
I209
I210
I211
I212
I213
I214
I215
NO_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I244
I162
I163
LVDS_B_CLK_N_SPN
LVDS_B_CLK_P_SPN
LVDS_B_DATA_N0_SPN
LVDS_B_DATA_N1_SPN
LVDS_B_DATA_N2_SPN
LVDS_B_DATA_P1_SPN
LVDS_B_DATA_P2_SPN
I164
8D5
I169
8D5
I166
8D5
I167
8D5
I168
8D5
I174
8D5
I171
I173
I175
I176
I178
I181
I223
I236
NO_TEST
TRUE
I11
7B1 46C6
7A7 46C6
22D4 44C8 46C6

22D4 44C8 46C6
22D4 44C8 46B6

24C8 37A5 44C5 46B6
23B5 46B6
I10
I21
I22
I24
I23
I25
I45
44B5 45C5 46B6

27D1 46B6
I29
44C1 46B6
I32
44B5 45C5 46B6
I31
44D1 46B6
I33
41A8 44B8 44C5 45D5

46B6
I36
46C5
I38
BATT_POS
BATT_NEG
TRUE
TRUE
57A5
57B5
57A5
Audio FUNC_TEST
=PP5V_S0_AUDIO_AMP
TRUE
=PP5V_S0_AUDIO
TRUE
GND_AUDIO_AMP
TRUE
GND_AUDIO_CODEC
TRUE
ACZ_SDATAIN<0>
TRUE
ACZ_SDATAOUT
TRUE
ACZ_BITCLK
TRUE
ACZ_RST_L
TRUE
ACZ_SYNC
TRUE
Battery FUNC_TEST
SMC_BATT_ISET
TRUE
SMC_BATT_CHG_EN
TRUE
SMC_BC_ACOK
TRUE
SMC_ADAPTER_EN
TRUE
SMC_BATT_TRICKLE_EN_L
TRUE
SYS_ONEWIRE
TRUE
7A7 54B8 54C8 54D8

7A7 53A7 56C4
8A4
8B4
8A5 53C7
8A5 53C7
8A5 53C7
8A5 53B7
8A5 53C7
44B5 66A8
44C8 45B6 66A4
66A6
44C5 45B6 57C3
57C7
45B3 57C4
33C7 35C7 38C6
44D5
44C8 45B6
66A3
44B8 45D5 57C8
29B3 46C4 75C3

22D4 44C8 46C4
22D4 44C8 46C4
24C8 44C8 46B4

24D5 44C5 46B4
44B5 45C5 46B4
44B5 45C5 46B4
44C3 45D7 46B4

44C1 46B4
41A8 44B8 44C5 45D5

46B4
I44
I47
I46
I48
I224
I225
I240
I241
USB FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TP_USB_EXCARD_P
TP_USB_EXCARD_N
TP_USB_EXTC_P
TP_USB_EXTC_N
USB2_BT_F_P
USB2_BT_F_N
USB2_3G_F_N
USB2_3G_F_P
8B2
8B2
8B2
8B2
43C2
43C2
43A4
43A4
24A7 24D5 46B4
FUNC_TEST
=PP1V05_S0_REG
TRUE
I57
DC-JACK FUNC_TEST
ACIN_ENABLE_GATE
TRUE
I58
Battery charger FUNC_TEST

PPVBAT_G3H_CHGR_OUT
TRUE
7D8 61B8
SMBus FUNC_TEST
SMBUS_SMC_B_S0_SCL
TRUE
SMBUS_SMC_B_S0_SDA
TRUE
FIREWIRE FUNC_TEST
PPFW_SWITCH
TRUE
SLEEP LED FUNC_TEST
SYS_LED_ANODE
TRUE
SMC FUNC_TEST
SMC_LID
TRUE
SMC_MANUAL_RST_L
TRUE
SMC_CPU_VSENSE
TRUE
Power Supply FUNC_TEST
ALL_SYS_PWRGD
TRUE
PPVCORE_S0_CPU
TRUE
PP1V05_S0_R
TRUE
PP1V05_S0
TRUE
PP1V5_S0
TRUE
PP1V8_S0
TRUE
PP3V3_S0
TRUE
PP5V_S0
TRUE
PP1V2_ENET_S0
TRUE
PP1V8_S3
TRUE
47C5 76C3
47C5 76C3
I60
I59
I61
38D3
I63
40C5 45A3
I221
I220
42C3 44B5 45C5 57A8
I222
45D8
I238
44C5 48B1
I237
I239
27A5 44D8 58A3
7D7
7D7
I227
7D7 45D2
I226
7C7
I228
7B7
I230
7D4 45D1
I229
7A7
I231
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S3
PP5V_S3
PP3V3_S5
PP5V_S5
PP3V42_G3H
PPBUS_G3H
TRUE
TRUE
TRUE
TRUE
PP18V5_G3H
PP0V9_S0
PP3V3_S3_BT_F
GND_BT_F
INVERTER
TRUE
TRUE
TRUE
TRUE
57C3 66A6
66B5 66C2
CONNECTOR FUNC_TEST
PPBUS_ALL_INV_CONN
INV_GND
PP5V_INV_F
INV_BKLIGHT_PWM_L
67D3
67D2
67D3
67D2
MIC FUNC_TEST
MIC_HI
TRUE
MIC_LO
TRUE
MIC_SHIELD
TRUE
MIC_HI_CONN
TRUE
MIC_LO_CONN
TRUE
MIC_SHLD_CONN
TRUE
55B3 56A6
55B3 56A6
B
55B1 55D3
55B1 55D3
55A1 55D3 56A6
SPEAKER FUNC_TEST
SPKRCONN_L_N_OUT
TRUE
SPKRCONN_L_P_OUT
TRUE
SPKRCONN_R_N_OUT
TRUE
SPKRCONN_R_P_OUT
TRUE
SPKRCONN_SUB_N_OUT
TRUE
SPKRCONN_SUB_P_OUT
TRUE
54C1 55C2
54C1 55C2
54C1 55C2
54D1 55C2
54B1 55C2
54B1 55C2
7B5
7B4
8D5
I172
I219
I9
28A4 29B6 75C3
FIREWARE NO_TESTS
I200
FUNC_TEST
=PP3V42_G3H_LPCPLUS
TRUE
=PP5V_S0_LPCPLUS
TRUE
LPC_AD<0>
TRUE
LPC_AD<1>
TRUE
LPC_FRAME_L
TRUE
PM_CLKRUN_L
TRUE
BOOT_LPC_SPI_L
TRUE
SMC_TMS
TRUE
DEBUG_RESET_L
TRUE
SMC_TRST_L
TRUE
SMC_TDO
TRUE
SMC_MD1
TRUE
SMC_TX_L
TRUE
FWH_INIT_L
TRUE
PCI_CLK33M_LPCPLUS
TRUE
LPC_AD<2>
TRUE
LPC_AD<3>
TRUE
INT_SERIRQ
TRUE
PM_SUS_STAT_L
TRUE
SMC_TDI
TRUE
SMC_TCK
TRUE
SMC_RESET_L
TRUE
SMC_NMI
TRUE
SMC_RX_L
TRUE
LINDACARD_GPIO
TRUE
Other Func Test Points
28B4 29B6 75C3
I151
I199
57A5
28B4 29C6 75C3
I182
NO_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
44C5 45C5 57A2
7C4 50C4

I20
FUNC_TEST
SMC_BS_ALRT_L
TRUE
SMBUS_BATT_SCL_F
TRUE
SMBUS_BATT_SDA_F
TRUE
7A4
I232
7A4
I233
7D1
I234
7C1
I235
7C1
I242
7B1
I243
THERMAL FUNC_TEST
THRM_HEATPIPE_P
TRUE
THRM_HEATPIPE_N
TRUE
THRM_DIMM_DX_F_N
TRUE
THRM_DIMM_DX_F_P
TRUE
THRM_FINSTACK_P
TRUE
THRM_FINSTACK_N
TRUE
7B1
49D6
49D6
49B6
49B6
49C6
49C6
FUNC TEST 1 OF 2
7D7
43D2
43C2

SMC_FAN_3_TACH

44A4 44A8

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
76
01
"S0,S0M" RAILS
58D3 58C4 58C3 58B8 58B3 58A3
=PP3V3_S0_FET
PP3V3_S0
=PPVORE_S0_CPU_REG
(CPU VCOR PWRE)
(REGULATOR OUTPUT CPU 0.90V PWR)
62B8
=PP0V9_S0_REG
(DDR2 TERMINATION 0.9V PWR)
PPVCORE_S0_CPU
=PPVCORE_S0_CPU
PP0V9_S0
=PP1V05_S0_REG
=PP3V3_S0_NB_VCCHV
=PP3V3_S0_NB_FOLLOW
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_VCCGLAN3_3
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_VCCPCORE
=PP3V3_S0_SB_VCC3_3_SATA
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3_S0_SB
=PP3V3_S0_SB_PM
=PP3V3_S0_RSTBUF
=PP3V3_S0_AIRPORT
=PP3V3_S0_FW
=PP3V3_S0_PATA
10B5 10D7 11D7 48B3 48B5
6A2
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PP0V9_S3M_MEM_TERM
61B8 6B2
6B2
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE
PP1V05_S0
32D4
6B2 45D2
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_SB_CPU_IO
=PPVCORE_S0_SB
61C7
=PP1V05_S0_REG_R
PP1V05_S0_R
22D2 25C3 26C4
25D3 26D2
=PP3V3_S0_SMC_LS
6B2
=PP1V05_S0_CPU
=PP1V05_S0_NB_PCIE
=PPVCORE_S0_NB
=PP1V25R1V05_S0_FSB_NB
=PP1V25R1V05_S0_NB_VTT
=PP1V05_S0M_NB_VCCAXM
64B2
=PP1V25_S0_REG
9B5 9B6 9C5 9D5 10C7 11A3 12B3 12C5

20D5
17D3 17D7 20B4 20D8
13B7 29B6 29C6
18D3 20C8
17B3 17C1 20D8
PP1V25_S0
=PP1V25_S0_NB_PLL
=PP1V25_S0_NB_VCCDMI
=PP1V25_S0_SB_DMI
=PP1V25_S0_NB_VCCAXF
=PP1V25_S0_NB_PLL
=PP1V25_S0_NB_VCC
=PP1V25_S0_NB_VCCA
=PP1V25_S0_FET
62C5 61B1
=PP1V5_S0_REG
PP1V5_S0
18C3 20A8
6B2
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_CPU
10B7 11B3
=PP1V5_S0_NB_TVDAC
21D8
=PP1V5_S0_SB
26A8 26C8 26D6
=PP1V5_S0_SB_VCC1_5_A_ARX
25B6 26D5
=PP1V5_S0_SB_VCC1_5_A_ATX
25B6 26C6
=PP1V5_S0_SB_VCC1_5_A
25B6 26C2
=PP1V5_S0_SB_VCCUSBPLL
25A6 26B6
=PP1V5_S0_SB_VCC1_5_A_USB_CORE 25B6 26C2
=PP1V5_S0_AIRPORT
33D2
=PP1V5_S0_NB_FOLLOW
21D5
35C1
=PP1V2_ENET_REG
PP1V2_ENET_S0
6A2
35D1 35B2
25C3 26A6 26C6

25C3 26B8
25C3 26A8
26D8 39C8
27B6 27B8
27D4
35D4
=PP3V3_ENET_PHY
PP3V3_ENET_FET
VOLTAGE=3.3V
MAKE_BASE=TRUE
38C6
=PP3V3_S5_SMBUS_SB_ME
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_SB_CLINK1
=PP3V3_S5_1V25S0
=PP3V3_S5_AIRPORT_AUX
39C2
63B8
=PP1V8_S0_FET
PP1V8_S0
=PPVCORE_S0_NB_GFX_IMVP
21C5
=PP1V8_S3_REG
62B2
60C7
60C2 61C5 66C3
7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C2 69C8
25A3 26B6 26D2

25B3 26B2
38A6 38A8
67C7
64B6
33C7 33D6 33D7
6A2
26D8
39D6
41C8
61C4
62C5
=PP5V_S5_PWRCTL
=PP5V_S5_FET
48D2
65B6
58B3 58C6 58D5 65B5
66B3
25B3 26C4
23A3
18C6 20A6
"G3H" RAILS
30A7 31A3 31A7

25A6 26B2
25A3 26D3
24C1
64C4
=PP3V42_G3H_REG
PP3V42_G3H
6A2
VOLTAGE=3.42V
MAKE_BASE=TRUE
28C8 28D3 28D8 29B2 29D2

18D6 21B5
69C8
=PP3V42_G3H_SMC
7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C2 69C8
=PP1V9_ENET_REG
PP1V9_ENET_S0
=PP1V8_S0_YUKON
34D6
36D8
=PP1V8R2V5_ENET_PHY
44D4 45C1 45D4 45D8 51B8
=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_ACIN
=PP3V42_G3H_LIDSWITCH
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LPCPLUS
VOLTAGE=2.5V
MAKE_BASE=TRUE
34C7
34D6
=PP18V5_G3H_INRUSH
PP18V5_G3H
45C8
47C3
57C4 66A5 66A8 66B8
57A8
65C7
27D7
41A6
6D2 46C6
6A2
=PP18V5_G3H_CHGR
VOLTAGE=18.5V
MAKE_BASE=TRUE
20A5 20A6
=PP1V8_S3_REG_R
=PP3V3_S3_FET
=PPBUSA_G3H
PPBUS_G3H
6A2
VOLTAGE=18.5V
MAKE_BASE=TRUE
35C3
PP1V8_S3_MEM_NB
66C2
=PPBUSB_G3H
43B5
6D2 46C6
48B8
6D2 50C4
6D1 53A7 56C4
6D1 54B8 54C8 54D8
6A2
67D4
62B3
63A6 63B6
63B3
61B3
61B5
45A6
33C2
37D5
37C5
43D3
51C7
47D3
62A2 62C2
Power Aliases
35D7
47C3 51B6
SYNC_MASTER=WFERRY
35D3
59D8
60D2

67D7
69D7
21D6
65B4
=PP5V_S3_FET
PP5V_S3
6A2
VOLTAGE=5V
MAKE_BASE=TRUE
39B7

=PP5V_S3_SYSLED
=PP5V_S3_GEYSER
=PP5V_S3_IR
=PP5V_S3_CAMERA
40B6 45A4
SIZE
42D6
43D8
APPLE INC.
67A5
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
60C2
=PPVIN_S5_1V8S30V9S0
=PPVIN_S5_5VS5
=PPVIN_S5_3V3S5
=PPVIN_S5_1V5S0
=PPVIN_S5_1V05S0
=PPVIN_S5_IMVP
20A4
=PP3V3_S3_FW
=PP3V3_S3_PCI
=PP3V3_S3_BT
=PP3V3_S3_SMS
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
=PP3V3_S3_ENETPWRCTL
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_ENET_P3V3ENETFET
40C6
48D7 59C2 59D4 59D8
=PPBUS_S5_INV
VOLTAGE=3.3V
MAKE_BASE=TRUE
26D8
38D5
=PPVIN_S5_CPU_IMVP
=PPVIN_S5_NB_GFX_IMVP
15D2 17D7 20C8 30D2 31D2
PP3V3_S3
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_LCD
=PP5V_S0_TMDS
=PP5V_S0_NB_TVDAC
=PP5V_S0_IDE_RESET
66C2
30B2 30D4 30D6 31B2 31D4 31D6
=PPVIN_S0_NB_DPLL
=PPBUS_S5_FWPWRSW
6A2
=PP5V_S0_CPU_IMVP
=PP5V_S0_NB_GFX_IMVP
B
64C6
58C5
17B7 17D5 21C5 48B3
65C3 65A4
=PP5V_S0_SB
=PP5V_S0_SATA
=PP5V_S0_3G
=PP5V_S0_LPCPLUS
=PP5V_S0_ISENSECAL
=PP5V_S0_FAN_RT
=PP5V_S0_AUDIO
=PP5V_S0_AUDIO_AMP
66D8
PPDCIN_G3H
=PPVIN_G3H_P3V42G3H
=PP1V8_S3_FET
=PP1V8_S3_MEMVREF
=PP1V8_S3_MEM
=PP1V8_S3M_MEM_NB
=PP1V8_S3_NB_VCC
PP5V_S0
=PPDCIN_G3H
6A2
VOLTAGE=1.8V
MAKE_BASE=TRUE
25A3 26D2
24B1
=PP5V_S5_1V51V05S0
=PP5V_S5_1V8S30V9S0
67B5 67B7 67C6
PP1V8_S3
68D6
62C4
58C5 65A5 65C4
52C6
=PP5V_S5_SB
=PP5V_S5_PATA
=PP5V_S5_USB
59D8
VOLTAGE=1.8V
MAKE_BASE=TRUE
21A7
PPVCORE_S0_NB_GFX
=PPVCORE_S0_NB_GFX
=PP5V_S0_FET
24A3 24A8 26D8 35C7
47A7
PP5V_S5
53A7 53D7 55D8 56B5
57D3
VOLTAGE=1.25V
MAKE_BASE=TRUE
58D4 58C8
24D8
VOLTAGE=5V
MAKE_BASE=TRUE
"S3" RAILS
6B2
=PP1V8_S0_NB_LVDS
=PP1V8_S0_NB_DPLL
=PP1V8_S0_TMDS
60C2
23C8
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP5V_S5_REG
8A4
57D1
58C4 58B8
27C5
33C6
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PP1V2_ENET_PHY
=PP3V3_S5_SB_PM
=PP3V3_S5_SB_USB
=PP3V3_S5_SB_GPIO
=PP3V3_S5_SB
=PP3V3_S5_FET
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S5_FWLATEVG
25B3 26B4
25C3 26B4
6D2 50C4
=PP3V3_S0_SB_PCI
58A3
25A6
49C2 49D2
=PP3V3_S0_NB_VCCA_PEG_BG
=PPSPD_S0_MEM
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PP3V3_S0MWOL_SB_CLINK0
=PP3V3_S0_CK505
=PP3V3_S0_NB_VCCSYNC
=PP3V3_S0_NB
=PP3V3_S0_TMDS
20B8
6A2
47C5
20D4
20A8
PP3V3_S5
VOLTAGE=3.3V
MAKE_BASE=TRUE
47D5
25C3 26A6
7C7 20B4 20D3
=PP3V3_S5_REG
22D2 22D7 24B3 24D8
47D8
=PP3V3_S0_PDCISENS
=PP3V3_S0_LCD
=PP3V3_S0_TMDS
=PP3V3_S0_CPUPOWER
=PP3V3_S0_PBATTISENS
=PP3V3R1V5_S0_SB_VCCHDA
7C7 20B4 20D3
63B1
20B2
46C4
=PP3V3_S0_IMVP
=PP3V3_S0_NB_GFX_IMVP
VOLTAGE=1.25V
MAKE_BASE=TRUE
15B7 15C7 18B3 20A8 21B7
45D4
=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMBUS_SB
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_THRM_SNR
=PP3V3_S0_FAN_RT
=PP3V3_S0_ENET
=PP3V3_S0_AUDIO
VOLTAGE=1.05V
MAKE_BASE=TRUE
"S5" RAILS
6A2 45D1
VOLTAGE=3.3V
MAKE_BASE=TRUE
(REGULATOR OUTPUT CPU VCORE PWR)

59D1
OF
76
01
(EMI PAD FOR INVERTER GONNECTOR)
LVDS ALIASES
67C2
INVT_CHGND
ZS0920
1 EMI-SPRING
VOLTAGE=0V
MAKE_BASE=TRUE
43B5 43A5
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
14C5
=GND_CHASSIS_3GPOWER
14C5
14C5
CHASSIS GND
14C5
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND
14C5
TP_LVDS_B_DATAN3
15C6
OMIT
GND_CHASSIS_IO Z0906
5R2P3-7SQBNP
=GND_BATT_CHGND
=GND_CHASSIS_AUDIO_JACK
57A6
55C3
30A5
LVDS_B_CLK_N_SPN
6A7
LVDS_B_CLK_P_SPNMAKE_BASE=TRUE
6A7
MAKE_BASE=TRUE
LVDS_B_DATA_N0_SPN
6A7
MAKE_BASE=TRUE
LVDS_B_DATA_N1_SPN
6A7
MAKE_BASE=TRUE
LVDS_B_DATA_N2_SPN
6A7
MAKE_BASE=TRUE
LVDS_B_DATA_N3_SPN
22B6
22B6
22B6
22B6
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
TP_LVDS_B_DATAP3
LVDS_B_DATA_P0_SPN
MAKE_BASE=TRUE
LVDS_B_DATA_P1_SPN
6A7
MAKE_BASE=TRUE
LVDS_B_DATA_P2_SPN
6A7
MAKE_BASE=TRUE
LVDS_B_DATA_P3_SPN
TP_LVDS_A_DATAP3
TP_LVDS_A_DATAN3
LVDS_A_DATA_P3_SPN
MAKE_BASE=TRUE
LVDS_A_DATA_N3_SPN
14C5
14C5
15C6
22B6
22B6
22B6
15C6
SATA,LVDS CONNECTOR CHASSIS GND

GND_CHASSIS_SATA
OMIT
Z0907
40C8
VOLTAGE=0V
MAKE_BASE=TRUE
=GND_CHASSIS_LVDS
6P5R2P6-7SQB
1
14D3
14D3
14D3
14D3
14D3
1 C0908
C0907
0.1UF
0.01UF
14D3
10%
10%
16V
2 X5R
402
14D3
2 16V
CERM
14D3
402
14D3
14C3
DCIN CONNECTOR CHASSIS GND OMIT
GND_CHASSIS_DCIN Z0902
VOLTAGE=0V
MAKE_BASE=TRUE
57C8
=GND_DCIN_CHGND
36B2
=GND_CHASSIS_RJ45
7X7R2P3-5B
14C3
14C3
14C3
14C3
14C3
69C4 69A4
C0930
14C3
0.1UF
=GND_CHASSIS_TMDS_UPPER
14C3
10%
16V
2 X5R
402
14C3
14C3
14C3
14C3
I/O CONNECTOR CHASSIS GND OMIT

GND_CHASSIS_IO
Z0908
8D7
VOLTAGE=0V
MAKE_BASE=TRUE
5P0R2P3-7BLB
1
38B1
41C4 41C2 41A4 41A2
=GND_CHASSIS_FW_DOWN
=GND_CHASSIS_USB
1 C0911
C0910
0.1UF
0.01UF
10%
2 16V
X5R
402
14C3
14C3
14C3
14C3
14C3
14C3
10%
2 16V
CERM
402
14C3
14C3
14C3
DIP DIMM CONNECTOR CHASSIS GND
OMIT
GND_CHASSIS_CENTER Z0910
VOLTAGE=0V
5R2P3-7SQB
MAKE_BASE=TRUE
31A5 30D5
=GND_CHASSIS_DIPDIMM_CENTER
C0916 1 C0917
0.01UF
10%
0.1UF
10%
2 16V
CERM
2 16V
X5R
402
402
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
DIP DIMM CONNECTOR CHASSIS GND
14B3
OMIT
GND_CHASSIS_RIGHT Z0909
VOLTAGE=0V
5R2P3-7SQB
MAKE_BASE=TRUE
31D4
=GND_CHASSIS_DIPDIMM_RIGHT
14B3
14B3
0.01UF
10%
0.1UF
14B3
14B3
C0914 1 C0915
10%
16V
2 X5R
402
14B3
14B3
2 16V
CERM
14B3
402
14B3
14B3
OMIT
OMIT
Z0901
Z0911
5R2P3-7SQBNP
5R2P3-7B
1
1
GND_CHASSIS_CPU
GND_CHASSIS_FANSCREW
14B3
14A3
14A3
14A3
14A3
1 C0913
C0912
0.1UF
0.01UF
10%
10%
2 16V
X5R
402
C0918
0.1UF
10%
2 16V
X5R
402
2 16V
CERM
402
0.01UF
10%
73C3 22C8
402
73C3 22C8
73C3 22C8
CPU HEATSINK STANDOFF SCREW HOLE

Z0903
NB_RIGHT_DOWN_SCREW 1
R0912
1/16W
MF-LF
2402
73B3 22B8
TP_PCIE_A_D2R_N
23D5 TP_PCIE_A_D2R_P
23D5 TP_PCIE_A_R2D_C_N
23D5
Z0904
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
STDOFF-4.2OD3.95H-5.52R3.37-7SQB
22C8
R0910
TP_HDA_SDIN3
15B6
OMIT
Z0921
15B6
15B6
15B6
15B6
NB_CFG<3>
NB_CFG<4>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
TP_NB_CFG<3>
TP_NB_CFG<4>
TP_NB_CFG<6>
TP_NB_CFG<7>
TP_NB_CFG<8>
R0921
R0911
28B4
28B4
28B4
28B4
75D3 28B6
75D3 28B6
34B8 28A4
USB_EXTA_P 23C2 73B3

USB_EXTA_N 23C2 73B3
USB_EXTA_OC_L 23C8
MAKE_BASE=TRUE
USB PORT [1] = PCI-E Mini Card

33B3 =USB2_AIRPORT_P
USB2_AIRPORT_P
33B3 =USB2_AIRPORT_N
USB2_AIRPORT_N
MAKE_BASE=TRUE
23C2 73B3
USB_MINI_N
23C2 73B3
USB PORT [2] = 3G USB

=USB2_3G_P
=USB2_3G_N
43A4
USB2_3G_P
USB_EXTD_P 23C2
USB2_3G_N MAKE_BASE=TRUE USB_EXTD_N 23C2
43A4
MAKE_BASE=TRUE
USB PORT [3] = CAMERA
NO-CONNECT UNUSED CLOCK INTERFACE PORTS

TP_CK505_SRC1_N
CK505_SRC1_N_SPN
CK505_SRC1_P_SPN MAKE_BASE=TRUE
TP_CK505_SRC1_P
MAKE_BASE=TRUE
CK505_SRC3_N_SPN
TP_CK505_SRC3_N
TP_CK505_SRC3_P
CK505_SRC3_P_SPN MAKE_BASE=TRUE
TP_CK505_SRC7_N
CK505_SRC7_N_SPN MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CK505_SRC7_P
CK505_SRC7_P_SPN
MAKE_BASE=TRUE
CK505_PCI2_CLK
CK505_PCI2_CLK_SPN
MAKE_BASE=TRUE
CK505_PCI4_CLK
CK505_PCI4_CLK_SPN
MAKE_BASE=TRUE
ENET_CLKREQ_L
=ENET_CLKREQ_L
67B4 =USB2_CAMERA_P
USB2_CAMERA_P
67A4 =USB2_CAMERA_N
USB2_CAMERA_N
MAKE_BASE=TRUE
USB_CAMERA_P
23C2 73B3
USB_CAMERA_N
23C2 73B3
MAKE_BASE=TRUE
USB PORT [4] = IR CONTROLLER

73B3 23C2
8C1
=USB2_IR_P
43C4 =USB2_IR_N
43C4
USB_IR_P
USB_IR_N
USB_IR_P
USB_IR_N
MAKE_BASE=TRUE
8C2 23C2 73B3

8C2 23C2 73B3
MAKE_BASE=TRUE
USB PORT [5] = Trackpad(Geyser)

42C7 =USB2_GEYSER_P
USB2_GEYSER_P
42C7 =USB2_GEYSER_N
USB2_GEYSER_N
USB_TPAD_P
USB_TPAD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
23C2 73B3
23C2 73B3
MAKE_BASE=TRUE
USB PORT [6] = BLUETOOTH

73B3 23C2
8C1
43C3 =USB2_BT_P
SB ALIASES
MAKE_BASE=TRUE
USB_BT_N
VR_PWRGD_CLKEN
=SB_CLINK_MPWROK
SB_SATA_CLKREQ_L
EXTGPU_RST_L
24C3
24C5
24C5 24B5
8C2 23C2 73B3

8B2 23C2 73B3
MAKE_BASE=TRUE
NO-CONNECT UNUSED CLOCK INTERFACE PORTS

24C5
USB_BT_P
USB_BT_N
USB_BT_P
43C3 =USB2_BT_N
USB PORT [7] = External USB2.0 Port B
VR_PWRGD_CK505
27A8
MAKE_BASE=TRUE
CLINK_MPWROK
8B1 27A6
MAKE_BASE=TRUE
SB_CLK100M_SATA_OE_L
28B4
MAKE_BASE=TRUE
TP_SB_GPIO17
41B5 =USB2_EXTB_P
USB2_EXTB_P
41B5 =USB2_EXTB_N
USB2_EXTB_N
MAKE_BASE=TRUE
EXTBUSB_OC_L
USB_EXTB_P 23C2
USB_EXTB_N 23C2
USB_EXTB_OC_L
MAKE_BASE=TRUE
41C8 =EXTBUSB_OC_L
73B3
73B3
23C8
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB PORT [8] = Unused
SO-DIMM ALIASES
TP_USB_EXCARD_P
30C4
31C4
15C6
MEM_A_A<15>
MEM_B_A<15>
MAKE_BASE=TRUE
TP_MEM_CLKN2
15C6 TP_MEM_CLKP5
15C6 TP_MEM_CLKN5
15C6
TP_USB_EXCARD_N
6C1
MEM_A_A15_SPN
MEM_B_A15_SPN MAKE_BASE=TRUE
MEM_CLK_P_2_SPNMAKE_BASE=TRUE
MEM_CLK_N_2_SPNMAKE_BASE=TRUE
MEM_CLK_P_5_SPNMAKE_BASE=TRUE
MEM_CLK_N_5_SPNMAKE_BASE=TRUE
TP_MEM_CLKP2
USB_EXCARD_P
23C2 73B3
USB_EXCARD_N
23C2 73B3
6C1
NO-CONNECT UNUSED ADDRESS INTERFACE PORTS
MAKE_BASE=TRUE
USB PORT [9] = Unused
TP_USB_EXTC_P
USB_EXTC_P
23C2 73B3
USB_EXTC_N
23C2 73B3
6C1
MAKE_BASE=TRUE
TP_USB_EXTC_N
6C1
MAKE_BASE=TRUE
ANALOG SWITCH GPIO
MAKE_BASE=TRUE
44B8 15B7
44B8 15B7
PM_EXTTS_L<0>
MAKE_BASE=TRUE
PM_EXTTS_L<1>
DIMM_OVERTEMPA_L
30C4
DIMM_OVERTEMPB_L
31C4
MAKE_BASE=TRUE
NB ALIASES
56A8 56A4 55B3
53D3 53B7 53A7
54C8 54B8 54A8
56C4 56B8 56B5
54B8 54A8 54A5
=GND_AUDIO_CODEC
6D1
GND_AUDIO_CODEC
6D1
GND_AUDIO_AMP
NB_CLK96M_DOT_P
NB_CLK96M_DOT_N
NB_CLK100M_DPLLSS_P
NB_CLK100M_DPLLSS_N
15C3
XW0802
SM
2
MAKE_BASE=TRUE
60C6
CLINK_MPWROK
15A3
MAKE_BASE=TRUE
=GND_AUDIO_AMP
GFX_VR_EN
=GFX_VR_EN
=NB_CLINK_MPWROK
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
15C3
15C3 =NB_CLK100M_DPLLSS_P
15C3 =NB_CLK100M_DPLLSS_N
19D2 =NB_TDE_SENSE
15B3
XW0801
SM
MAKE_BASE=TRUE
8B3 27A6
MAKE_BASE=TRUE
29B3 75B3
MAKE_BASE=TRUE
29B3 75B3
MAKE_BASE=TRUE
29C3 75B3
MAKE_BASE=TRUE
29C3 75B3
MAKE_BASE=TRUE
6C1 53C7
MAKE_BASE=TRUE
6C1 53C7
MAKE_BASE=TRUE
Ethernet ALIASES
6C1 53B7
MAKE_BASE=TRUE
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
6D1 53C7
TABLE_5_ITEM
MAKE_BASE=TRUE
6D1 53C7
860-0876
THERMAL STANDOFF
Z0903,Z0904,Z0905,Z0921STANDOFF
860-0723
STANDOFF WIRELESS
Z0912
STANDOFF
860-0749
STANDOFF W/THRU HOLES,WIRELESS
Z0913
STANDOFF
TABLE_5_ITEM
7C4
=PP3V3_S0_ENET
=ENET_VMAIN_AVLBL
34C2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
34C7
=YUKON_EC_PP2V5_ENET
TABLE_5_ITEM
SIGNAL ALIAS /RESET

SYNC_MASTER=GPU
MAKE_BASE=TRUE
69A3
=GND_CHASSIS_TMDS_DOWN
38B1
=GND_CHASSIS_FW_UPPER
VOLTAGE=0V
MAKE_BASE=TRUE
AIRPORT CARD STANDOFF SCREW HOLE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
OMIT
OMIT
Z0912
Z0913
STDOFF-4.2OD2.15H-1.2-3.2-TH
STDOFF-4.2OD3.95H-5.52R3.37-6B
NC 1
NC
SIZE
D
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
USB_MINI_P
MAKE_BASE=TRUE
CLOCK ALIASES
28B4
USB2_EXTA_N
MAKE_BASE=TRUE
EXTAUSB_OC_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28B4
USB2_EXTA_P
41C8 =EXTAUSB_OC_L
=NB_TDE_FORCE
19C2 =NB_TDB_FORCE
19C2 =NB_TDB_SENSE
GND_CHASSIS_IO1
1/16W
MF-LF
2402
1/16W
MF-LF
2402
TP_PCIE_FW_D2R_N
23D5 TP_PCIE_FW_D2R_P
23D5 TP_PCIE_FW_R2D_C_N
23D5 TP_PCIE_FW_R2D_C_P
23D5
MAKE_BASE=TRUE
0
5%
0
5%
TP_PCIE_EXCARD_R2D_C_N
23D5 TP_PCIE_EXCARD_R2D_C_P
23D5
USB PORT [0] = External USB2.0 Port A

41A8 =USB2_EXTA_P
41A8 =USB2_EXTA_N
NB CFG ALIASES
Z0905
STDOFF-4.5OD3.95H-1.1-3.2-TH
STDOFF-4.5OD3.95H-1.1-3.2-TH
CPU_THERMAL_SCREW_RIGHT
MAKE_BASE=TRUE
PCIE_A_D2R_N_SPN
MAKE_BASE=TRUE
PCIE_A_D2R_P_SPN
MAKE_BASE=TRUE
PCIE_A_R2D_C_N_SPN
MAKE_BASE=TRUE
PCIE_A_R2D_C_P_SPN
PCIE_B_D2R_N_SPN MAKE_BASE=TRUE
PCIE_B_D2R_P_SPN MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_B_R2D_C_N_SPN
MAKE_BASE=TRUE
PCIE_B_R2D_C_P_SPN
PCIE_C_D2R_N_SPN MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_C_D2R_P_SPN
MAKE_BASE=TRUE
PCIE_C_R2D_C_N_SPN
MAKE_BASE=TRUE
PCIE_C_R2D_C_P_SPN
MAKE_BASE=TRUE
PCIE_D_D2R_N_SPN
PCIE_D_D2R_P_SPN MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_D_R2D_C_N_SPN
MAKE_BASE=TRUE
PCIE_D_R2D_C_P_SPN
MAKE_BASE=TRUE
Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

5%
1/16W
FOR LAYOUT PLACEMENT
MF-LF
402
2
BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL
CPU_THERMAL_SCREW_DOWN
1
ACZ_BITCLK
ACZ_SYNC
ACZ_RST_L
ACZ_SDATAIN<0>
ACZ_SDATAOUT
HDN_SDIN1_SPN
HDN_SPIN2_SPN
HDN_SPIN3_SPN
TP_HDA_SDIN1
22C8 TP_HDA_SDIN2
22C8
OMIT
TP_PCIE_A_R2D_C_P
TP_PCIE_B_D2R_N
23D5 TP_PCIE_B_D2R_P
23D5 TP_PCIE_B_R2D_C_N
23D5 TP_PCIE_B_R2D_C_P
23D5 TP_PCIE_EXCARD_D2R_N
23D5 TP_PCIE_EXCARD_D2R_P
23D5
23D5
MAKE_BASE=TRUE
CPU_THERMAL_SCREW_UP1
0
5%
73C3 22C8
OMIT
STDOFF-4.2OD3.95H-5.52R3.37-6B
SATA_C_D2R_N_SPN
MAKE_BASE=TRUE
SATA_C_D2R_P_SPN
MAKE_BASE=TRUE
SATA_C_R2D_C_N_SPN
MAKE_BASE=TRUE
SATA_C_R2D_C_P_SPN
19C2
2 16V
CERM
OMIT
37B3
PCI_EXP ALIASES
MAKE_BASE=TRUE
C0919
FW_B_TPBIAS_SPN
6B7
FW_B_TPA_P_SPNMAKE_BASE=TRUE
6B7
FW_B_TPA_N_SPNMAKE_BASE=TRUE
6B7
MAKE_BASE=TRUE
FW_B_TPB_P_SPN
6B7
FW_B_TPB_N_SPNMAKE_BASE=TRUE
6B7
MAKE_BASE=TRUE
FW_C_TPBIAS_SPN
6B7
FW_C_TPA_P_SPNMAKE_BASE=TRUE
6B7
MAKE_BASE=TRUE
FW_C_TPA_N_SPN
6B7
FW_C_TPB_P_SPNMAKE_BASE=TRUE
6B7
FW_C_TPB_N_SPNMAKE_BASE=TRUE
6B7
FW_B_TPBIAS
FW_B_TPA_P
FW_B_TPA_N
37B3 FW_B_TPB_P
37B3 FW_B_TPB_N
37B3 FW_C_TPBIAS
37B3 FW_C_TPA_P
37B3 FW_C_TPA_N
37B3 FW_C_TPB_P
37B3 FW_C_TPB_N
37B3
37B3
NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS
PCI_EXPRESS GRAPHICS ALIASES

NO-CONNECT UNUSED SDVO INTERFACE PORTS
PEG_D2R_N<0>
PEG_D2R_N0_SPN
PEG_D2R_N<2>
PEG_D2R_N2_SPN MAKE_BASE=TRUE
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
MAKE_BASE=TRUE
PEG_D2R_N<8>
PEG_D2R_N8_SPN
MAKE_BASE=TRUE
PEG_D2R_N<9>
PEG_D2R_N9_SPN
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_P0_SPN MAKE_BASE=TRUE
PEG_D2R_P<0>
PEG_D2R_P<2>
PEG_D2R_P<3>
MAKE_BASE=TRUE
PEG_D2R_P<4>
PEG_D2R_P4_SPN
MAKE_BASE=TRUE
PEG_D2R_P<5>
PEG_D2R_P5_SPN
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>
MAKE_BASE=TRUE
PEG_R2D_C_N<4>
PEG_R2D_C_N4_SPN
PEG_R2D_C_N5_SPNMAKE_BASE=TRUE
PEG_R2D_C_N<5>
MAKE_BASE=TRUE
PEG_R2D_C_N<6>
PEG_R2D_C_N6_SPN
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
MAKE_BASE=TRUE
PEG_R2D_C_N<10>
PEG_R2D_C_N10_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N<11>
PEG_R2D_C_N11_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N<12>
PEG_R2D_C_N12_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N<13>
PEG_R2D_C_N13_SPN
MAKE_BASE=TRUE
PEG_R2D_C_N14_SPN
PEG_R2D_C_N<14>
MAKE_BASE=TRUE
PEG_R2D_C_N15_SPN
PEG_R2D_C_N<15>
PEG_R2D_C_P<4>
PEG_R2D_C_P4_SPNMAKE_BASE=TRUE
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
MAKE_BASE=TRUE
PEG_R2D_C_P<10>
PEG_R2D_C_P10_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P11_SPN
PEG_R2D_C_P<11>
MAKE_BASE=TRUE
56B4 56B1
PEG_R2D_C_P<12>
PEG_R2D_C_P12_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P13_SPN
PEG_R2D_C_P<13>
MAKE_BASE=TRUE
PEG_R2D_C_P14_SPN
PEG_R2D_C_P<14>
MAKE_BASE=TRUE
PEG_R2D_C_P<15>
PEG_R2D_C_P15_SPN
54C8
NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS
MAKE_BASE=TRUE
MAKE_BASE=TRUE
67B2 67A6 67A4 67A2
SATA_C_D2R_N
SATA_C_D2R_P
SATA_C_R2D_C_N
SATA_C_R2D_C_P
MAKE_BASE=TRUE
15C6
FIREWIRE ALIASES
NO-CONNECT UNUSED SATA INTERFACE PORTS

SATA_B_D2R_N_SPN
SATA_B_D2R_N
MAKE_BASE=TRUE
SATA_B_D2R_P
SATA_B_D2R_P_SPN
MAKE_BASE=TRUE
SATA_B_R2D_C_N
SATA_B_R2D_C_N_SPN
MAKE_BASE=TRUE
SATA_B_R2D_C_P
SATA_B_R2D_C_P_SPN
MAKE_BASE=TRUE
22B6
MAKE_BASE=TRUE
14C5
=GND_CHASSIS_AUDIO_MIC
=GND_CHASSIS_DIPDIMM_LEFT
56A4
SATA ALIASES
NO-CONNECT UNUSED LVDS INTERFACE PORTS
CLIP-SM-M42
OF
76
01
OMIT
70C3 13D3
BI
70C3 13D3
BI
70C3 13D3
BI
70C3 13D3
BI
70C3 13D3
BI
70C3 13D3
BI
70C3 13D3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13A3
BI
70C3 13A3
BI
70C3 13A3
BI
70C3 13A3
BI
70C3 13A3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 13C3
BI
70C3 22C4
70C3 22C2
70B3 22C4
IN
IN
70C3 22C4
IN
70B3 22C4
K3
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
IN CPU_A20M_L
OUT CPU_FERR_L
70B3 22C4
70C3 22C4
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IN
IN
J1
N3
P5
P2
L2
P4
P1
R1
M1
H2
K2
J3
L1
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
CPU_IGNNE_L
C4
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8
TP_CPU_RSVD9
N2
D5
C6
B4
A3
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
DEFER*
DRDY*
DBSY*
H5
E1
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
BR0*
F1
FSB_BREQ0_L
F21
BI
13C3 70D3
BI
13C3 70D3
BI
13C3 70D3
BI
13B3 70D3
BI
13B3 70D3
BI
13B3 70D3
BI
13B3 70D3
=PP1V05_S0_CPU
IERR*
INIT*
D20 70C3 CPU_IERR_L

B3
CPU_INIT_L
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
HIT*
HITM*
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
F3
F4
G3
G2
E4
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
R1002
54.9
1%
1/16W
MF-LF
2 402
7C7 9B5 9B6 9C5 10C7 11A3 12B3 12C5
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY
22C4 46B2 70B3
13B3 70D3
IN
12B5 13A5 70D3
IN
13A3 70D3
IN
13A3 70D3
IN
13A3 70D3
IN
13B3 70D3
OMIT
FSB_HIT_L
FSB_HITM_L
G6
BI
13B3 70D3
BI
13B3 70D3
BI
12B2 70A3
BI
12B2 70A3
BI
12B2 70A3
BI
12B3 70A3
BI
12B2 70A3
=PP1V05_S0_CPU
1%
1/16W
MF-LF
402
XDP_TDI
THERMTRIP*
BI
B25
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
C7
PM_THRMTRIP_L
D21
A24
BCLK0
BCLK1
FSB_CLK_CPU_P
FSB_CLK_CPU_N
A22
A21
BI
70D3 13D5
BI
OUT
9A7 12B5 70B3
70D3 13D5
BI
IN
9B7 12B2 70B3
70D3 13D5
BI
IN
9A7 12B3 70A3
70D3 13D5
BI
OUT
12B4 27C6
70D3 13C5
R1004
OUT
OUT
49C7
OUT
49B7
OUT
15A6 22C2 45B3 70B3
45B5 45C3 59C8 70C3
PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)
BI
70D3 13C5
BI
70D3 13C5
BI
70D3 13B3
BI
70D3 13B3
BI
70D3 13B3
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
BI
IN
29D3 75C3
70C3 13C5
IN
29D3 75C3
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
70C3 13C5
BI
=PP1V05_S0_CPU
NC
1%
1/16W
MF-LF
402 2
7C7 9B5 9C5 9D5 10C7 11A3 12B3 12C5
70C3 13C5
BI
70C3 13C5
BI
70C3 13B3
BI
70C3 13B3
BI
70C3 13B3
BI
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
0.5" MAX LENGTH FOR CPU_GTLREF

70B3 CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
NOSTUFF
TP_CPU_TEST6
C1000
AD26
C23
D25
C24
AF26
AF1
A26
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DATBP1*
DINV1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
U1000
MEROM
FCBGA
2 OF 4
PLACE C1000 CLOSE TO CPU_TEST4

PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND
54.9
1%
1/16W
MF-LF
402
10%
16V
X5R
402
70B3 29C6
OUT
70B3 29B6
OUT
70B3 29A6
OUT
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
B22
B23
C21
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
COMP0
COMP1
COMP2
COMP3
MISC
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
0.1uF
R1024
PLACEMENT_NOTE=Place R1024 near ITP connector (if present)
BI
9B7 12B3 70B3
2
1%
1/16W
MF-LF
402
BI
70D3 13D5
IN
1%
1/16W
MF-LF
402
54.9
BI
BI
1%
1/16W
MF-LF
402
=PP1V05_S0_CPU
70D3 13D5
70D3 13D5
1K
54.9
BI
70D3 13D5
12B2 70A3
R1005
B1
BI
70D3 13D5
9A7 12B2 12B3 70B3
12C5 12B3 11A3 10C7 9D5 9C5 9B6 7C7
NC
70D3 13D5
IN
H CLK
R1021
70B3 12B5 9C6
70D3 13D5
5%
1/16W
MF-LF
2 402
PROCHOT*
THERMDA
THERMDC
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
XDP_TDO
BI
2.0K
70B3 12B3 9C6
70D3 13D5
54.9
THERMAL
R1020
XDP_TMS
BI
R1003 1
R1006
70B3 12B2 9C6
7C7 9B5 9B6 9D5 10C7 11A3 12B3 12C5

70D3 13D5
68
A20M*
FERR*
IGNNE*
STPCLK*
LINT0
LINT1
SMI*
G5
DATA GRP 2
BI
1 OF 4
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
H1
E2
DATA GRP 3
BI
70C3 13D3
M3
FCBGA
DATA GRP 0
70C3 13D3
K5
ADS*
BNR*
BPRI*
MEROM
DATA GRP 1
BI
L4
CONTROL
70C3 13D3
L5
U1000
XDP/ITP SIGNALS
BI
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
ADDR GROUP0
BI
70C3 13D3
J4
ADDR GROUP1
70C3 13D3
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ICH
BI
RESERVED
70C3 13D3
BSEL0
BSEL1
BSEL2
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
BI
13C5 70C3
BI
13C5 70C3
BI
13C5 70C3
BI
13C5 70C3
BI
13C5 70C3
BI
13C5 70C3
BI
13C5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B3 70C3
BI
13A3 70C3
BI
13B3 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B5 70C3
BI
13B3 70C3
BI
13A3 70C3
BI
13B3 70C3
LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
R1016
27.4
R1017
54.9
CPU_COMP<0>
70B3 CPU_COMP<1>
70B3 CPU_COMP<2>
70B3 CPU_COMP<3>
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R1018
R1019
1%
1/16W
MF-LF
402
27.4
70B3
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
54.9
IN
15B6 22C4 59C7 70B3
IN
22C4 70B3
IN
13B3 70D3
IN
12B1 22C4 70C3
IN
13A5 70B3
OUT
1%
1/16W
MF-LF
402
27B3
NOSTUFF
R1030
0
R1022
70B3 12B3 12B2 9C6
54.9
XDP_TCK
R1023
70A3 12B3 9C6
649
XDP_TRST_L
NOSTUFF
R1012 1
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NOSTUFF
1
1K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R1007
1K
5%
1/16W
MF-LF
402
CPU FSB
SYNC_MASTER=T9_MLB_NOME

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
76
01
A4
P6
A8
P21
(CPU CORE POWER)
OMIT
A11
=PPVCORE_S0_CPU
A14
7D7 10B5 11D7 48B3 48B5
Standard Voltage:
Low Voltage:
Ultra Low Voltage:
44.0 A (Design Target)
41.0 A (HFM)
30.4 A (LFM)
25.5 A (SuperLFM)
21.0 A (HFM)
18.7 A (LFM)
TBD A (SuperLFM)
TBD
TBD
OMIT
A9
AB7
A10
U1000
AC7
A12
MEROM
AC9
A13
FCBGA
AC12
A15
3 OF 4
AC13
A17
AC15
A18
AC17
A20
AC18
B7
AD9
B10
AD10
B12
AD12
B14
A16
B15
AD15
B17
AD17
A (HFM)
A (LFM)
R25
AF2
T1
B6
T4
TBD
TBD
A (Auto-Halt/Stop-Grant HFM)
A (Auto-Halt/Stop-Grant SuperLFM)
TBD
TBD
A (Auto-Halt/Stop-Grant HFM)
A (Auto-Halt/Stop-Grant LFM)
27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)
TBD
TBD
A (Sleep HFM)
A (Sleep SuperLFM)
TBD
TBD
A (Sleep HFM)
A (Sleep LFM)
B8
T23
B11
T26
B13
U3
B16
U6
B19
U21
B21
U24
B24
25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)
TBD
TBD
A (Deep Sleep HFM)

A (Deep Sleep SuperLFM)
TBD
TBD
A (Deep Sleep HFM)

A (Deep Sleep LFM)
V2
C5
V5
C8
11.5 A (Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Deeper Sleep)
V22
C11
V25
C14
TBD
A (Enhanced Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
W1
C16
W4
C19
W23
C2
W26
AD18
B20
VCC
AE10
C10
AE12
C12
C22
Y3
C25
Y6
AE9
C9
D1
Y21
D4
Y24
D8
AA2
D11
AA5
D13
AA8
D16
AA11
D19
AA14
D23
AA16
D26
AA19
E3
AA22
AE13
C13
AE15
C15
AE17
C17
AE18
C18
AE20
D9
AF9
AF10
D10
AF12
D12
AF14
D14
VCC
E6
AA25
E8
AB1
E11
AB4
AF15
AF17
D17
D18
AF18
E7
AF20
(CPU IO POWER 1.05V)
E14
=PP1V05_S0_CPU
E9
E10
VSS
VSS
AB8
E16
AB11
E19
AB13
E21
AB16
E24
AB19
F5
AB23
F8
AB26
7C7 9B5 9B6 9C5 9D5 11A3 12B3 12C5
G21
E12
V6
E13
J6
E15
K6
E17
4500 mA (before VCC stable)

2500 mA (after VCC stable)
M6
E18
J21
E20
K21
VCCP
F9
F11
AC3
F13
AC6
F16
AC8
F19
AC11
F2
AC14
F22
AC16
F25
AC19
G4
AC21
G1
AC24
M21
N21
F10
N6
F12
R21
F14
R6
F15
T21
F17
T6
F18
G23
AD2
G26
AD5
H3
AD8
V21
(CPU INTERNAL PLL POWER 1.5V)

F20
W21
=PP1V5_S0_CPU
AA7
7C7 11B3
H6
AD11
H21
AD13
H24
AD16
J2
AD19
J5
AD22
J22
AD25
J25
AE1
K1
AE4
K4
AE8
B26
AA9
AA10
R22
4 OF 4
A23
AD14
B18
R5
FCBGA
A19
27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)
9.4 A (Enhanced Deeper Sleep)
F7
R2
MEROM
AD7
B9
D15
P24
U1000
AB20
A7
VCCA
130 mA
C26
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
59C7 70A3
OUT
59C7 70A3
OUT
59C7 70A3
OUT
59C7 70A3
OUT
59C7 70A3
OUT
59C7 70A3
OUT
59C7 70A3
=PPVCORE_S0_CPU
1
R1100
100
AB10
AB12
AB14
7D7 10D7 11D7 48B3 48B5
1%
1/16W
MF-LF
402
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
VCCSENSE
AF7
CPU_VCCSENSE_P
OUT
59A4 59A5 70A3
AB15
AB17
AB18
VSSSENSE
AE7
CPU_VCCSENSE_N
OUT
1
M2
A2
M5
AF6
M22
AF8
M25
AF11
N1
AF13
N4
AF16
N23
AF19
N26
AF21
59A4 59A5 70A3
R1101
100
1%
1/16W
MF-LF
2 402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
P3
A25
AF25
CPU Power & Ground
SYNC_MASTER=T9_MLB_NOME

SIZE
D
APPLE INC.
REV.
051-7455
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
DRAWING NUMBER
OF
10
76
01
CPU VCORE HF AND BULK DECOUPLING

4x 330uF. 20x 10uF 0805
48B5 48B3 10D7 10B5 7D7
=PPVCORE_S0_CPU
LAYOUT NOTE:
CRITICAL
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)
C1200
10UF
10%
2 6.3V
X5R
805-2
LAYOUT NOTE:
CRITICAL
1
10UF
C1210
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1211
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1203
10UF
C1212
C1213
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
10%
2 6.3V
X5R
805-2
C1204
10UF
CRITICAL
1
C1214
10UF
C1215
10%
2 6.3V
X5R
805-2
C1206
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1205
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1202
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)
C1201
CRITICAL
1
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1216
10UF
10%
2 6.3V
X5R
805-2
C1207
CRITICAL
1
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1217
10UF
10%
2 6.3V
X5R
805-2
C1208
CRITICAL
1
10UF
10%
2 6.3V
X5R
805-2
CRITICAL
1
C1218
10UF
10%
2 6.3V
X5R
805-2
C1209
CRITICAL
1
C1219
10UF
10%
2 6.3V
X5R
805-2
VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE:
PLACE ON BOTTOMSIDE
CRITICAL
1
CRITICAL
1
C1250
330UF
10%
2 2.0V
TANT
D2T
CRITICAL
1
C1251
330UF
CRITICAL
1
C1252
330UF
10%
2 2.0V
TANT
D2T
10%
2 2.0V
TANT
D2T
C1253
330UF
LAYOUT NOTE:
10B7 7C7
PLACE ON BOTTOMSIDE
=PP1V5_S0_CPU
10%
2 2.0V
TANT
D2T
1x 10uF, 1x 0.01uF
C1280 1
10uF
C1281
0.01UF
10%
16V
2 CERM
402
20%
6.3V 2
X5R
603
LAYOUT NOTE:
PLACE C1281 NEAR PIN B26 OF U1000
C1250, C1251, C1252 AND C1253 NEED TO USE 6mOHM CAPS.
VCCP (CPU I/O) DECOUPLING

12C5 12B3 10C7 9D5 9C5 9B6 9B5 7C7
=PP1V05_S0_CPU
1X 330UF, 6X 0.1UF
CRITICAL
1
C1235 1
10%
2.5V 2
TANT
D2T
C1236
0.1UF
330uF
20%
2 10V
CERM
402
C1237
0.1UF
20%
2 10V
CERM
402
C1238
0.1UF
20%
2 10V
CERM
402
C1239
0.1UF
C1240
0.1UF
20%
2 10V
CERM
402
C1241
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
LAYOUT NOTE:
PLACE C1235 CLOSE TO CPU
CPU Decoupling & VID
SYNC_MASTER=MSARWAR

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
11
76
01
CPU ITP700FLEX DEBUG SUPPORT

C
C
ITP
12B3 11A3 10C7 9D5 9C5 9B6 9B5 7C7
CRITICAL
=PP1V05_S0_CPU
J1302
NOSTUFF
QT500306-L021-9F
M-ST-SM
R1301
54.9
1%
1/16W
MF-LF
2402
70B3 9C6 9A7
IN
70B3 9C6 9B7
ITP
R1302
22.6
XDP_TDO
ITP
R1300
22.6
70D3 13A5 9D6
IN
70A3 9C6 9A7
FSB_CPURST_L
70B3 12B2 9C6 9A7
OUT
OUT
OUT
1%
1/16W
MF-LF
402
29D3
IN
(FROM CK505 HOST 133/167MHZ)
29D3
IN
XDP_TDI
XDP_TRST_L
(TCK)
XDP_TCK
ITP_TDO
CPU_XDP_CLK_N
CPU_XDP_CLK_P
ITPRESET_L
1%
1/16W
MF-LF
402
70A3 9C6
27C6 9C6
OUT
IO
XDP_BPM_L<3>
XDP_DBRESET_L
12C5 11A3 10C7 9D5 9C5 9B6 9B5 7C7
=PP1V05_S0_CPU
32
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
34
33
ITP
C1300
0.1UF
10%
2 16V
X5R
402
70B3 9C6 9B7
XDP_TMS
LVDS_CTRL_DATA
LVDS_CTRL_CLK
(FBO)
XDP_TCK
OUT
14D5 67A7
14D5 67A7
70B3 12B3 9C6 9A7

70A3 9C5
70A3 9C6
70A3 9C6
70A3 9C6
70A3 9C6
OUT
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
IO
IO
IO
IO
CPU_PWRGD
IO
9B2 22C4 70C3
516S0394
(DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 965GM CHIPSET SYSTEM.
(DEBUG PORT ACTIVE)
(DBR#)
TO ICH8M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)
ITP TCK SIGNAL LAYOUT NOTE:

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
CONNECTORS FBO PIN.
CPU ITP700FLEX DEBUG

SYNC_MASTER=MASTER SYNC_DATE=5/23/05

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
12
76
01
OMIT
U1400
CRESTLINE
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70D3 9C4
BI
70C3 9C4
BI
70C3 9C4
BI
70C3 9C4
B
29C6 29B6 7C7
R1421
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
R1420
R1410
54.9
54.9
221
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9B4
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9C2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B2
BI
70C3 9B4
70C3 9B4
BI
70D3 9C4
BI
70C3 9B2
BI
70C3 9B2
BI
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
NB_FSB_SCOMP
NB_FSB_SCOMP_L
B3
C2
W1
W2
1%
1/16W
MF-LF
402 2
70D3 12B5 9D6
OUT
70B3 9A2
OUT
FSB_CPURST_L
FSB_CPUSLP_L
B6
NB_FSB_VREF
B9
E5
A9
1
1
2.0K
1%
1/16W
MF-LF
402
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP*
C1425
0.1uF
2
2
10%
16V
X5R
402
R1415
R1411
24.9
100
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
H_CPURST*
H_CPUSLP*
H_AVREF
H_DVREF
H_A3*
H_A4*
H_A5*
H_A6*
H_A7*
H_A8*
H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
H_A17*
H_A18*
H_A19*
H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*
J13
H_ADS*
H_ADSTB0*
H_ADSTB1*
H_BNR*
H_BPRI*
H_BREQ*
H_DEFER*
H_DBSY*
HPLL_CLK
HPLL_CLK*
H_DPWR*
H_DRDY*
H_HIT*
H_HITM*
H_LOCK*
H_TRDY*
G12
FCBGA
(1 OF 10)
1K
R1426
H_D0*
H_D1*
H_D2*
H_D3*
H_D4*
H_D5*
H_D6*
H_D7*
H_D8*
H_D9*
H_D10*
H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*
H_D24*
H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*
H_D31*
H_D32*
H_D33*
H_D34*
H_D35*
H_D36*
H_D37*
H_D38*
H_D39*
H_D40*
H_D41*
H_D42*
H_D43*
H_D44*
H_D45*
H_D46*
H_D47*
H_D48*
H_D49*
H_D50*
H_D51*
H_D52*
H_D53*
H_D54*
H_D55*
H_D56*
H_D57*
H_D58*
H_D59*
H_D60*
H_D61*
H_D62*
H_D63*
NB_FSB_SWING
NB_FSB_RCOMP
R1425
E2
HOST
70D3 9C4
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
H_DINV0*
H_DINV1*
H_DINV2*
H_DINV3*
K5
H_DSTBN0*
H_DSTBN1*
H_DSTBN2*
H_DSTBN3*
M7
H_DSTBP0*
H_DSTBP1*
H_DSTBP2*
H_DSTBP3*
L7
L2
AD13
AE13
K3
AD2
AH11
K2
AC2
AJ10
H_REQ0*
H_REQ1*
H_REQ2*
H_REQ3*
H_REQ4*
M14
H_RS0*
H_RS1*
H_RS2*
E12
E13
A11
H13
B12
D7
D8
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_DEFER_L
FSB_DBSY_L
FSB_CLK_NB_P
FSB_CLK_NB_N
FSB_DPWR_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L
FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>
FSB_DSTB_L_N<0>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<3>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9C8 70C3
BI
9D6 70D3
BI
9D8 70C3
BI
9C8 70C3
BI
OUT
BI
OUT
9D6 70D3
9D6 70D3
9D6 70D3
9D6 70D3
IN
29D3 75C3
IN
29D3 75C3
BI
9B2 70D3
BI
9D6 70D3
BI
9D6 70D3
BI
BI
9C6 70D3
9C6 70D3
IN
9D6 70D3
OUT
9D6 70D3
BI
9C4 70D3
BI
9B4 70C3
BI
9C2 70C3
BI
9B2 70C3
BI
9C4 70D3
BI
9B4 70C3
BI
9C2 70C3
BI
9B2 70C3
BI
9C4 70D3
BI
9B4 70C3
BI
9C2 70C3
BI
9B2 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9D8 70C3
BI
9C8 70C3
OUT
9D6 70D3
OUT
9D6 70D3
OUT
9D6 70D3
1
1
NB CPU Interface
C1410
0.1uF
2
2
10%
16V
X5R
402
SYNC_MASTER=T9_MLB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
13
76
01
PP1V05_S0_NB_VCCPEG
1
U1400
2
R1510
1%
1/16W
MF-LF
402
CRESTLINE
67C6
OUT
67D8
OUT
67A7 12B1
If SDVO is used, VCCD_LVDS must remain powered with proper

decoupling. Otherwise, tie VCCD_LVDS to GND also.
BI
67A7 12B1
BI
67B6
BI
67B6
BI
67B8
71C3 67A8
OUT
BI
IN
IN
71D3 67B3
OUT
71D3 67B3
OUT
8D6
8D6
OUT
71D3 67B2
OUT
71D3 67B2
OUT
71D3 67B2
OUT
71D3 67B2
OUT
71D3 67B2
OUT
71D3 67B2
OUT
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
LVDS_BKLT_CTL
LVDS_BKLT_EN
LVDS_CTRL_CLK
LVDS_CTRL_DATA
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_VDD_EN
LVDS_IBG
TP_LVDS_VBG
TP_LVDS_VREFH
TP_LVDS_VREFL
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
J40
L_BKLT_CTRL
H39
E39
L_BKLT_EN
L_CTRL_CLK
FCBGA
PEG_COMPI
N43
(3 OF 10)
PEG_COMPO
M43
E40
PEG_RX0*
PEG_RX1*
J51
L_CTRL_DATA
C37
L_DDC_CLK
L_DDC_DATA
PEG_RX2*
N47
D35
L_VDD_EN
PEG_RX3*
PEG_RX4*
T45
K40
U40
L41
LVDS_IBG
PEG_RX5*
PEG_RX6*
L43
PEG_RX7*
Y40
N41
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
PEG_RX8*
PEG_RX9*
AB51
N40
LVDSA_CLK*
LVDSA_CLK
PEG_RX10*
AD44
LVDSB_CLK*
PEG_RX11*
PEG_RX12*
AD40
PEG_RX13*
AH49
PEG_RX14*
PEG_RX15*
AG45
D46
C45
D44
E42
LVDSB_CLK
Unused DAC outputs must remain powered, but can

omit filtering components. Unused DAC outputs
should connect to GND through 75-ohm resistors.
69D8
OUT
69D8
OUT
69D8
OUT
69B8
69A8
TV-Out Disable / CRT Enable
69A8
Tie TVx_DAC and TVx_RTN to GND. Must power all

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can
share filtering with VCCA_CRT_DAC.
OUT
OUT
OUT
69C8
OUT
69C8
OUT
=TV_A_DAC
=TV_B_DAC
=TV_C_DAC
=TV_A_RTN
=TV_B_RTN
=TV_C_RTN
TV_DCONSEL<0>
TV_DCONSEL<1>
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

VSYNC and CRT_TVO_IREF to GND.
Can tie the following rails to GND:
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
NOTE: Must keep VDDC_TVDAC powered
and filtered at all times!
OUT
69B8
OUT
69D7
OUT
69A8
OUT
69D7
OUT
69A8
OUT
69B8
BI
69B8
BI
69D7
OUT
69D8
OUT
69D7
OUT
=CRT_BLUE
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN_L
=CRT_RED
=CRT_RED_L
CRT_DDC_CLK
CRT_DDC_DATA
=CRT_HSYNC_R
=CRT_TVO_IREF
=CRT_VSYNC_R
Y44
W49
AG46
AG41
E51
LVDSA_DATA1*
PEG_RX0
J50
F49
LVDSA_DATA2*
PEG_RX1
PEG_RX2
L50
LVDSA_DATA0
LVDSA_DATA1
PEG_RX3
U44
T49
LVDSA_DATA2
PEG_RX4
PEG_RX5
PEG_RX6
W45
PEG_RX7
PEG_RX8
W41
PEG_RX9
PEG_RX10
Y48
PEG_RX11
AC41
PEG_RX12
PEG_RX13
AH47
PEG_RX14
AH45
PEG_RX15
AG42
PEG_TX0*
PEG_TX1*
N45
PEG_TX2*
U47
PEG_TX3*
PEG_TX4*
N51
PEG_TX5*
PEG_TX6*
T42
PEG_TX7*
W46
PEG_TX8*
PEG_TX9*
W38
G50
E50
F48
G44
LVDSB_DATA0*
B47
LVDSB_DATA1*
LVDSB_DATA2*
B45
E44
LVDSB_DATA0
A47
LVDSB_DATA1
LVDSB_DATA2
A45
G27
TVA_DAC
TVB_DAC
K27
TVC_DAC
E27
F27
J27
L27
TVA_RTN
TVB_RTN
TVC_RTN
M35
TV_DCONSEL0
P33
TV_DCONSEL1
M47
T41
AB50
AC45
AG49
U39
R50
Y43
AD39
PEG_TX10*
AC46
PEG_TX11*
PEG_TX12*
AC49
PEG_TX13*
AH39
PEG_TX14*
PEG_TX15*
AE49
AC42
AH44
PEG_TX0
M45
CRT_BLUE
CRT_BLUE*
PEG_TX1
PEG_TX2
T38
G32
K29
CRT_GREEN
PEG_TX3
N50
J29
F29
CRT_GREEN*
CRT_RED
PEG_TX4
PEG_TX5
R51
E29
CRT_RED*
PEG_TX6
W42
PEG_TX7
PEG_TX8
Y47
H32
VGA
CRT & TV-Out Disable
69D7
T50
LVDSA_DATA0*
CRT Disable / TV-Out Enable

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
All CRT/TVDAC rails must be powered. All
rails must be filtered except for VCCA_CRT.
L51
G51
TV-Out Signal Usage:

Composite: DACA only
S-Video:
DACB & DACC only
Component: DACA, DACB & DACC
LVDS
Can leave all signals NC if LVDS is not implemented.

Tie VCC_TX_LVDS and VCCA_LVDS to GND.
TV
PCI-EXPRESS GRAPHICS
LVDS Disable
18B3 20D3
24.9
OMIT
T46
U43
Y39
PEG_TX9
PEG_TX10
AC38
G35
CRT_DDC_CLK
CRT_DDC_DATA
F33
CRT_HSYNC
PEG_TX11
AC50
C32
CRT_TVO_IREF
CRT_VSYNC
PEG_TX12
PEG_TX13
AD43
PEG_TX14
AE50
PEG_TX15
AH43
K33
E33
Internal Graphics Disable
AD47
AG39
PEG_COMP
SDVO Alternate Function

PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
IN
PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
8D6
IN
68B6 71D3
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
68B6 71D3
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8C6
IN
8B6
IN
8B6
IN
8B6
OUT
68C6 71D3
OUT
68C6 71D3
OUT
68B6 71D3
OUT
68B6 71D3
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
68C6 71D3
OUT
68C6 71D3
OUT
68B6 71D3
OUT
68B6 71D3
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8B6
OUT
8A6
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN
SDVOB_RED
SDVOB_GREEN
SDVOB_BLUE
SDVOB_CLKP
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP
Follow instructions for LVDS and CRT & TV-Out Disable above.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
TV_DCONSELx to GND.
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
NB PEG / Video Interfaces
SYNC_MASTER=T9_MLB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
14
76
01
7
NB_CFG<5>
RESERVED
U1400
CRESTLINE
NB_CFG<9>
15B6
NBCFG_PEG_REVERSE
NB_CFG<7>
RESERVED
R1659
3.9K
RESERVED
NB_CFG<8>
NB_CFG<9>
High = Normal
PCIe Graphics
Lane Reversal
Low
5%
1/16W
MF-LF
402
= Reversed
NB_CFG<16>
RESERVED
NB_CFG<10>
15B6
NBCFG_DYN_ODT_DISABLE
1
R1666
3.9K
RESERVED
NB_CFG<11>
NB_CFG<12>
5%
1/16W
MF-LF
402
See Below
NB_CFG<13>
See Below
=PP3V3_S0_NB_VCCHV
7D4 15B7 15C7 18B3 20A8 21B7
8B4
NBCFG_DMI_REVERSE
NB_CFG<14>
RESERVED
NB_CFG<15>
RESERVED
2
8B4
3.9K
8B4
5%
1/16W
MF-LF
402
72D3 32C6 30C4

72B3 32A5 31C4
NB_CFG<19>
NB_CFG<16>
High = Enabled
FSB Dynamic
ODT
Low
8B4
R1669
= Disabled
RESERVED
8D6
7D4 15B7 15C7 18B3 20A8 21B7
8D6
NBCFG_SDVO_AND_PCIE
1
8D6
R1670
8D6
3.9K
RESERVED
NB_CFG<18>
NB_CFG<19>
Low
NB_CFG<20>
5%
1/16W
MF-LF
402
NB_CFG<20>
High = Reversed
DMI Lane
Reversal
15B6
70B3 29C8
IN
70B3 29B8
IN
70B3 29B8
NB CFG<8:0> used for debug access
OUT
8A6
BI
8A6
=
=
=
=
RESERVED
XOR Mode Enabled
All-Z Mode Enabled
Normal Operation
IN
8A6
15D7
NB_CFG<13:12>
00
01
10
11
FCBGA
SM_CK0
AV29
(2 OF 10)
SM_CK1
SM_CK3
BB23
R35
RSVD2
RSVD3
N35
RSVD4
SM_CK4
AV23
AR12
SM_CK0*
AW30
AR13
RSVD5
RSVD6
RSVD7
SM_CK1*
SM_CK3*
BA23
AM12
AN13
RSVD8
RSVD9
SM_CK4*
AW23
SM_CKE0
BE29
SM_CKE1
SM_CKE3
AY32
SM_CKE4
BG37
SM_CS0*
SM_CS1*
BG20
SM_CS2*
BG16
SM_CS3*
BE13
SM_ODT0
SM_ODT1
BH18
SM_ODT2
BJ14
J12
AR37
RSVD10
AM36
RSVD11
RSVD12
AL36
AM37
D20
BI
OUT
8A6
OUT
8A6
OUT
15D7
NB CFG<13:12> require ICT access
21B7 20A8 18B3 15C7 7D4
=PP3V3_S0_NB_VCCHV
15D7
B
R1630 1
44B8 8B2
44B8 8B2
IN
IN
R1631
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
15C7
15C7
24D5
70B3 59C7 22C4 9B2
OUT
IN
RSVD20
B51
RSVD21
BJ20
BK22
RSVD22
RSVD23
BF19
RSVD24
BH20
RSVD25
RSVD26
BK18
BD24
BJ29
IN
70B3 45B3 22C2 9C6

70B3 59D8 24C3
OUT
IN
BK14
SM_RCOMP_VOH
BK31
SM_RCOMP_VOL
BL31
SA_MA14
SB_MA14
RSVD34
AW20
RSVD35
BK20
RSVD36
RSVD37
C48
D47
B44
SM_VREF0
SM_VREF1
DPLL_REF_SSCLK
DPLL_REF_SSCLK*
H48
RSVD43
B34
C34
RSVD44
RSVD45
NB_BSEL<0>
NB_BSEL<1>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<5>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>
TP_NB_CFG<10>
TP_NB_CFG<11>
TP_NB_CFG<12>
TP_NB_CFG<13>
TP_NB_CFG<14>
TP_NB_CFG<15>
NB_CFG<16>
TP_NB_CFG<17>
TP_NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
P27
CFG0
DMI_RXN0
AN47
N27
CFG1
DMI_RXN1
AJ38
N24
CFG2
CFG3
DMI_RXN2
DMI_RXN3
AN42
DMI_RXP0
AM47
DMI_RXP1
DMI_RXP2
AJ39
DMI_RXP3
AN45
DMI_TXN0
AJ46
DMI_TXN1
DMI_TXN2
AJ41
DMI_TXN3
AM44
DMI_TXP0
DMI_TXP1
AJ47
DMI_TXP2
AM39
DMI_TXP3
AM43
PM_BMBUSY_L
CPU_DPRSTP_L
GFX_VID0
E35
GFX_VID1
A39
GFX_VID2
GFX_VID3
C38
GFX_VR_EN
E36
N23
CFG6
J20
CFG7
CFG8
C20
CFG9
R24
L23
CFG10
CFG11
J23
CFG12
E23
CFG13
CFG14
G23
E20
K23
M20
CFG15
CFG16
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
M24
CFG17
L32
N33
CFG18
CFG19
L35
CFG20
G41
PM_BM_BUSY*
L39
PM_DPRSTP*
PM_EXT_TS0*
VR_PWRGOOD_DELAY
NB_RESET_L
PM_THRMTRIP_L
PM_DPRSLPVR
AW49
PM_EXT_TS1*
PWROK
AV20
RSTIN*
TP_NB_NC<1>
TP_NB_NC<2>
TP_NB_NC<3>
TP_NB_NC<4>
TP_NB_NC<5>
TP_NB_NC<6>
TP_NB_NC<7>
TP_NB_NC<8>
TP_NB_NC<9>
TP_NB_NC<10>
TP_NB_NC<11>
TP_NB_NC<12>
TP_NB_NC<13>
TP_NB_NC<14>
TP_NB_NC<15>
TP_NB_NC<16>
BJ51
NC1
BK51
NC2
BK50
NC3
NC4
N20
G36
BL50
BL49
BL3
BL2
BK1
BJ1
THERMTRIP*
DPRSLPVR
NC5
NC6
NC7
NC8
NC9
E1
NC10
A5
C51
NC11
NC12
B50
NC13
A49
NC14
NC15
BK2
NC16
A50
30D4 72D3
OUT
30A4 72D3
OUT
31D4 72B3
OUT
31A4 72B3
OUT
30C6 32D6 72D3
OUT
30C4 32D6 72D3
OUT
31C6 32D6 72B3
OUT
31C4 32D5 72B3
OUT
30B4 32D6 72D3
OUT
30B6 32D6 72D3
OUT
31B4 32D6 72B3
OUT
31B6 32D6 72B3
OUT
30B4 32D6 72D3
OUT
30B6 32D6 72D3
OUT
31B4 32D6 72B3
OUT
31B6 32D6 72B3
31D2 30D2 20C8 17D7 7A4
R1610 1
1%
1/16W
MF-LF
402
K44
PEG_CLK*
K45
C1623
10%
16V
CERM
402
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N
NB_CLK100M_PCIE_P
NB_CLK100M_PCIE_N
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
AN46
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
AN41
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
AM40
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
AJ42
B39
R1600
1
CL_CLK
AM49
CL_DATA
AK50
CL_PWROK
CL_RST*
AT43
CL_VREF
AM50
AN49
GFX_VID<0>
GFX_VID<1>
GFX_VID<2>
GFX_VID<3>
=GFX_VR_EN
GFX_VID<4>
5%
1/16W
MF-LF
402
CLINK_NB_CLK
CLINK_NB_DATA
=NB_CLINK_MPWROK
CLINK_NB_RESET_L
74A3 NB_CLINK_VREF
IN
8B2
IN
8B2
IN
8B2
IN
8B2
IN
29C3 75B3
IN
29C3 75B3
IN
23D2 71D3
IN
23D2 71D3
IN
23D2 71D3
IN
23D2 71D3
IN
23D2 71D3
IN
23D2 71D3
IN
23D2 71D3
IN
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
23D2 71D3
OUT
21B6 60C6
OUT
21B6 60C6
OUT
21B6 60C6
OUT
21B6 60C6
OUT
8B2
OUT
60C6
20%
10V
CERM
402
IN
20A5
IN
20A4
0.1uF
2.2UF
20%
6.3V
CERM1
603
R1622
3.01K
C1625
20
1%
1/16W
MF-LF
402
0.01UF
10%
16V
CERM
402
1%
1/16W
MF-LF
402
C1624
R1624
1K
2.2UF
20%
6.3V
CERM1
603
1%
1/16W
MF-LF
402
BI
24C3 74A3
BI
24C3 74A3
IN
OUT
24C3 74A3
H35
SDVO_CTRL_DATA
CLKREQ*
K36
ICH_SYNC*
G40
TEST1
A37
TEST2
R32
G39
SDVO_CTRLCLK
SDVO_CTRLDATA
NB_CLKREQ_L
NB_SB_SYNC_L
BI
68A6
BI
68A6
OUT
28B4
OUT
24B5
R1640
1K
8B2
C1640
SDVO_CTRL_CLK
18C3 20A6
NOTE: GMCH CL_PWROK input must be PWRGD signal for

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CL_PWROK to PWROK.
R1641
392
0.1uF
20%
10V
CERM
402
1%
1/16W
MF-LF
402
2
2
1%
1/16W
MF-LF
402
NB Misc Interfaces
SYNC_MASTER=T9_MLB
NB_TEST1
NB_TEST2
1

R1690
5%
1/16W
MF-LF
402

SIZE
D
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
R1611 1
20%
10V
CERM
402
PP1V25_S0M_NB_VCCAXD
5%
1/16W
MF-LF
402
C1622
C1616
20K
1%
1/16W
MF-LF
402
Clk used for PEG and DMI
R1691 1
0.01UF
=PP0V9_S3M_MEM_NBVREFA
=PP0V9_S3M_MEM_NBVREFB
R1620
1K
MEM_RCOMP_VOH
MEM_RCOMP_VOL
H47
PEG_CLK
=PP1V8_S3M_MEM_NB
MEM_RCOMP
MEM_RCOMP_L
C42
B36
F23
31A4 72B3
OUT
0.1uF
B42
RSVD41
RSVD42
CFG4
CFG5
31D4 72B3
OUT
C1615
DPLL_REF_CLK
DPLL_REF_CLK*
RSVD38
RSVD39
RSVD40
C23
30A4 72D3
OUT
AW4
B37
C21
30D4 72D3
OUT
AR49
A35
J36
27D1
SM_RCOMP*
SM_CK5
SM_CK5*
BH39
BE24
L36
IN
SM_CK2*
OUT
20
MEM_ODT<0>
MEM_ODT<1>
MEM_ODT<2>
MEM_ODT<3>
BJ15
BL15
BC23
MEM_CS_L<0>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>
BK16
BE16
BG23
MEM_CKE<0>
MEM_CKE<1>
MEM_CKE<3>
MEM_CKE<4>
BD39
SM_ODT3
RSVD27
SM_CK2
BJ18
MEM_CLK_N<0>
MEM_CLK_N<1>
MEM_CLK_N<3>
MEM_CLK_N<4>
AW25
SM_RCOMP
BF23
MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<3>
MEM_CLK_P<4>
BA25
C44
PM_EXTTS_L<0>
PM_EXTTS_L<1>
59C7 27B5
RSVD13
RSVD14
H10
= Normal
High = Both active

Low = Only SDVO
or PCIe x16
Concurrent
SDVO/PCIe x1
OUT
15B6
=PP3V3_S0_NB_VCCHV
NB_CFG<17>
OUT
TP_NB_RSVD<20>
TP_NB_RSVD<21>
TP_NB_RSVD<22>
TP_NB_RSVD<23>
TP_NB_RSVD<24>
TP_NB_RSVD<25>
TP_NB_RSVD<26>
TP_NB_RSVD<27>
TP_MEM_CLKP2
TP_MEM_CLKN2
TP_MEM_CLKP5
TP_MEM_CLKN5
MEM_A_A<14>
MEM_B_A<14>
TP_NB_RSVD<34>
TP_NB_RSVD<35>
TP_NB_RSVD<36>
TP_LVDS_A_DATAN3
TP_LVDS_A_DATAP3
TP_LVDS_B_DATAN3
TP_LVDS_B_DATAP3
TP_NB_RSVD<41>
TP_NB_RSVD<42>
TP_NB_RSVD<43>
TP_NB_RSVD<44>
TP_NB_RSVD<45>
RSVD1
P37
RSVD
RESERVED
P36
DDR MUXING
TP_NB_RSVD<1>
TP_NB_RSVD<2>
TP_NB_RSVD<3>
TP_NB_RSVD<4>
TP_NB_RSVD<5>
TP_NB_RSVD<6>
TP_NB_RSVD<7>
TP_NB_RSVD<8>
TP_NB_RSVD<9>
TP_NB_RSVD<10>
TP_NB_RSVD<11>
TP_NB_RSVD<12>
TP_NB_RSVD<13>
TP_NB_RSVD<14>
= DMIx2
CLK
NB_CFG<6>
5%
1/16W
MF-LF
402
CFG
DMI
Low
OMIT
3.9K
PM
GRAPHICS VID
High = DMIx4
DMI x2 Select
R1655
ME
RESERVED
NB_CFG<5>
15B6
NC
NB_CFG<4>
NBCFG_DMI_X2
1
MISC
NB_CFG<3>
OF
15
76
01
OMIT
BI
72D3 30D4
BI
72D3 30D4
BI
72D3 30D4
BI
72D3 30D6
BI
72D3 30D6
BI
72D3 30D6
BI
72D3 30D4
BI
72D3 30D4
BI
72D3 30D6
BI
72D3 30D4
BI
72D3 30D4
BI
72D3 30C4
72D3 30C4
BI
BI
72D3 30C6
BI
72D3 30C6
BI
72D3 30C4
72D3 30C6
BI
BI
72D3 30C4
BI
72D3 30C6
BI
72D3 30D6
BI
72D3 30C6
BI
72D3 30C4
BI
72D3 30C6
BI
72D3 30C4
BI
72D3 30D4
BI
72D3 30C4
BI
72D3 30C6
BI
72D3 30B4
BI
72D3 30B6
BI
72D3 30B4
72D3 30B4
BI
BI
72D3 30B6
BI
72D3 30B4
BI
72D3 30B6
BI
72D3 30B6
BI
72D3 30B4
BI
72D3 30B6
BI
72D3 30B6
BI
BI
72D3 30A6
BI
72D3 30B4
BI
72D3 30A4
BI
72D3 30A6
BI
72D3 30A4
BI
72D3 30A4
BI
72D3 30A6
BI
72D3 30A4
BI
72D3 30A6
BI
72D3 30A6
BI
72D3 30A4
BI
72D3 30A4
BI
72D3 30A6
BI
72D3 30A6
BI
72D3 30A6
BI
72D3 30A4
BI
72D3 30A6
BI
72D3 30A4
BI
72D3 30A4
BI
72D3 30A4
72D3 30A6
BI
BI
AR43
AW44
BA45
SA_DQ0
SA_DQ1
SA_DQ2
AR41
SA_DQ3
SA_DQ4
AR45
SA_DQ5
AY46
AW47
SA_DQ6
SA_DQ7
BB45
SA_DQ8
BF48
SA_DQ9
SA_DQ10
AT42
BG47
BJ45
SA_DQ11
BB47
SA_DQ12
SA_DQ13
BG50
BH49
BE45
AW43
SA_DQ14
SA_DQ15
SA_DQ16
BG42
SA_DQ17
SA_DQ18
BE40
SA_DQ19
BE44
BF44
BH45
SA_DQ20
SA_DQ21
BG40
SA_DQ22
BF40
SA_DQ23
SA_DQ24
AR40
FCBGA
(4 OF 10)
SA_BS0
BB19
SA_BS1
SA_BS2
BK19
BF29
BL17
MEM_A_CAS_L
SA_DM0
AT45
SA_DM1
BD44
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
SA_DM2
SA_DM3
BD42
SA_DM4
AW13
SA_DM5
SA_DM6
BG8
SA_DM7
AN6
AW38
AY5
SA_DQS0
AT46
SA_DQS1
SA_DQS2
BE48
SA_DQS3
BC37
BB43
SA_DQS4
SA_DQS5
BB16
SA_DQS6
BB2
SA_DQS7
SA_DQS0*
AP3
SA_DQS1*
SA_DQS2*
BH6
AT47
BD47
BC41
SA_DQS3*
BA37
AT39
SA_DQ27
SA_DQS4*
SA_DQS5*
BA16
AW36
SA_DQS6*
BC1
BH7
AY41
SA_DQ28
SA_DQ29
AV38
SA_DQ30
AT38
SA_MA0
BJ19
AV13
SA_DQ31
SA_DQ32
SA_DQ33
SA_MA1
SA_MA2
BD20
AT13
AW11
SA_DQ34
SA_DQ35
AW41
AV11
SA_DQS7*
AP2
BK27
SA_MA3
SA_MA4
BH28
BL24
SA_DQ36
SA_DQ37
SA_MA5
BK28
AT11
SA_DQ38
SA_MA6
SA_MA7
BJ27
BA13
AU15
BJ25
SA_MA8
BE10
SA_DQ39
SA_DQ40
SA_DQ41
SA_MA9
SA_MA10
BA28
BD10
SA_MA11
BE28
AY9
SA_DQ42
SA_DQ43
BG10
SA_DQ44
SA_MA12
SA_MA13
BA11
BD8
AW9
BD7
SA_DQ45
SA_DQ46
MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_BS<2>
SA_CAS*
SA_DQ25
SA_DQ26
AW40
BL28
BC19
BG30
BJ16
SA_RAS*
BE18
SA_RCVEN*
AY20
OUT
30B6 32C6 72D3
72B3 31D4
BI
OUT
30B4 32C6 72D3
72B3 31D6
BI
OUT
30C6 32C6 72D3
72B3 31D4
BI
72B3 31D6
BI
72B3 31D6
BI
72B3 31D4
BI
OUT
30B6 32B6 72D3
OUT
30D4 72C3
OUT
30D4 72C3
OUT
30C4 72C3
OUT
30B4 72C3
OUT
30B6 72C3
OUT
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_RAS_L
TP_MEM_A_RCVEN_L
30D6 72C3
BI
30C4 72C3
BI
30C6 72C3
72B3 31D4
BI
BI
72B3 31D6
BI
72B3 31D6
BI
72B3 31D4
BI
72B3 31D4
BI
72B3 31C6
BI
30A4 72C3
BI
30A6 72C3
72B3 31C4
BI
72B3 31C4
30D6 72C3
BI
30D6 72C3
BI
30C4 72C3
30C6 72C3
BI
30B6 72C3
BI
30B4 72C3
BI
30A4 72C3
72B3 31C4
BI
OUT
30B6 32C6 72D3
OUT
30B4 32C6 72D3
OUT
30B6 32C6 72D3
OUT
30B4 32C6 72D3
OUT
30B6 32C6 72D3
OUT
30C4 32C6 72D3
OUT
30C4 32C6 72D3
BI
72B3 31C4
BI
72B3 31C6
BI
BI
72B3 31C6
BI
72B3 31C6
BI
72B3 31B6
BI
72B3 31B4
BI
72B3 31B4
BI
BI
72B3 31B4
BI
OUT
OUT
30C4 32C6 72D3
BI
72B3 31A6
BI
72B3 31A4
BI
72B3 31B4
OUT
30C6 32C6 72D3
OUT
30B4 32C6 72D3
BI
72B3 31B6
30C6 32C6 72D3
30B6 32C6 72D3
BI
72B3 31B4
72B3 31B6
30C6 32C6 72D3
BI
72B3 31C6
72B3 31B6
OUT
BI
72B3 31C4
30A6 72C3
30B4 32C6 72D3
BI
BI
72B3 31C4
OUT
BI
72B3 31C6
72B3 31C4
BI
BI
BI
72B3 31C6
BI
BI
72B3 31C6
30B6 72C3
30B4 72C3
BI
72B3 31D4
72B3 31C4
BI
OUT
BI
30A4 72C3
30D6 72C3
OUT
72B3 31D6
30A6 72C3
BI
BI
BI
72B3 31D6
BI
BI
BI
30C6 72C3
OUT
OUT
72B3 31D4
72B3 31D6
BI
72B3 31B4
BI
72B3 31A6
BI
72B3 31B6
BI
72B3 31A4
BI
72B3 31B6
BI
72B3 31A6
BI
72B3 31A4
BI
72B3 31A6
BI
72B3 31A4
BI
30B4 32B6 72D3
BB5
SA_DQ47
SA_DQ48
AY7
SA_DQ49
AT5
AT7
SA_DQ50
SA_DQ51
AY6
SA_DQ52
72B3 31A6
BI
BB7
72B3 31A4
BI
AR5
SA_DQ53
SA_DQ54
72B3 31A4
BI
AR8
SA_DQ55
72B3 31A6
BI
AR9
SA_DQ56
SA_DQ57
72B3 31A6
BI
72B3 31A6
BI
SA_DQ58
SA_DQ59
72B3 31A4
BI
AN10
72B3 31A4
BI
AT9
SA_DQ60
72B3 31A4
BI
AN9
SA_DQ61
SA_DQ62
72B3 31A6
BI
AM9
AN11
SA_DQ63
72B3 31A6
BB9
AN3
AM8
U1400
CRESTLINE
SA_WE*
BA19
MEM_A_WE_L
OUT
30B6 32B6 72D3
72B3 31A4
BI
BI
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
AP49
SB_DQ0
CRESTLINE
AR51
SB_DQ1
SB_DQ2
(5 OF 10)
AW50
AN51
SB_DQ3
SB_DQ4
AN50
SB_DQ5
AW51
AV49
SB_DQ6
SB_DQ7
BA50
SB_DQ8
BB50
SB_DQ9
SB_DQ10
AV50
BA49
BE50
SB_DQ11
BA51
SB_DQ12
SB_DQ13
AY49
BF49
SB_DQ14
SB_DQ15
BJ50
SB_DQ16
BF50
BJ43
SB_DQ17
SB_DQ18
BL43
SB_DQ19
BJ44
BK47
BK49
SB_DQ20
SB_DQ21
BK43
SB_DQ22
BK42
SB_DQ23
SB_DQ24
BJ41
FCBGA
DDR SYSTEM MEMORY B
BI
72D3 30D6
72D3 30D6
BI
72D3 30D6
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
DDR SYSTEM MEMORY A
72D3 30D6
BI
OMIT
U1400
72D3 30D4
SB_BS0
AY17
SB_BS1
SB_BS2
BG18
BG36
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>
SB_CAS*
BE17
MEM_B_CAS_L
SB_DM0
AR50
SB_DM1
BD49
SB_DM2
SB_DM3
BK45
SB_DM4
BH12
SB_DM5
SB_DM6
BJ7
SB_DM7
AW2
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
BL39
BF3
SB_DQS0
AT50
SB_DQS1
SB_DQS2
BD50
SB_DQS3
BK39
SB_DQS4
SB_DQS5
BL7
SB_DQS6
BE2
SB_DQS7
SB_DQS0*
AV2
SB_DQS1*
SB_DQS2*
BC50
BK46
BJ12
AU50
BL45
SB_DQS3*
BK38
BJ37
SB_DQ25
SB_DQ26
BJ36
SB_DQ27
SB_DQS4*
SB_DQS5*
BK7
SB_DQS6*
BF2
SB_DQS7*
AV3
BL41
BK12
BJ40
SB_DQ28
SB_DQ29
BL35
SB_DQ30
BK37
SB_MA0
BC18
BK13
SB_DQ31
SB_DQ32
SB_DQ33
SB_MA1
SB_MA2
BG28
BE11
BK11
SB_DQ34
SB_DQ35
SB_MA3
SB_MA4
AW17
BK41
BC11
BG25
BF25
SB_DQ36
SB_DQ37
SB_MA5
BE25
BE12
SB_DQ38
SB_MA6
SB_MA7
BA29
BC12
SB_MA8
AY28
BJ10
SB_DQ39
SB_DQ40
SB_DQ41
SB_MA9
SB_MA10
BD37
BL9
SB_MA11
BE37
BL5
SB_DQ42
SB_DQ43
SB_DQ44
SB_MA12
SB_MA13
BA39
BK9
BC13
BG12
BK5
BK10
BJ8
SB_DQ45
SB_DQ46
BF4
SB_DQ47
SB_DQ48
BH5
SB_DQ49
BG1
BC2
SB_DQ50
SB_DQ51
BK3
SB_DQ52
BE4
BD3
SB_DQ53
SB_DQ54
BJ2
SB_DQ55
BA3
SB_DQ56
SB_DQ57
BJ6
BB3
AT3
SB_DQ58
SB_DQ59
AY2
SB_DQ60
AY3
AU2
SB_DQ61
SB_DQ62
AT2
SB_DQ63
AR1
BC28
BG17
BG13
OUT
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
31B4 32A6 72B3
OUT
31C6 32A6 72B3
OUT
31B6 32A6 72B3
OUT
31D4 72B3
OUT
31D4 72B3
OUT
31C4 72B3
OUT
31C6 72B3
OUT
31B4 72B3
OUT
31A6 72B3
OUT
31A4 72A3
OUT
31A6 72A3
BI
31D6 72A3
BI
31D6 72A3
BI
31C6 72A3
BI
31C4 72A3
BI
31B6 72A3
BI
31A4 72A3
BI
31A6 72A3
BI
31A4 72A3
BI
31D6 72A3
BI
31D6 72A3
BI
31C6 72A3
BI
31C4 72A3
BI
31B6 72A3
BI
31B4 72A3
BI
31A6 72A3
BI
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
31B6 32A6 72B3
OUT
OUT
OUT
31A4 72A3
31B4 32B5 72B3

31B6 32B5 72B3
OUT
31B4 32B5 72B3
OUT
31B6 32B5 72B3
OUT
31B4 32B5 72B3
OUT
31B6 32B5 72B3
OUT
31C4 32B5 72B3
OUT
31C4 32B5 72B3
OUT
31C6 32B5 72B3
OUT
31C6 32B5 72B3
OUT
31B6 32B5 72B3
OUT
31C4 32A5 72B3
OUT
31C6 32A5 72B3
OUT
31B4 32A5 72B3
SB_RAS*
AV16
31B4 32A6 72B3
AY18
MEM_B_RAS_L
TP_MEM_B_RCVEN_L
OUT
SB_RCVEN*
SB_WE*
BC17
MEM_B_WE_L
OUT
31B6 32A6 72B3
NB DDR2 Interfaces
SYNC_MASTER=T9_MLB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
16
76
01
AJ31
VCC7
AJ28
VCC8
VCC9
AH31
VCC10
AH29
VCC11
AF32
VCC12
R30
=PP1V8_S3M_MEM_NB
(2 ch, 667MHz)
(2 ch, 533MHz)
(1 ch, 667MHz)
(1 ch, 533MHz)
(standby)
AU33
AU35
AV33
AW33
VCC_SM4
VCC_SM5
VCC_SM6
AY35
VCC_SM7
VCC_SM8
BA33
VCC_SM9
BA35
VCC_SM10
VCC_SM11
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
BF33
VCC_SM20
BF34
VCC_SM21
VCC_SM22
BG32
BG33
BG35
BH32
BH34
BH35
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
BJ32
VCC_SM28
BJ33
VCC_SM29
VCC_SM30
BJ34
BK32
VCC_SM31
BK33
VCC_SM32
VCC_SM33
BK34
BK35
VCC_SM34
BL33
VCC_SM35
VCC_SM36
AU30
=PPVCORE_S0_NB_GFX
7700 mA (Int Graphics)
R20
VCC_AXG1
T14
VCC_AXG2
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
VCC_AXG5
VCC_AXG6
VCC_AXG7
VCC_AXG8
VCC_AXG9
VCC_AXG10
VCC_AXG11
VCC_AXG12
AC20
VCC_AXG13
AC21
VCC_AXG14
VCC_AXG15
AC23
AC24
VCC_AXG16
AC26
VCC_AXG17
VCC_AXG18
AC28
AC29
VCC_AXG3
VCC_AXG4
AD20
VCC_AXG19
VCC_AXG20
AD23
VCC_AXG21
AD24
AD28
VCC_AXG22
VCC_AXG23
AF21
VCC_AXG24
AF26
AA31
VCC_AXG25
VCC_AXG26
AH20
VCC_AXG27
AH21
VCC_AXG28
VCC_AXG29
AH23
AH24
AH26
VCC_AXG30
VCC_AXG31
AD31
VCC_AXG32
AJ20
VCC_AXG33
VCC_AXG34
AN14
VCC GFX
48B3 21C5 17D5 7B7
VCC_SM2
VCC_SM3
AW35
BA32
VCC_SM1
VCC GFX NCTF
AU32
mA
mA
mA
mA
mA
VCC SM
31D2 30D2 20C8 15D2 7A4
3300
2700
1700
1395
5
VCC13
T19
VCC_AXG_NCTF4
VCC_AXG_NCTF5
T21
VCC_AXG_NCTF6
VCC_AXG_NCTF7
T23
VCC_AXG_NCTF8
U15
VCC_AXG_NCTF9
VCC_AXG_NCTF10
U16
VCC_AXG_NCTF11
U19
VCC_AXG_NCTF12
VCC_AXG_NCTF13
U20
VCC_AXG_NCTF14
U23
VCC_AXG_NCTF15
VCC_AXG_NCTF16
U26
VCC_AXG_NCTF17
VCC_AXG_NCTF18
V17
VCC_AXG_NCTF19
V20
VCC_AXG_NCTF20
VCC_AXG_NCTF21
V21
VCC_AXG_NCTF22
V24
VCC_AXG_NCTF23
VCC_AXG_NCTF24
Y15
These connections can break without

impacting part performance.
OMIT
T22
U1400
20D8 20B4 17D7 7C7
T25
=PPVCORE_S0_NB
CRESTLINE
AB33
AB36
VCC_NCTF1
VCC_NCTF2
AB37
VCC_NCTF3
AC33
AC35
VCC_NCTF4
VCC_NCTF5
AC36
VCC_NCTF6
AD35
VCC_NCTF7
VCC_NCTF8
U17
U21
AD36
AF33
AF36
VCC_NCTF9
VCC_NCTF10
AH33
VCC_NCTF11
AH35
VCC_NCTF12
VCC_NCTF13
V16
V19
AH36
AH37
VCC_NCTF14
AJ33
AJ35
VCC_NCTF15
VCC_NCTF16
AK33
VCC_NCTF17
AK35
VCC_NCTF18
VCC_NCTF19
V23
Y16
VCC_AXG_NCTF25
Y17
VCC_AXG_NCTF26
VCC_AXG_NCTF27
Y19
VCC_AXG_NCTF28
VCC_AXG_NCTF29
Y21
VCC_AXG_NCTF20
Y24
VCC_AXG_NCTF31
VCC_AXG_NCTF32
Y26
VCC_AXG_NCTF33
Y29
VCC_AXG_NCTF34
VCC_AXG_NCTF35
AA16
VCC_AXG_NCTF36
AB16
VCC_AXG_NCTF37
VCC_AXG_NCTF38
AB19
VCC_AXG_NCTF39
VCC_AXG_NCTF40
AC17
VCC_AXG_NCTF41
AD15
VCC_AXG_NCTF42
VCC_AXG_NCTF43
AD16
VCC_AXG_NCTF44
AF16
VCC_AXG_NCTF45
VCC_AXG_NCTF46
AF19
VCC_AXG_NCTF47
AH16
VCC_AXG_NCTF48
VCC_AXG_NCTF49
AH17
VCC_AXG_NCTF50
VCC_AXG_NCTF51
AJ16
VCC_AXG_NCTF52
AJ19
VCC_AXG_NCTF53
VCC_AXG_NCTF54
AK16
VCC_AXG_NCTF55
AL16
VCC_AXG_NCTF56
VCC_AXG_NCTF57
AL17
VCC_AXG_NCTF58
AL20
VCC_AXG_NCTF59
VCC_AXG_NCTF60
AL21
VCC_AXG_NCTF61
VCC_AXG_NCTF62
AM15
VCC_AXG_NCTF63
AM19
VCC_AXG_NCTF64
VCC_AXG_NCTF65
AM20
VCC_AXG_NCTF66
AM23
VCC_AXG_NCTF67
VCC_AXG_NCTF68
AP15
VCC_AXG_NCTF69
AP17
VCC_AXG_NCTF70
VCC_AXG_NCTF71
AP19
VCC_AXG_NCTF72
VCC_AXG_NCTF73
AP21
VCC_AXG_NCTF74
AP24
VCC_AXG_NCTF75
VCC_AXG_NCTF76
AR20
VCC_AXG_NCTF77
AR23
VCC_AXG_NCTF78
VCC_AXG_NCTF79
AR24
VCC_AXG_NCTF80
V26
VCC_AXG_NCTF81
VCC_AXG_NCTF82
V28
VCC_AXG_NCTF83
Y31
AK36
AK37
AD33
VCC_NCTF20
VCC_NCTF21
AJ36
VCC_NCTF22
AM35
AL33
VCC_NCTF23
VCC_NCTF24
AL35
VCC_NCTF25
AA33
AA35
VCC_NCTF26
VCC_NCTF27
AA36
VCC_NCTF28
AP35
VCC_NCTF29
VCC_NCTF30
Y20
Y23
Y28
AA17
AP36
AR35
AC16
AR36
VCC_NCTF33
Y33
Y35
VCC_NCTF34
VCC_NCTF35
Y36
VCC_NCTF36
Y37
T30
VCC_NCTF37
VCC_NCTF38
T34
VCC_NCTF39
T35
VCC_NCTF40
VCC_NCTF41
AD17
AH15
U29
U31
U32
VCC_NCTF42
VCC_NCTF43
U33
VCC_NCTF44
U35
U36
VCC_NCTF45
VCC_NCTF46
V32
VCC_NCTF47
V33
V36
VCC_NCTF48
VCC_NCTF49
V37
VCC_NCTF50
AH19
AJ17
AK19
AL19
20D8 17C1 7C7
AL23
VCC_NCTF31
VCC_NCTF32
Y32
AC19
FCBGA
(7 OF 10)
POWER
VCC4
VCC6
VCC_AXG_NCTF3
NCTF balls are Not Critical To Function
7B7 17B7 21C5 48B3
T18
VSS NCTF
AK32
T17
VSS SCB
VCC5
AC31
AH32
=PPVCORE_S0_NB_GFX
VCC_AXG_NCTF1
VCC_AXG_NCTF2
VSS_NCTF1
VSS_NCTF2
T27
VSS_NCTF3
U24
VSS_NCTF4
VSS_NCTF5
U28
VSS_NCTF6
VSS_NCTF7
V35
VSS_NCTF8
AB17
VSS_NCTF9
VSS_NCTF10
AB35
VSS_NCTF11
AD37
VSS_NCTF12
VSS_NCTF13
AF17
VSS_NCTF14
AK17
VSS_NCTF15
VSS_NCTF16
AM17
VSS_NCTF17
VSS_NCTF18
AP26
VSS_NCTF19
AR15
VSS_NCTF20
VSS_NCTF21
AR19
T37
V31
AA19
AD19
AF35
AM24
AP28
AR28
VSS_SCB1
VSS_SCB2
A3
VSS_SCB3
VSS_SCB4
C1
VSS_SCB5
BL51
VSS_SCB6
A51
VCC_AXM1
AT33
VCC_AXM2
VCC_AXM3
AT31
VCC_AXM4
VCC_AXM5
AK24
VCC_AXM6
AJ26
VCC_AXM7
AJ23
B2
BL1
VCC AXM
AC32
(6 FCBGA
OF 10)
VCC SM LF
AH28
VCC2
VCC3
POWER
VCC1
AT34
VCC CORE
1310 mA (Ext Graphics)

1573 mA (Int Graphics)
CRESTLINE
AT35
VCC NCTF
=PPVCORE_S0_NB
OMIT
U1400
20D8 20B4 17D3 7C7
AK29
AK23
AL24
VCC_AXM_NCTF1
AL26
VCC_AXM_NCTF2
AL28
AM26
VCC_AXM_NCTF3
VCC_AXM_NCTF4
AM28
VCC_AXM_NCTF5
AM29
AM31
VCC_AXM_NCTF6
VCC_AXM_NCTF7
AM32
VCC_AXM_NCTF8
AM33
VCC_AXM_NCTF9
VCC_AXM_NCTF10
AM16
AM21
AP16
AP29
AP31
AP32
VCC_AXM_NCTF11
VCC_AXM_NCTF12
AP33
VCC_AXM_NCTF13
AL29
AL31
VCC_AXM_NCTF14
VCC_AXM_NCTF15
AL32
VCC_AXM_NCTF16
AR31
AR32
VCC_AXM_NCTF17
VCC_AXM_NCTF18
AR33
VCC_AXM_NCTF19
AP20
AP23
AR21
AR26
V29
NB Power 1
VCC_SM_LF1
AW45
VCC_SM_LF2
VCC_SM_LF3
BC39
VCC_SM_LF4
BD17
BE39
VCC_SM_LF5
VCC_SM_LF6
BD4
VCC_SM_LF7
AT6
AW8
NB_VCCSM_LF1
NB_VCCSM_LF2
NB_VCCSM_LF3
NB_VCCSM_LF4
NB_VCCSM_LF5
NB_VCCSM_LF6
NB_VCCSM_LF7
SYNC_MASTER=T9_MLB

C1807
0.1uF
20%
10V
CERM
402
C1806
0.1uF
2
20%
10V
CERM
402
C1805
0.22UF
20%
6.3V
X5R
402
C1804
0.22UF
2
20%
6.3V
X5R
402
C1803
0.47UF
2
10%
6.3V
CERM-X5R
402
C1802
1uF
2
10%
6.3V
CERM
402
C1801
1uF
2
10%
6.3V
CERM
402
SIZE
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
Current numbers from Crestline EDS, doc #21749.
7C7 17B3 20D8
540 mA
VCC AXM NCTF
OF
17
76
01
OMIT
U1400
CRESTLINE
21D1
5 mA
21B1
21B1
J32
PP3V3_S0_NB_VCCA_CRTDAC
A33
VCCA_CRT_DAC1
B33
VCCA_CRT_DAC2
A30
VCCA_DAC_BG
PP3V3_S0_NB_VCCA_DAC_BG
B32
=GND_NB_VSSA_DAC_BG
FCBGA
VTT1
U13
(8 OF 10)
VTT2
VTT3
U12
VTT4
VTT5
U9
VTT6
U7
VTT7
VTT8
U5
VTT9
U2
VTT10
VTT11
U1
VTT12
T11
VTT13
VTT14
T10
VTT15
VTT16
T7
VCC_SYNC
VSSA_DAC_BG
21A3
PP1V25_S0_NB_VCCA_DPLLA
B49
VCCA_DPLLA
21A3
PP1V25_S0_NB_VCCA_DPLLB
H49
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VTT
80 mA
POWER
21B5 7C4
CRT
30 mA
PP1V25_S0M_NB_VCCA_HPLL
150 mA
20C1
PP1V25_S0M_NB_VCCA_MPLL
AM2
640 mA (667MHz DDR)

550 mA (533MHz DDR)
VSSA_LVDS
K50
20A6
=GND_NB_VSSA_PEG_BG
K49
VSSA_PEG_BG
20B2
PP1V25_S0_NB_PEGPLL
U51
VCCA_PEG_PLL
20B5
PP1V25_S0M_NB_VCCA_SM
20A6 7C4
100 mA
B41
VCCA_SM1
AV19
VCCA_SM2
VCCA_SM3
AU18
VCCA_SM4
AU17
VCCA_SM5
AT22
VCCA_SM7
AT21
VCCA_SM8
VCCA_SM9
AT19
AT18
VCCA_SM10
AT17
VCCA_SM11
AR17
AR16
20B5
U8
U3
T13
T9
T6
VTT17
T5
VTT18
VTT19
T3
VTT20
R3
VTT21
VTT22
R2
T2
R1
AT23
VCC_AXD3
AU24
VCC_AXD4
VCC_AXD5
AT29
VCC_AXD6
AT30
VCC_AXD_NCTF
AR29
PP1V25_S0M_NB_VCCAXD
15A2 20A6
515 mA
PP1V25_S0_NB_VCCAXF
20D5
495 mA
7C7 20A8
100 mA
PP1V8_S3M_NB_VCCSMCK
20A2
200 mA
18C6 21C3
100 mA
7D4 15B7 15C7 20A8

21B7
100 mA
PP1V05_S0_NB_VCCPEG
14D2 20D3
1260 mA
PP1V05_S0_NB_VCCRXRDMI
20C3
260 mA
AU28
AT25
C
AW18
AU19
35 mA
VCCA_PEG_BG
U11
VCC_AXD1
VCC_AXD2
AXF
0.4 mA
=GND_NB_VSSA_LVDS
VCCA_LVDS
SM CK
21B3
A41
A SM
21C3
VCCA_SM_NCTF1
VCCA_SM_NCTF2
PP1V25_S0M_NB_VCCA_SM_CK
BC29
VCCA_SM_CK1
BB29
VCCA_SM_CK2
A CK
10 mA
S0 or S3M is acceptable
18B3 PP1V8_S0_NB_VCCTXLVDS
A LVDS
20D1
A PEG
AXD
50 mA
AL2
PLL
100 mA
VCC_AXF1
VCC_AXF2
B23
VCC_AXF3
A21
B21
VCC_DMI
AJ50
VCC_SM_CK1
BK24
VCC_SM_CK2
VCC_SM_CK3
BK23
VCC_SM_CK4
BJ23
VCC_TX_LVDS
BJ24
S0 or S3M is acceptable
PP1V8_S0_NB_VCCTXLVDS
A43
40 mA
21D1
C27
PP3V3_S0_NB_VCCA_TVDACB
PP3V3_S0_NB_VCCA_TVDACA
VCCA_TVB_DAC2
B28
VCCA_TVC_DAC1
VCCA_TVC_DAC2
A28
60 mA
60 mA
21C7
21D6
=PP1V5_S0_NB_VCCD_CRT
PP1V5_S0_NB_VCCD_TVDAC
5 mA
21C5
PP1V5_S0_NB_VCCD_QDAC
250 mA
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
21B3
=PP1V8_S0_NB_VCCD_LVDS
J41
VCCD_LVDS1
H42
VCCD_LVDS2
LVDS
150 mA
VCC_HV1
C40
VCC_HV2
B40
VCC_PEG1
AD51
VCC_PEG2
W50
VCC_PEG3
VCC_PEG4
W51
VCC_PEG5
V50
V49
VCC_RXR_DMI1
AH50
VCC_RXR_DMI2
AH51
=PP1V25_S0M_NB_VCCD_HPLL
20D1
VCCA_TVA_DAC2
VCCA_TVB_DAC1
B27
PEG
21C1
VTTLF
40 mA
VCCA_TVA_DAC1
CRT
B25
DMI
C25
PP3V3_S0_NB_VCCA_TVDACC
TV/CRT
21C1
HV
=PP3V3_S0_NB_VCCHV
40 mA
TBD mA @ 1067MHz FSB (1.25V)

850 mA @ 800MHz FSB (1.05V)
770 mA @ 667MHz FSB (1.05V)
7C7 20C8
VTTLF1
A7
VTTLF2
F2
VTTLF3
AH1
NB_VTTLF_CAP1
NB_VTTLF_CAP2
NB_VTTLF_CAP3
1
C1913
0.47UF
2
10%
6.3V
CERM-X5R
402
C1912
0.47UF
2
10%
6.3V
CERM-X5R
402
C1911
0.47UF
10%
6.3V
CERM-X5R
402
NB Power 2
SYNC_MASTER=T9_MLB

SIZE
D
APPLE INC.
REV.
051-7455
SCALE
SHT
NONE
Current numbers from Crestline EDS, doc #21749.
DRAWING NUMBER
OF
18
76
01
OMIT
U1400
VSS100
AW24
C46
VSS199
FCBGA
VSS287
W11
A15
VSS2
VSS3
(9 OF 10)
VSS101
VSS102
AW29
C50
VSS200
VSS201
(10 OF 10)
VSS288
VSS289
W39
VSS103
VSS104
AW5
D13
D24
VSS202
VSS203
VSS290
VSS291
W47
AW7
VSS105
AY10
D3
VSS204
VSS292
W7
W43
VSS4
VSS5
AA24
VSS6
AA29
VSS7
VSS8
VSS106
VSS107
AY24
D32
AY37
D39
VSS205
VSS206
VSS293
VSS294
Y13
AB20
AB23
VSS9
VSS108
AY42
D45
VSS207
VSS295
Y41
AB26
VSS10
VSS11
VSS109
VSS110
AY43
D49
AY45
E10
VSS208
VSS209
VSS296
VSS297
Y45
AB28
AB31
VSS12
VSS111
AY47
E16
VSS210
VSS298
Y5
AC10
VSS13
VSS14
VSS112
VSS113
AY50
E24
E28
VSS211
VSS212
VSS299
VSS300
Y50
B10
E32
VSS301
P29
VSS302
T29
AC39
VSS15
VSS16
VSS114
VSS115
B20
B24
E47
VSS213
VSS214
AC43
VSS17
VSS116
B29
F19
VSS215
AC47
VSS18
VSS19
VSS117
VSS118
B30
F36
AD1
B35
F4
VSS216
VSS217
AD21
VSS20
VSS119
B38
F40
VSS218
AD26
VSS21
VSS22
VSS120
VSS121
B43
F50
AD29
G1
VSS219
VSS220
AD3
VSS23
VSS122
B5
G13
VSS221
AD41
VSS24
VSS25
VSS123
VSS124
B8
G16
BA1
G19
VSS222
VSS223
G24
AD45
B46
AD5
VSS26
VSS27
VSS125
VSS126
BA17
BA18
G28
VSS224
VSS225
AD50
VSS28
VSS127
BA2
G29
VSS226
G33
AD49
AD8
TDE_SENSE
W5
Y2
Y49
Crestline Thermal Diode Pins
Y11
Mainly for investigation. If not used,

alias these nets directly to GND.
=NB_TDE_SENSE
TDE_FORCE
VSS303
T31
=NB_TDE_FORCE
8A2
TDB_FORCE
VSS304
T33
=NB_TDB_FORCE
8A2
NOTE: TDB = _N
TDB_SENSE
VSS305
R28
=NB_TDB_SENSE
AE10
VSS29
VSS30
VSS128
VSS129
BB12
G42
VSS227
VSS228
AE14
VSS31
VSS130
BB25
G45
VSS229
VSS306
AA32
AE6
VSS32
VSS33
VSS131
VSS132
BB40
G48
BB44
G8
VSS230
VSS231
VSS307
VSS308
AB32
AF20
AF23
VSS34
VSS133
BB49
H24
VSS232
VSS309
AF28
AF24
VSS35
VSS36
VSS134
VSS135
BB8
H28
H4
VSS233
VSS234
VSS310
VSS311
AF29
BC16
VSS37
VSS38
VSS136
VSS137
BC24
H45
J11
VSS312
VSS313
AV25
BC25
VSS235
VSS236
J16
VSS237
AG2
AG38
AG43
VSS39
VSS138
BC36
AG47
VSS40
VSS41
VSS139
VSS140
BC40
J2
AG50
BC51
J24
VSS238
VSS239
AH3
VSS42
VSS141
BD13
J28
VSS240
AH40
VSS43
VSS44
VSS142
VSS143
BD2
J33
AH41
BD28
J35
VSS241
VSS242
AH7
VSS45
VSS144
BD45
J39
VSS243
AH9
VSS46
VSS47
VSS145
VSS146
BD48
BD5
K12
VSS245
VSS48
VSS49
VSS147
VSS148
BE1
K47
BE19
K8
VSS246
VSS247
L1
VSS248
AJ11
AJ13
AJ21
AJ24
VSS50
VSS149
BE23
AJ29
VSS51
VSS52
VSS150
VSS151
BE30
L17
AJ32
BE42
L20
VSS249
VSS250
AJ43
VSS53
VSS152
BE51
L24
VSS251
AJ45
VSS54
VSS55
VSS153
VSS154
BE8
L28
AJ49
BF12
L3
VSS252
VSS253
AK20
VSS56
VSS155
BF16
L33
VSS254
AK21
VSS57
VSS58
VSS156
VSS157
BF36
L49
BG19
M28
VSS255
VSS256
VSS59
VSS60
VSS158
VSS159
BG2
M42
BG24
M46
VSS257
VSS258
M49
VSS259
AK26
AK28
AK31
AK51
VSS61
VSS160
BG29
AL1
VSS62
VSS63
VSS161
VSS162
BG39
M5
BG48
M50
VSS260
VSS261
VSS163
BG5
M9
VSS262
N11
AM11
AM13
AM3
VSS64
AM4
VSS65
VSS66
VSS164
VSS165
BG51
BH17
N14
VSS263
VSS264
AM41
VSS67
VSS166
BH30
N17
VSS265
AM45
VSS68
VSS69
VSS167
VSS168
BH44
N29
BH46
N32
VSS266
VSS267
VSS70
VSS71
VSS169
VSS170
BH8
N36
BJ11
N39
VSS268
VSS269
N44
VSS270
N49
N7
VSS271
VSS272
P19
VSS273
AN1
AN38
AN39
AN43
VSS72
VSS171
BJ13
AN5
VSS73
VSS74
VSS172
VSS173
BJ38
AN7
BJ4
AP4
VSS75
VSS174
BJ42
AP48
VSS76
VSS77
VSS175
VSS176
BJ46
P2
AP50
BK15
P23
VSS274
VSS275
AR11
VSS78
VSS177
BK17
P3
VSS276
AR2
VSS79
VSS80
VSS178
VSS179
BK25
P50
BK29
R49
VSS277
VSS278
VSS180
VSS181
BK36
T39
AR47
VSS81
VSS82
BK40
T43
VSS279
VSS280
AR7
VSS83
VSS182
BK44
T47
VSS281
AT10
VSS84
VSS85
VSS183
VSS184
BK6
U41
BK8
U45
VSS282
VSS283
U50
VSS284
VSS285
VSS286
AR39
AR44
AT14
AT41
VSS86
VSS185
BL11
AT49
VSS87
VSS88
VSS186
VSS187
BL13
V2
AU1
BL19
V3
AU23
VSS89
VSS188
BL22
AU29
VSS90
VSS91
VSS189
VSS190
BL37
VSS92
VSS93
VSS191
VSS192
C12
AU49
AU51
VSS94
VSS193
C19
AV39
VSS194
VSS195
C28
AV48
VSS95
VSS96
AW1
VSS97
VSS196
C33
AW12
VSS98
VSS99
VSS197
VSS198
C36
AU3
AU36
AW16
8A2
NOTE: TDE = _P
BA24
AF31
C7
AW32
AA21
AC3
VSS
FCBGA
AC13
CRESTLINE
VSS1
A24
U1400
CRESTLINE
A13
A17
OMIT
VSS
8A2
AD32
AT27
H50
NB Grounds
SYNC_MASTER=T9_MLB
BL47

C16

C29
SIZE
C41
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
19
76
01
18C3
=PPVCORE_S0_NB
Host PLL Digital Supply
PP1V25_S0_NB_VCCAXF
=PP1V25_S0_NB_VCCAXF
350 mA
VOLTAGE=1.25V
CRITICAL
C2100 1
I/O voltage Supply
GMCH Core Power

20B4 17D7 17D3 7C7
C2101
22UF
470UF
20%
2.5V 2 3
TANT
D2T
C2102
0.22uF
C2103
0.22uF
20%
6.3V
2 X5R
402
20%
6.3V
2 CERM
805
C2170
C2104
10uF
0.1UF
20%
6.3V
2 X5R
402
20%
6.3V 2
X5R
603
20%
2 10V
CERM
402
7C7
=PP1V25_S0_NB_PLL
20B4 7C7
=PP1V25_S0M_NB_VCCD_HPLL
450 mA
C2171
1UF
20%
2 10V
CERM
402
250mA,0.5ohm
L2181
Host PLL Analog Supply

PP1V25_S0M_NB_VCCA_HPLL
120-OHM-0.3A-EMI
CRITICAL
GMCH ME Core Power
L2173
7C7
C2110
22UF
C2111
0.22uF
0.22uF
20%
6.3V
2 X5R
402
20%
6.3V
2 CERM
805
C2112
C2113
C2114
0.1UF
20%
6.3V
2 X5R
402
20%
0.1UF
20%
2 10V
CERM
2 10V
CERM
C2115
OMIT
1210
CRITICAL
C2173
Layout Note:
Place L and C
close to MCH
0.1UF
20%
2 10V
CERM
402
402
402
VOLTAGE=1.05V
1450 mA
C2174
20%
2 6.3V
X5R
603
20%
2.5V 2
POLY
CASE-B2
0402-LF
C2181
22UF
1200 mA
20%
402
250mA,0.5ohm
L2183
1
MPLL Analog Supply

PP1V25_S0M_NB_VCCA_MPLL
VOLTAGE=1.25V
2
0402-LF
GMCH FSB I/O Rail
RX and I/O Logic for DMI

PP1V05_S0_NB_VCCRXRDMI
VOLTAGE=1.05V
850 mA
C2121 1
C2122 1
C2123 1
4.7uF
4.7uF
2.2uF
20%
6.3V 2
CERM
603
20%
6.3V 2
CERM
603
C2124 1
0.47UF
20%
6.3V
CERM1 2
603
C2177
R21831
20%
6.3V
2 X5R
603
0.51
18B3
1%
1/16W
MF-LF
402
250 mA
C2183 1
C2184
0.1UF
PLACEMENT_NOTE=Place C2184 by U1400.AM2
VOLTAGE=1.25V
22UF
These supplies are still needed even using external GPU
20%
6.3V 2
CERM
805
PLACEMENT_NOTE=Place close to U1400
18D6
150 mA
20%
10V
2 CERM
402
PP1V25_S0M_NB_MPLL_RC
Layout Note:
10uF caps should
be close to MCH
on opposite side.
10uF
10%
6.3V
CERM-X5R 2
402
C2182
10V
2 CERM
120-OHM-0.3A-EMI
18D3 7C7
18D6
50 mA
0.1UF
20%
6.3V 2
CERM
805
Layout Note:
10uF caps should
be close to MCH
on opposite side.
10uF
220UF
VOLTAGE=1.25V
Analog,I/O logic,and Term Voltage for PCI-E Graphics

PP1V05_S0_NB_VCCPEG
14D2 18B3
91NH
=PP1V05_S0_NB_PCIE
1
540 mA
1
C2180
0.1UF
10%
2 6.3V
CERM
402
PLACEMENT_NOTE=Place in GMCH cavity
17C1 17B3 7C7
18A6
250 mA
WF: Matanzas has 270uF
GMCH Memory I/O Rail

=PP1V8_S3M_MEM_NB
31D2 30D2 17D7 15D2 7A4
2400 mA
OMIT
CRITICAL
C2130 1
330UF
20%
2.5V 2
POLY
CASE-C2
C2135
0.1UF
C2131
22UF
this is "1 of 2" 1.8V bulk decoupling caps.
C2132
22UF
20%
2 6.3V
CERM
805
20%
2 6.3V
CERM
805
20%
2 10V
CERM
402
PLACEMENT_NOTE=Place close to U1400

WF: "Place where LVDS
and DDR2 taps." (C2125)
spec requires "3.9uH ferrite,1A,32mohm max".
R2141
=PP1V25_S0_NB_VCCA
7C7
??? mA
OMIT
CRITICAL
VOLTAGE=1.25V
5%
1/16W
MF-LF
402
C2140 1
330UF
C2142
22UF
20%
2 6.3V
CERM
805
20%
2.0V 2
POLY
CASE-B2
C2143
4.7UF
22UF
20%
6.3V
2 CERM
805
SOD-723
C2144
PP3V3_S0_NBCORE_FOLLOW_R
10
VOLTAGE=3.3V
=PP3V3_S0_NB_FOLLOW
7D4
1%
1/16W
MF-LF
402
NOTE: This follower is redundant if VCORE is always 1.05V.
VOLTAGE=1.25V
NOSTUFF
C2145
10%
2 6.3V
CERM
402
=PPVCORE_S0_NB
??? mA
Memory clock logic voltage.

PP1V25_S0M_NB_VCCA_SM_CK
5%
1/16W
MF-LF
402
R2186
1SS418
17D7
7C7
17D3
20D8
1UF
10%
6.3V
2 X5R-CERM
603
R2145
1
D2186
Memory I/O logic and DLL voltage.

PP1V25_S0M_NB_VCCA_SM
18C6
C2147
2.2UF
20D3 7C7
WF: 220-ohm
L2190
FERR-220-OHM-2.5A
1
100 mA
??? mA
PP1V25_S0_NB_PEGPLL
VOLTAGE=1.25V
2
0603
R21901
C2148
0.1UF
WF: Should be 1.0, 1%
20%
10V
2 CERM
402
20%
6.3V
2 CERM
402-LF
Analog PLL Voltage for PCI-E GPU
=PP1V25_S0_NB_PLL
18B6
1.1
1%
1/16W
MF-LF
402 2
C2191
0.1UF
18C6
100 mA
C2192
0.1UF
20%
20%
10V
2 CERM
2 10V
CERM
402
402
PP1V25_S0_NB_PEGPLL_RC
5.6nH,0.9A,45mohm max.no bigger than 0603
Memory voltage supply.
mA
R2109
PP1V25_S0M_NB_VCCAXD200
7C7 =PP1V25_S0_NB_VCC
15A2 18C3
0 2
1
200 mA
VOLTAGE=1.25V
5%
NOSTUFF
1/16W
1 C2151
MF-LF
C2150 1
20A5 7B4 =PP1V8_S3_MEMVREF
402
10uF
1UF
20%
6.3V
X5R 2
603
C2190
10uF
20%
6.3V 2
X5R
603
20A6 7B4
=PP1V8_S3_MEMVREF
R21121
10%
2 6.3V
CERM
402
1K
1%
1/16W
MF-LF
4022
R21101
15C7 15B7 7D4

21B7 18B3
18C3 7C7
PP0V9_S3M_MEM_NBVREFB
MAKE_BASE=TRUE
VOLTAGE=0.9V
MAKE_BASE=TRUE
VOLTAGE=0.9V
R21131
=PP3V3_S0_NB_VCCHV
1%
1/16W
MF-LF
4022
C2160
0.1UF
C2161
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2165
7C4 18C6
5 mA
=PP0V9_S3M_MEM_NBVREFB
L2195
1.0UH-0.23A
1
2
7A4 200 mA=PP1V8_S3_NB_VCC
15C2
R21951
1.1
WF: Should be 1.0, 1%
R2111
1%
1/16W
MF-LF
402 2
1K
1%
1/16W
MF-LF
4022
PP1V8_S3M_NB_VCCSMCK
VOLTAGE=1.8V
0603
1K
need to find "1uH,220mA,150mohm max"
PP0V9_S3M_MEM_NBVREFA 1K
=PP0V9_S3M_MEM_NBVREFA
100 mA
100 mA
VOLTAGE=1.25V
1%
1/16W
MF-LF
4022
C2196
22UF
20%
6.3V 2
CERM
805
C2197
0.1UF
20%
2 10V
CERM
NB Standard Decoupling
402
PP1V8_S3_NB_VCCSMCK_RC
0.1UF
C2195
20%
2 10V
CERM
402
18B3
200 mA
SYNC_MASTER=WFERRY
VOLTAGE=1.8V
10uF
20%
6.3V
X5R 2
603
LAYOUT NOTE: PLACE THOSE COMPONENT CLOSE TO GMCH
=GND_NB_VSSA_PEG_BG
18C6

Layout Note: Route to caps, then GND

SIZE
D
APPLE INC.
Current numbers from Crestline EDS Addendum, doc #20127.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
20
76
01
7A7
=PP5V_S0_NB_TVDAC
205 mA
R2281
U2280
C2280
5%
1/16W
MF-LF
2 402
C2289
22000pF-1000mA
NO STUFF
C2281
1UF
NOTE: This filter is required even if using only external graphics.
NC
VOLTAGE=3.3V
P3V3TVDAC_NOISE
80 mA
1
1
C2288
C2282 1
THRML
PAD
GND
10UF
0.01UF
20%
6.3V
2 X5R
603
10%
16V
CERM 2
402
C2285
22000pF-1000mA
PP1V5_S0_NB_VCCD_TVDAC
65 mA
1
18B6
60 mA
PP1V5_S0_NB_VCCD_CRT 21C5
VOLTAGE=1.5V
0.1UF
20%
10V
2 CERM
402
18B6
R2205
100
NO STUFF
NO STUFF
1SS418
R2285
D2285
VOLTAGE=1.5V
C2200
7B7
=PP1V5_S0_NB_FOLLOW
6 mA
=PP1V5_S0_NB_VCCD_CRT
PP3V3_S0_NB_TVDAC_FOLLOW
VOLTAGE=3.3V
SOD-723
PP1V5_S0_NB_VCCD_CRT
10
16V
NFM18
0402-LF
1%
1/16W
MF-LF
402
C2290
125 mA
10uF
16V
NFM18
18B6
VOLTAGE=1.5V
PP3V3_S0_NB_VCCA_TVDACB
3
5 mA
C2207
0.1UF
20%
2 10V
CERM
402
Layout Note:
These 4 caps should be
within 6.35 mm of NB edge
10%
10V
2 X5R
402
20%
2 10V
CERM
402
C2294
PP1V5_S0_NB_VCCD_QDAC
1
1UF
18B6
40 mA
CRITICAL
C2205
VOLTAGE=3.3V
22000pF-1000mA
16V
NFM18
PP3V3_S0_NB_VCCA_TVDACA
3
C2291
CRITICAL
0.1UF
20%
6.3V
X5R 2
603
21D6
PP3V3_S0_NB_TVDAC_F
VOLTAGE=3.3V
C2206
PP1V5_S0_NB_QDAC
Layout Note:
22000pF-1000mA
22000pF-1000mA
VOLTAGE=1.5V
18D6
80 mA
C2292
L2290
120-OHM-0.3A-EMI
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2402
VOLTAGE=3.3V
CRITICAL
16V
NFM18
=PP1V5_S0_NB_TVDAC
20%
2 10V
CERM
402
C2201
7B7
PP3V3_S0_NB_VCCA_CRTDAC
3
0.1UF
5 NC
2 10%
6.3V
CERM
402
CRITICAL
NR 2
16V
NFM18
120-OHM-0.3A-EMI
1
2
PP3V3_S0_NB_CRTDAC_F
PP3V3_S0_NB_TVDAC 205 mA
SON OUT 1
6 IN
4 EN
P3V3TVDAC_EN_RC
10%
6.3V 2
CERM
402
VCCD_TVDAC also powers internal thermal sensors.
TPS79933
L2288
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
0402-LF
1UF
CRITICAL
CRITICAL
20%
2 10V
CERM
402
=PPVCORE_S0_NB_GFX
7700 mA
18B6
40 mA
0.1UF
GMCH Graphics Core Power

48B3 17D5 17B7 7B7
C2293
VOLTAGE=3.3V
Layout Note:
CRITICAL
C2210 1
C2212
22UF
470UF
C2213
10uF
20%
6.3V
2 CERM
805
20%
2.5V 2 3
TANT
D2T
20%
2 6.3V
X5R
603
C2214
1UF
10%
2 6.3V
CERM
402
C2215
0.47UF
10%
2 6.3V
CERM-X5R
402
C2216
0.1UF
20%
2 10V
CERM
402
C2217
C2296
20%
2 10V
CERM
402
22000pF-1000mA
16V
NFM18
WF: Matanzas has 2x 330uF
CRITICAL
0.1UF
PP3V3_S0_NB_VCCA_TVDACC
3
PLACEMENT_NOTE=Place in GMCH cavity
C2295
VOLTAGE=3.3V
18B6
40 mA
0.1UF
20%
2 10V
CERM
402
NEED TO FIND A "1#GH, 500MA, 78MOHM" INDUCTOR

WF: Should be 1uH, 30% L2220
WF: Check
7B7
20A8 18B3 15C7 15B7 7D4
part properties
PP1V8_S0_NB_VCCTXLVDS
1.0UH-0.5A-0.675A
=PP1V8_S0_NB_LVDS
=PP3V3_S0_NB_VCCHV
260 mA
VOLTAGE=1.8V
2
1007
OMIT
NO STUFF
1
R2242 R2243
22K
22K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
CRITICAL1
C2220
NO STUFF
1
R2244
22K
R2245
NO STUFF
1
R2247 1R2248
22K
22K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
OUT
15B3 60C6
OUT
15B3 60C6
OUT
15B3 60C6
OUT
15B3 60C6
R2249
22K
5%
1/16W
MF-LF
2 402
C2298
22000pF-1000mA
16V
NFM18
0.001uF
20%
2 50V
CERM
402
=GND_NB_VSSA_LVDS
18C6
=PP1V8_S0_NB_VCCD_LVDS
C2297
PP3V3_S0_NB_VCCA_DAC_BG
3
VOLTAGE=3.3V
18D6
5 mA
0.1UF
20%
2 10V
CERM
402
=GND_NB_VSSA_DAC_BG
18D6
18A6
Layout Note: Route to caps, then GND
150 mA
C2226
NO STUFF
1
CRITICAL
C2223
Layout Note: Route to cap, then GND
GFX_VID<0>
GFX_VID<1>
GFX_VID<2>
GFX_VID<3>
VID<3:0>=1001=1.05575V
1000=1.08150V
0011=1.21025V
C2221
20%
2 50V
CERM
402
20%
2.5V 2
POLY
CASE-B2-SM
22K
0.001uF
220UF
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
18B3 18C6
110 mA
1UF
R2250
10%
6.3V
2 CERM
402
22K
5%
1/16W
MF-LF
2 402
18D6 7C4
10 mA
C2230
0.1UF
20%
2 10V
CERM
402
CRITICAL
U2265
WARNING VOLTAGE DROP

7B7
=PP1V8_S0_NB_DPLL
(1.7V - 5.5V)
80 mA
TPS731125
Vout = 1.204V * (Ra + Rb)/Rb

Ra || Rb should be 19Kohms
SOT23-5
1 IN
3 EN
C2265 1
1UF
OUT 5
NR/FB 4
GND
P1V25S0NBDPLL_FB
C2266
10UF
20%
6.3V
2 X5R
603
80 mA
1
10%
6.3V 2
CERM
402
R2261
PP1V25_S0_NB_DPLL
VOLTAGE=1.25V
PP1V25_S0_NB_VCCA_DPLLA
18D6
VOLTAGE=1.25V
5%
1/16W
MF-LF
402
C2261
NB Graphics Decoupling
0.1UF
20%
10V
2 CERM
402
80 mA
SYNC_MASTER=WFERRY
PP1V25_S0_NB_DPLL_RF
1
C2267
R2266
0.01UF
0.300
10%
2 16V
CERM
402
5%
1/10W
FF
2 603
R2262
1
PP1V25_S0_NB_VCCA_DPLLB

18D6
VOLTAGE=1.25V
5%
1/16W
MF-LF
402

C2262
0.1UF
20%
10V
2 CERM
402
WF: Is this the best part to use?

WF: Check C2266 value, R2267 value
SIZE
D
APPLE INC.
Current numbers from Crestline EDS Addendum, doc #20127.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
21
76
01
24D8 24B3 22D2 7D4
27D4 26A5 25D6
5%
1/16W
MF-LF
402
R2300 1
27C8
27C8
IN
OUT
8.2K
PP1V5_S0_SB_VCC1_5_B
PP3V3_G3_SB_RTC
R2301
332K
24.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R2311
10K
5%
1/16W
MF-LF
402
R2302
332K
OMIT
SB_RTC_X1
SB_RTC_X2
AG25
AF24
U2300
RTCX1
RTCX2
ICH8M
BGA
SB_RTC_RST_L
AF23
RTCRST*
IN
SB_SM_INTRUDER_L
AD22
INTRUDER*
D22
TP_LAN_D2R<0>
TP_LAN_D2R<1>
TP_LAN_D2R<2>
C21
TP_LAN_R2D<0>
TP_LAN_R2D<1>
TP_LAN_R2D<2>
D21
LAN_ENERGY_DET
74B3
B24
GLAN_COMP
B21
C22
E20
C20
AH21
D25
C25
HDA_RST_L
73C3 8A6
IN
8A6
8A6
8A6
73B3 8A6
OUT
1
1
R2315
33
HDA_BIT_CLK_R
73C3 HDA_SYNC_R
73C3
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
73C3
HDA_RST_L_R
HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
HDA_SDOUT
AD13
73B3
5%
1/16W
MF-LF
HDA_SDOUT_R
AF26
FERR*
AD24
CPUPWRGD/GPIO49
AG29
IGNNE*
INT PD
INT PD
TP_SB_SATALED_L
73D3 40D4
73D3 40C4
IN
IN
73D3 40D4
OUT
73D3 40D4
OUT
8D4
IN
8D4
IN
8D4
OUT
8D4
OUT
8D4
IN
8D4
IN
8D4
OUT
8D4
OUT
75B3 29C3
IN
75B3 29C3
IN
40D2
40D2
IN
IN
SATA_A_D2R_N
SATA_A_D2R_P
SATA_A_R2D_C_N
SATA_A_R2D_C_P
AE10
AG14
AF10
AF6
AF5
AH5
AH6
SATA_B_D2R_N
SATA_B_D2R_P
SATA_B_R2D_C_N
SATA_B_R2D_C_P
AG3
SATA_C_D2R_N
SATA_C_D2R_P
SATA_C_R2D_C_N
SATA_C_R2D_C_P
AF2
SB_CLK100M_SATA_N
SB_CLK100M_SATA_P
AB7
SATA_RBIAS_N
SATA_RBIAS_P
AG1
AG4
AJ4
AJ3
AF1
AE4
AE3
AC6
AG2
SB_A20GATE
CPU_A20M_L
6C2 44C8 46C4
BI
OUT
BI
OUT
CPU_PWRGD
OUT
9B2 12B1 70C3
AF27
CPU_IGNNE_L
OUT
9C8 70B3
INIT*
INTR
RCIN*
AE24
CPU_INIT_L
CPU_INTR
SB_RCIN_L
OUT
9D6 46B2 70B3
OUT
9B8 70C3
NMI
SMI*
AD23
CPU_NMI
CPU_SMI_L
OUT
9B8 70C3
AG28
OUT
9B8 70B3
STPCLK*
AA24
CPU_STPCLK_L
OUT
9B8 70B3
THRMTRIP*
AE27
CPU_THERMTRIP_R
AC20
AH14
INT PD
HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO34
INT PU
INT PD
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIAS*
SATARBIAS
R2306
10K
5%
1/16W
MF-LF
2 402
R2305 1
54.9
1%
1/16W
MF-LF
402
R2309
54.9
1%
1/16W
MF-LF
402
CPU_FERR_L
AA23
TP_SB_TP8
V1
IDE_PDD<0>
IDE_PDD<1>
IDE_PDD<2>
IDE_PDD<3>
IDE_PDD<4>
IDE_PDD<5>
IDE_PDD<6>
IDE_PDD<7>
IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>
7D7 25C3 26C4
IN
9C8 70C3
C
R2308
1
R2304
24.9
1%
1/16W
MF-LF
402
PM_THRMTRIP_L
IN
9C6 15A6 45B3 70B3
PLACEMENT_NOTE=Place R2308 within 50mm of U2300
2.2K
INT PD
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
8.2K
NO STUFF
TP8
7D4 22D7 24B3 24D8
PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)
9B2 70B3
AE26
R2303
5%
1/16W
MF-LF
402
9B2 15B6 59C7 70B3
CPU_DPRSTP_L
CPU_DPSLP_L
=PP3V3_S0_SB_GPIO
6C2 44C8 46C4
6C2 44C8 46B6
INT PD
HDA_SDOUT
SATALED*
AG26
6D2 44C8 46C6
BI
OUT
INT PD
INT PD
E6
TP_LPC_DRQ0_L
EXTGPU_PWR_EN
6D2 44C8 46C6
BI
9C8 70C3
GLAN_COMPI
GLAN_COMPO
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
G9
BI
OUT
402
HDA_DOCK_EN_L
TP_HDA_DOCK_RST_L
AE13
LPC_FRAME_L
GLAN_DOCK*/GPIO13
HDA_RST*
AH15
33
INT PU
LAN_TXD0
LAN_TXD1
LAN_TXD2
AE14
AH17
R2316
INT PU
AJ15
AJ17
C4
DPRSTP*
DPSLP*
INT PU
HDA_BIT_CLK
HDA_SYNC
AJ16
FWH4/LFRAME*
G8
AF13
LAN_RSTSYNC
IDE
OUT
33
33
F6
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
F5
A20GATE
A20M*
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES RS
OUT
73C3 8A6
R2313
R2314
INT PU
SATA
73C3 8A6
HDA_BIT_CLK
HDA_SYNC
OUT
E5
LDRQ0*
LDRQ1*/GPIO23
GLAN_CLK
LAN_RXD0
LAN_RXD1
LAN_RXD2
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
INT PU
CPU
TP_LAN_RSTSYNC
AD21
INTVRMEN
LAN100_SLP
LAN/GLAN
TP_ENET_GLAN_CLK
AF25
IHDA
SB_INTVRMEN
SB_LAN100_SLP
LPC
IN
27C5
(1 OF 6)
RTC
27D5
73C3 8A6
=PP3V3_S0_SB_GPIO
R2310 1
26C6 26A4 25D6 23C2
INT PU
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DA0
DA1
DA2
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
DCS1*
DCS3*
Y6
DIOR*
DIOW*
DDACK*
IDEIRQ
IORDY
DDREQ
W4
Y5
W3
Y2
Y3
Y1
W5
IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>
IDE_PDCS1_L
IDE_PDCS3_L
IDE_PDIOR_L
IDE_PDIOW_L
IDE_PDDACK_L
IDE_IRQ14
IDE_PDIORDY
IDE_PDDREQ
BI
39C5 73D3
BI
39C5 73D3
BI
39C5 73D3
BI
39C5 73D3
BI
39C5 73D3
BI
39C5 73D3
BI
39C5 73D3
BI
39C5 73D3
BI
39C3 73D3
BI
39C3 73D3
BI
39C3 73D3
BI
39C3 73D3
BI
39C3 73D3
BI
39C3 73D3
BI
39C3 73D3
BI
5%
1/16W
MF-LF
402
39C3 73D3
OUT
39B5 73D3
OUT
39B5 73D3
OUT
39B3 73D3
OUT
39B5 73D3
OUT
39B3 73D3
OUT
39C3 73D3
OUT
39B5 73D3
OUT
39B3 73D3
IN
39B5 73D3
IN
39B5 73D3
IN
39C3 73D3
SB Enet, Disk, FSB, LPC
HDA
SYNC_MASTER=T9_MLB
24.000MHZ CLOCK W/INTERNAL WEAK PD
HDA_BIT_CLK

HDA_RST#
HDA_SDIN[0-2]
INTEGRATED PDs
HDA_SDOUT
INTEGRATED PD
ACZ_SYNC
INTEGRATED PD

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
22
76
01
OMIT
8D4
Spares
8D4
(x2-capable,
pull HDA_SYNC
high for x2)
8D4
8D4
8C4
8C4
8C4
8C4
ExpressCard
8C4
8C4
8C4
8C4
FireWire
8C4
8C4
33B6
PCIe Mini Card

(AirPort)
33B6
33B6
33B6
OUT
TP_PCIE_B_D2R_N
TP_PCIE_B_D2R_P
TP_PCIE_B_R2D_C_N
TP_PCIE_B_R2D_C_P
M27
TP_PCIE_EXCARD_D2R_N
TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_P
K27
TP_PCIE_FW_D2R_N
TP_PCIE_FW_D2R_P
TP_PCIE_FW_R2D_C_N
TP_PCIE_FW_R2D_C_P
H27
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
F27
P26
N29
N28
M26
L29
L28
K26
J29
J28
H26
G29
G28
F26
E29
E28
U2300
PERN1
PERP1
PETN1
PETP1
ICH8M
BGA
(2 OF 6)
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
=PP3V3_S5_SB_USB
R2402
8C1
IN
39B8
OUT
33B6
OUT
IN
OUT
OUT
OUT
IN
IN
IN
R2404
R2408
10K
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
R2401
R2403
R2405
34C8
Ethernet
Yukon-PCIE
Nineveh-GLCI
10K
34C8
IN
IN
34C8
OUT
34C8
OUT
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
D27
SPI_SCLK_R
SPI_CE_R_L<0>
TP_SPI_CE_R_L<1>
C23
SPI_SI_R
SPI_SO
D23
D26
C29
C28
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
R2407
BI
73A3 52C7
BI
B23
E22
SPI_CLK
SPI_CS0*
SPI_CS1*
INT PU
SPI_MOSI
SPI_MISO
INT PU
INT PU
R2409
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
73A3 52C3
BI
73A3 52C3
BI
F21
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
AB26
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
DMI_N2S_N<1>
DMI_N2S_P<1>
DMI_S2N_N<1>
DMI_S2N_P<1>
Y26
W29
W28
DMI_N2S_N<2>
DMI_N2S_P<2>
DMI_S2N_N<2>
DMI_S2N_P<2>
AB25
AA29
AA28
DMI_N2S_N<3>
DMI_N2S_P<3>
DMI_S2N_N<3>
DMI_S2N_P<3>
AD26
AC29
AC28
SB_CLK100M_DMI_N
SB_CLK100M_DMI_P
T25
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
G3
USB_EXTA_N
USB_EXTA_P
USB_MINI_N
USB_MINI_P
USB_EXTD_N
USB_EXTD_P
USB_CAMERA_N
USB_CAMERA_P
USB_IR_N
USB_IR_P
USB_TPAD_N
USB_TPAD_P
USB_BT_N
USB_BT_P
USB_EXTB_N
USB_EXTB_P
USB_EXCARD_N
USB_EXCARD_P
USB_EXTC_N
USB_EXTC_P
USBRBIAS*
USBRBIAS
F2
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
USB
INT PD
INT PD
INT PD
INT PD
INT PD
15B3 71D3
IN
15B3 71D3
15C3 71D3
OUT
15B3 71D3
IN
15B3 71D3
IN
15B3 71D3
OUT
15C3 71D3
OUT
15B3 71D3
IN
15B3 71D3
IN
15B3 71D3
OUT
15B3 71D3
OUT
15B3 71D3
IN
15B3 71D3
IN
15B3 71D3
OUT
15B3 71D3
OUT
15B3 71D3
IN
29C3 75B3
IN
29C3 75B3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
1/16W
MF-LF
R2414
73B3
F3
22D7 25D6 26A4 26C6
24.9
1%
INT PD
IN
OUT
R2413
DMI_IRCOMP_R
INT PD
NOSTUFF
R2406
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
U28
Y24
INT PU
OC0*
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
OC8*
OC9*
Y27
U29
Y23
INT PD
AJ19
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
V26
DMI_ZCOMP
DMI_IRCOMP
INT PD
USB_EXTA_OC_L
SB_GPIO40
USB_EXTD_OC_L
SB_GPIO42
PM_LATRIGGER_L
EXTGPU_LVDS_EN
SB_GPIO30
USB_EXTB_OC_L
EXCARD_OC_L
USB_EXTC_OC_L
V27
T26
INT PD
73A3 52C7
DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_S2N_N<0>
DMI_S2N_P<0>
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI_CLKN
DMI_CLKP
INT PD
EHCI0
EHCI1
R2400
8B1
IN
OUT
P27
SPI
7D1
IN
TP_PCIE_A_D2R_N
TP_PCIE_A_D2R_P
TP_PCIE_A_R2D_C_N
TP_PCIE_A_R2D_C_P
DIRECT MEDIA INTERFACE
8D4
PCI_EXPRESS
8D4
402
BI
8C1 73B3
BI
8C1 73B3
BI
8C1 73B3
BI
8C1 73B3
BI
8C1
BI
8C1
BI
8C1 73B3
BI
8C1 73B3
BI
8C1 8C2 73B3
BI
8C1 8C2 73B3
BI
8C1 73B3
BI
8C1 73B3
BI
8B1 8B2 73B3
BI
8C1 8C2 73B3
BI
8B1 73B3
BI
8B1 73B3
BI
8B1 73B3
BI
8B1 73B3
BI
8B1 73B3
BI
8B1 73B3
External A
AirPort (PCIe Mini-Card)
External D / WWAN
Camera
IR
Geyser Trackpad/Keyboard
Bluetooth
External B
ExpressCard
External C
NOTE: USBP[0-9]P/N have internal 15K pull-downs.
22.6
USB_RBIAS
100K
2
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
NOTE: GNT[0-3]# have internal 20K pull-ups

enabled only when PCIRST# = 0 and PWROK = 1
OMIT
If used, ensure GNT2# is not low when PWROK

rises, or PCIe ports 5 & 6 will be disabled.
U2300
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
74D3 37C5
BI
74D3 37C5
BI
74D3 37C5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B6
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74D3 37B5
BI
74C3 23A4
BI
74C3 23A4
BI
74C3 23A4
74C3 37A5 23A4
BI
BI
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
F9
B5
C5
A10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PIRQA*
PIRQB*
PIRQC*
PIRQD*
ICH8M
BGA
(3 OF 6)
INT PU
INT PU
INT PU
REQ0*
INT PU
GNT0*
REQ1*/GPIO50
GNT1*/GPIO51
REQ2*/GPIO52
GNT2*/GPIO53
REQ3*/GPIO54
GNT3*/GPIO55
A4
PCI_FW_REQ_L
IN
23A4 37A5 74D3
IN
23A4 74D3
PCI_FW_GNT_L
D7
E18
C18
B19
F18
A11
C10
MAKE_BASE=TRUE
PCI_REQ1_L
TP_SB_GPIO51
PCI_REQ2_L
TP_SB_GPIO53
ODD_RST_5VTOL_L
TP_SB_GPIO55
IN
23A4 74D3
BOOT_LPC_SPI_L
1
C/BE0*
C/BE1*
C/BE2*
C/BE3*
IRDY*
PAR
PCIRST*
DEVSEL*
PERR*
PLOCK*
SERR*
STOP*
TRDY*
FRAME*
C17
E15
F16
E17
C8
D9
G6
D16
A7
B7
F10
C16
C9
A17
37A5 74D3
OUT
6C2 46B6
SB BOOT BIOS SELECT
R2415
I/F
1K
OUT
39A8 73D3
PCI
OUT
PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>
PCI_IRDY_L
PCI_PAR
PCI_RST_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
BI
37B5 74D3
BI
37B5 74D3
BI
37B5 74D3
BI
37B5 74D3
BI
23A4 37A5 74D3
BI
OUT
5%
1/16W
MF-LF
402
R2415 pull-down on GNT0#

selects SPI ROM by default.
NOTE:
INT
AG24
B10
G7
PLT_RST_L
PCI_CLK33M_SB
TP_PCI_PME_L
23A4 37A5 74D3
74D3 37A5 23A6
BI
23A4 74D3
74D3 37A5 23A6
BI
23A4 37A5 74D3
74D3 37A5 23A6
BI
23A4 37A5 74D3
74D3 37A5 23A6
BI
23A4 37A5 74D3
74D3 37A5 23A6

74D3 37A5 23A6
23A4 37A5 74D3
74D3 23A6
27D4 67C6
29A5 29B3 75B3
74D3 37A5 23B6

74D3 23B6
74D3 23B6
74C3 23A8
74C3 23A8
INTERRUPT I/F
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
F8
G11
F12
B3
74C3 23A8
INT_PIRQE_L
INT_PIRQF_L
DVI_HOTPLUG_DET
ODD_PWR_EN_L
7C4
BI
IN
SPI
37B5 74D3
37A6
23A4 37A5 74D3
OUT
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
74D3 37A5 23A6
PLTRST*
PCICLK
PME*
PU
LPC
GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
BI
BI
GNT0#
BI
23A4 74C3
BI
23A4 74C3
74C3 37A5 23A8
IN
68A4 68B8
OUT
23A4 39C8
Provide a pull-down on this GPIO if not used.
74C3 23A6
74C3 23A6
39C8 23A6
FireWire INT*
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L
R2423
R2424
R2425
R2426
R2427
R2428
R2430
R2429
PCI_FW_REQ_L
PCI_REQ1_L
PCI_REQ2_L
R2432
R2431
R2433
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
INT_PIRQE_L
INT_PIRQF_L
ODD_PWR_EN_L
R2437
R2436
R2438
R2439
R2440
R2441
R2442
=PP3V3_S0_SB_PCI
1
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
SB PCI, PCIe, DMI, USB

SYNC_MASTER=T9_MLB
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
23
76
01
24B3 22D7 22D2 7D4

7D1
NO_REBOOT_MODE
1
R2506
10K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2550
R2552
R2547
R2505 1
R2507
10K
10K
10K
10K
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2532 2
R2510
10K
OMIT
U2300
74A3
BI
73A3 47A8
BI
73A3 47A8
BI
SMB_CLK
SMB_DATA
CLINK_WLAN_RESET_L
SMB_ME_CLK
SMB_ME_DATA
IN
PM_RI_L
73A3 47D8
BI
73A3 47D8
BI
24A5
46B4 44C5 6C2
OUT
44B8 27C5
IN
15B6
RI*
AC17
PM_SUS_STAT_L
PM_SYSRST_L
F4
AD15
AG12
LINDACARD_GPIO
BGA
SUS_STAT*/LPCPD*
SYS_RESET*
OUT
AG18
STP_PCI*/GPIO15
STP_CPU*/GPIO25
BI
PM_CLKRUN_L
AH11
CLKRUN*/GPIO32
AE17
PCIE_WAKE_L
INT_SERIRQ
IN
37A5 24A5
IN
24B5
IN
44C5
IN
AC13
WAKE*
SERIRQ
THRM*
VR_PWRGD_CLKEN
AJ20
VRMPWRGD
TP_SB_TP7
AJ22
TP7
AF12
8B4
44B8
PM_THRM_L
PCI_PME_FW_L
TP_SB_GPIO6
AJ8
AJ9
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
AH9
AE16
24A5
24B5 8B4
OUT
OUT
24A5
24A7
8B4
OUT
LAN_PHYPC
EXTGPU_RST_L
SB_GPIO18
TP_SB_GPIO20
SB_SCLOCK
SATA_B_PWR_EN_L
FWH_MFG_MODE
SB_SATA_CLKREQ_L
SB_SLOAD
SB_SDATAOUT<0>
SB_SDATAOUT<1>
AC19
AG8
AH12
AE11
AG10
AH25
AD16
AG13
AF9
AJ11
AD10
TACH1/GPIO1 INT PU
TACH2/GPIO6 INT PU
TACH3/GPIO7 INT PU
GPIO8
GPIO12
TACH0/GPIO17 INT PU
GPIO18
GPIO20 INT PD
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ*/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO
IN
BI
POWER MGT
SMBALERT*/GPIO11
IN
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
IN
SPKR
NB_SB_SYNC_L
AJ13
MCH_SYNC*
TP_SB_TP3
AJ21
TP3
5%
1/16W
MF-LF
402
R2534
10K
5%
1/16W
MF-LF
402
RSVD_EXTGPU_LVDS_EN
SATA_B_DET_L
SB_GPIO36
SB_CRT_TVOUT_MUX_L
AJ12
AJ10
AF11
AG11
OUT
OUT
D
69A6
D3
SUS_CLK_SB
SLP_S3*
SLP_S4*
SLP_S5*
AG23
AD18
PM_SLP_S3_L
TP_PM_SLP_S4_L
PM_SLP_S5_L
S4_STATE*/GPIO26
AH27
PM_S4_STATE_L
PWROK
AE23
PM_SB_PWROK
IN
DPRSLPVR/GPIO16
AJ14
PM_DPRSLPVR
OUT
BATLOW*
AE21
PM_BATLOW_L
IN
24A5 44B8
PWRBTN*
C2
PM_PWRBTN_L
IN
44C8
LAN_RST*
AH20
PM_LAN_ENABLE
IN
44D8
RSMRST*
AG27
PM_RSMRST_L
IN
44C8
CK_PWRGD
E1
CLK_PWRGD
CLPWROK
E3
See note below

=SB_CLINK_MPWROK
SUSCLK
INT PU
AG9
AF21
IN
29A5 29D6 75B3
IN
29A5 29D6 75B3
OUT
45A8
OUT
33C7 35C7 44C5 45A6 58B7 62B8
OUT
44C5 45C3
OUT
OUT
33B7 44C5 65A6 65C4
27A6
15A6 59D8 70B3
28A4
IN
AJ25
TP_PM_SLP_M_L
F23
CLINK_NB_CLK
CLINK_WLAN_CLK
BI
15A3 74A3
BI
74A3
CL_DATA0
CL_DATA1
F22
CLINK_NB_DATA
CLINK_WLAN_DATA
BI
15A3 74A3
BI
74A3
SLP_M*
AE18
AF19
NOTE: DPRSLPVR HAS INT 20K PD ENABLED

AT BOOT/RESET FOR STRAPPING FUNCTION
PM_LAN_ENABLE must remain deasseted
until VccCL3_3, VccLAN3_3 and VccLAN1_05
have been up for at least 1ms.
R2524 1
100K
8B4
CL_CLK0
CL_CLK1
5%
1/16W
MF-LF
402
R2525
10K
5%
1/16W
MF-LF
402
=PP3V3_S0MWOL_SB_CLINK0
1
CL_VREF0
CL_VREF1
D24
74A3
AH23
74A3
AJ23
AJ27
CLINK_NB_RESET_L
OUT
15A3 74A3
C2500
INT PU
Test access required

for XOR chain testing.
AF22
AG19
1%
1/16W
MF-LF
402
ARB_DETECT_L
SB_GPIO10_CL1
SB_GPIO14_CL2
35B7 WOL_EN
BI
10%
16V
X5R
402
24A7
24A5
R2527
453
0.1uF
AJ24
R2526
SB_CLINK_VREF0
SB_CLINK_VREF1
1
CL_RST*
MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9
7C4
3.24K
INT PD
MISC
15A3
AD9
10K
SB_CLK14P3M_TIMER
SB_CLK48M_USBCTLR
INT PU
SB_SPKR
R2533 2
5%
1/16W
MF-LF
402
G5
CLK14
CLK48
BMBUSY*/GPIO0
AG22
34B8 33C5
46B4 44C8 6C2
AF17
AG21
ICH8M
(4 OF 6)
AE20
46B4 24A7 6C2
46B6 44C5 37A5 6C2
AE19
SMBCLK
SMBDATA
LINKALERT*
SMLINK0
SMLINK1
AD19
PM_BMBUSY_L
IN
AJ26
PM_STPPCI_L
PM_STPCPU_L
29C2 28C4
5%
1/16W
MF-LF
402
R2535
10K
10K
SATA
GPIO
R2504
8.2K
CLOCKS
R2553
8.2K
CONTROLLER LINK
R2551
1K
SMB
R2502
R2500
SYS GPIO
OUT
=PP3V3_S0_SB_GPIO
=PP3V3_S5_SB_GPIO
29C2 28C4
2
2
1%
1/16W
MF-LF
402
24A5
NOSTUFF
R2523 1
100K
NOTE: ICH CLPWROK input must be PWRGD signal for

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CLPWROK to PWROK.
5%
1/16W
MF-LF
402
=PP3V3_S5_SB_CLINK1
1
C2501
TP_SB_GPIO6
10%
16V
X5R
402
24C5 8B4
EXTGPU_RST_L
35C7 26D8 24A3 7D1
SATA_B_PWR_EN_L
R2511
10K
R2514
5%
1/16W
MF-LF
402
R2515
NOSTUFF
1
A
2
R2512
24D5
10K
1%
1/16W
MF-LF
402
24B3
=PP3V3_S5_SB
0
5%
1/16W
MF-LF
402
R2544
PM_BATLOW_L
LAN_PHYPC
R2598
10K
1

SB_GPIO10_CL1
SB_GPIO14_CL2
SYNC_MASTER=T9_MLB
R2546
24B3
SB Pwr Mgt, GPIO, Clink
10K
1%
1/16W
MF-LF
402
24B3
8.2K
5%
1/16W
MF-LF
402
R2545
24C5
7D1 24A8 26D8 35C7
R2516
5%
1/16W
MF-LF
402
PM_RI_L
6C2 24D5 46B4
44B8 24C3
R2536
24C5
ARB_ONLY
1
10K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
FWH_MFG_MODE
LINDACARD_GPIO
ARB_DETECT_L
10K
1
10K
100K
5%
1/16W
MF-LF
402
PCI_PME_FW_L
1%
1/16W
MF-LF
402
R2530
1
R2531
37A5 24C5
453
2
1%
1/16W
MF-LF
402
=PP3V3_S5_SB
R2529
10K
1
PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE

24C5
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R2596
LAYOUT NOTE:
10K
0.1uF
7D4 22D2 22D7 24D8
R2597
24C5
R2528
3.24K
=PP3V3_S0_SB_GPIO
10K
1%
1/16W
MF-LF
402

SIZE
1%
1/16W
MF-LF
402
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
7C1
OF
24
76
01
7
6 uA S0-G3
A5
1 mA
L1
ICH8M
AA2
27D4 26A5 22D7
PP3V3_G3_SB_RTC
AD25
VCCRTC
K7
U2300
26D7
PP5V_S0_SB_V5REF
L13
A16
T7
(5 OF 6)
C14
D14
26C7
PP5V_S5_SB_V5REF_SUS
G4
26C6 26A4 23C2 22D7
AA25
G14
1 mA S0-S5
L26
V5REF_SUS
E14
F14
L27
AB1
657 mA
L4
AC11
L5
AA26
L11
AC14
M12
AA27
L12
AC25
M13
AB27
L14
AC26
M14
AB28
AC27
M15
AB29
AD17
M16
D28
AD20
M17
D29
M11
AD28
M23
E25
M18
AD29
M28
E26
P11
AD3
M29
E27
P18
AD4
M3
F24
T11
AD6
N1
F25
T18
CORE
L17
L18
AE1
N11
G24
U18
N12
H23
V17
AE2
N13
H24
V14
AE22
N14
J23
V11
AD1
N15
J24
U11
AE25
N16
K24
V18
AE5
N17
K25
AE6
N18
L23
AE9
N26
L24
AF14
N27
L25
AF16
N4
M24
AF18
N5
M25
AF3
N6
N23
AF4
P12
N24
AG5
V16
VCCA3GP
VCC1_5_B
V12
VCCDMIPLL
VCC_DMI
R29
PP1V5_S0_SB_VCCDMIPLL
26A6
23 mA
AE28
=PP1V25_S0_SB_DMI
7C7 26A6
50 mA
AE29
P13
N25
AG6
P14
P24
AH10
P15
P25
AH13
P16
R24
AH16
P17
R25
AH19
P23
R26
AH2
P28
R27
P29
T23
R11
T24
R12
T27
AH26
R13
T28
AH3
R14
T29
AH4
R15
U24
AA3
AH8
R16
W25
U7
AJ5
R17
V24
B11
R18
U25
B14
R28
Y25
B17
R4
V25
V23
VSS
B2
T12
B20
T13
B22
T14
B8
T15
C24
T16
C26
T17
47 mA
26D5
PP1V5_S0_SB_VCCSATAPLL
AJ6
VCCP CORE
AH22
AC23
1 mA
7D7 22D2 26C4
V_CPU_IO
AC24
VCC3_3
AF29
7D4 26A8
VCC3_3
AD2
7D4 26B8
AC8
7D4 26A6 26C6
7D4 26B4
7D4 26B4
AD8
VCC3_3
AE8
AF8
V7
IDE
AF28
L16
VCC1_05
AE12
VSS
1130 mA
7D7 26D2
C13
(6 OF 6)
V5REF
AB24
AH24
=PPVCORE_S0_SB
OMIT
OMIT
B13
L15
A25
A13
ICH8M
BGA
BGA
AA7
U2300
(VCC3_3 total)
A23
VCC3_3
W1
442 mA
W6
W7
Y7
VCCSATAPLL
A8
B15
26D5 7B7
AE7
B18
AF7
B4
AH7
C6
PCI
T2
C27
VCC1_5_A
ARX
AG7
B9
VCC3_3
C15
U12
D13
AJ7
D12
U13
D15
U14
D18
U15
D2
U16
U17
1080 mA
E21
U23
E24
U26
E4
U27
E9
U3
E10
AC1
AC2
AC3
VCC1_5_A
E7
F11
AC4
AC5
26C2 7B7
AC10
AC9
F15
U5
E23
V13
F28
V15
F29
V28
G12
F7
V29
G17
G1
W2
E2
W26
G10
W27
G13
Y28
G19
Y29
G23
Y4
G25
AB4
F1
G26
AB23
L6
G27
AB5
L7
H25
AB6
M6
H28
AD5
M7
H29
U4
26C2 7B6
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
AC12
7C4 26C4
VCCSUSHDA
AD11
7D1 26B2
J6
32 mA
11 mA S0,
1 mA S3-S5
VCC1_5_A
AA5
AA6
VCCHDA
VCCSUS1_05
AF20
TP_VCCSUS1_05_INTERNAL_REG1
VCCSUS1_5
AC16
VCCSUS1_5
J7
VCCSUS3_3
C3
VCC1_5_A
H7
7D1 26B6 26D2
AC7
D1
VCCPSUS
VCCUSBPLL
VCC1_5_A
W23
A2
J26
A28
J27
A29
J4
AH1
J5
TP_VCCLAN1_05_INTERNAL_REG1
TP_VCCLAN1_05_INTERNAL_REG2
AH28
19 mA S0,26B2 7C4
63 mA M1 & WOL
AJ1
K28
AJ2
K29
G18
VCCLAN1_05
C1
P2
VCCSUS3_3
G21
P4
SYNC_MASTER=T9_MLB
VCCCL3_3
C2600
R3
26B7
PP1V5_S0_SB_VCCGLANPLL
A24
80 mA
26A4
B27
VCCGLANPLL
AJ29
B28
B1
VCCGLAN1_5
B26
B29
A26
1 mA
7D4
B25
10%
6.3V
CERM
402
R6
VCCCL1_05
G22
1uF
R5
23 mA
C2601

0.1uF
2
20%
10V
CERM
402
TP_VCCCL1_05_INTERNAL_REG

VCCCL1_5
A22
VCCCL1_5V
F19
SIZE
VCCLAN3_3
19 mA S0,
51 mA M1 & WOL
7C4 26D3
G20
VCCGLAN3_3
D
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
P5
R1
A27
K6
SB Power & Ground
P3
F20
AJ28
K3
7D1 26D2
P7
AH29
VSS_NCTF
K23
117 mA S0,
44 mA S3-S5
P1
F17
GLAN POWER
J25
AC22
AG20
VCC1_5_A24
H6
A1
Current figures provided assume 1.5V.
N7
W24
J1
AC21
VCCSUS3_3
P6
VCCPUSB
H3
26B6 7B7
AC18
VCC1_5_A
USB CORE
AD7
10 mA
NOTE:
VccHDA and VccSusHDA can be 1.5V or 3.3V
depending on VIO of HD Audio interface.
VCC1_5_A
(VCCSUS3_3 total)
D4
ATX
(VCC1_5_A total)
D5
26C6 7B7
OF
25
76
01
8
7A7
39C8 7D4 =PP3V3_S0_SB

=PP5V_S0_SB
D2702
1/16W
MF-LF
402
5%
25B6 7B7
HN2S02JE
0.1UF
L2702
PLACEMENT NOTE:
PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
10%
2 16V
X5R
402
=PP1V5_S0_SB
C2702
CRITICAL
1
C2716
0.1UF
10%
2 16V
X5R
402
330UF
20%
2 2.5V
POLY
CASE-C2
C2731
PLACEHOLDER
FOR 270UF
0.1UF
C2734
0.1UF
10%
16V
2 X5R
402
PLACEMENT NOTE:
PLACE CAPS NEAR PINS
AC18..AH28
10%
16V
2 X5R
402
VOLTAGE=1.5V
10UH-100MA
26C8 26A8 7B7
C2718
0.1UF
L2702 MAY HAVE CHANGE TO 1.0UH PART
C2703
10%
2 16V
X5R
402
10%
6.3V
402
VOLTAGE=5V
7D7 25D3
OMIT
1UF
2 CERM
25D6
ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)
26B6 25A3 7D1
C2711
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS AE7..AJ7
PLACEMENT NOTE:
PLACE CAPS AT EDGE OF SB
ICH CORE/VCC1_05 BYPASS

(ICH CORE 1.05V PWR)
=PPVCORE_S0_SB
PP5V_S0_SB_V5REF
ICH VCC1_5_A/ARX BYPASS

(ICH LOGIC&IO[ARX] 1.5V PWR)
SOT-363
NC
100
ICH V5REF BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
R2702
PP1V5_S0_SB_VCCSATAPLL
0805
35C7 24A8 24A3 7D1
R2701
2
1/16W
MF-LF
402
5%
1UF
10%
6.3V
CERM
402
2 X5R
603
25A3 7C4
1
PLACEMENT NOTE:
PLACE CAP UNDER SB NEAR PINS
F19 AND G20
25D6
26A6 25C3 7D4
VOLTAGE=5V
0.1UF
10%
C2704
PLACEMENT NOTE:
PLACE C2704 < 2.54MM OF PIN G4 OF SB
C2713
=PP1V5_S0_SB
L2700 MAY HAVE CHANGE TO 0.5UH PART

ICH VCCA3GP(VCC1_5_B BYPASS
L2700
FERR-330-OHM-1.5A (ICH IO,LOGIC 1.5V PWR)
25B6 7B7
0805-1
2
10%
2 16V
X5R
402
25B3 7C4
VOLTAGE=1.5V
OMIT
CRITICAL NOSTUFF
1
C2700
220UF
20%
2 2.5V
POLY
CASE-B2
C2705
C2706
22UF
C2707
22UF
20%
6.3V
2 CERM
805
20%
6.3V
2 CERM
805
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AC1..AC5
2.2UF
ICH VCC1_5A BYPASS

(ICH LOGIC&IO 1.5V PWR)
1
C2721
0.1UF
25B6 7B7
402
PLACEMENT NOTE:
PLACE CAP NEAR PINS
AC10..AD7 OF SB
C2714
25C3 22D2 7D7
ICH USB CORE/VCC1_5_A BYPASS

(ICH USB CORE 1.5V PWR)
25B6 7B6
PLACEMENT NOTE:
PLACE CAPS NEAR PIN C2..AH28
M70 DOES NOT USE GIGABIT IN SB, SO NO NEED FOR PLL FILTERING
VOLTAGE=1.5V
25A6
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C2743
0.1UF
C2742
10UF
20%
2 6.3V
X5R
603
C2724
4.7UF
20%
6.3V
2 CERM
603
ICH IDE/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)
20%
2 6.3V
CERM1
603
ICH VCCUSBPLL BYPASS

(ICH USB PLL 1.5V PWR)
25C3 7D4
1
PLACEMENT NOTE:
PLACE C2715 NEAR PIN D1 OF SB
=PP1V5_S0_SB
C2738
C2712
0.1UF
10%
2 16V
X5R
402
25A6 7C4
C2725
0.1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS F20,G21
1/16W 5%
MF-LF 402
10%
16V
2 X5R
402
25B3 7D4
26C6 25C3 7D4
C2740
0.1UF
10%
2 16V
X5R
402
NEED CHANGE TO 1UH PART

L2703
ICH VCCDMIPLL BYPASS
1.0UH-0.5A-0.675A
(ICH DMI PLL 1.5V PWR)
1
2
PP1V5_S0_SB_VCCDMIPLL_F
PP1V5_S0_SB_VCCDMIPLL 25C3
25B3 7D1
C2709
0.1UF
10%
16V
2 X5R
402
NOSTUFF
PLACEMENT NOTE:
DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS A8 ... F11
C2726
0.1UF
10%
2 16V
X5R
402
C2727
0.1UF
10%
2 16V
X5R
402
C2728
0.1UF
10%
2 16V
X5R
402
C2701
0.01UF
10%
2 16V
CERM
402
25C3 7C7
0.1UF
10%
=PP1V25_S0_SB_DMI
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AE29
2 16V
X5R
402
MAKE_BASE=TRUE
25A6
SB Decoupling
SYNC_MASTER=WFERRY
C2730
1
10%
16V
X5R 2
402
C2739
C2729
0.1UF
10%
2 16V
X5R
402
PLACEMENT NOTE:
PLACE CAP NEAR PIN B27..A26
C2736
4.7uF

20%
6.3V
2 CERM
603

22UF
20%
6.3V
2 CERM
805
SIZE
PLACEMENT NOTE:
PLACE CAPS NEAR PIN AD25 OF SB
D
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
0.1UF
10%
16V
2 X5R
402
0.1UF
C2737
C2741
26C6 25D6 23C2 22D7
ICH VCCRTC BYPASS

(ICH RTC 3.3V PWR)
PP3V3_G3_SB_RTC
10UF
A
PLACEMENT NOTE:
PLACE CAP < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AF29
PLACEMENT NOTE:
OR 3.56MM ON PRIMARY NEAR PIN AD11
C2708
20%
6.3V
2 X5R
603
27D4 25D6 22D7
VOLTAGE=1.5V
1007
PLACEMENT NOTE:
PLACE CAPS < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY
ICH VCC3_3/VCCHDA BYPASS

(ICH INTEL HDA CORE 3.3V PWR)
PLACEMENT NOTE:
PLACE C2709 NEAR PIN B27 OF SB
VOLTAGE=1.5V
ICH PCI/VCC3_3 BYPASS

(ICH PCI I/O 3.3V PWR)
ICH VCC3_3 BYPASS

(ICH IO BUFFER 3.3V PWR)
0.1UF
L2703
R2700
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS AA3...Y7
C2715
0.1UF
25C3 7D4
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS F1..M7
PLACEMENT NOTE:
OR 3.56MM ON PRIMARY NEAR PIN AD2
10%
2 16V
X5R
402
402
2.2uF
25A6 7B7
0.1UF
10%
C2732
26D6 26C8 7B7
C2722
2 16V
X5R
NOSTUFF
25C3 7D4
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
PP1V5_S0_SB_VCCGLANPLL
PLACEMENT NOTE:
PLACE CAPS < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN A24
C2723
0.1UF
C2720
0.1UF
ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)
1
C2710
10%
2 16V
X5R
402
ICH V_CPU_IO BYPASS

(ICH CPU I/O 1.05V PWR)
1UF
10%
2 6.3V
CERM
402
PLACEMENT NOTE:
PLACE NEAR PINS AC23,AC24 OF SB
26D2 25A3 7D1
10%
2 16V
X5R
20%
6.3V
2 CERM1
603
PLACEMENT NOTE:
PLACE C2700 & C2705-07 < 2.54MM OF SB
DISTRIBUTED BETWEEN AA25..V23
4.7uF
20%
6.3V
2 CERM
603
ICH VCC1_5_A/ATX BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)
22D7 23C2 25D6 26A4
C2733
ICH VCCHDA BYPASS

(ICH INTEL HDA CORE 3.3V/1.5V PWR)
0.1UF
PLACEMENT NOTE:
OR 3.56MM ON PRIMARY NEAR PIN AC12
26A8 7B7
26D6
PLACEMENT NOTE:
PLACE CAP NEAR PINS
P6..R6
ICH VCC3_3 BYPASS

(ICH IO BUFFER 3.3V PWR)
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AH11
C2719
402
10%
2 16V
X5R
402
25A3 7D1
16V
2 X5R
SOT-363
0.1UF
ICH USB/VCCSUS3_3 BYPASS

(ICH SUSPEND USB 3.3V PWR)
ICH VCC_PAUX/VCCLAN3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)
D2702
PP5V_S5_SB_V5REF_SUS
1
C2717
10UF
HN2S02JE
NC
10
C2735
20%
6.3V
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AJ6
=PP5V_S5_SB
2
7C1
ICH V5REF_SUS BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
=PP3V3_S5_SB
OF
26
76
01
Platform Reset Connections

Unbuffered
D2800
7B1
HN2S02JE
=PP3V42_G3H_SB_RTCSOT-363
1
PP3V3_G3C_SB_RTC_D PP3V3_G3_SB_RTC
5
2
67C6 23A6
22D7 25D6 26A5
MAKE_BASE=TRUE
NC
IN
R2886
100
PLT_RST_L
MAKE_BASE=TRUE
R2887
0
C2810
1UF
10%
HN2S02JE
R2800
20K
SOT-363
4
3
PPVBATT_G3C_RTC_R
R2807
1K
PPVBATT_G3C_RTC
NC
22D8
5%
1/16W
MF-LF
402
OUT
7D4
C2805
Buffered
2
1
22D8
TMDS_RST_L
68B5
D
AIRPORT_RST_L
33C3
CRITICAL
2 6.3V
CERM
402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
=PP3V3_S0_RSTBUF
1UF
10%
R2806
1M
VOLTAGE=3V
SB_RTC_RST_L
15B6
5%
1/16W
MF-LF
402
R2885
0
1
5%
1/16W
MF-LF
2402
1
2
VOLTAGE=3V
2 NC
CRITICAL
J2800
78171-0002
M-RT-SM
3
NC
2 6.3V
CERM
402
D2800
RTC Battery Connector
NB_RESET_L
5%
1/16W
MF-LF
402
SB_SM_INTRUDER_L
OUT
1
C2880
0.1UF
5 TC7SZ08AFEF
SOT665
U2880Y
B
R2880
100K
R2881
0
1
5%
1/16W
MF-LF
402
DEBUG_RESET_L
Linda Card represents 3 loads
6C2 46B6
R2883
100
1
5%
1/16W
MF-LF
2402
20%
10V
CERM 2
402
518S0519
PLT_RST_BUF_L
SMC_LRESET_L
44C8
ENET_RESET_L
34B8
5%
1/16W
MF-LF
402
R2801
0
1
5%
1/16W
MF-LF
402
SB RTC Crystal Circuit

C
22D8
SB_RTC_X1
SB_RTC_X1_R
5%
1/16W
MF-LF
402
1
R2809
10M
5%
1/16W
MF-LF
4022
=PP3V3_S5_SB_PM
1
R2897
10K
C2808
10PF
R2810
0
1
7D1
CRITICAL
1
Y2800
32.768K
7X1.5X1.4-SM
197S0219
5%
50V
CERM
402
R2896
12B4 9C6
1K
2
XDP_DBRESET_L
IN
1 XDP_DBRESET_L_R
44B8
24D5
OMIT
5%
1/16W
MF-LF
402
C2809
10PF
5%
1/16W
MF-LF
4022
I59
R2898
100K
This part is never stuffed,
5%
1/16W
it provides a set of pads
MF-LF
4022
on the board to short or
to solder a reset button.
1
2
SB_RTC_X2
Change
Y2800 to 197S019 -7.0mmx1.5mmx1.4mm
5%
In CLOSE=12.5pF
50V
22D8
CERM
402
PM_SYSRST_LOUT
MAKE_BASE=TRUE
Silk: "SYS RST"
CPU VCORE PSI

MAKE_BASE=TRUE
CPU_PSI_L
9A2
27B6 7D4
=PP3V3_S0_SB_PM
27B8 7D4
1
C2811
0.1UF
1
C2807
0.1UF
20%
10V
CERM 2
402
VCC
OUT
VR_PWRGD_CK505
4
U2803 A
SON
PM_SB_PWROK
VR_PWRGD_CK505_L
IN
R28121
MAKE_BASE=TRUE
R2802
10K
0 2
5%
CLINK_MPWROK1
1/16W
OUT
24C3
59C7
GND
1
R2803
100K
8B3 8B1
5%
1/16W
MF-LF
4022
5%
1/16W
MF-LF
402
OUT
R2811
1.8K
5%
1/16W
MF-LF
2402
TC7SZ08AFEF 5 CRITICAL
2
SOT665
A
YTC7SH00FEF
U28011
B
59C7 15B6
58A3 44D8 6B2
VR_PWRGOOD_DELAY
IN
ALL_SYS_PWRGD IN
MF-LF
402 2
CK410_PD_VTT_PWRGD_L
Initial resistor values are based on CRB,

but may change after characterization.
Pulled a new APN for U2803(0.6mm max

2-input NAND gate-APN:311S0304
It may take a few days before this is done through
This will allow us to sequence this part under wireless card
59C7
20%
10V
CERM 2
402
5 CRITICAL
8B3
IMVP6_PSI_L
=PP3V3_S0_SB_PM
SB Misc
SYNC_MASTER=NB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
27
76
01
SELIGO RECOMMEND TO REMOVE L2903,R2900,C2907,C2910

R2901,L2902,C2916,C2911,C2914 and R2902
PP3V3_S0_CK505_VDD48
ORIGINAL DESIGN:
USE 155S0302 FOR L2902(R2906) AND L2903(R2907)
STUFF C2907,C2910,C2916,C2911,C2914
USE 2.2OHM FOR R2900,R2901 AND 1OHM FOR R2902
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V
R2901
R2906
C2909
0.1UF
10%
2 16V
X5R
402
5%
1/16W
MF-LF
402
NOSTUFF
C2910
10UF
5%
1/16W
MF-LF
402
20%
2 6.3V
X5R
603
=PP3V3_S0_CK505
7C4 28C8 28D8 29B2 29D2
NOSTUFF
1
C2911
1UF
10%
2 6.3V
CERM
402
D
L2901
28D3 28C8 7C4

29D2 29B2
FERR-120-OHM-1.5A
1
2
PP3V3_S0_CK505_VDD_CPU_SRC
=PP3V3_S0_CK505
VOLTAGE=3.3V
0402-LF
C2900
C2901
1UF
10UF
10%
6.3V
CERM 2
402
0.1UF
20%
6.3V 2
X5R
603
R2907
0
PP3V3_S0_CK505_VDDA_R
VOLTAGE=3.3V
PP3V3_S0_CK505_VDD_PCI
C2902
C2903
0.1UF
10%
2 16V
X5R
402
C2904
0.1UF
10%
2 16V
X5R
402
C2905
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
NOSTUFF
VOLTAGE=3.3V
C2906
C2912
0.1UF
0.1UF
0.1UF
10%
16V
2 X5R
402
10%
2 16V
X5R
402
10%
16V
2 X5R
402
C2913
R2900
0
C2914
10UF
20%
2 6.3V
X5R
603
R2902
PP3V3_S0_CK505_VDDA
VOLTAGE=3.3V
5% MIN_LINE_WIDTH=0.5mm
1/16W MIN_NECK_WIDTH=0.2mm
MF-LF
402
5%
1/16W
MF-LF
402
PP3V3_S0_CK505_VDD_REF
VOLTAGE=3.3V
1
NOSTUFF
1
C2907
10UF
20%
2 6.3V
X5R
603
C2908
0.1UF
NOSTUFF
C2915
0.1UF
10%
2 16V
X5R
402
10%
16V
2 X5R
402
1
1
C2916
10UF
5%
1/16W
MF-LF
402
20%
2 6.3V
X5R
603
18PF
5%
2 50V
CERM
402
C2990
49
61
67
12
17
28
35
18PF
5%
50V
2 CERM
402
CRITICAL
U2900
38
39
CK505_XTAL_IN
CK505_XTAL_OUT
29D2 29B2 28D8 28D3 7C4
(EACH POWER PIN PLACED ONE 0.1UF)

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
VDD_SRC
C2989
VDD_REF
VDD_PCI
5X3.2-SM
VDD_CPU
VDD_48
14.31818
43
CRITICAL
Y2901
NEED TO CHECK CAP VALUE
=PP3V3_S0_CK505
29B8
IN
PCI_STOP*
CPU_STOP*
SLG2AP101
QFN
VDD_A
VSS_A
56
55
PM_STPPCI_L
PM_STPCPU_L
IN
24C8 29C2
IN
24C8 29C2
CK505_CPU0_N
CK505_CPU0_P
OUT
6C7 29D6 75D3
CPU_0
44
45
OUT
6C7 29D6 75D3
CPU_1_MCH*
CPU_1_MCH
41
42
CK505_CPU1_N
CK505_CPU1_P
OUT
6C7 29D6 75D3
OUT
6C7 29D6 75D3
CPU_ITP*/SRC_10*
FS_B/TEST_MODE
CPU_ITP/SRC_10
36
37
OUT
6C7 29D6 75D3
OUT
6C7 29D6 75D3
57 PCI_1
SRC_0*/LCD_CLK*
58 PCI_2
SRC_0/LCD_CLK
63 PCI_3
SRC_1*
64 PCI_4
SRC_1
65 PCI_5/FCT_SEL
(NO INT PD)
CLKREQ_1*
(INT
PU)
68 PCIF_0/ITP_EN
(NO INT PU)
SRC_2*
1
11
10
OUT
6C7 29C6 75C3
OUT
6C7 29C6 75D3
OUT
8C4
51
50
8
CK505_FSB_TEST_MODE
XTAL_IN
XTAL_OUT
CPU_0*
(FROM ICH8M GPIO15 STPPCI* )

(FROM ICH8M GPIO25 STPCPU* )
(CPU HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(ITP HOST 133/167MHZ)
R2903(FW
10K
5%
1/16W
MF-LF
2 402
75D3 29B6
OUT
PCI 33MHZ)
(TPM LPC 33MHZ)
(SMC LPC 33MHZ)
(PCI SLOT)
(PORT80 LPC 33MHZ)
75D3 29B6
OUT
75D3 8C4
OUT
75D3 29A6
OUT
75D3 8C4
75D3 29B2
OUT
BI
CK505_PCI1_CLK
CK505_PCI2_CLK
CK505_PCI3_CLK
CK505_PCI4_CLK
CK505_PCI5_FCTSEL1
CK505_PCIF0_CLK
(ICH8M PCI 33MHZ)
75D3 29B6 6C7
OUT
CK505_PCIF1_CLK
PCIF_1
SRC_2
14
13
9
16
15
CK505_LVDS_N
CK505_LVDS_P
TP_CK505_SRC1_N
TP_CK505_SRC1_P
CK505_SRC_CLKREQ1_L
CK505_SRC2_N
CK505_SRC2_P
OUT
8C4
IN
29C2
OUT
6C7 29C6 75C3
OUT
6C7 29C6 75C3
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

(SLOT F - GPU PCI-E 100 MHZ )
(ICH8M DMI 100 MHZ )
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(ICH SM BUS)
47D6
47D6
IN
BI
=SMBUS_CK505_SCL
=SMBUS_CK505_SDA
CK505_PGMODE
47
48
SCL
SDA
SRC_3*
SRC_3
CLKREQ_3*
(INT PU)
28A4
(INT PU)
SRC_4*
NOSTUFF
1
R2905
0 = VTT_PWRGD#/PD
1 = CKPWRGD/PD#
475
1%
1/16W
MF-LF
U2900 HAS INTERNAL PU ON PGMODE
2 402
475 OHM FOR CK410M

COMPATIBILITY
STUFF R2905 FOR CK410M MODE
SRC_4
CLKREQ_4*
VSS_48
TP_CK505_SRC3_N
TP_CK505_SRC3_P
CK505_SRC_CLKREQ3_L
22
21
20
CK505_SRC4_N
CK505_SRC4_P
SB_CLK100M_SATA_OE_L
(INT PU)
46
VSS_CPU
62
66
VSS_PCI
SRC_5*
SRC_5
52
VSS_REF
31
VSS_SRC
69
19
18
59
CLKREQ_5*
24
23
60
OUT
CK505_SRC5_N
CK505_SRC5_P
NB_CLKREQ_L
SRC_6*
SRC_6
CLKREQ_6*
(INT PU)
SRC_7*
SRC_7
THRM_PAD
CLKREQ_7*
SRC_8*
SRC_8
CLKREQ_8*
27
26
25
TP_CK505_SRC7_N
TP_CK505_SRC7_P
CK505_PGMODE
32
33
34
CK505_SRC8_N
CK505_SRC8_P
=ENET_CLKREQ_L
OUT
IN
OUT
OUT
(SLOT D - 4 LANE PCI-E FOR EXPRESSCARD)
6C7 29C6 75C3

6C7 29C6 75C3
(ICH SATA 100 MHZ)
8B3
(FROM ICH8M GPIO35)
6C7 29C6 75C3

6C7 29C6 75C3
(GMCH G_CLKIN 100 MHZ )
15A3
(FROM GMCH CLK_REQ*)
6C7 29B6 75C3

6C7 29C6 75C3
IN
33C5
OUT
8C4
OUT
8C4
(WIRELESS PCI-E 100 MHZ )

(DB400 SRC )
28B5
7
6
CK505_DOT96_27M_N
CK505_DOT96_27M_P
CKPWRGD/PD*
CLK_PWRGD
4
54
53
CK505_USB48_FSA
CK505_CLK14P3M_TIMER
CK505_REF1
48M/FS_A
REF_0/FS_C/TEST_SEL
GPU_STOP*
OUT
IN
DOT_96*/27M_SS
DOT_96/27M
(INT PD)
29C2
OUT
CK505_SRC6_N
CK505_SRC6_P
CK505_SRC_CLKREQ6_L
30
29
40
8C4
IN
OUT
(INT PU)
8C4
OUT
OUT
OUT
IN
OUT
OUT
IN
6B7 29B6 75C3
6C7 29B6 75D3
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
6C7 29B6 75D3
24C3
OUT
29D8 75D3
OUT
29D8 75D3
BI
(SLOT E )
6B7 29B6 75C3

8C4 34B8
(FROM ICH8M)
(ICH8M USB 48MHZ)
(ICH8M,SIO,LPC REF. 14.318MHZ)
Clock (CK505)
FCTSEL1
0
1
PIN 6
PIN 7
DOT96T
DOT96C
27M NON
SPREAD
27M
SPREAD
PIN 10
100MT_SST
SRCT0
SYNC_MASTER=DSIMON
PIN 11
100MC_SST
SRCC0
* FOR INT. GRAPHIC SYSTEM

* FOR EXT. GRAPHIC SYSTEM

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
28
76
01
IN
CK505_USB48_FSA
33
CLK Termination
R3032
75D3 28A4
SB_CLK48M_USBCTLR
OUT
24D3 29A5 75B3
5%
1/16W
MF-LF
402
R3000
R3033
1
75D3 28C4 6C7
2.2K 2
CK505_FSA
CK505_CPU0_P
75D3 28C4 6C7
IN
FSB_CLK_CPU_P
5%
1/16W
MF-LF
402
29C8 75B3
5%
1/16W
MF-LF
402
IN
CK505_CPU0_N
75D3 28A4
IN
33
SB_CLK14P3M_TIMER
OUT
75D3 28C4 6C7
IN
CK505_CPU1_P
75D3 28C4 6C7
IN
CK505_CPU1_N
10K
75D3 28C4 6C7
CK505_FSC
IN
5%
1/16W
MF-LF
402
75D3 28C4 6C7
IN
5%
1/16W
MF-LF
402
29A8 75B3
7C7 13B7 29B6 29C6
75D3 28B4 6C7
IN
CK505_LVDS_P
1K
(TO MCH FS_A)

70B3 15C6
OUT
NB_BSEL<0>
R3081
1
1K
5%
1/16W
MF-LF
2 402
R3082
CK505_FSA
(TO ICH8M USB 48MHZ)
1K
5%
1/16W
MF-LF
402
R30831
IN
CK505_LVDS_N
CPU_BSEL<0>
IN
75C3 28B4 6C7
IN
CK505_SRC2_P
75C3 28B4 6C7
IN
CK505_SRC2_N
5%
1/16W
MF-LF
402 2
75C3 28B4 6C7
IN
CK505_SRC4_P
IN
CK505_SRC4_N
7C7 13B7 29B6 29C6
IN
CK505_SRC5_P
75C3 28B4 6C7
IN
CK505_SRC5_N
1K
70B3 15C6
OUT
NB_BSEL<1>
R3085
1
1K
OUT
75C3 28B4 6C7
IN
IN
CK505_SRC6_P
R3086
0
5%
1/16W
MF-LF
402
R3087
1K
75C3 28A4 6B7
CPU_BSEL<1>
IN
IN
CK505_SRC8_P
75C3 28A4 6B7
IN
CK505_SRC8_N
75D3 28A4 6C7
B
IN
IN
CK505_DOT96_27M_P
OUT
NB_BSEL<2>
75B3 29D6
CK505_DOT96_27M_N
NOSTUFF
75D3 28B8
IN
CK505_PCIF0_CLK
75D3 28B6 6C7
IN
CK505_PCIF1_CLK
75D3 28B6
IN
CK505_PCI1_CLK
R3091
1K
5%
1/16W
MF-LF
402
CPU_BSEL<2>
IN
9A4 70B3
(FROM CPU FS_C)
8B1 75B3
OUT
10K
PM_STPPCI_L
OUT
5%
1
2
402
MF-LF
10K
PM_STPCPU_L
R3047
5%
1
2
402
MF-LF
23C2 75B3
(ICH8M DMI 100MHZ)

SB_CLK100M_DMI_N
OUT
23D2 75B3
SB_CLK100M_SATA_P
OUT
22B6 75B3
28B4
10K
CK505_SRC_CLKREQ1_L
OUT
NOSTUFF
R3050
5%
1
1/16W
402
22B6 75B3
10K
CK505_SRC_CLKREQ3_L
NOSTUFF
R3051
5%
1
1/16W
402
MF-LF
NB_CLK100M_PCIE_P
2
OUT
PCIE_CLK100M_MINI_P
2
OUT
15C3 75B3
OUT
33C5 75B3
(WIRELESS PCI-E MINI 100MHZ)

PCIE_CLK100M_MINI_N
PCIE_CLK100M_ENET_P
2
15C3 75B3
(GMCH PEG/DMI 100MHZ)

NB_CLK100M_PCIE_N
OUT
33C5 75A3
OUT
34C8
(FOR YUKON 100MHZ)

PCIE_CLK100M_ENET_N
OUT
29D2 28D8 28D3 28C8 7C4
=PP3V3_S0_CK505
NOSTUFF
34C8
R3067
10K
5%
1/16W
MF-LF
2 402
NB_CLK96M_DOT_P
R3025
33
33
OUT
8B1 75B3
(Int GFX DOT 96MHZ)

NB_CLK96M_DOT_N
OUT
75D3 28B6
BI
CK505_PCI5_FCTSEL1
8B1 75B3
5%
1/16W
MF-LF
402
R3066
10K
5%
1/16W
MF-LF
2 402
(PORT80 LPC 33MHZ)
PCI_CLK33M_LPCPLUS
OUT
6C2
46C4 75C3
PCI_CLK33M_SB
OUT
23A6
29A5 75B3
PCI_CLK33M_FW
OUT
29A5
37A5 75B3
PCI_CLK33M_SMC
OUT
29A5
44C8 75B3
R3027
33
5%
1/16W
MF-LF
402
(TO ICH8M PCI 33MHZ)

(TO FIREWIRE PCI 33MHZ)
IN
CK505_PCI3_CLK
33
(TO SMC PCI 33MHZ)
5%
1/16W
MF-LF
402
75B3 29D6 24D3
NOSTUFF R3082, R3086, R3090

FOR MANUAL CPU FREQUENCY
75B3 29D6 24D3
75B3 37A5 29B3
Place close to CLK Gen

For reducing noise coupling to wireless frequencies
PCI_CLK33M_SMC
PCI_CLK33M_SB
SB_CLK48M_USBCTLR
SB_CLK14P3M_TIMER
PCI_CLK33M_FW
Clock Termination
SYNC_MASTER=DSIMON-WF
NOSTUFF
1
CPU speed is currently set to 200MHz
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
C3000 1 C3001 1 C3002 1 C3003 1 C3004

3.3PF
0.25%
2 50V
CERM
402
3.3PF
0.25%
2 50V
CERM
402
3.3PF
0.25%
2 50V
CERM
402
3.3PF
0.25%
2 50V
CERM
402

3.3PF
0.25%
2 50V
CERM
402

SIZE
D
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
MF-LF
(ICH8M SATA 100MHZ)

SB_CLK100M_SATA_N
R3023
1
R3046
1/16W
8A1 75B3
28B4
5%
1/16W
MF-LF
402
=PP3V3_S0_CK505
R3030
75D3 28B6
75B3 29B3 23A6
OUT
29B2 28D8 28D3 28C8 7C4
5%
1/16W
MF-LF
402
75B3 44C8 29A3
R3090
1
12B3
1/16W
R3019
R3028
5%
1/16W
MF-LF
402 2
FS_C FS_B FS_A CPU

0
0
0
266M
0
0
1
133M
0
1
1
166M
0
0
1
200M
1
1
0
400M
1
1
1
Resrvd
1
0
1
100M
0
1
0
333M
5%
1/16W
MF-LF
402
CK505_FSC
(ICH8M 14.318MHZ)
OUT
28C4 24C8
5%
1/16W
MF-LF
402
R3026
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
NB_CLK100M_DPLLSS_N
R3017
5%
1/16W
MF-LF
402
1K
70B3 15B6
7C7 13B7 29C6
R3088
1K
CLKREQ Controls
R3024
75D3 28A4 6C7
R3089
12B3
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
OUT
28C4 24C8
5%
1/16W
MF-LF
402
9A4 70B3
(FROM CPU FS_B)
13B3 75C3
(Int Gfx LVDS 100MHz)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CK505_SRC6_N
NB_CLK100M_DPLLSS_P
R3015
R3022
CK505_FSB_TEST_MODE
NOSTUFF
(TO MCH FS_C)
CPU_XDP_CLK_N
5%
1/16W
MF-LF
402
28C6
75C3 28B4 6C7
5%
1/16W
MF-LF
2 402
OUT
5%
1/16W
MF-LF
402
R3018
R3084
(TO MCH FS_B)
(ITP HOST 133/167MHZ)
5%
1/16W
MF-LF
402
CPU_XDP_CLK_P
R3011
1
5%
1/16W
MF-LF
402
13B3 75C3
SB_CLK100M_DMI_P
R3016
75C3 28B4 6C7
OUT
(GMCH HOST 133/167MHZ)
5%
1/16W
MF-LF
402
FSB_CLK_NB_P
5%
1/16W
MF-LF
402
R3014
75C3 28B4 6C7
9B6 75C3
R3007
9B4 70B3
(FROM CPU FS_A)
OUT
FSB_CLK_NB_N
5%
1/16W
MF-LF
402
R3010
5%
1/16W
MF-LF
402
75B3 29D6
75C3 28B4 6C7
5%
1/16W
MF-LF
402
R3080
FSB_CLK_CPU_N
R3005
R3006
NOSTUFF
5%
1/16W
MF-LF
402
R3004
R3035
R3003
1
9B6 75C3
(CPU HOST 133/167MHZ)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
24D3 29A5 75B3
5%
1/16W
MF-LF
402
R3002
R3034
OUT
R3001
OF
29
76
01
7
31D6 31D4 31B2 30D4 30B2 7B4
30D1
=PP1V8_S3_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MEM_VREF_A
1
C3120 1 C3100
2.2UF
20%
2 4V
X5R
402
0.1UF
20%
2 10V
CERM
402
72D3
MEM_A_DQS_N<0>
16C5 MEM_A_DQS_P<0>
72C3 16C5
72C3
72D3
72D3
MEM_A_DQ<3>
16D8 MEM_A_DQ<7>
72D3 16D8
72D3
72D3
16D8 MEM_A_DQ<1>
16D8 MEM_A_DQ<2>
16C8 MEM_A_DQ<8>
16C8 MEM_A_DQ<13>
72C3 16C5
72C3 16C5
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQ<9>
16C8 MEM_A_DQ<10>
72D3 16C8
72D3
MEM_A_DQ<24>
16C8 MEM_A_DQ<25>
72D3 16C8
72D3
72C3
72C3
16C5 MEM_A_DQS_N<3>
16C5 MEM_A_DQS_P<3>
72D3 16C8
72D3 16C8
72D3 16C8
72D3 16C8
72C3 16C5
MEM_A_DQ<31>
MEM_A_DQ<27>
MEM_A_DQ<23>
MEM_A_DQ<19>
MEM_A_DM<2>
NC
72D3 16C8
72D3 16C8
MEM_A_DQ<18>
MEM_A_DQ<21>
72D3 32D6 15D3
MEM_CKE<0>
72D3 32C6 16D5
MEM_A_BS<2>
NC
72D3 32C6 16B5

72D3 32C6 16B5
72D3 32C6 16B5
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
16B5 MEM_A_A<3>
16C5 MEM_A_A<1>
72D3 32C6 16B5

72D3 32C6
72D3 32C6
MEM_A_A<10>
16D5 MEM_A_BS<0>
16B5 MEM_A_WE_L
72D3 32C6 16B5

72D3 32C6
72D3 32B6
MEM_A_CAS_L
15D3 MEM_CS_L<1>
72D3 32B6 16D5

72D3 32D6
72D3 32D6 15C3
72D3 16B8
72D3 16B8
B
72C3 16C5
72C3 16C5
MEM_ODT<1>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQ<36>
16C8 MEM_A_DQ<33>
72D3 16B8
72D3
MEM_A_DQ<41>
16B8 MEM_A_DQ<42>
72D3 16B8
72D3
72C3 16C5
72D3
72D3
72D3
72D3
MEM_A_DM<5>
16B8 MEM_A_DQ<43>
16B8 MEM_A_DQ<46>
16B8 MEM_A_DQ<56>
16B8 MEM_A_DQ<57>
NC
MEM_A_DQS_N<7>
16C5 MEM_A_DQS_P<7>
72C3 16C5
72C3
MEM_A_DQ<59>
16A8 MEM_A_DQ<63>
72D3 16B8
72D3
MEM_A_DQ<52>
16B8 MEM_A_DQ<49>
72D3 16B8
72D3
72C3 16C5
72D3 16B8
31A7 31A3 7C4
72D3 16B8
=PPSPD_S0_MEM
1
1 C3121
C3122
2.2UF
0.1UF
20%
2 4V
X5R
402
20%
2 10V
CERM
402
MEM_A_DM<6>
MEM_A_DQ<51>
MEM_A_DQ<55>
=I2C_SODIMMA_SDA
47D6 =I2C_SODIMMA_SCL
47D6
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
OMIT
VREF
CRITICAL VSS0
VSS1
DQ0
DQ1
J3101 DQ4
DQ5
F-RT-TH3
VSS4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
CK0
CK0*
VSS12
DQ10
DQ11
VSS13
DQ14
DQ15
VSS14
VSS15
KEY
VSS16
VSS17
DQ16
DQ17
VSS18
DQ20
DQ21
VSS19
DQS2*
DQS2
NC0
DM2
VSS21
DQ18
DQ19
VSS22
DQ22
DQ23
VSS23
DQ24
VSS24
DQ28
DQ25
VSS25
DM3
DQ29
VSS26
DQS3*
NC1
VSS27
DQS3
VSS28
DQ26
DQ27
VSS29
DQ30
DQ31
VSS30
CKE0
VDD0
NC2
NC/CKE1
VDD1
NC/A15
BA2
VDD2
NC/A14
VDD3
A11
A7
A6
VDD4
A5
VDD5
A4
A3
A1
VDD6
A2
A0
VDD7
A10/AP
BA0
BA1
RAS*
WE*
VDD8
CAS*
S0*
VDD9
ODT0
NC/S1*
VDD10
NC/ODT1
NC/A13
VDD11
NC3
VSS31
DQ32
VSS32
DQ36
DQ33
VSS33
DQS4*
DQ37
VSS34
DM4
DQS4
VSS36
VSS35
DQ38
DQ34
DQ35
VSS38
DQ39
VSS37
DQ44
DQ40
DQ41
DQ45
VSS39
VSS40
DM5
VSS41
DQ42
DQ43
VSS43
DQ48
DQ49
DQS5*
DQS5
VSS42
DQ46
DQ47
VSS44
DQ52
DQ53
VSS45
NC_TEST
VSS47
VSS46
CK1
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
DQ50
DQ51
VSS50
DQ54
DQ55
VSS51
DQ56
VSS52
DQ60
DQ57
VSS53
DM7
DQ61
VSS54
DQS7*
VSS55
DQ58
DQ59
DQS7
VSS56
DQ62
VSS57
SDA
DQ63
VSS58
SCL
VDDSPD
516-0135
VSS2
DQS1*
DQS1
A12
A9
A8
=PP1V8_S3_MEM
=GND_CHASSIS_DIPDIMM_CENTER
SA0
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
202=GND_CHASSIS_DIPDIMM_LEFT
16D8 72D3
16D5 72C3
MEM_A_DQ<0>
MEM_A_DQ<6>
16D8 72D3
MEM_A_DQ<12>
MEM_A_DQ<14>
MEM_A_DM<1>
MEM_CLK_P<0>
MEM_CLK_N<0>
MEM_A_DQ<11>
MEM_A_DQ<15>
MEM_A_DQ<29>
MEM_A_DQ<28>
One 0.1uF per connector
16D8 72D3
31D2 20C8 17D7 15D2 7A4
R3100
1K
16C8 72D3
MEM_VREF_A
15D3 72D3
R3101
1K
16C8 72D3
1%
1/16W
MF-LF
2 402
16C8 72D3
16C8 72D3
16C8 72D3
16C5 72C3
Yellow uses 10K divider and TLV2463

to drive MCH and DIMM connectors.
(See Capell Valley pg 47)
16C8 72D3
16C8 72D3
Page Notes
16C8 72D3
16C8 72D3

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
16C5 72C3
MEM_A_DQ<20>
MEM_A_DQ<17>
16C8 72D3
MEM_CKE<1>
15D3 32D6 72D3
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_BS<1>
MEM_A_RAS_L
MEM_CS_L<0>
MEM_ODT<0>
MEM_A_A<13>
16C5 72C3

- =I2C_MEM_SCL
- =I2C_MEM_SDA
16C8 72D3
8B4
15C6 32C6 72D3
DDR2 Bypass Caps
16B5 32C6 72D3

16B5 32C6 72D3
(For return current)
16B5 32C6 72D3
31D6 31D4 31B2 30D6 30D4 7B4
=PP1V8_S3_MEM
16B5 32C6 72D3

16B5 32C6 72D3
16C5 32C6 72D3
4.7uF
20%
2 6.3V
CERM
603
16B5 32B6 72D3

15D3 32D6 72D3
15C3 32D6 72D3

16B5 32C6 72D3
C3110
MEM_A_DQ<44>
MEM_A_DQ<40>
MEM_A_DQ<47>
MEM_A_DQ<45>
MEM_A_DQ<60>
MEM_A_DQ<61>
C3114
16C5 72C3
16C8 72D3
16B8 72D3
16B8 72D3
16C5 72C3
0.1UF
C3115
C3116
2.2UF
0.1UF
20%
2 10V
CERM
402
20%
6.3V
2 CERM
402-LF
C3117
2.2UF
20%
6.3V
2 CERM
402-LF
C3130
C3131
2.2UF
C3132
2.2UF
20%
6.3V
2 CERM
402-LF
20%
6.3V
2 CERM
402-LF
16B8 72D3
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

when they get cheaper.
16A8 72D3
16A8 72D3
16C5 72C3
MEM_A_DQ<62>
MEM_A_DQ<58>
16B8 72D3
15D3 72D3
16A8 72D3
30A4
MEM_A_SA0
R3102
10K
1
DDR2 SO-DIMM Connector A
5%
1/16W
MF-LF
402
16B8 72D3
16B8 72D3
16C5 72C3
30A4
MEM_A_SA1
SYNC_MASTER=MEMORY
R3103
10K
1

5%
1/16W
MF-LF
402
16C5 72C3

16B8 72D3

16B8 72D3
SIZE
MEM_A_SA0
MEM_A_SA1
C3113
20%
10V
2 CERM
402
2 10V
CERM
402
16B8 72D3
MEM_A_DM<7>
MEM_A_DQ<50>
MEM_A_DQ<54>
20%
20%
2 10V
CERM
402
20%
6.3V
2 CERM
402-LF
16C5 72C3
15D3 72D3
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
C3112
16B8 72D3
MEM_CLK_P<1>
MEM_CLK_N<1>
MEM_A_DQ<48>
MEM_A_DQ<53>
0.1UF
20%
10V
2 CERM
402
16B8 72D3
2.2UF
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
C3111
0.1UF
0.1UF
MEM_A_DQ<32>
MEM_A_DQ<35>
16B8 72D3
30A4
30A4
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
8D8
ADDR=0xA0(WR)/0xA1(RD)
C3109
16D5 32C6 72D3
20%
10V
2 CERM
402
MEM_A_DM<4>

(NONE)
0.1UF
MEM_A_DQ<37>
MEM_A_DQ<34>
30D7
VOLTAGE=0.9V
1
15D3 72D3
8B1
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
1%
1/16W
MF-LF
2 402
16D5 72C3
MEM_A_DM<3>
MEM_A_A<15>
MEM_A_A<14>
=PP1V8_S3M_MEM_NB
16C8 72D3
DIMM_OVERTEMPA_L
MEM_A_DQ<16>
MEM_A_DQ<22>
DDR2 VRef
16D8 72D3
MEM_A_DM<0>
MEM_A_DQ<26>
MEM_A_DQ<30>
7B4 30B2 30D6 31B2 31D4 31D6
MEM_A_DQ<4>
MEM_A_DQ<5>
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84 NC
86 NC
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120 NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
5
DIP DIMM CONN201
DDR2-SODIMM-STD
OF
30
76
01
31D4 31B2 30D6 30D4 30B2 7B4
31D1
=PP1V8_S3_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MEM_VREF_B
1
1 C3200
C3220
2.2UF
0.1UF
20%
2 4V
X5R
402
20%
2 10V
CERM
402
MEM_B_DQ<1>
16D4 MEM_B_DQ<4>
72B3 16D4
72B3
72A3 16C1
72A3 16C1
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQ<7>
16D4 MEM_B_DQ<3>
72B3 16D4
72B3
72B3 16C4
72B3 16C4
72A3 16C1
72A3 16C1
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQ<10>
16C4 MEM_B_DQ<8>
72B3 16C4
72B3
MEM_B_DQ<17>
16C4 MEM_B_DQ<20>
72B3 16C4
72B3
72A3 16C1
72A3 16C1
72B3 16C4
72B3 16C4
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQ<22>
MEM_B_DQ<18>
72B3 16C4
MEM_B_DQ<29>
MEM_B_DQ<27>
72B3 16C1
MEM_B_DM<3>
72B3 16C4
NC
72B3 16C4
72B3 16C4
72B3 32D6 15D3
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_CKE<3>
NC
72B3 32A6 16D1
72B3 32A5
72B3 32B5
72B3 32B5
MEM_B_BS<2>
16B1 MEM_B_A<12>
16B1 MEM_B_A<9>
16B1 MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
16C1 MEM_B_A<1>
72B3 32B5 16B1

72B3 32B5 16B1
72B3 32B5
MEM_B_A<10>
16D1 MEM_B_BS<0>
16B1 MEM_B_WE_L
72B3 32B5 16B1

72B3 32A6
72B3 32A6
72B3 32A6 16D1

72B3 32D6 15C3
72B3 32D6 15C3
72B3 16B4
72B3 16C4
MEM_B_CAS_L
MEM_CS_L<3>
MEM_ODT<3>
MEM_B_DQ<38>
MEM_B_DQ<32>
MEM_B_DQS_N<4>
16C1 MEM_B_DQS_P<4>
72A3 16C1
72A3
MEM_B_DQ<39>
16B4 MEM_B_DQ<35>
72B3 16B4
72B3
72B3 16B4
72B3 16B4
72B3 16C1
MEM_B_DQ<47>
MEM_B_DQ<45>
MEM_B_DM<5>
MEM_B_DQ<44>
16B4 MEM_B_DQ<40>
72B3 16B4
72B3
MEM_B_DQ<48>
16B4 MEM_B_DQ<52>
72B3 16B4
72B3
NC
MEM_B_DQS_N<6>
16C1 MEM_B_DQS_P<6>
72A3 16C1
72A3
MEM_B_DQ<50>
16B4 MEM_B_DQ<55>
72B3 16B4
72B3
72B3 16B4
MEM_B_DQ<56>
MEM_B_DQ<57>
72A3 16C1
MEM_B_DM<7>
72B3 16B4
31A3 30A7 7C4
=PPSPD_S0_MEM
72B3 16A4
1 C3221
C3222
2.2UF
0.1UF
20%
2 4V
X5R
402
20%
2 10V
CERM
402
72B3 16A4
MEM_B_DQ<61>
MEM_B_DQ<63>
=I2C_SODIMMB_SDA
47C6 =I2C_SODIMMB_SCL
47C6
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
OMIT
VREF
CRITICAL VSS0
VSS1
DQ4
DQ0
J3201
DQ1
F-RT-TH3
VSS4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DQS1*
DQS1
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
CK0
CK0*
VSS12
VSS13
DQ10
DQ14
DQ11
DQ15
VSS14
VSS15
KEY
VSS16
VSS17
DQ16
DQ20
DQ17
DQ21
VSS18
VSS19
DQS2*
NC0
DQS2
DM2
VSS21
VSS22
DQ18
DQ22
DQ19
DQ23
VSS23
VSS24
DQ24
DQ28
DQ25
DQ29
VSS25
VSS26
DM3
DQS3*
NC1
DQS3
VSS27
VSS28
DQ26
DQ30
DQ27
DQ31
VSS29
VSS30
CKE0
NC/CKE1
VDD0
VDD1
NC2
NC/A15
BA2
NC/A14
VDD2
VDD3
A12
A11
A9
A7
A8
A6
VDD4
VDD5
A5
A4
A3
A2
A1
A0
VDD6
VDD7
A10/AP
BA1
RAS*
BA0
WE*
S0*
VDD8
VDD9
CAS*
ODT0
NC/S1*
VDD10
NC/A13
VDD11
NC/ODT1
VSS31
NC3
VSS32
DQ32
DQ36
DQ33
DQ37
VSS33
VSS34
DQS4*
DM4
DQS4
VSS35
DQ38
VSS36
DQ34
DQ39
DQ35
VSS37
VSS38
DQ44
DQ40
DQ45
DQ41
VSS39
VSS40
DQS5*
DM5
DQS5
VSS41
VSS42
DQ42
DQ46
DQ43
DQ47
VSS43
VSS44
DQ48
DQ52
DQ49
DQ53
VSS45
VSS46
NC_TEST
CK1
VSS47
CK1*
DQS6*
VSS48
DQS6
DM6
VSS49
VSS50
DQ50
DQ54
DQ51
DQ55
VSS51
VSS52
DQ56
DQ60
DQ57
DQ61
VSS53
VSS54
DM7
DQS7*
VSS55
DQS7
DQ58
VSS56
DQ59
DQ62
VSS57
DQ63
VSS58
SDA
SCL
SA0
VDDSPD
SA1
516-0135
=GND_CHASSIS_DIPDIMM_RIGHT
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84 NC
86 NC
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120 NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202=GND_CHASSIS_DIPDIMM_CENTER
=PP1V8_S3_MEM
5
DIP DIMM CONN201
DDR2-SODIMM-STD
7B4 30B2 30D4 30D6 31B2 31D6
MEM_B_DQ<5>
MEM_B_DQ<0>
DDR2 VREF (FOR CONNECTOR B)
16D4 72B3
One 0.1uF per connector
16D4 72B3
MEM_B_DM<0>
16D1 72B3
=PP1V8_S3M_MEM_NB
30D2 20C8 17D7 15D2 7A4
MEM_B_DQ<6>
MEM_B_DQ<2>
16D4 72B3
R3201
16D4 72B3
MEM_B_DQ<15>
MEM_B_DQ<11>
1K
1%
1/16W
MF-LF
2 402
16C4 72B3
16C4 72B3
MEM_VREF_B
MEM_B_DM<1>
MEM_CLK_P<3>
MEM_CLK_N<3>
MEM_B_DQ<9>
MEM_B_DQ<14>
MEM_B_DQ<21>
MEM_B_DQ<16>
DIMM_OVERTEMPB_L
16C4 72B3
16C4 72B3
Yellow uses 10K divider and TLV2463

to drive MCH and DIMM connectors.
(See Capell Valley pg 47)
16C4 72B3
8B1
16C4 72B3
MEM_CKE<4>
1%
1/16W
MF-LF
2 402
16C4 72B3
MEM_B_DQ<23>
MEM_B_DQ<19>
MEM_B_DQ<24>
MEM_B_DQ<26>
1K
15D3 72B3
16C1 72B3
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
R3202
15D3 72B3
MEM_B_DM<2>
MEM_B_DQ<25>
MEM_B_DQ<28>
Page Notes
16C4 72B3

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
16C4 72B3
16C4 72B3

- =I2C_MEM_SCL
- =I2C_MEM_SDA
16C1 72A3
16C1 72A3

(NONE)
16C4 72B3
16C4 72B3
NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.
15D3 32D5 72B3
MEM_B_A<15>
MEM_B_A<14>
D
31D7
VOLTAGE=0.9V
1
16D1 72B3
8B4
15C6 32A5 72B3
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
DDR2 Bypass Caps
16B1 32A5 72B3

16B1 32B5 72B3
(For return current)
16B1 32B5 72B3

31D6 31D4 30D6 30D4 30B2 7B4
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
=PP1V8_S3_MEM
16B1 32B5 72B3

16B1 32B5 72B3
C3209
16C1 32B5 72B3
4.7uF
MEM_B_BS<1>
MEM_B_RAS_L
MEM_CS_L<2>
20%
6.3V
2 CERM
603
16D1 32A6 72B3

16B1 32A6 72B3
15D3 32D6 72B3
MEM_ODT<2>
MEM_B_A<13>
15C3 32D6 72B3
C3210
16B1 32A5 72B3
0.1UF
MEM_B_DQ<41>
MEM_B_DQ<46>
MEM_B_DQ<53>
MEM_B_DQ<49>
MEM_CLK_P<4>
MEM_CLK_N<4>
MEM_B_DM<6>
0.1UF
16B4 72B3
C3214
C3215
0.1UF
C3216
20%
2 10V
CERM
402
20%
2 6.3V
CERM
402-LF
16B4 72B3
16C1 72A3
2 6.3V
CERM
16C4 72B3
2.2UF
20%
2 10V
CERM
402
16B4 72B3
C3217
2.2UF
20%
2 6.3V
CERM
402-LF
16B4 72B3
C3230
2.2UF
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
C3213
20%
2 10V
CERM
402
402
402
0.1UF
MEM_B_DQ<43>
MEM_B_DQ<42>
2 10V
CERM
16B4 72B3
16C1 72B3
MEM_B_DQ<34>
MEM_B_DQ<33>
C3212
20%
2 10V
CERM
402
MEM_B_DM<4>
0.1UF
20%
2 10V
CERM
MEM_B_DQ<36>
MEM_B_DQ<37>
C3211
0.1UF
20%
20%
402-LF
16C1 72A3
C3231
2.2UF
C3232
2.2UF
20%
20%
2 6.3V
CERM
2 6.3V
CERM
402-LF
402-LF
16B4 72B3
16B4 72B3
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

when they get cheaper.
16B4 72B3
16B4 72B3
15D3 72B3
15D3 72B3
16C1 72A3
MEM_B_DQ<51>
MEM_B_DQ<54>
MEM_B_DQ<60>
MEM_B_DQ<62>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_SA0
J3201_SA1
16B4 72B3
31A4
16B4 72B3
MEM_B_SA0
R3203
10K
1
DDR2 SO-DIMM Connector B
5%
1/16W
MF-LF
402
16A4 72B3
SYNC_MASTER=MEMORY
16C1 72A3
=PPSPD_S0_MEM

7C4 30A7 31A7
16C1 72A3
1
16B4 72B3
16B4 72B3
31A3
R3200
10K
5%
1/16W
MF-LF
2 402
SIZE
Resistor prevents pwr-gnd short
APPLE INC.
ADDR=0xA4(WR)/0xA5(RD)
16A4 72B3
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
31
76
01
One cap for each side of every RPAK, one cap for every two discrete resistors
BOMOPTION shown at the top of each group applies to every part below it
7D7
72D3 72B3 31B6 31B4 30B6 30B4 15D3 15C3
IN
MEM_CS_L<3..0>
0
1
15D3 31C4 72B3
D
IN
MEM_CKE<0>
MEM_CKE<1>
MEM_CKE<3>
MEM_CKE<4>
IN
MEM_ODT<3..0>
72D3 30C6 15D3
IN
72D3 30C4 15D3
IN
72B3 31C6 15D3
IN
72D3 72B3 31B6 31B4 30B6 30B4 15C3
0
1
2
3
72D3 30C6 30C4 30B6 30B4 16C5 16B5 15C6
IN
MEM_A_A<14..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
72D3 30C6 30B6 30B4 16D5
IN
MEM_A_BS<2..0>
0
1
2
=PP0V9_S3M_MEM_TERM
RP3300
R3301
RP3301
RP3302
56
56
56
56
3
1
2
4
6
2
7
5
RP3303
RP3304
RP3305
R3327
56 1
56 1
56 1
56 1
8
8
8
RP3300
R3309
RP3301
R3311
56
56
56
56
1
3
2
6
5% 1/16W SM-LF
5% 1/16WMF-LF402
5% 1/16W SM-LF
5% 1/16WMF-LF402
RP3307
RP3308
RP3307
RP3308
RP3307
RP3308
RP3307
RP3304
RP3308
RP3303
RP3309
RP3304
RP3303
R3325
RP3304
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
4
4
3
3
2
2
1
4
1
4
1
3
3
5
5
6
6
7
7
8
5
8
5
8
6
6
1
2
2
7
56
56
56
2
1
2
RP3309
RP3300
RP3303
7
8
7
5%
5%
5%
5%
1/16W SM-LF
1/16WMF-LF402
1/16W SM-LF
1/16W SM-LF
5%
5%
5%
5%
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W MF-LF402
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16WSM-LF
1/16WMF-LF402
1/16W SM-LF
5% 1/16W SM-LF
5% 1/16W SM-LF
5% 1/16W SM-LF
20%
10V
2 CERM
402
C3302
20%
10V
2 CERM
402
C3304
IN
72D3 30B6 16D5
IN
72D3 30B6 16B5
IN
RP3300
RP3309
RP3309
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
56
56
56
2
4
3
7
5
6
5% 1/16W SM-LF
5% 1/16W SM-LF
5% 1/16W SM-LF
0.1UF
C3306
C3308
0.1UF
0.1UF
C3310
0.1UF
0.1UF
20%
2 10V
CERM
402
IN
72B3 31B6 16B1
IN
72B3 31B4 16B1
IN
72B3 31B6 16B1
IN
72B3 31B4 16B1
IN
72B3 31B6 16B1
IN
72B3 31C4 16B1
IN
72B3 31C4 16B1
IN
72B3 31C6 16B1
IN
72B3 31C6 16B1
IN
72B3 31B6 16C1
IN
72B3 31C4 16B1
IN
72B3 31C6 16B1
IN
72B3 31B4 16B1
IN
IN
72B3 31C6 31B6 31B4 16D1
IN
MEM_B_BS<2..0>
0
1
2
72B3 31B4 16B1
IN
72B3 31B6 16D1
IN
72B3 31B6 16B1
IN
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
56 3
56 3
56 2
56 1
56 1
56 2
56 4
56 3
56 1
56 4
56 4
56 2
56 3
56 4
56 1
6
6
7
2
8
7
5
6
8
5
5
7
6
5
8
C3312
C3314
RP3302
RP3311
RP3305
56
56
56
1
4
2
8
5
7
RP3301
RP3302
RP3302
56
56
56
1
2
3
8
7
6
C3316
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16WMF-LF402
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16W SM-LF
1/16WSM-LF
1/16W SM-LF
1/16WSM-LF
5% 1/16W SM-LF
5% 1/16WSM-LF
5% 1/16W SM-LF
20%
10V
2 CERM
402
C3318
C3320
0.1UF
C3322
0.1UF
C3317
0.1UF
20%
10V
2 CERM
402
C3319
0.1UF
20%
10V
2 CERM
402
C3321
0.1UF
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3315
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3313
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3311
0.1UF
0.1UF
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED
TO PP0V9_S0_MEM_TERM
20%
2 10V
CERM
402
0.1UF
RP3311
RP3310
RP3311
R3335
RP3311
RP3310
RP3306
RP3306
RP3310
RP3305
RP3310
RP3306
RP3305
RP3301
RP3306
C3309
20%
10V
2 CERM
402
20%
2 10V
CERM
402
MEM_B_A<0>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<10>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<1>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
C3307
20%
10V
2 CERM
402
0.1UF
72B3 31B4 16C1
C3305
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3303
0.1UF
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
C3301
20%
10V
2 CERM
402
0.1UF
20%
10V
2 CERM
402
72D3 30B4 16B5
0.1UF
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
C3300
C3323
0.1UF
20%
2 10V
CERM
402
Memory Active Termination

5% 1/16WSM-LF
5% 1/16W SM-LF
5% 1/16W SM-LF
C3324
0.1UF
20%
10V
2 CERM
402
C3325
0.1UF
20%
10V
2 CERM
402

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
32
76
01
CRITICAL
Q3401
FDC638P
SM-LF
5%
1/16W
MF-LF
402
R3405
10K
PM_WLAN_EN_L
Q3402
D 6
2 G
S 1
SSM6N15FE
SOT563
Q3402
D 3
5 G
S 4
C3411
0.033UF3
10%
2 16V
X5R
402
PP3V3_S3_AP_AUX
C34081 C3407
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
VOLTAGE=3.3V
NOSTUFF
C3412
5%
1/16W
MF-LF
402
C3404
0.1UF
0.1UF
20%
10V
2 CERM
402
PM_WLAN_EN_L_SS
=PP1V5_S0_AIRPORT
1
C3405
0.1UF
20%
10V
2 CERM
402
7B7
C3406
0.1UF
20%
10V
2 CERM
402
R3404
100K
33D6 33C7 7C1
6
5
2
1
4
33D7 33C7 7C1
0.01UF
16V
402
10%
CERM
SSM6N15FE
SOT563
R3403
1/8W 805
5% MF-LF
62B8 58B7 45A6 44C5 35C7 24D3

57C4 45B3 44D5 38C6 35C7 6C1
PM_SLP_S3_L
SMC_ADAPTER_EN
PM_WLAN_EN_L1
CRITICAL
D 6
J3400
SSM6N15FE
SOT563
AS0B22-S45N-7F
F-ST-SM
54
2 G
S 1
34B8 24C8
PM_WLAN_EN_L2
5%
1/16W
MF-LF
402
R3406
100K
=PP3V3_S0_AIRPORT 2
NOSTUFF
Q3403
33D7 33D6 7C1
7D4
33B5
WOW_EN
ICH8 GPIO42
28B4
Q3403
D 3
SSM6N15FE
75A3 29B3
SOT563
OUT
OUT
IN
75B3 29C3 IN
1
3
5
7
9
11
13
PCIE_WAKE_L
CK505_SRC_CLKREQ6_L
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
15
5 G
S 4
74B3 33B5
65C4 65A6 44C5 24D3
74C3 33B5
PM_S4_STATE_L
74C3 33B5
OUT
OUT
PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
IN
IN
74C3 33B5
1
PCIE_E_R2D_C_P
C3400
1
2
0.1UF
CERM 402
2
0.1UF 20% 10V
CERM 402
20% 10V
PCIE_E_R2D_N
PCIE_E_R2D_P
C3401
PLACE CAPS < 250 MILS FROM (U2100) SB
23C8
SB_GPIO42
WOW_EN
33C7
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
KEY
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
C
27D1
AIRPORT_RST_L
IN
VOLTAGE=3.3V
7A4
C34091 C3410
10UF
20%
6.3V
2 X5R
603
0.1UF
20%
2 10V
CERM
402
402 1/16W
R3401MF-LF
5%
SMB_AIRPORT_CONN_CLK
SMB_AIRPORT_CONN_DATA
0
0
2
2
47C3
=SMB_AIRPORT_CLK
IO
47C3
=SMB_AIRPORT_DATA
IO
1/16W
R3402402
MF-LF 5%
=USB2_AIRPORT_N
IO
8C2 =USB2_AIRPORT_P
IO
8C2
SB HAS INTERNAL 15K PULL-DOWNS
53
MAKE_BASE=TRUE
23D5
23C5
23C5
23C5
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
PCIE_E_R2D_C_P
33C5 74B3
MAKE_BASE=TRUE
33B5 74C3
MAKE_BASE=TRUE
33B6 74C3
MAKE_BASE=TRUE
33B6 74C3
MAKE_BASE=TRUE
CONNECT TO M35 MODULE

Plexi: 516S0363
* Enclosure: 516S0406
AIRPORT CONN
A

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
33
76
01
Page Notes
- =PP3V3_ENET_PHY
(EC
/ Ultra)
- =PP1V8R2V5_ENET_PHY
(2.5V / 1.8V)
- =YUKON_EC_PP2V5_ENET
(2.5V / GND)
- =PP1V2_ENET_PHY
No link:
10 Mbps:
100 Mbps:
1000 Mbps:

- =ENET_CLKREQ_L (NC/TP for Yukon EC)
- =ENET_VMAIN_AVLBL
7B5 =PP1V2_ENET_PHY
Yukon Ultra
Yukon EC
171
179
203
426
mA
mA
mA
mA
No link:
10 Mbps:
100 Mbps:
1000 Mbps:
130
130
150
290
mA
mA
mA
mA
C3700
4.7UF
C3701
0.1UF
20%
6.3V
CERM 2
603
C3702
0.1UF
10%
2 16V
X5R
402
C3703
0.1UF
10%
16V
2 X5R
402
C3704
0.1UF
C3705
0.1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
10%
16V
2 X5R
402
C3706
0.001UF
10%
2 50V
CERM
402
C3707
0.001UF
C3708
0.001UF
10%
2 50V
CERM
402
10%
2 50V
CERM
402

YUKON_EC - Selects Yukon EC RSET value.
YUKON_ULTRA - Selects Yukon Ultra RSET.
7B5 =PP3V3_ENET_PHY
Yukon Ultra
Yukon EC
NOTE: Yukon IC and EEPROM are OMITted

on this page. Proper part numbers
must be called out elsewhere.
No link:
10 Mbps:
100 Mbps:
1000 Mbps:
NOTE: See bottom of page for

instructions for dual Yukon EC /
Yukon Ultra schematic support.
4
4
4
4
mA
mA
mA
mA
No link:
10 Mbps:
100 Mbps:
1000 Mbps:
60
70
70
80
mA
mA
mA
mA
C3710
4.7UF
C3711
0.1UF
20%
6.3V
CERM 2
603
C3712
0.1UF
10%
16V
2 X5R
402
C3713
0.1UF
10%
2 16V
X5R
402
C3714
0.001UF
C3715
0.001UF
10%
2 50V
CERM
402
10%
16V
2 X5R
402
10%
2 50V
CERM
402
L3720
FERR-120-OHM-1.5A
PCIE_ENET_D2R_P
C3735
OUT
PCIE_ENET_D2R_N
C3736
IN
PCIE_ENET_R2D_C_P
0.1UF
C3730
0.1UF
C3731
PCIE_ENET_R2D_C_N
0.1UF
2
10%
2
10%
16V
16V
X5R
X5R
0.1UF
PLACEMENT_NOTE=Place C3730 close to southbridge.
IN
2
10%
16V
X5R
402
2
10%
16V
X5R
402
C3724
0.001UF
EC:AVDD 2.5V
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
49 TX_P
50 TX_N
CRITICAL
U3700
402
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
88E8058
54 RX_P
QFN
53 RX_N
402
ANALOG
PLACEMENT_NOTE=Place C3731 close to southbridge.

29B3
IN
29B3
IN
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
28A4 8C4
OUT
=ENET_CLKREQ_L
33C5 24C8
OUT
PCIE_WAKE_L
IN
ENET_RESET_L
27C1
74B3 36B7
BI
74B3 36B7
BI
PCI EXPRESS
Yukon EC: Pin 42 should be NC (or TP) net.
42 CLKREQ*
BI
74B3 36C7
BI
LED
17 MDIP0
18 MDIN0
20 MDIP1
21 MDIN1
MEDIA
BI
74B3 36C7
BI
74B3 36C7
BI
ENET_MDI_P<2>
ENET_MDI_N<2>
TWSI
26 MDIP2
27 MDIN2
ENET_MDI_P<3>
ENET_MDI_N<3>
30 MDIP3
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
R3740
R3741
49.9
1%
1/16W
MF-LF
2 402
49.9
1%
1/16W
MF-LF
402 2
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
R3742
C3740
0.001UF
10%
50V
2 CERM
402
R3743
49.9
1%
1/16W
MF-LF
2 402
ENET_MDI0
1
49.9
1%
1/16W
MF-LF
402 2
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
12
9
VMAIN_AVLBL
47
SWITCH_VCC
11
R3744
49.9
1%
1/16W
MF-LF
2 402
ENET_MDI1
1
R3745
49.9
1%
1/16W
MF-LF
402 2
R3746
C3742
0.001UF
C3744
0.001UF
10%
50V
2 CERM
402
10%
50V
2 CERM
402
R3747
49.9
1%
1/16W
MF-LF
2 402
ENET_MDI2
49.9
CRITICAL
1%
1/16W
MF-LF
402 2
14 XTALO
C3746
C3750 1
0.001UF
15PF
5%
50V
CERM 2
402
NC
Must be high in S0 state (can use PP3V3_S0 as input)

=ENET_VMAIN_AVLBL
IN 8A3
NC
CTRL12
TP_YUKON_CTRL18
TP_YUKON_CTRL12
RSET
16
YUKON_RSET
LED_ACT*
LED_LINK10/100*
59
LED_LINK1000*
62
LED_DUPLEX*
63
(IPU)
SPI_DO
34
(IPU)
SPI_DI
SPI_CLK
35
(IPU)
60
37
(IPU)
SPI_CS
36
(IPU)
VPD_CLK
38
(IPU)
VPD_DATA
41
(IPD)
TESTMODE
46
RSVD_24
24
RSVD_25
RSVD_29
25
RSVD_43
43
MAIN CLK
29
R3765
4.99K
1%
1/16W
MF-LF
2 402
If characterization shows eye height is

too small, make R3765 smaller
NC
NC
NC
NC
YUKON_VPD_CLK
YUKON_VPD_DATA
NC
NC
NC
NC
VPD ROM
1
C3780
4.7K
10%
2 16V
X5R
402
NC
NC
16pF
C3751
15PF
5%
2 50V
CERM
402
VCC
E2
NC1 OMIT SDA
NC0 U3780 SCL
M24C08
WC*
R3781
4.7K
5%
1/16W
MF-LF
402 2
R37801
0.1UF
3
OUT
1
4
OUT
NC
NC
NC
NC
THRML_PAD
25.0000M
3
10%
50V
2 CERM
402
15 XTALI
Y3750
SM-3.2X2.5MM
ENET_MDI3
1
ENET_CLK25M_XTALI
ENET_CLK25M_XTALO
ENET_LOM_DIS_L
CTRL18
TEST/RSVD
31 MDIN3
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
VDD6 48
VDD7 58
10
65
BI
74B3 36C7
NC
NC
74B3 36B7
5%
1/16W
MF-LF
402 2
VAUX_AVLBL
SWITCH_VAUX
EC:CTRL25
5 PERST*
ENET_MDI_P<1>
ENET_MDI_N<1>
4.7K
YUKON_ULTRA
EC:NO CONNECT
6 WAKE*
ENET_MDI_P<0>
ENET_MDI_N<0>
R37601
LOM_DISABLE*
55 REFCLKP
56 REFCLKN
SPI
74B3 36C7
VDD5 44
10%
2 50V
CERM
402
VDD3 33
VDD4 39
10%
16V
2 X5R
402
VDD2 13
C3723
0.1UF
10%
16V
2 X5R
402
VDD0 2
VDD1 7
0.1UF
AVDDH 8
C3722
VDDO_TTL3 61
OUT
23C5
23C5
10%
16V
2 X5R
402
=YUKON_EC_PP2V5_ENET
Yukon EC:
Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps
Yukon Ultra: Alias to GND
23C5
23C5
C3721
0.1UF
20%
6.3V 2
CERM
603
VDDO_TTL1 40
VDDO_TTL2 45
4.7UF
NC_32 32
NC_51 51
8A4
C3720
(EC:2.5V)
mA
mA
mA
mA
AVDD3 28
No link:
0
10 Mbps:
30
100 Mbps:
40
1000 Mbps: 150
VDDO_TTL0 1
No link:
82 mA
10 Mbps:
108 mA
100 Mbps: 126 mA
1000 Mbps: 218 mA
PP1V8R2V5_ENET_PHY_AVDD
VOLTAGE=1.8V
AVDD1 22
AVDD2 23
2
0402-LF
AVDD0 19
Yukon Ultra (1.8V)
NC_57 57
NC_64 64
=PP1V8R2V5_ENET_PHY
NC_52 52
7B3
Yukon EC (2.5V)
5%
1/16W
MF-LF
2 402
5
6
SO8
CRITICAL
VSS
4
PART NUMBER
114S0285
QTY
DESCRIPTION
REFERENCE DES
RES,4.87K,1%,1/16W,0402,LF
R3760
CRITICAL
BOM OPTION
YUKON_EC
To support Yukon EC and Ultra on the same board:

-
Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps

Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY
Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)
Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part
Ethernet (Yukon)
SYNC_MASTER=USB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
34
76
01
35D4 7B6
PP3V3_ENET_FET
"ENET" = "S0" || AC
15K
5%
3.3V ENET FET
1/16W
MF-LF
2 402
CRITICAL
Q3810
R3801
5%
1/16W
MF-LF
2 402
35A3
Q3801
2 G
S 1
C3811
PM_ENET_EN_L
Q3801
D 3
5 G
S 4
R3810
10K
1
10%
2 16V
X5R
402
CRITICAL
R3824
33K
7B6 35D4
=PP1V9_ENET_REG
3
4
5
R3821
16.9K
27PF
50V
5%
CERM
402
NC
1%
1/16W
MF-LF
2 402
20%
2 6.3V
X5R
603
PP1V9_S3_FB
2 6.3V
CERM
402
R3822
C3823
10UF
30.1K
1%
1/16W
MF-LF
2 402
NOSTUFF
C3810
0.01UF
P3V3ENET_SS
7B4
35B2
C38221
NC
1UF
10%
5%
1/16W
MF-LF
2402
C3820
OUT1
OUT2
NR/FB
0.033UF
100K
D 6
SON
1 IN1
2 IN2
8 EN
GND THRM_PAD
PP3V3_ENET_FET
=PP3V3_S3_ENETPWRCTL
1.8A
0.085ohm
SOT-23
7A4
7A4
PP1V9_ENET_EN
NTR4101P
U3820
LREG_TPS79501DRB
R3823
1.9V ENET LDO
ENET Enable Generation
5%
1/16W
MF-LF
402
1
10%
16V
CERM
402
Vout = 1.2246V * (1 + R3821 / R3822)
SSM6N15FE
SOT563
SSM6N15FE
SOT563
PM_SLP_S3_L
IN
SMC_ADAPTER_EN
1.2V ENET LDO
26D8 24A8 24A3 7D1
=PP3V3_S5_SB
R3802
100K
5%
1/16W
MF-LF
2 402
24B3
Q3802
CRITICAL
D 6
SSM6N15FE
7B4
SOT563
2 G
35B2
S 1
WOL_EN
2
3
PP1V2_ENET_EN 1 EN
4
5
10
1 C3831
C3830
22UF
4.7UF
20%
6.3V
2 CERM
603
NC0
NC1
NC2
GND
20%
2 6.3V
CERM
805
U3830
SOP OUT0
IN0
IN1
MAX8516
57C4 45B3 44D5 38C6 33C7 6C1
PM_ENET_WOL_EN_L
IN
OUT1
8
9
FB
=PP1V2_ENET_REG 7B6
R3830
5.11K
1%
1/16W
MF-LF
2 402
PP1V2_S3_FB
THRML
PAD
R3831
11
62B8 58B7 45A6 44C5 33C7 24D3
C3832
4.7UF
20%
2 6.3V
CERM
603
3.65K
1%
1/16W
MF-LF
2 402
Name
PM_SLP_S3_L
Logic
S0
SMC_ADAPTER_EN PM_ENET_EN_L
PM_ENET_EN
AC
Yukon Power
Powered by S3
S0 on Battery
High (3.3V)
Low (0V)
Low (0V)
High (3.3V)
Power
S3 on Battery
Low (0V)
Low (0V)
High (3.3V)
Low (0V)
Power
B
35D1 7B4
S0 on AC
High (3.3V)
High (3.3V)
Low (0V)
High (3.3V)
Power
S3 on AC
Low (0V)
High (3.3V)
Low (0V)
High (3.3V)
Power
S5 on anything
N/A
N/A
N/A
N/A
No Power
=PP1V9_ENET_REG
R3832
100K
5%
1/16W
MF-LF
2 402
PP1V2_ENET_EN
35B3
Q3802
D 3
5 G
S 4
SSM6N15FE
SOT563
35C6
PM_ENET_EN_L
Yukon Power Control

SYNC_MASTER=USB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
35
76
01
D
L3950
FERR-120-OHM-1.5A
1
7B3 =PP1V8_S0_YUKON
PLACE ONE PAIR OF CAPS AT EACH PIN 3 AND 6 OF TRANSFORMERS
PP1V8_S0_YUKON_AVDD
0402-LF
1
C3900
C3904
10%
50V
2 CERM
402
10%
16V
2 X5R
402
C3901
0.1UF
0.001UF
0.1UF
10%
16V
2 X5R
402
C3905
0.001UF
10%
2 50V
CERM
402
C3902
0.1UF
10%
16V
2 X5R
402
C3906
0.001UF
10%
50V
2 CERM
402
C3903
0.1UF
C3907
ETHERNET CONNECTOR
0.001UF
10%
50V
10%
16V
2 X5R
402
2 CERM
402
OMIT
CRITICAL
CRITICAL
R3911
0
2
MF-LF
402
R3910
0
1
2
1
5%1/16W
74B3 34B8
IO
ENET_MDI_P<1>
74B3 34B8
IO
ENET_MDI_N<1>
5%1/16W
MF-LF
402
T3901
SM
1
ENET_MDI_R_P<1>
J3900
12
ENET_MDI_TRAN_P<1>
11
ENET_MDI_TRAN_N<1>
10
TX
R3909
2 0
MF-LF
402
R3908
1
2 0
1
5%1/16W
IO
ENET_MDI_P<3>
74B3 34B8
IO
ENET_MDI_N<3>
5%1/16W
MF-LF
402
1% 1/16W
6
ENET_MDI_R_N<3>
MF-LF
402
R3902
2 75
ENET_CENTER_TAP<3> 1
5
ENET_MDI_R_P<3>
SYM_VER-1
1
2
3
4
5
6
7
8
R3903
2 75
1% 1/16W
TLA-6T213LF
4
74B3 34B8
F-RT-TH
9
2
ENET_MDI_R_N<1>
3
RJ45-M71
MF-LF
402
ENET_MDI_TRAN_P<3>
ENET_MDI_TRAN_N<3>
10
RX
CRITICAL
74B3 34B8
IO
74B3 34B8
IO
R3907
1
2 0
5%1/16W
MF-LF
402
R3906
1
2 0
ENET_MDI_P<2>
ENET_MDI_N<2>
5%1/16W
MF-LF
402
1
ENET_MDI_R_N<2>
T3902
SM
2
ENET_MDI_R_P<2>
514-0443
10
IO
74B3 34B8
IO
R3905
1
2 0
5%1/16W
MF-LF
402
R3904
0
1
2
ENET_MDI_P<0>
ENET_MDI_N<0>
5%1/16W
MF-LF
402
ENET_MDI_TRAN_P<2>
R3901
2 75
1% 1/16W
TX
TLA-6T213LF
74B3 34B8
ENET_MDI_TRAN_N<2>
12
11
MF-LF
402
R3900
2 75
1% 1/16W
5
ENET_MDI_R_N<0>
MF-LF
402
ENET_MDI_TRAN_N<0>
6
ENET_MDI_R_P<0>
ENET_MDI_TRAN_P<0>
7
RX
ENET_BOB_SMITH_CAP
CRITICAL
1
C3910
1000PF
10%
2KV
2 CERM
1206
8C8
=GND_CHASSIS_RJ45
OUT
PLACE C3911 AND C3912

ON EACH SIDE OF J3900
C3911
0.001UF
10%
2 50V
CERM
402
C3912
0.001UF
10%
2 50V
CERM
402
TABLE_5_HEAD
CRITICAL
BOM OPTION
514-0443
PART#
QTY
DESCRIPTION
CONN,8P RJ-45 JACK,TH,MG3,LF
J3900
CRITICAL
NORMAL
514-0475
CONN,8P RJ-45 JACK,TH,BLACK,LF
J3900
CRITICAL
FANCY
TABLE_5_ITEM
TABLE_5_ITEM
ETHERNET CONNECTOR
SYNC_MASTER=USB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
36
76
01
PAGE NOTES
MOBILE TURNS OFF CONTROLLER POWER DURING SLEEP
0.001A DURING SLEEP
INPUT
=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)
=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)
PCI_GNT3_L - PCI GRANT FROM SB
PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE
PCI_RST_L - PCI RESET FROM SB
FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER
7A4
=PP3V3_S3_FW
PLACE ONE CAP PER TWO PINS STARTING WITH C4024 ON VDD0
1
C40241 C40181 C4022 1 C4026 1 C4028 1 C4030 1 C4032

10UF
20%
INPUT/OUTPUT
0.1UF
20%
2 10V
CERM
402
2 6.3V
X5R
PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,
PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L
FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS
FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS
FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS
603
L4000
600-OHM-300MA
OUTPUT
PCI_REQ3_L - PCI REQUEST TO SB

PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL
INT_PIRQD_L - INTERRUPT TO SB
PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)
0.1UF
0.1UF
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
0.1UF
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
PLACE ONE CAP PER TWO PINS STARTING WITH C4016 ON VDDA0
PP3V3_S3_FW_AVDD
VOLTAGE=3.3V
0402
1 C4017 1 C4029 1 C4025
C4016
0.1UF
0.1UF
0.1UF
10UF
20%
2 6.3V
X5R
603
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
PAGE HISTORY
FIRST REVISION OF PAGE
BGA VERSION OF FW323-06 ADDED
CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)
CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)
CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)
ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L
CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT
REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE
REMOVED C4421 - REDUNDANT
BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE
CONNECTED PIN E10 TO GND
7A4
=PP3V3_S3_PCI
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23B8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
74D3 23A8
IO
PCI_AD<19>
74D3 23A8
IO
1
R4031
22
5%
1/16W
MF-LF
4022
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23A8
IO
74D3 23B6
IO
74D3 23B6
IO
74D3 23B6
IO
74D3 23B6
IO
74D3 23A6
IO
74D3 23A6 23A4
IO
74D3 23A6 23A4
IO
74D3 23A6 23A4
IO
74D3 23A6 23A4
IO
74D3 23A6 23A4
OUT
R4032
100
IN
23A6
PCI_RST_L1
IN
74D3 23B5
IO
74D3 23A6 23A4
IO
74D3 23A6 23A4
IN
75B3 29B3 29A5
IO
46B6
44C5 24C8 6C2
1%
1/16W
MF-LF
402
74D3 23B6 23A4
OUT
OUT
74C3
23A8 23A4
24C5 24A5
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
PCI_C_BE_L<0>
K12
PCI_C_BE_L<1>M9
PCI_C_BE_L<2>L3
PCI_C_BE_L<3>L1
PCI_PAR
N10
PCI_FRAME_L N6
PCI_IRDY_L
M6
PCI_TRDY_L
N7
PCI_DEVSEL_L N8
PCI_STOP_L
M7
FW_PCI_IDSEL L2
PCI_FW_REQ_L E2
PCI_FW_GNT_L E1
PCI_PERR_L
M8
PCI_SERR_L
N9
PCI_CLK33M_FWG2
PM_CLKRUN_L D1
FW_PCI_RST_L F1
INT_PIRQD_L D2
PCI_PME_FW_L F2
A2
CRITICAL
VDDA5
74D3 23B8
VDDA4
VDDA3
74D3 23B8
IO
VDDA2
IO
VDDA1
VDDA0
74D3 23B8
VDD9
IO
F10
G10
H10
H12
J13
J12
K13
K10
L12
M13
L11
M12
M11
N12
M10
N11
M4
N5
N4
M3
M2
N3
K4
M1
K2
J4
K1
J2
J1
H2
H4
H1
VDD7
IO
74D3 23B8
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
VDD6
VDD5
74D3
23A8
IO
74D3 23B8
VDD4
IO
74D3 23B8
VDD3
VDD2
IO
VDD1
VDD0
G13
CONNECT TO VDD FOR 3.3V OPERATION
197S0030 3.2MMX2.5MM
D10
A13
B13
A7
A8
D6
G4
N1
N2
K5
K6
K7
L13
H13
5/19/2005
6/20/2005
6/21/2005
6/21/2005
6/21/2005
6/22/2005
6/22/2005
6/22/2005
6/22/2005
6/22/2005
7/26/2005
R4000
390
1
Y4003
SM-3.2X2.5MM
24.576MHZ
3
FW_XO_R 1
5%
1/16W
MF-LF
402
PCI_VIOS
2 4
1
C4011
15PF
PCI_AD0
PCI_AD1
CRITICAL
PCI_AD2
U4000
PCI_AD3
PCI_AD4
FW32306
PCI_AD5
PCI_AD6
XI
A5
FW_XI
XO
B5
FW_XO
5%
50V
CERM 2
402
PCI_AD7
RESET*
B4
PCI_AD8
PCI_AD9
A6
SPEC RECOMMENDS 2.49K
R0 B7
R1
PCI_AD11
PCI_AD12
NEED TO CHECK CRYSTAL LOAD CAPACITANCE
BGA
PCI_AD10
C4012
15PF
5%
2 50V
CERM
402
FW_PWRON_RST_L
1 C4020 1
R4020
R4052
0.1UF
510K
10%
2.1K
FW_R1
1%
1/16W
MF-LF
2 402
FW_R0
PCI_AD13
PCI_AD14
PCI_AD15
TPBIAS0
TPA0_P
PCI_AD16
PCI_AD17
TPA0_N
PCI_AD18
TPB0_P
TPB0_N
PCI_AD19
PCI_AD20
TPBIAS1
PCI_AD21
TPA1_P
TPA1_N
PCI_AD22
PCI_AD23
TPB1_P
PCI_AD24
TPB1_N
TPBIAS2
PCI_AD25
PCI_AD26
TPA2_P
TPA2_N
PCI_AD27
PCI_AD28
TPB2_P
TPB2_N
PCI_AD29
B8
A9
B9
B10
A10
D8
A11
B11
B12
A12
C13
C11
C12
D13
D12
38C6
38B6
38B6
38B6
38B6
8D2
8D2
8D2
8D2
8D2
8D2
8D2
8D2
8D2
8D2
FW_A_TPBIAS
FW_A_TPA_P
FW_A_TPA_N
FW_A_TPB_P
FW_A_TPB_N
FW_B_TPBIAS
FW_B_TPA_P
FW_B_TPA_N
FW_B_TPB_P
FW_B_TPB_N
FW_C_TPBIAS
FW_C_TPA_P
FW_C_TPA_N
FW_C_TPB_P
FW_C_TPB_N
5%
1/16W
MF-LF
2 402
2 16V
X5R
402
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PCI_AD30
PCI_AD31
PCI_CBE0*
PCI_CBE1*
PCI_CBE2*
PCI_CBE3*
PCI_PAR
MODE_420
MODE_A
PCI_FRAME*
PCI_IRDY*
PCI_TRDY*
PC0
PCI_DEVSEL*
PCI_STOP*
PC1
PC2
CONTENDER
PCI_IDSEL
CARDBUSN
MPCI_ACTN_323
PCI_REQ*
PCI_GNT*
PCI_PERR*
TEST0
PCI_SERR*
MANUFACTURING TEST
TEST1
PINS
PTEST
PCI_CLK
CLKRUN*
SE
SM
PCI_RST*
PCI_INTA*
C2
C1
A4
A3
B3
38C8
FW_PC0IO
FW_TEST0
FW_TEST1
FW_PTEST
1
1
FW_SE
R4036 R4037
47
1
FW_SM
5%
R4035 47
1/16W
5%
MF-LF
47
1
1/16W
R4034
1
5%
MF-LF
2402
R4033
402
1/16W
5%
1/16W
MF-LF
MF-LF
FIREWIRE CONTROLLER
SYNC_MASTER=ENETSYNC_DATE=08/30/2005
2 402

VSSA3
VSSA4
VSSA1
VSSA2
VSSA0
47
2 402

E13
E9
D9
D7
D5
VSS21
VSS22
VSS20
VSS18
VSS19
VSS17
VSS15
VSS16
VSS12
VSS13
VSS14
VSS11
VSS9
VSS10
VSS8
VSS6
VSS7
VSS4
VSS5
VSS3
A1
B2
C3
D4
E4
E5
F4
F6
F7
F8
G1
G6
G7
G8
H6
H7
H8
J5
J9
J10
K8
K9
N13
DUAL PORT DEVICES ARE POWER CLASS 4 (100)

SINGLE PORT DEVICES ARE POWER CLASS 0 (000)
LOW = NOT BUS MANAGER

LOW = PCI OPERATION
5%
1/16W
MF-LF
2 402
PLACE R4032 VERY CLOSE TO SB

VSS1
VSS2
E12
F13
F12
G12
B1
E10
MODE FOR EXTERNAL LINK
47
PCI_PME*
THIS IS FROM ICH-8
VSS0
M5
B6
SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
37
76
01
Page Notes
INPUT:
PPBUS_S5_FWPWRSW_F
=PPBUS_FW - PORT POWER
VOLTAGE=18.5V
=PP3V3_S5_FW - DIGITAL POWER

=GND_CHASSIS_FW_PORT0 - CHASSIS GROUND
CRITICAL
INPUT/OUTPUT:
FW_TPA0_P/N,FW_TPB0_P/N,FW_TPBIAS0 - FIREWIRE DIFF PAIRS
OUTPUT:
R43901
INITIAL REVISION
CHANGED DIFF PAIR NAMES TO MATCH REUSE
REMOVED CONSTRAINTS BECAUSE USING ALLEGRO CONST MANAGER
CONNECTED FW_PC0 FOR SINGLE PORT
UPDATED LATE-VG POWER RAIL CIRCUIT FROM M1
CHANGED CONNECTOR PORT NAMING TO PORT0
SWITCHED TO 514-0124 FOR PRE-PROTO CONNECTOR
REMOVED R4520 - IT HASNT BEEN STUFFED FOR MANY PRODUCTS
CHANGED FL4590 TO 1.1A VERSION
REMOVED ETHERNET LOW-POWER MODE CIRCUIT
UPDATED SIGNAL NAMES FOR FW PORT POWER ENABLE
VOLTAGE=16.5V
SM
CRS08
CRITICAL
C4310
10%
2 50V
CERM
402
10%
25V
2 X7R
402
R43911
3.3K
5%
1/16W
MF-LF
402 2
HN2D01JEF
FWPWR_EN_L
SOT665
R4394
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
45B3 44D5 35C7 33C7 6C1

57C4
10K
1
SMC_ADAPTER_EN
FWPWR_ACIN 1
5%
1/16W
MF-LF
402
Q4392
D 6
FWPWR_EN 2 G
S 1
SSM6N15FE
SOT563
"Snapback" & "Late VG" Protection
=PP3V3_S0_FW
NC
NC
7D4
R4395
470K
FWPWR_EN_AND
Q4392
D 3
5 G
S 4
SSM6N15FE
SOT563
5%
1/16W
MF-LF
2 402
PORT POWER CLASS

0 FOR SINGLE PORT
1 FOR DUAL PORT
OUT
PPFW_PORT0_VP
L4310
FERR-250-OHM
FWPWR_EN_L_DIV
Enables port power whenever

machine AC Adapter is plugged
or system at run state with battery only
D4391
37A3
C4390
0.01UF
5%
1/16W
MF-LF
402 2
CRITICAL
4.7K
PAGE HISTORY
-
VOLTAGE=16.5V
0.001UF
FW_PC0 - POWER CLASS IDENTIFIER (SINGLE PORT - TIE LOW)
5/19/05
6/22/05
6/22/05
6/22/05
7/26/05
7/26/05
7/26/05
7/26/05
7/26/05
7/26/05
7/26/05
PPFW_PORT0_VP_F
D4390
SM
6
5
2
1
MINISMDC
Cable Power
6B2
VOLTAGE=19V
FDC638P
SM-LF
1.1A-24V
7B1 =PPBUS_S5_FWPWRSW
PPFW_SWITCH
Q4390
CRITICAL
FL4390
=FWPWR_PWRON - ADDITIONAL POWER CONTROL
38A4
FW_PORTPWR_EN
FW_PC0
[LATE VG NOTES]
38A7
PP2V4_FWLATEVG
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
CRITICAL
D4320
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A 0.5V DROP
37B3
IO
FW_A_TPBIAS
CRITICAL
D4320
BAV99DW-X-F
1
1
R4300
R4301
56.2
56.2
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
C4320
0.01UF
SOT-363
5
C4321
0.01UF
10%
16V
CERM 2
402
C4300
0.33UF
10%
2 6.3V
CERM-X5R
402
BAV99DW-X-F
SOT-363
2
10%
16V
CERM 2
402
1394A
PORT 0
CRITICAL
FL4320
OMIT
J4300
CRITICAL
TCM2010-100-4P
FW_PORT0_TPA_P
SM
1394A
F-RT-TH3
FW_PORT0_TPA_N
FW_A_TPA_P
37B3 FW_A_TPA_N
37B3 FW_A_TPB_P
37B3 FW_A_TPB_N
FW_PORT0_TPA_P_FL
FW_PORT0_TPA_N_FL
37B3
IO
IO
IO
IO
R4302
CRITICAL
D4321
56.2
56.2
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
FW_PORT0_TPB
1
R4304
0.01UF
10%
4.99K
220PF
(TPA+)
TPO#
(TPA-)
TPI
(TPB+)
TPI#
(TPB-)
VP
VGND
7
C4323 1
FW_PORT0_TPB_N_FL
TPO
(GND_FW_PORT0_VGND)
SOT-363
5
0.01UF
10%
16V
CERM 2
402
1%
1/16W
MF-LF
2 402
5%
2 25V
CERM
402
C4322 1
C4301
(PPFW_PORT0_VP)
BAV99DW-X-F
SOT-363
2
FW_PORT0_TPB_P_FL
CRITICAL
D4321
BAV99DW-X-F
FW_PORT0_TPB_N
R4303
FW_PORT0_TPB_P
10%
2 50V
X7R
603-1
16V
CERM 2
402
514-0456
C4324 C4325 1
0.01UF
0.01UF
=GND_CHASSIS_FW_UPPER
10%
16V
CERM 2
402
=GND_CHASSIS_FW_DOWN
8A6
8C8
LATE-VG DETECTION CIRCUIT

38A8 7D1
R4350
330
=PP3V3_S5_FWLATEVG1
5%
1/16W
MF-LF
402
=PP3V3_S5_FWLATEVG
TABLE_5_HEAD
PART#
38C5
NO STUFF
1
C4352
VOLTAGE=3.3V
CRITICAL
0.001UF
D4350
SOT23
402
10%
50V
2 CERM
PP2V4_FWLATEVG
38A6 7D1
MMBZ5227B
R4352
R4351
10K
10K
1
5%
1/16W
MF-LF
2402
4
PP2V4_FWLATEVG_RC
-
5%
2 50V
CERM
402
CRITICAL
BOM OPTION
CONN,6P 1394A RCPT,MIDPLANE,MG3,LF
J4300
CRITICAL
NORMAL
514-0476
CONN,6P 1394A RCPT,MIDPLANE,BLACK,LF
J4300
CRITICAL
FANCY
TABLE_5_ITEM
5%
1/16W
MF-LF
2402
1SS418
2
FW_PORTPWR_EN
FIREWIRE PORT
38C5
SYNC_MASTER=GPU
SOD-723
PLACEHOLDER FOR SMALL PACKAGE DIODE

1
C4355

0.33UF
10%
2 6.3V
CERM-X5R
402
R4354
200K
1
80.6K
1%
1/16W
MF-LF
2402
D4351
LATEVG_EVENT_L 1
V-
NC
1
C4353
100PF R4353
SC70
1
V+
3
FWLATEVG_3V_REF
+
1
U4350
TLV7211
DESCRIPTION
514-0456
CRITICAL
2
QTY
TABLE_5_ITEM
R4356
2.0M
10%
2 16V
X5R
402
1%
1/16W
MF-LF
2402
C4354
0.1UF

1%
1/16W
MF-LF
402
SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
38
76
01
CRITICAL
Q4410
FDC606P
SOT-6
R4465
6
5
2
1
=PP5V_S5_PATA
7C1
26D8 7D4
R4425
ODD_PWR_EN_SLOW_START_L
10K
1
R4476
Q4475
10K
5%
1/16W
MF-LF
2 402
SSM6N15FE
SOT563
1
ODD_PWR_EN_SLOW_START
Q4475
5 G
2 ODD_PWR_EN_SLOW_START_R
5%
1/16W
MF-LF
402
D 6
SSM6N15FE
23A6 23A4
39A5
2 16V
X5R
402
NOSTUFF
C4476
0.1UF
1
5%
1/16W
MF-LF
402
16V
X5R
402
ODD_PWR_EN_L
C4475
73D3
ODD_RST_BUF_L
IDE_PDD<7>
22B4 IDE_PDD<6>
22B4 IDE_PDD<5>
22B4 IDE_PDD<4>
22B4 IDE_PDD<3>
22B4 IDE_PDD<2>
22C4 IDE_PDD<1>
22C4 IDE_PDD<0>
73D3
22B4 IDE_PDIOW_L
73D3
73D3
73D3
73D3
73D3
39A6
R4402
0
1
10K
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
4022
Per ATA Spec
1
CRITICAL
J4401
5-1775184-0
M-ST-SM
51
NC 2
NC 4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
NC38
40
42
44
46
48
50
39A7
ODD_PWR_RESUME
SB_GPIO40
23C8
NOSTUFF
73D3 22B4
73D3
ODD_PWR_EN_L_R
73D3 22A4
OUT
73D3 22B4
OUT
IDE_PDIORDY
IDE_IRQ14
IDE_PDA<1>
IDE_PDA<0>
22B4 IDE_PDCS1_L
73D3 22B4
5%
1/16W
MF-LF
402
73D3 22B4
NOSTUFF
1
C4404
10PF
CORE RAIL 5V
73D3
5%
50V
CERM 2
402
ODD detect need less than 100ms include OS latency

ODD_PWR_EN_L is OD and core well
7D4
R4420
R44241
100K
5%
1/16W
MF-LF
2 402
S 1
5%
1/16W
MF-LF
402
=PP3V3_S0_PATA
S 4
R4401
0
ICH8 GPIO5
ODD_PWR_EN_SLOW_START_L_R
10%
2 6.3V
CERM-X5R
402
G
=PP5V_S0_IDE_PATA
0.47UF
10%
SOT563
both pull up resistors 2

ODD_PWR_CORE
on SB page.
C4477
R4451
4.7K
R4477
330
D 3
0.1UF
10%
1/16W
MF-LF
2402
MAKE_BASE=TRUE
6.2K
5%
=PP3V3_S0_SB
PP5V_S0_IDE_PATA
VOLTAGE=5V
IDE_CSEL_PD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NC
52
NC
NC
R4453
33K
NC
5%
1/16W
MF-LF
2402
73D3
IDE_PDD<8> 22B4 73D3

IDE_PDD<9> 22B4 73D3
IDE_PDD<10> 22B4 73D3
IDE_PDD<11> 22B4 73D3
IDE_PDD<12> 22B4 73D3
IDE_PDD<13> 22B4 73D3
IDE_PDD<14> 22B4 73D3
IDE_PDD<15> 22B4 73D3
22A4 IDE_PDDREQ
This signal has integrated series resistor and pull down in ICH8M
OUT
IDE_PDIOR_L 22B4 73D3
IDE_PDDACK_L 22B4
SMC_ODD_DETECT
73D3
Indicates disk presence, to SMC
NC
IDE_PDA<2> 22B4 73D3
IDE_PDCS3_L 22B4 73D3
NC
516S0339
R4458
1
7A7
0
5%
=PP5V_S0_IDE_RESET
1/16W
MF-LF
2402
PER ATA SPEC
R4459
6.2K
5%
1/16W
MF-LF
2402
PER ATA7 SPEC
R4460
100K
5%
1/16W
MF-LF
2402
73D3
23B6 ODD_RST_5VTOL_L
ICH8 GPIO54
39C4
CRITICAL
1
2
MC74VHC1G09
SC70
U4401Y
ODD_RST_BUF_L
39C5
39C7
=PP5V_S0_IDE_PATA
R4461
1%
1/16W
MF-LF
402
24.9K2ODD_PWR_EN_L_B
2
ODD_PWR_EN_L_R
1
Q4420
MMDT3904XF
SOT-363-LF
ODD_POWER_DISCHARGE
R4462
PATA CONNECTOR
4.7
5%
1/16W
MF-LF
2 402

BLEED CIRCUIT TO DISCHARGE ODD POWER RAIL WHEN ODD IS DISABLED.

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
39
76
01
SATA CONNECTOR
PLACE L4501 NEAR J4501
CRITICAL
518S0390
1210-4SM1
CRITICAL
20
C4503
1
2
SATA_A_R2D_F_N
0.0047UF
402
CAPS TO BE SAME DISTANCE

FROM SB WITHIN EACH PAIR
73D3 22B6 SATA_A_R2D_C_P
IN
C4501
1
2
73D3 22B6
SATA_A_R2D_C_NIN
0.0047UF
402
SYM_VER-1
PLACE NEAR ICH8 PIN
CRITICAL
73D3
73D3
SATA_A_R2D_P
SATA_A_R2D_N
SATA_A_D2R_C_N
SATA_A_D2R_C_P
NC
C4502
1
2
402
402
73D3 22B6
SATA_A_D2R_N
MAKE_BASE=TRUE
SATA_A_D2R_P
22B6
SATA_RBIAS_N
OUT
22A6
SATA_RBIAS_P
OUT
SATA_RBIAS_PN
OUT
R4501
OUT
24.9
1%
SYM_VER-1
C4520
C4521
0.1UF
10UF
10%
22B6
SATA_A_D2R_F_P
2 16V
X5R
90-OHM-100MA
1210-4SM173D3
2
0.0047UF
402
=PP5V_S0_SATA 7A7
NOSTUFF
NOSTUFF
1
SATA_A_D2R_F_N
0.0047UF
73D3
73D3
L4502
C4500
1
2
1/16W
MF-LF
2402
PLACE L4502 NEAR SB
20%
2 6.3V
X5R
603
NC
NC
NC
SYSTEM (SLEEP) LED FILTER
21
8C7
SATA_A_R2D_F_P
3
J4501
20247-019E
F-ST-SM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VALUE=3900PF IN REFERENCE SCHEM
L4501
90-OHM-100MA
R4522
10
1
SYS_LED_ANODE_L
GND_CHASSIS_SATA
IR_RX_OUT 43C8
R4550
100
(TO IR RECEIVER)
PP5V_S3_SYSLED_F 1
1
C4550
4.7UF
20%
C
SATA DIFF PAIR GND VIAS
SYS_LED_ANODE 6B2
45A3
5%
1/16W
MF-LF
0.01UF 402
HOLE-VIA-P5RP25
GV4503
HOLE-VIA-P5RP25
GV4504
HOLE-VIA-P5RP25
GV4505
HOLE-VIA-P5RP25
GV4506
HOLE-VIA-P5RP25
C4522
10%
2 16V
CERM
402
GV4501
HOLE-VIA-P5RP25
1
PLACE R4522 AND C4522 NEAR J4501
=PP5V_S3_SYSLED
GV4502
GV4507
7A4 45A4
HOLE-VIA-P5RP25
5%
1/16W
MF-LF
402
GV4508
HOLE-VIA-P5RP25
1
PLACE R4550 AND C4550 NEAR J4501
2 6.3V
CERM
603
SATA CONNECTOR
A

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
40
76
01
USB 2.0 CONNECTORS

L4602
41D2
PP5V_S3_USB2_EXTA_F
VOLTAGE=5V
FERR-120-OHM-1.5A
2
0402-LF
OMIT
CRITICAL

ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS
J4600
USB-M71-MG3
F-RT-TH
5
CRITICAL
L4600 L4600 Monitor SMT for tombstone
90-OHM-100MA
TCM1005
SYM_VER-1
7C1
41A5
USB2_MUXED_EXTA_N
41A5
USB2_MUXED_EXTA_P
=PP5V_S5_USB
1
20%
6.3V
X5R
603
20%
10V
CERM
402
OMIT
R4650
1K
=EXTAUSB_OC_L
U4600
5%
TPS2060
MF-LF
C46501/16W
402
2 IN
0.47UF
10%
8
3
5
4
6.3V
2 CERM-X5R
402
1K
=EXTBUSB_OC_L
1
OC2*
0.01UF
C4603
514-0457
0.01UF
10%
2 16V
CERM
402
=GND_CHASSIS_USB3
LAYOUT NOTE:C4602,C4603 ARE EMC BY-PASS CAPS FOR J4600
41C4 41A4 41A2 8C8
=GND_CHASSIS_USB
PP5V_S3_USB2_EXTA
PP5V_S3_USB2_EXTB
VOLTAGE=5V
EN2*
VOLTAGE=5V
OC1*
OUT2
C4602
10%
2 16V
CERM
402
RCLAMP0502B
7
MSOP
EN1*
41C2 41A4 41A2 8C8
41B2
GND TPAD
R4651
8B2
OUT1
C4610
100UF
20%
2 6.3V
POLY
B2
CRITICAL
2 EXTAUSB_OC_F_L
VOLTAGE=0V
D4600
SC-75
CRITICAL
8C2
2
0402-LF
CRITICAL
1 VBUS
2 D3 D+
4 GND
6
FERR-120-OHM-1.5AMIN_LINE_WIDTH=0.6MM
0.1UF
2
PP5V_S3_USB2_EXTA_F
USB2_EXTA_F_N
USB2_EXTA_F_P
USB2_GND_EXTA_F
L4604
C4613 1 C4612
10uF
41D3
PP5V_S3_USB2_EXTB_F
L4603
FERR-120-OHM-1.5A
2 EXTBUSB_OC_F_L
5%
1/16W
MF-LF
402
2
0402-LF
OMIT
C4651
0.47UF
VOLTAGE=5V
CRITICAL
1
10%
2 6.3V
CERM-X5R
402
C4611
100UF
20%
2 6.3V
POLY
B2
65B6
PM_SLP_S4_LS5V
OMIT
CRITICAL

ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS
J4601
USB-M71-MG3
CRITICAL
F-RT-TH
5
L4601 L4601 Monitor SMT for tombstone
90-OHM-100MA
TCM1005
SYM_VER-1
8B2
=USB2_EXTB_N
8B2
=USB2_EXTB_P
41C3
1 VBUS
2 D3 D+
4 GND
PP5V_S3_USB2_EXTB_F
USB2_EXTB_F_N
USB2_EXTB_F_P
USB2_GND_EXTB_F
CRITICAL
D4601
SC-75
1
PLACE C4675 NEAR U4675
C4675
0.1UF
1
41C4 41C2 41A2 8C8
=PP3V42_G3H_SMCUSBMUX
20%
10V
CERM
402
1
7
46B4 45D5 44C5 44B8 6C2

46B6 45D5 44C5 44B8 6C2
D+A
D-A
1/16W
MF-LF
2402
41C4 41C2 41A4 8C8
8C2
=USB2_EXTA_P
=USB2_EXTA_N
2 D+B
6 D-B
41C5
41C5
VOLTAGE=0V
0402-LF
TQFN
CRITICAL
USB_DEBUGPRT_EN_L
SEL 10
8 OE*
USB EXTERNAL CONNECTORS

44B8
SEL=0 CHOOSE SMC

SEL=1 CHOOSE USB
GND
SYNC_MASTER=USB
5%
1/16W
MF-LF
402

R4670
1
=GND_CHASSIS_USB
FERR-120-OHM-1.5A
PI3USB10LP
8C2
514-0457
10%
2 16V
CERM
402
L4605
USB2_MUXED_EXTA_P
USB2_MUXED_EXTA_N
D+ 3
D- 5
C4607
0.01UF
LAYOUT NOTE:C4606,C4607 ARE EMC BY-PASS CAPS FOR J4601
RCLAMP0502B
10K
5%
U4675
R4677
SMC_RX_L
SMC_TX_L
C4606
0.01UF
10%
2 16V
CERM
402
=GND_CHASSIS_USB3
7B1
VCC

TABLE_5_HEAD
2 NOSTUFF
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION

TABLE_5_ITEM
R4671
514-0457
CONN,4P USB RCPT,MIDPLANE,MG3,LF
J4600,J4601
CRITICAL
NORMAL
514-0477
CONN,4P USB RCPT,MIDPLANE,BLACK,LF
J4600,J4601
CRITICAL
FANCY
SIZE
TABLE_5_ITEM
2 NOSTUFF
5%
1/16W
MF-LF
402
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
41
76
01
GEYSER AND DIMM0 REMOTE TEMP SENSORS
D
L4700
600-OHM-300MA
7A4
=PP5V_S3_GEYSER
2
0402
R4710
45D5 45C8 44C5
OUT
SMC_ONOFF_L
CONN_GEYSER_ONOFF_L
C4710
0.1UF
C4700
0.1UF
20%
2 10V
CERM
402
CONN_GEYSER_ONOFF_FLTR_L
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
1
1K
PP5V_S3_GEYSER_F
VOLTAGE=5V
PLACE C4700 NEAR J4700
20%
10V
CERM
402
CRITICAL
J4700
53307-1039
F-ST-SM
8C2
8C2
CONN_GEYSER_USB_N
=USB2_GEYSER_N
SYM_VER-1
TCM1005
90-OHM-100MA
L4701
CRITICAL
CRITICAL
D4700
SC-75
1
2
4
6
8
10
1
3
5
7
9
CONN_GEYSER_USB_P
=USB2_GEYSER_P
L4702
600-OHM-300MA
1
2 GEYSER_GND_F
0402
L4703
600-OHM-300MA
0402
1
SMC_LID_LC
516S0588
SMC_LID 6B2
44B5 45C5 57A8
C4703
0.01uF
10%
2 16V
CERM
402
VOLTAGE=0V
3
2
RCLAMP0502B
CONNECTOR MISC
SYNC_MASTER=USB SYNC_DATE=06/29/2006

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
42
76
01
BLUETOOTH
IR CYPRESS ENCORE II USB CONTROLLER
L4810
PLACE C4810 C4811 NEAR 120-OHM-0.3A-EMI

L4810
PLACE C4800 AND C4801
NEAR U4800 PIN 16
7A4
=PP3V3_S3_BT
2
0402-LF
R4803
7A4
=PP5V_S3_IR
5%
1/16W
MF-LF
402
20%
6.3V
2 X5R
603
C4802
C4804 C4801
0.1UF
0.001UF
1UF
10%
2 10V
X5R
402
C4810
10UF
PP5V_S3_IR_R
1
20%
2 10V
CERM
402
10%
2 50V
CERM
402
C4811
0.1UF
20%
2 10V
CERM
402
6A2
PP3V3_S3_BT_F
VOLTAGE=3.3V
CRITICAL
J4810
78171-0004
CRITICAL
16
TP_IR_P00
TP_IR_P01
TP_IR_P02
TP_IR_P03
TP_IR_P04
IR_RX_OUT_RC
R4800
40C6
IR_RX_OUT
100 2
1
5%
1/16W
MF-LF
402
C4803
0.001UF
10%
2 50V
CERM
402
7
6
5
4
3
2
1
32
9 P2_0
8 P2_1
C4803 CLOSE TO U4800 PIN 2
VDD
P0_0
P0_1
P0_2/INT0
P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
P0_7
P1_0/D+
P1_1/DP1_2/VREG
P1_3/SSEL
P1_4/SCLK
P1_5/SMOSI
P1_6/MISO
OMIT
P1_7
U4800
P3_0
CY7C63833
QFN
CRITICAL P3_1
14
15
18
20
23
24
25
26
USB2_IR_P_R
USB2_IR_N_R
ENCORE_VREG_C
1
M-RT-SM
5
L4812
R4801
=USB2_IR_P
5%
1/16W
MF-LF
402
8B2
=USB2_BT_N
1
2
3
4
USB2_BT_F_N
6C1 USB2_BT_F_P
6C1
=USB2_IR_N
8C2
8C2
5%
1/16W
MF-LF
402
C4800
SYM_VER-1
8C2
R4802
1
90-OHM-100MA
TCM1005
SB HAS INTERNAL 15K PULL-DOWNS
=USB2_BT_P
TO M13D SLOT

6
1UF
10%
6A2
2 10V
X5R
402
L4811
120-OHM-0.3A-EMI
1
21
22
GND_BT_F 518S0521
VOLTAGE=0V
0402-LF
27
28
29
NC
30
31
10
11
12 NC
17
19
33
13
VSS THRM_PAD
3G CONNECTOR
NOSTUFF
L4852
FERR-220-OHM-2A
7A7
=PP5V_S0_3G
PP5V0_S0_3G_F
0603
NOSTUFF
1
NOSTUFF
C4850
0.01UF
10%
C4851
0.01UF
10%
2 50V
X7R
402
NOSTUFF
CRITICAL
2 50V
X7R
402
J4850
LVC-D10SFYG
F-RT-SM
43A5 8D8
13
11
NOSTUFF
L4853
FERR-220-OHM-2A
1
GND_3G_F
0603
NOSTUFF
1
NOSTUFF
CRITICAL
C4852
L4855
0.01UF
10%
2 50V
X7R
402
43B5 8D8
90-OHM-100MA
TCM1005
SYM_VER-1
8C2
=USB2_3G_P
8C2
=USB2_3G_N
6C1
USB2_3G_F_P
USB2_3G_F_N
12
NOSTUFF
L4854
FERR-120-OHM-1.5A
1
6C1
1
2
3
4
5
6
7
8
9
10
14
IR CONTROLLER & BT INTERFACE
GND_CHASSIS_3G_CONN
0402

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
43
76
01
45C6
51B8 45D8 45D4 45C1 7C1
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
PP3V3_S5_AVREF_SMC
=PP3V42_G3H_SMC
C4902
22UF
20%
6.3V
CERM
805
C4903
C4904
C4905
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C4906
0.1UF
20%
10V
CERM
402
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
R4999
PP3V3_S5_SMC_AVCC
OUT
66A4 45B6 6C1
SMC_P20
44B4 SMC_P21
44B4 SMC_P22
44B4 SMC_P23
OUT
SMC_BATT_CHG_EN
OUT
44B4 SMC_P26
44B4 SMC_P27
46C6 22D4 6D2
BI
46C6 22D4 6D2
BI
46C4 22D4 6C2
BI
46C4 22D4 6C2
BI
46B6 22D4 6C2
IN
27C1
IN
75B3 29A5 29A3

46B4 24C8 6C2
44A4
45A6
47B3
44B4
46B6 45D5 44C5 41A8 6C2
IN
BI
OUT
47D6
IN
BI
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
K13
K14
D12
P65/KIN5*
P66/IRQ6*/KIN6*
C15
P17
P67/IRQ7*/KIN7*
J13
D13
P20
P70/AN0
N12
D14
P21
P22
P71/AN1
P72/AN2
R13
P73/AN3
P74/AN4
R14
E14
P23
P24
E15
P25
P75/AN5
R15
E13
P26
P27
P76/AN6
P77/AN7
N13
F14
K12
J12
P14
P15
(OC)
SMC_WAKE_SCI_L
SMC_P81
PM_CLKRUN_L
PM_SUS_STAT_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_S4_STATE_L
PM_SLP_S5_L
SMC_SUS_CLK
SMB_0_S0_DATA
6C1 33C7 35C7 38C6 45B3 57C4
45C5
46B4 45D7 6C2
IN
45D1
IN
48C1 59C7
IN
6B2 48B1
IN
44A4
IN
44A4
IN
66C2
45C5
45C7
IN
48D6
IN
66B1
IN
45B3
P81/GA20
A7
B7
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
C6
P86/IRQ5*/SCK1/SCL1
B6
P90/IRQ2*
K4
P91/IRQ1*
P92/IRQ0*
J2
B5
P40/TMIO
P41/TMO0
D5
P42/SDA1
P93/IRQ12*
J3
C3
P94/IRQ13*
P95/IRQ14*
J4
B1
P43/TMI1/EXSCK1
P44/TMO1
C2
P45
P96/EXCL
H1
D3
P97/IRQ15*/SDA0
G2
C1
P46/PWX0/PWM0
P47/PWX1/PWM1
G1
P50
44C8
G4
P51
P52/SCL0
44C8
P37/SERIRQ
A5
J1
H2
F2
OUT
24C8
OUT
6C2 24C8 37A5 46B6
IN
OUT
6C2 41A8 44B8 45D5 46B6
IN
6C2 41A8 44B8 45D5 46B4
27C5 24D5
41A5
OUT
OUT
15B7 8B2
BI
15B7 8B2
BI
57C8 45D5 6C1

24C3 24A5
BI
OUT
(DEBUG_SW_3)
PA1/KIN9*/PA2DD
PA2/KIN10*/PS2AC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
R2
OUT
39B2
48A8
IN
OUT
45C3
44B4
IN
OUT
45D5
IN
45D5
44B4
50B4 6D2
IN
OUT
OUT
44B4
OUT
44B4
OUT
44B4
IN
50C4 6D2
IN
44B4
IN
44A4 6A7
IN
51C2
IN
51C2
IN
51C2
IN
45C6
IN
61C5
IN
62C2
IN
44A4
IN
44A4
IN
R1
PA3/KIN11*/PS2AD
PA4/KIN12*/PS2BC
N2
PA5/KIN13*/PS2BD
N3
M4
N1
SMC_PB0
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
ISENSE_CAL_EN
SMC_EXCARD_CP
SMC_EXCARD_PWR_EN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
45C5
24C8
PA0/KIN8*/PA2DC
P3
BI
M3
M2
42C8 45C8 45D5
IN
6C1 45B6 57C3 57C7 66A6
IN
6D1 45C5 57A2
IN
24D3 33C7 35C7 45A6 58B7 62B8
IN
24D3 33B7 65A6 65C4
IN
24D3 45C3
IN
45A7
BI
PE3*/ETDO
PE4*/ETMS
L4
L2
PF0/IRQ8*/PWM2
M7
PF1/IRQ9*/PWM3
P6
PB0/LSMI*
PF2/IRQ10*/TMOY
PF3/IRQ11*/TMOX
A10
PB1/LSCI
PF4/PWM4
M6
D10
PB2
PB3
PF5/PWM5
PF6/PWM6
R5
C11
PB4
PB5
A12
PB6
D11
PB7
P5
PF7/PWM7
N5
PG0/EXIRQ8*/TMIX
PG1/EXIRQ9*/TMIY
P9
PG2/EXIRQ10*/SDA2
N9
R9
PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PG3/EXIRQ11*/SCL2
PG4/EXIRQ12*/EXSDAA
P8
G13
PC2/TIOCC0/TCLKA/WUE10*
PG5/EXIRQ13*/EXSCLA
M8
G12
PG6/EXIRQ14*/EXSDAB
PG7/EXIRQ15*/EXSCLB
P7
H14
PC3/TIOCD0/TCLKB/WUE11*
PC4/TIOCA1/WUE12*
H15
PC5/TIOCB1/TCLKC/WUE13*
H13
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
H12
M11
PD0/AN8
P11
PD1/AN9
PD2/AN10
R11
SMC_PF0
SMC_PF1
SMC_LID
SMC_PF3
SMC_BATT_ISET
SMC_BATT_VSET
SMC_SYS_ISET
SMC_SYS_VSET
N6
G15
G14
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
M1
B10
B11
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_1V8_ISENSE
ALS_LEFT
ALS_RIGHT
PE0
PE1*/ETCK
PE2*/ETDI
R6
A11
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
6C2 46B6
SMC_NMI
IN
6C2 46B4
M15
M14
A1
P1
P2
F1
VCL
R12
R4902
SMC_TRST_L
IN
6C2 46B6
R4998
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
C
GND_SMC_AVSS
44D8
47D6
44C8
SMC_P14
SMC_P20
SMC_P21
SMC_P22
SMC_P23
SMC_P26
SMC_P27
SMC_P46
SMC_P44
SMC_P43
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_P62
SMC_P63
SMC_P64
SMC_P81
SMC_PF1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
45B6 48A1 48B1 48C1 48C6 60B2 61C5 62C2 66B1 66C2
NC_SMC_P14
NC_SMC_P20
NC_SMC_P21
NC_SMC_P22
NC_SMC_P23
NC_SMC_P26
NC_SMC_P27
NC_SMC_P46
NC_SMC_P44
NC_SMC_P43
OMIT
U4900
SMC_H8S2116
BGA
U4900
SMC_H8S2116
BGA
L1
IN
47B3
IN
44C8
(2 OF 4)
ETRST*
SMC_MD1
SMC_KBC_MDE
44C8
R3
F4
5%
1/16W
MF-LF
402
OMIT
SMC_PA0
SMC_PA1
PM_SYSRST_L
USB_DEBUGPRT_EN_L
PM_EXTTS_L<0>
PM_EXTTS_L<1>
SYS_ONEWIRE
PM_BATLOW_L
NMI
SM
44B8
45C5
EXTAL
K1
XW4900
44C8
45C5
XTAL
B2
6C2 24D5 46B4
44C8
(DEBUG_SW_1)
(DEBUG_SW_2)
A2
E2
MD2
10K
44B4
44C8
(OC)
SMC_XTAL
SMC_EXTAL
MD1
AVSS
P80/PME*
P36/LCLK
RES*
VSS
P82/CLKRUN*
P83/LPCPD*
D7
E3
R4901
NO STUFF
P32/LAD2
P33/LAD3
A8
SMC_RESET_L
P12
P31/LAD1
A6
IN
45C7
P30/LAD0
C8
5%
1/16W
MF-LF
402
(3 OF 4)
IN
10K
SMC_H8S2116
44B4
A9
D6
R4909 1
BGA
C9
P34/LFRAME*
P35/LRESET*
U4900
44B4
C7
D8
OMIT
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
44B4
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_1V25_ISENSE
P13
65C6
OUT
D9
B9
(OC)
(1 OF 4)
OUT
AVREF
AVREF
P64/KIN4*
P15
P16
E12
OUT
46B4 45D5 44C5 41A8 6C2
P14
C14
D15
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
PCI_CLK33M_SMC
INT_SERIRQ
SMC_GFX_THROTTLE_L
SMC_SYS_LED
OUT
SMB_MGMT_DATA
BI
44B4 SMC_P43
44B4 SMC_P44
44A4 SMC_P45
44B4 SMC_P46
SMC_SYS_KBDLED
OUT
B15
A15
44B4
66A3 45B6 6C1
P62/KIN2*
P63/KIN3*
L15
B14
P12
P13
BGA
SMC_PM_G2_EN
SMC_ADAPTER_EN
SMC_P62
SMC_P63
SMC_P64
PM_LAN_PWRGD
SMC_PROCHOT_3_3_L
SMC_P67
0.47UF
10%
6.3V
CERM-X5R
402
D2
OUT
24C3
L14
B4
59C7
L13
P61/KIN1*
A4
IN
OUT
P60/KIN0*
SMC_H8S2116
A13
24C2
U4900
P11
B13
63B5 63B4 45D5
P10
C13
F13
IN
B12
F12
58A3 27A5 6B2
PM_LAN_ENABLE
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
44B4 SMC_P14
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
R4
OUT
P4
OUT
D1
24C2
VCC
20%
10V
CERM
402
OMIT
44A4
0.1UF
VCC
VCC
C4920
J15
C4907
N15
VOLTAGE=3.3V
VCC
5%
1/16W
MF-LF
402
N14
4.7
AVCC
AVCC
SMC_VCL
R8
R7
PH0/EXIRQ6*
E1
PH1/EXIRQ7*
PH2/FWE
F3
PH3/EXEXCL
C4
PH4
PH5
D4
K2
B3
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMC_PG0
SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_FWE
ALS_GAIN
SMC_PH4
SMS_ONOFF_L
IN
45B3
IN
6C2 45C5 46B4
IN
6C2 45C5 46B4
44D5
44D5
44D5
OUT
6C2 45C5 46B6
IN
6C2 45C5 46B6
44C5
44B5
(4 OF 4)
NC_SMC_P62
NC_SMC_P63
NC_SMC_P64
NC_SMC_P81
NC_SMC_PF1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
44A4
44B4
BI
47C3
BI
47C3
44A8
BI
47D3
44A8
SMC_SYS_KBDLED
ALS_GAIN
SMC_EXCARD_PWR_EN
SMC_FAN_0_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
ALS_LEFT
ALS_RIGHT
BI
47D3
44B5
SMC_PF0
BI
47C6
44B5
BI
47C6
IN
6B2 42C3 45C5 57A8

44B8
45C1
44A5
OUT
6C1 66A8
OUT
44A4
OUT
66B8
OUT
44A4
IN
51A8
44B8
44A8
44A8
44A8
45C5
44A8
44A8
44A8 6A7
44B5
44D8
OUT
45B6
44C8
OUT
45B5
IN
45C5
OUT
44B4
OUT
51C7
44A4
44C5
44C5
N11
PD3/AN11
44C8
P10
44A5
R10
PD4/AN12
PD5/AN13
N10
PD6/AN14
M10
PD7/AN15
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
SMC_BATT_VSET
SMC_SYS_VSET
SMC_RSTGATE_L
SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
SMC_GPU_ISENSE
MAKE_BASE=TRUE
SMC_GPU_VSENSE
SMC_P45
SMC_PH4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMC_PF0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMC_SYS_KBDLED
NC_ALS_GAIN
NC_SMC_EXCARD_PWR_EN
NC_SMC_FAN_0_CTL
NC_SMC_FAN_2_CTL
NC_SMC_FAN_3_CTL
NC_SMC_FAN_0_TACH
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_TACH
NC_ALS_LEFT
NC_ALS_RIGHT
NC0
NC1
NC12
NC13
F15
NC2
NC3
NC14
NC15
C12
L3
N4
NC4
NC16
C5
M5
NC17
NC18
A3
N7
NC5
NC6
M12
NC7
NC19
E4
M13
NC20
NC21
H4
L12
NC8
NC9
K15
NC10
NC22
N8
J14
NC11
G3
H3
K3
A14
C10
B8
M9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC_SMC_BATT_VSET
NC_SMC_SYS_VSET
NC_SMC_RSTGATE_L
NC_SMC_GFX_THROTTLE_L
SMC_GPU1_ISENSE
SMC_GPU1_VSENSE
SMC_ENRGYSTR_LDO_EN
SMC_ENRGYSTR_LDO_PGOOD
60B2 60C7
48B1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
66D3
SMC
45C5 66C1
SYNC_MASTER=T9_MLB

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
44
76
01
SMC Reset Button / Brownout Detect

51B8 45D4 45C1 44D4 7C1
SMS_INT_L
SMC_TPM_RESET_L
1
C5000
0.1UF
U5000
SOT23-5
44A8
46B4
44C3 6C2
OUT 1
CD
NC
R5001C5001 1
0
0.01UF
R5078
470
63B5 63B4 44D8
Silk: "SMC RST"
44B8
46B6 44C5 44B8 41A8 6C2
46B4 44C5 44B8 41A8 6C2
57C8 44B8 6C1
57A2 44C5 6D1
Debug Power Button
46B6 44B5 6C2
SMC Crystal Circuit
46B4 44B5 6C2
C5020
15PF
SMC_ONOFF_L
OUT
NOSTUFF
44C3
R5010
0
SMC_XTAL
5%
50V
CERM
402
Y5020
44A5
57A8 44B5 42C3 6B2
CRITICAL
Silk: "PWR BTN"
46B4 44B5 6C2
20.00MHZ
5X3.2-SM
66C1 44A2
44C5
44B8
C5021
44B8
15PF
SMC_EXTAL
Is this the best part to use?
44C3
44B8
44C5
5%
50V
CERM
402
44B5
3.3K
=PP3V42_G3H_SMC
51B8 45D8 45C1 44D4 7C1
R50941
RSMRST_PWRGD
R50531
SMC_ONOFF_L
R50281
SMC_EXCARD_OC_L
R50801
SMC_TX_L
R50811
SMC_RX_L
R50821
SYS_ONEWIRE
R50831
SMC_BS_ALRT_L
R50841
SMC_TMS
R50851
SMC_TDO
R50861
SMC_TDI
R50871
SMC_TCK
R50481
SMC_FWE
R50731
SMC_LID
SMC_ENRGYSTR_LDO_PGOODR50951
R50911
PM_LAN_PWRGD
R50981
SMC_PA0
R50991
SMC_PA1
R50901
SMC_PB0
R50891
SMC_P67
R50791
SMC_PG0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5%
1/16W
MF-LF
2402
100K
10K
10K
10K
100K
2.0K
470K
10K
10K
10K
10K
10K
100K
10K
10K
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
2 402
R5070
45C8 44C5 42C8
10K
PP3V3_S0
SMC_RESET_L
OUT
10%
16V
CERM 2
402
5%
1/10W
MF-LF
2603
R50301
SMC_GFX_OVERTEMP_L
7D4 6A2
PP1V05_S0
GND
45D5 44C5 42C8
7D7 6B2
SMS_INT_L
5%
1/16W
MF-LF
2402
RN5VD30A-F
5
4
=PP3V3_S0_SMC_LS
7D4
R5000
1K
VDD
SMC_MANUAL_RST_L
NOSTUFF
NC
5%
1/16W
MF-LF
2402
CRITICAL
2
20%
10V
CERM 2
402
6B2
SMC 1.05V to 3.3V Level Shifting
THESE NEED TO BE PULLED TO THE PROPER RAIL:
=PP3V42_G3H_SMC
44C5
SMC_PROCHOT_3_3_L
3
5
Q5077
BC847BV-X-F
SOT563
CPU_PROCHOT_BUF
4
R5071
3.3K
70C3 59C8 45B5 9C5
CPU_PROCHOT_L 5%
1/16W
MF-LF
402
Q5077
BC847BV-X-F
SOT563
CPU_PROCHOT_L_R
1
7C1 44D4 45D4 45D8 51B8
=PP3V42_G3H_SMC
1
R5076
10K
5%
1/16W
MF-LF
2402
SMC AVREF Supply
SMC_PF3
SMC_CPU_RESET_3_3_L
44B5
NOSTUFF
R5072
0
1
2
5%
1/16W
MF-LF
402
VR5065
7C1
44A8
=PP3V42_G3H_SMCVREF ISL60002-33
SOT23-3
1
VOUT
VIN
CRITICAL
PP3V3_S5_AVREF_SMC
VOLTAGE=3.3V
44D4
66A3 44C8 6C1
R50491
R50541
SMC_ANALOG_ID
GND
C5067
66A4 44C8 6C1
0.01UF
10%
2 16V
CERM
402
C5065
C5066 1
0.47UF 10uF
10%
2 6.3V
CERM-X5R
402
20%
6.3V
X5R 2
603
66A6 57C7 57C3 44C5 6C1
GND_SMC_AVSS
R50551
R50881
SMC_BATT_CHG_EN
SMC_BC_ACOK
R50061
100K
R50241
10K
10K
R50471
10K
R50961
R50971
2 470K
PM_SLP_S5_L
24D3 44C5
10K
SMC_EXCARD_CP
44B8
10K
SMC_CASE_OPEN
44B5
10K
SMC_ADAPTER_EN
6C1 33C7 35C7 38C6 44D5 57C4
10K
SMC_NB_1V25_ISENSE
44C5
SMC 3.3V to 1.05V Level Shifting
44C1 48A1 48B1 48C1 48C6 60B2 61C5 62C2 66B1
MIN_LINE_WIDTH=0.4 MM66C2
VOLTAGE=0V
CPU_PROCHOT_L
PM_THRMTRIP_L
9C5 45C3 59C8 70C3
9C6 15A6 22C2 70B3
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
353S1278
353S1381
VR5065
COMMENTS:
Q5001
D 6
2 G
S 1
SSM6N15FE
SOT563
TABLE_ALT_ITEM
TI REF3133
44A5
Q5001
D 3
5 G
S 4
SSM6N15FE
SOT563
SMC_PROCHOT
44A5
SMC_THRMTRIP
SYSTEM (SLEEP) LED CURRENT DRIVER

40B6 7A4
=PP5V_S3_SYSLED
TABLE_5_HEAD
PART#
3.3V TO PBUS LEVEL SHIFTING

=PPVIN_S5_IMVP
7A1
R5075
470K
1
Q5002
24D3
SUS_CLK_SB
2
5%
1/16W
MF-LF
402
44C5
2 G
C5050
0.001UF
10%
2 50V
CERM
402
31.6
1%
Q5050
Q5002
D 3
31.6, 1%, 1/16W, MF-LF, 402
R5050
NORMAL
114S0086
44.2, 1%, 1/16W, MF-LF, 402
R5050
FANCY
SYS_LED_ILIM
Q5050
MMDT3906XF
SOT-363
R5052
S 1
BOM OPTION
114S0071
3.74K2
MMDT3906XF
SYS_LED_EN1
DESCRIPTION
TABLE_5_ITEM
1/16W
MF-LF
2402
SOT-363
PM_SLP_S3_L
R5011 CLOSE TO SB
D 6
SMC_SUS_CLK
OUT
62B8 58B7 44C5 35C7 33C7 24D3 IN
SYS_LED_ISET
48D7
ENABLE VSENSE IN S0 ONLY
SSM6N15FE
SOT563
R5011
0
357
1%
QTY
TABLE_5_ITEM
R5050
1/16W
MF-LF
2402
PBUS_SMC_VSENSE_EN_L
1%
1/16W
MF-LF
402
R5051
1OMIT
SMC SUPPORT
RC FILTERED AT SATA CONN
SYNC_MASTER=GPU SYNC_DATE=07/17/2006
SYS_LED_BIAS
40C5 6B2
1%
1/16W
MF-LF
402
SYS_LED_ANODE
OUT
0.0094A NORMAL
0.007A FANCY

SSM6N15FE
SOT563

5 G
S 4
SIZE
44C8
IN
SMC_SYS_LED
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
45
76
01
FWH_INIT_L Generation
LPC+ Connector
7C4
=PP3V3_S0_LPCPLUS
LPCPLUS
7B1 6D2
7A7 6D2
=PP3V42_G3H_LPCPLUS
=PP5V_S0_LPCPLUS
44C8 22D4 6D2
BI
44C8 22D4 6D2
BI
44C8 22D4 6C2
IN
44C5 37A5 24C8 6C2
OUT
23B5 6C2
OUT
45C5 44B5 6C2
OUT
27D1 6C2
IN
44C1 6C2
OUT
45C5 44B5 6C2

44D1 6C2
45D5 44C5 44B8 41A8 6C2
IN
OUT
IN
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RESET_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
2
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1.3K
5%
1/16W
MF-LF
2 402
SM1
R5191
330
J5100
1
R5192
F-ST-5047
6C2
FWH_INIT_L
PCI_CLK33M_LPCPLUS
IN
LPCPLUS
CRITICAL
LPCPLUS
5%
1/16W
MF-LF
2 402
6C2 29B3 75C3
3
LPCPLUS
LPC_AD<2>
LPC_AD<3>
BI
6C2 22D4 44C8
BI
6C2 22D4 44C8
Q5190
BC847BV-X-F
SOT563
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LINDACARD_GPIO
BI
6C2 24D5 44C5
OUT
6C2 44B5 45C5
OUT
6C2 44B5 45C5
OUT
6C2 44C3 45D7
OUT
6C2 44C1
OUT
6C2 41A8 44B8 44C5 45D5
OUT
6C2 24A7 24D5
CPU_INIT_LS3V3
LPCPLUS
6
Q5190
BC847BV-X-F
6C2 24C8 44C8
IN
LPCPLUS
4
R5190
2
SOT563
CPU_INIT_R_L
330
CPU_INIT_L
IN
9D6 22C4 70B3
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub
516S0416

SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
46
76
01
ICH8-M SMBus Connections
SMC "0" SMBus Connections
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
7C4
=PP3V3_S0_SMBUS_SB
7C4
R52001
ICH8-M
4.7K
U2300
(MASTER)
73A3 24D5
SMB_CLK
73A3 24D5
SMB_DATA
5%
1/16W
MF-LF
402 2
R5201
4.7K
5%
1/16W
MF-LF
2 402
SMBUS_SB_SCL
Clock Chip
SMC
SLG8LP537V: U2900
(Write: 0xD2 Read: 0xD3)
U4900
(MASTER)
=PP3V3_S0_SMBUS_SMC_0_S0
R52501
4.7K
5%
1/16W
MF-LF
402 2
=SMBUS_CK505_SCL
28B6
44B8
SMB_0_S0_CLK
76C3
=SMBUS_CK505_SDA
28B6
44B5
SMB_0_S0_DATA
76C3
MAKE_BASE=TRUE
7A4
R5251 HEAT PIPE/FIN-STACK

4.7K
SMBUS_SMC_0_S0_SCL
THRM_HEATPIPE_SMB_CLK
49D4
R52701
SMC
U5500
5%
1/16W
MF-LF
2 402
=PP3V3_S3_SMBUS_SMC_A_S3
100K
5%
1/16W
MF-LF
2 402
44A5
SMB_A_S3_CLK
76C3
44A5
SMB_A_S3_DATA
76C3
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
THRM_HEATPIPE_SMB_DATA
49D4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R5271
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
SMBUS_SB_SDA
100K
U4900
(MASTER)
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SO-DIMM "A"
J3100
(Write: 0xA0 Read: 0xA1)
=I2C_SODIMMA_SCL
30A6
=I2C_SODIMMA_SDA
30A6
SMC "B" SMBus Connections

7C4
SMC "Battery A" SMBus Connections
=PP3V3_S0_SMBUS_SMC_B_S0
7B1
SO-DIMM "B"
=I2C_SODIMMB_SCL
31A6
=I2C_SODIMMB_SDA
31A6
R52601
SMC
J3200
(Write: 0xA4 Read: 0xA5)
4.7K
U4900
(MASTER)
5%
1/16W
MF-LF
402 2
44A5
SMB_B_S0_CLK
76C3 6B2
44A5
SMB_B_S0_DATA
76C3 6B2
CPU Temp
R5261
4.7K
5%
1/16W
MF-LF
2 402
THRM_CPU_SMB_CLK
49B4
THRM_CPU_SMB_DATA
49B4
R5281
8.2K
U4900
(MASTER)
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
R52801
SMC
EMC1043-5: U5520
(Write: 0x98 Read: 0x99)
SMBUS_SMC_B_S0_SCL
=PP3V42_G3H_SMBUS_SMC_BSA
44A5
SMB_BSA_CLK
76C3
44A5
SMB_BSA_DATA
76C3
Battery
8.2K
5%
1/16W
MF-LF
402 2
J6950
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
=SMBUS_BATT_SCL
57A2
=SMBUS_BATT_SDA
57A2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
AIRPORT
J3400
SMC "MANAGEMENT" SMBUS CONNECTIONS

=SMB_AIRPORT_CLK
33B3
=SMB_AIRPORT_DATA
33B3
51B6 7A4
SMC
U4900
SMC MGMT Bus
44C5
SMB_MGMT_CLK
44C8
SMB_MGMT_DATA
R52321
SMS
R5233
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
76C3
76C3
U5930
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
=I2C_SMS_SCL
51A6
=I2C_SMS_SDA
51A6
ICH8-M ME SMBus Connections
7D1
=PP3V3_S5_SMBUS_SB_ME
SMBUS CONNECTIONS
R52301
ICH8-M
U2300
(MASTER?)
73A3 24D5
SMB_ME_CLK
73A3 24D5
SMB_ME_DATA
R5231
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SYNC_MASTER=WFERRY

SMBUS_SB_ME_SCL
MAKE_BASE=TRUE
SMBUS_SB_ME_SDA
MAKE_BASE=TRUE

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
47
76
01
PROCESSOR DCIN VOLTAGE SENSE
CPU CURRENT SENSE

C5300
470PF
1
59D8 59D4 59C2 7B1
2
=PPVIN_S5_CPU_IMVP
R5307
0
PBUS_S0_SMC_VSENSE
D
G
1
59B6 59A4
SOT-723
1
IMVP6_DROOP
R5305
30.1K2
1
IMVP6_CPU_ISENSE_P
5%
1/16W
MF-LF
402
SSM3J15FV
Q5350
R5350
NOSTUFF
1
27.4K
1%
45A5
C5304
C5301
0.1UF
1
SMC_PBUS_VSENSE
5.49K
1%
C5350
0.22UF
10%
2 6.3V
CERM-X5R
402
1/16W
MF-LF
2 402
=PP3V3_S0_CPUPOWER
7C4
20%
10V
CERM
402
44C5
R5351
1%
1/16W
MF-LF
402
20%
2 10V
CERM
402
PBUS_SMC_VSENSE_EN_L
DRIVEN LOW IN S0
CPU_ISENSE_R_P 1
R5308
0
GND_SMC_AVSS
44C1 45B6 48A1 48B1 48C1 60B2 61C5 62C2
66B1 66C2
PLACE C5350 NEAR SMC
59B6 59A4
IMVP6_VO 1
R5306
30.1K
1
IMVP6_CPU_ISENSE_N
5%
1/16W
MF-LF
402
NOSTUFF
1
C5355
CRITICAL
+
V+
CPU_ISENSE_R_N 3
1%
1/16W
MF-LF
402
U5300
HPA00141AIDCKR
R5302
SC70-5
4.53K
4
1
2
CPU_ISENSE_OUT_R
1%
1/16W
MF-LF
402
V2
SMC_CPU_ISENSE
1
44C5 59C7
C5302
0.22UF
20%
2 6.3V
X5R
402
0.1UF
20%
2 10V
CERM
402
R5300
1M
1%
1/16W
MF-LF
402
0.1UF
1/16W
MF-LF
2 402
10%
50V
CERM
402
GND_SMC_AVSS
1
R5303
C5303
470PF 1M
10%
2 50V
CERM
402
44C1 45B6 48A1 48B1 48C6 60B2 61C5 62C2

66B1 66C2
PLACE RC FILTER CLOSE TO SMC
1%
1/16W
MF-LF
2402
CPU VOLTAGE SENSE

48B5 11D7 10D7 10B5 7D7
=PPVCORE_S0_CPU
R5312
4.53K
1
SMC_CPU_VSENSE
1%
1/16W
MF-LF
402
6B2 44C5
C5312
0.22UF
C5312 CLOSE TO SMC
20%
2 6.3V
X5R
402
GND_SMC_AVSS
Current Sense Calibration Circuit
44C1 45B6 48A1 48C1 48C6 60B2 61C5 62C2 66B1

66C2
Switches in fixed load on power supplies to calibrate current sense circuits
GPU VOLTAGE SENSE

48B3 11D7 10D7 10B5 7D7
R5381
=PPVCORE_S0_CPU
21C5 17D5 17B7 7B7
R5343
1.00
7A7
CRITICAL
=PP5V_S0_ISENSECAL
SI3446DV
TSOP-LF
CRITICAL
U5302
44B8
IN
2
ISENSE_CAL_EN
R5342
5 SN74AHCT1G125DCKRE4
1K 2
4 ISENSE_CAL_EN_5V
1
SC70-5
5%
1/16W
3 1
MF-LF
402
ISENSE_CAL_EN_5V_R3
21206
1
2
5
6
44A2
1%
1/16W
MF-LF
402
1%
1/4W
MF-LF
Q5300
SMC_GPU1_VSENSE
=PPVCORE_S0_NB_GFX 14.53K
2
C5376
0.22UF
20%
2 6.3V
X5R
CPUVCORE_ISENSE_CAL
C5376 CLOSE TO SMC
402
GND_SMC_AVSS
44C1 45B6 48B1 48C1 48C6 60B2 61C5 62C2 66B1

66C2
CPU Current & Voltage Sense
SYNC_MASTER=GPU

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
48
76
01
HEAT-PIPE/FIN-STACK TEMPERATURE ZONE

R5501
33
PP3V3_S0_THRM_HEATPIPE_F
PLACE C5501 NEXT
1
TO U5500 VDD
0.1UF
10%
2 16V
X5R
402
C5501 C5502
1. ROUTE DXP AND DXN DIFFERENTIALLY

2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD
6A1 THRM_HEATPIPE_P
CRITICAL
J5550
78171-0004
M-RT-SM
5
CRITICAL
=PP3V3_S0_THRM_SNR
7C4 49C2
5%
1/16W
MF-LF
402
1UF
10%
2 6.3V
CERM
402
6 PLACE C5501 NEAR U5500 VDD

VDD
U5500
EMC1043-5
1
CONNECTOR DRIVES TWO

TEMP DIODE JUNCTIONS
PLACE C5510
NEXT TO U5500
2
3
4
6A1
C5510
0.0022UF
10%
2 50V
CERM
402
1
2
DP1
DN1
3
4
DP2
MSOP
SMCLK
SMDATA
THRM_HEATPIPE_N
8
7
47D3
47D3
THRM_HEATPIPE_SMB_CLK
THRM_HEATPIPE_SMB_DATA
ADDR= 1001 100B
(WRITE: 0X98 READ: 0X99)
IO
IO
DN2
GND
518S0521
6A1
C5511
0.0022UF
10%
2 50V
CERM
402
THRM_FINSTACK_P
PLACE C5511
NEXT TO U5500
6A1
THRM_FINSTACK_N
C
LAYOUT NOTE:
LAYOUT NOTE:
ADD GND GUARD TRACE
ROUTE CPU_THERMD_P AND
FOR CPU_THERMD_P AND
CPU_THERMD_N ON SAME
CPU_THERMD_N
LAYER.
R5524
33
1
PP3V3_S0_THRM_CPU_F
1
C5522
0.1UF
10%
10 MIL TRACE
2 16V
X5R
CPU TEMPERATURE ZONE
10 MIL SPACING
OUT
9C6
402
C5523
1UF
C
=PP3V3_S0_THRM_SNR 7C4
49D2
5%
1/16W
MF-LF
402
10%
2 6.3V
CERM
402
CPU_THERMD_P
CRITICAL
1
(TO CPU INTERNAL THERMAL DIODE)
IN
9C6
C5520
0.0022UF
10%
2 50V
CERM
402
PLACE C5522 NEAR U5520 VDD
6
CPU_THERMD_N
VDD
U5520
EMC1043-5
1
2
DP1
DN1
MSOP
SMCLK
SMDATA
6A1
THRM_DIMM_DX_F_P
THRM_DIMM_DX_P
THRM_DIMM_DX_N
R5522
10
CRITICAL
Q5520
BC846BM3T5G
SOT732-3
NOSTUFF
PLACE UNDER J3101
47C3
THRM_CPU_SMB_CLK
THRM_CPU_SMB_DATA
ADDR= 1001 100B
IO
IO
DN2
GND
PLACE C5524 NEXT TO Q5520
1
6A1
C5521
0.0022UF
DP2
47C3
10%
2 50V
CERM
402
C5524
0.0022UF
10%
2 50V
CERM
402
1%
1/16W
MF-LF
402
3
4
8
7
THRM_DIMM_DX_F_N
R5523
10
1%
1/16W
MF-LF
402

TEMPERATURE SENSE
SYNC_MASTER=GPU

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
49
76
01
7A7 6D2
7C4 6D2
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
R5660 1
47K
5%
R5665
44A8 6D2
1/16W
MF-LF
402
J5601
78171-0004
M-RT-SM
NC 5
1
2
3
4
147K2 FAN_RT_TACH
SMC_FAN_1_TACH
6D2
5%
1/16W
MF-LF
402
NC
5V DC
TACH
MOTOR CONTROL
GND
R5661 1
44A8 6D2
SSM3K15FV
6D2
FAN_RT_PWM
SOD-VESM
2
SMC_FAN_1_CTL
518S0521
Q5660
1/16W
MF-LF
402
100K
5%
Fan
SYNC_MASTER=ENET

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
50
76
01
PAGE NOTES
INPUT
=PP3V3_S3_SMS - 3.3V POWER FOR SMS (STAYS ALIVE IN SLEEP)
SMS_ONOFF_L - CONNECT TO SMC TO BE ABLE TO PUT SMS INTO LOW-POWER MODE
OUTPUT
SMS_ACC_*_AXIS - ACCELEROMETER OUTPUT TO SCU
PAGE HISTORY
5/19/2005
7/26/2005
7/26/2005
7/26/2005
- FIRST REVISION OF PAGE

- REMOVED BOM TABLE AND UPDATED SYMBOL TO KXM52-2050
- CONNECTED PD PIN TO SMCS SMS_ONOFF_L
-
Desired Orientation
(Placed on board bottom side)
Package Top
1
7A4
+Y
=PP3V3_S3_SMS
+X
NC
C5920
0.1UF
+Z (up)
10%
16V 2
X5R
402
CRITICAL
3 12
VDD VMUX
U5920
KXPA42050
DFN
SMS_ACC_SELFTEST
44A5
9 SELF
OUTPUTX
8 PS
OUTPUTY
10 S1
11 S0
OUTPUTZ
TEST
SMS_ONOFF_L
1
R5921
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
NC1 1
NC2 2
NC13 13
NC14 14
10K
5%
1/16W
MF-LF
2402
GND
THRML
PAD
15
NC
NC
NC
NC
44A8
44A8
44A8
C
1
1 C5905 1 C5906
C5904
0.033UF 0.033UF 0.033UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
SMC_ACC_SELFTEST-->is a test signal

0 -->Normal operation
1 -->Self test
Desired Orientation
(Placed on board bottom side)
Package Top
+Z (UP)
+Y
+X
=PP3V42_G3H_SMC
NOSTUFF
R5930
10K
5%
47B1
=I2C_SMS_SCL
6 SCK
7 SDO
1/16W
MF-LF
2 402
44B5
VDD
47B1
=I2C_SMS_SDA
8 SDI
SMC_SMS_INT
U5930
BMA150
1/16W
MF-LF
2 402
11 NC
NC
LGA
CRITICAL
C5931
0.022UF
10%
16V
CERM-X5R
402
C5932
0.1UF
10%
16V
X5R
402
12 NC
1 NC
RESERVED
5 CSB
R5931
VDDIO
4 INT
10 NC
GND
STUFF R5930 TO USE U5920

STUFF R5931 TO USE U5930
10K
5%
2
45D8 45D4 45C1 44D4 7C1
47C3 7A4
SMS
SYNC_MASTER=SMC SYNC_DATE=08/23/2005

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
51
76
01
7D1
=PP3V3_S5_ROM
R61001
3.3K
5%
1/16W
MF-LF
402 2
73A3 23C5
73A3 23C5
IN
5%
1/16W
MF-LF
2 402
0.1UF
10%
16V
X5R 2
402
CRITICAL
VDD
U6100
SOI
73A3
SPI_A_SCLK_R
15
SCK
SI
SO
PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100

R6193 R6193 close to SB
15 2
1
73A3 SPI_A_SI_R
SPI_SI_R IN 23C5 73A3
SST25VF016B
R6191
73A3
SPI_CE_L<0>
5%
R6191 close to 1/16W

SB
MF-LF
402
R6101 C6100 1
3.3K
16MBIT
R6190 close to SB
R6190
15 2
SPI_SCLK_R 1
IN
5%
1/16W
MF-LF
SPI_CE_R_L<0> 402
SPI_A_WP_L
SPI_A_HOLD_L
3
7
CE*
WP*
HOLD*
R6114
OMIT
73A3
SPI_A_SO_R 1
15
5%
1/16W
MF-LF
402
VSS
5%
1/16W
MF-LF
402
SPI_SO
OUT
23C5 73A3
R6114 close to u6100

SPI ROMs
SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
52
76
01
AUDIO CODEC
APPLE P/N 353S1538
L6202
VOLTAGE=4.5V
FERR-220-OHM
PP4V5_AUDIO_ANALOG
D
53A3
0402
VOLTAGE=3.3V
2
0402
53C8
CODEC_DVDD
AVDD_ADC_DAC
OMIT
CRITICAL
CRITICAL
C6200 1
1UF
C6201
0.001UF
10%
8A5 6D1
IN
NO STUFF
53D6
ACZ_BITCLK
ACZ_SYNC
ACZ_SDATAOUT
R6204
R6270
100K
8A5 6D1
5%
1/16W
MF-LF
2 402
OUT
54A8
R6271
ACZ_SDATAIN<0>
39
CODEC_SDATA_IN
AUD_GPIO_0
AUD_GPIO_1
54B8
54C8
2
3
23
24
AUD_BI_PORT_D_L
AUD_BI_PORT_D_R
35
36
NC_BAL_IN_L
NC_BAL_IN_COM
NC_BAL_IN_R
SYNC
SDATA_OUT
SPDIFI/EAPD/MIDI-I/DMIC-R
U6200
SDATA_IN
NO_TEST18
NO_TEST19
NO_TEST20
BEEP
ACZ_RST_L
AUD_SPDIF_O
48
47
0.001UF
=GND_AUDIO_CODEC
39
8B4 53A7 53B7 54A8 54B8 54C8 55B3 56A4 56A8 56B1 56B4
56B5 56B8 56C4
AUD_SPDIF_OUT 55D3
5%
1/16W
MF-LF
402
13
34
REV B3
GPIO0/DMIC-CLK
GPIO1/DMIC-L
PORT-A-L
PORT-A-R
39
41
PORT-C-L
PORT-C-R
PORT-F-L
16 NO_TEST
17 NO_TEST
30 NO_TEST
33
14 NO_TEST
15 NO_TEST
31 NO_TEST
28
21
22
NC_AUD_BI_PORT_F_L
NC_AUD_BI_PORT_F_R
NC_AUD_VREF_PORT_F
29 NO_TEST
32 NO_TEST
NC_AUD_VREF_PORT_C
NC_AUD_VREF_PORT_D
PORT-F-R
PORT-F-VREFO
PORT-A-VREFO/DCVOL
PORT-D-L
PORT-E-L
PORT-E-R
PORT-D-R
CD-L
PORT-E-VREFO
CD-GND
CD-R
PORT-B-VREFO
PORT-B-L
12
BEEP
11
RESET*
PORT-B-VREFO2
PORT-G-R
PORT-H-L
CRITICAL
PORT-H-R
AUD_SPDIF_I
AUD_SENSE_A
AUD_SENSE_B
49
AVSS2
VREF
AVSS1
10%
16V
2 X5R
402
JDREF
NC
AUD_BI_PORT_A_L
AUD_BI_PORT_A_R
55B3
56A8 56C8
56C8
56C4
AUD_VREF_PORT_A
56C2
AUD_VREF_PORT_B
AUD_BI_PORT_B_L
AUD_BI_PORT_B_R
56B4
56A4
56A4
NC_AUD_BI_PORT_G_L
43 NO_TEST
44
AUD_BI_PORT_G_R
54A8
NC_AUD_BI_PORT_H_L
NC_AUD_BI_PORT_H_R
45 NO_TEST
46 NO_TEST
AUD_CODEC_VREF
27
40 AUD_CODEC_JDREF
37 NC_VRP
1
R6209
100K
5%
1/16W
MF-LF
2 402
R6205
NO_TEST
20.0K
1%
1/16W
MF-LF
2 402 CRITICAL
NO STUFF
C6210
R6201
10%
16V
TANT
SMA-LF
5%
1/16W
MF-LF
2 402
C6212
0.001UF
3.3UF
0
=GND_AUDIO_CODEC
56C4
NC_AUD_BI_PORT_E_L
NC_AUD_BI_PORT_E_R
NC_AUD_VREF_PORT_E
26
42
0.1UF
5%
1/16W
MF-LF
2 402
DVSS
C6208
100K
THRM_PAD
R6203
4
7
56B1 56A8 56A4 55B3 54C8 54B8 54A8 53D3 53A7 8B4
56C4 56B8 56B5 56B4
C6207
20%
2 50V
CERM
402
20%
6.3V 2
POLY
CASE-B2
SENSE_A
SENSE_B
PORT-G-L
150UF
CRITICAL
PORT-C-VREFO
IN
C6205 1
R6206
SPDIFO
PORT-B-R
8A5 6C1
0.001UF
QFN
AUD_BI_PORT_C_L
56A1 AUD_BI_PORT_C_R
5%
1/16W
MF-LF
2 402
BCLK
C6206
10%
2 50V
CERM
402
20%
6.3V 2
POLY
CASE-B2
ALC885Q-VB3-GR
5%
1/16W
MF-LF
402
56B1
10K
6
10
5
8
AVDD1
IN
DVDD
IN
DVDD_IO
CODEC_DVDD
8A5 6C1
8A5 6C1
150UF
10%
2 50V
CERM
402
1
9
402
OMIT
CRITICAL
C6204 1
0.001UF
10%
2 50V
CERM
402
6.3V
CERM 2
C6203
25
38
56B5 55D8 53A7
L6201
FERR-220-OHM
AVDD2
VOLTAGE=3.3V
7C4 =PP3V3_S0_AUDIO
10%
50V
2 CERM
402
VOLTAGE=0V
AUDIO 4.5V REGULATOR

APPLE P/N 353S1576
U6201
L6200
FERR-220-OHM
=PP5V_S0_AUDIO
AUD_4V5_REG_IN
1
2
8
0402
R6202
=PP3V3_S0_AUDIO
1K
OUT1
OUT2
NR/FB
GND THRM_PAD
PP4V5_AUDIO_ANALOG
3
4
5
4V5_REG_FB
NC
5%
1/16W
MF-LF
402
R6210
80.6K
AUD_REG_SHDN_L
6
56B5 55D8 53D7 7C4
LREG_TPS79501DRB
SON
IN1
IN2
EN
1%
1/16W
MF-LF
2 402
56C4 7A7 6D1
VOLTAGE=5V
53D3
C6224
15PF
5%
50V
2 CERM
402
CRITICAL
C6221
1
C6220
0.1UF
10%
16V
2 X5R
402
10UF
20%
6.3V 2
X5R
603
C6223
0.001UF
VOUT=1.2246V*[1+(R6210/R6211)]=4.58V
10%
2 50V
CERM
402
R6211
PLACE R6210, R6211, AND C6224 CLOSE TO U6201
AUDIO: CODEC
29.4K
1%
1/16W
MF-LF
2 402
SYNC_MASTER=M70AUDIO

=GND_AUDIO_CODEC
56B1 56A8 56A4 55B3 54C8 54B8 54A8 53D3 53B7 8B4
56C4 56B8 56B5 56B4

NO STUFF
R6200
1
5%
1/16W
MF-LF
402

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
53
76
01
SATELLITE
& SUB TWEETER AMPLIFIER
APN:353S1595
SATELLITE
169 HZ < FC < 282 HZ
SUB
GAIN
80 HZ < FC < 132 HZ

12DB
D
54C4 SPKRAMP_R_P_OUT
54C8 54B8 7A7
VOLTAGE=5V
6D1 =PP5V_S0_AUDIO_AMP
54C4 SPKRAMP_R_N_OUT
AUD_SPKRAMP_INR_L
10%
6.3V
CERM 2
402
1
VDD
MAX9705_R_N
10%
16V
X7R
402
1UF
10
PVDD
2 IN+
3 IN-
OUT+
OUTSYNC
CRITICAL
5 SHDN*
54D3
R6601
100
GND PGND PAD

7
4
11
5%
1/16W
MF-LF
2 402
54B4
54A4 54B4
54B4
SPKRAMP_L_N_OUT
C6604 1
FERR-1000-OHM
1
AUD_SPKRAMP_INL_L
0.047UF
0402
10%
6.3V
CERM 2
402
C
OUT
6B1 55C2
1UF
OUT
6B1 55C2
5%
1/16W
MF-LF
402
C6603
20%
POLY
CASE-B3-SM
6.3V
U6620
SPKRCONN_L_N_OUT
47UF
10%
CERM 2
402
10
PVDD
LEFT SATELLITE
2 6.3V
MAX9705
TDFN1
AUD_SPKRAMP_INL
2 IN+
3 IN-
MAX9705_L_N
10%
16V
X7R
402
AUD_SPKRAMP_SHUTDOWN_L
1
VDD
1uF
C6620
R6671
OMIT
CRITICAL
CRITICAL
SPKRCONN_L_P_OUT
R6670
SPKRAMP_SYNC1 54A4
C6608 1
54C8 54A6
SPKRAMP_L_P_OUT
5%
1/16W
MF-LF
402
SPKRAMP_THERMPLANE
=PP5V_S0_AUDIO_AMP
PP5V_S0_AUDIO_F
AUD_BI_PORT_D_L
6B1 55C2
54C3
=GND_AUDIO_AMP
IN
OUT
RIGHT SATELLITE
=GND_AUDIO_CODEC
L6620
5%
1/16W
MF-LF
402
C6601
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
8
9
55B3 54B8 54A8 53D3 53B7 53A7 8B4

56C4 56B8 56B5 56B4 56B1 56A8 56A4
53C7
20%
POLY
CASE-B3-SM
10%
16V
X7R 2
402
54C4 54B8
SPKRCONN_R_N_OUT
R6661
2 6.3V
THRML
CRITICAL
C6611 1
54D8 54B8 7A7 6D1
6B1 55C2
47UF
10%
6.3V
CERM 2
402
U6610
0.047UF
54B8 54A8 54A5 8A4
TDFN1
54B8 54A6
MAX9705
0.047UF AUD_SPKRAMP_INR
0402
C6602
1uF
C6610
FERR-1000-OHM
AUD_BI_PORT_D_R
54B8 54C8
OMIT
CRITICAL
C6607 1
CRITICAL
L6610
PP5V_S0_AUDIO_F
VOLTAGE=5V
5%
1/16W
MF-LF
402
IN
SPKRCONN_R_P_OUT
OUT
R6660
5%
1/16W
MF-LF
402
R6600
53C7
OUT+
OUT-
CRITICAL SYNC
5 SHDN*
SPKRAMP_L_P_OUT 54C3
SPKRAMP_L_N_OUT 54C3
SPKRAMP_SYNC2 54A4
THRML
GND PGND PAD
4
11
7
CRITICAL
C6621
0.047UF
10%
16V
X7R 2
402
=GND_AUDIO_CODEC
SPKRAMP_THERMPLANE
55B3 54C8 54A8 53D3 53B7 53A7 8B4

56C4 56B8 56B5 56B4 56B1 56A8 56A4
54C8 54A8 54A5 8A4
54D8 54C8 7A7 6D1
=PP5V_S0_AUDIO_AMP
C6606
2
0402
L6611
AUD_GPIO_0
IN
0.1UF
1
1UF
U6630
MAX9705_SUB_N
2 IN+
3 IN-
OUT+
OUTCRITICAL SYNC
5 SHDN*
0402
4
54B8 54C8
11
OUT
6A1 55C2
5%
1/16W
MF-LF
402 2
OUT
6A1 55C2
SUB-TWEETER
SPKRAMP_SUB_P_OUT 54B3
SPKRAMP_SUB_N_OUT 54B3
SPKRAMP_SYNC1 54C4
5%
1/16W
MF-LF
402
20%
POLY
CASE-B2
2 6.3V
8
9
SPKRCONN_SUB_N_OUT
R6681
R6602
100
5%
1/16W
MF-LF
CRITICAL
C6631 1
10K
2 402
0.1UF
10%
16V
X5R 2
402
SPKRAMP_SYNC2 54B4
=GND_AUDIO_CODEC
SPKRAMP_THERMPLANE
55B3 54C8 54B8 53D3 53B7 53A7 8B4

56C4 56B8 56B5 56B4 56B1 56A8 56A4
54C8 54B8 54A5 8A4
C6605
120UF
10%
6.3V
CERM 2
402
10
PVDD
THRML
GND PGND PAD
R6610
MAX9705
2
1
TDFN1
AUD_SPKRAMP_INSUB
10%
16V
X5R
402
FERR-1000-OHM
1
10%
6.3V
CERM 2
402
C6630
AUD_SPKRAMP_INSUB_L
1
VDD
1uF
CRITICAL
L6630
FERR-1000-OHM
IN
54A4 SPKRAMP_SUB_N_OUT
OMIT
CRITICAL
PP5V_S0_AUDIO_F
AUD_BI_PORT_G_R
SPKRCONN_SUB_P_OUT
R6680
5%
1/16W
MF-LF
402
C6609 1
53C7
SPKRAMP_SUB_P_OUT
=GND_AUDIO_AMP
54C8 54C4
53B2
54A4
54A4 54C4
54A4 54B4 54C4
AUDI0: SPEAKER AMP
=GND_AUDIO_AMP
54C8 54B8 54A8 8A4 =GND_AUDIO_AMP
XW6600
SM
1
SPKRAMP_THERMPLANE

54A4 54B4 54C4

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
54
76
01
MIC CONNECTOR
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX
CRITICAL
APN:518S0392
J6701
48227-0301
L6790
M-RT-SM1
4
FERR-220-OHM
=PP3V3_S0_AUDIO
53D7 53A7 7C4

56B5
IN
0402
L6700
AUD_CONNJ1_SLEEVE
PP3V3_S0_AUDIO_SPDIF
53C2
55B1 6B1
L6701
FERR-120-OHM-1.5A
55B8
55B1 6B1
FERR-120-OHM-1.5A
AUD_CONNJ1_SLEEVE_F
0402-LF
56A6 55A1 6B1
MIC_LO_CONN
MIC_HI_CONN
MIC_SHLD_CONN
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
0402
8
9
L6707
AUD_CONNJ1_TIP_F
AUD_CONNJ1_SLEEVEDET
GND_AUDIO_SPDIF_DGND
0405
CRITICAL
6.8V-100PF
R6791
0
NO STUFF
2
CRITICAL
402
DZ6701
DZ6705
6.8V-100PF
6.8V-100PF
402
402
1
0405
2
1
2
AUD_PORTA_L
BI
78171-0004
56C1
M-RT-SM
5
10K
AUD_J1_SLEEVEDET_R
OUT
56B6 56B8
54B1 6A1
IN
54B1 6A1
IN
54D1 6B1
IN
54C1 6B1
IN
SPKRCONN_SUB_P_OUT
SPKRCONN_SUB_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT
4.7
1
2
3
4
APN:518S0521
AUD_J1_TIPDET_R
OUT
56C8
5%
1/16W
MF-LF
402
CRITICAL
DZ6703
5.6V-15A
5%
1/16W
MF-LF
402
SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT
R6701
402
DZ6702
1
DZ6704
6.8V-100PF
5.6V-15A
10%
2 6.3V
CERM
402
IN
5%
1/16W
MF-LF
402
CRITICAL
DZ6700
1UF
IN
54C1 6B1
J6703
R6700
AUD_CONNJ1_SLEEVEDET_F
NO STUFF
C6700
54C1 6B1
CRITICAL
0402
56C1
0402
FERR-1000-OHM
10
BI
FERR-1000-OHM
AUD_PORTA_R
L6706
FERR-1000-OHM
APN:514-0459
55C1 55A8 55A3
2
0402
L6705
AUD_CONNJ1_RING
1
7
55A8
0402
SHLD_PIN
FERR-1000-OHM
AUD_CONNJ1_RING_F
M-RT-SM
3
APN:518S0519
L6704
FERR-1000-OHM
1
J6702
78171-0002
L6703
F-RT-TH
2
3
CRITICAL
SPEAKER CONNECTOR
0402
AUDIO-OUT-M71-MG3
SHLD_PIN
AUD_CONNJ1_TIPDET_F
J6700
FERR-1000-OHM
OMIT
CRITICAL
0402-LF
L6702
VCC
GND
VIN
AUD_SPDIF_OUT
XW6705
SM
C6705
8D8
=GND_CHASSIS_AUDIO_JACK
CHASSIS_AUDIO_JACK_ISOL
55A3 55A8 55C8
100PF
5%
2 50V
CERM
402
XW6700
SM
AUD_J1_COM
XW6701
SM
AUD_J2_COM
AUD_J2_OPT_OUT
55D8
10
OUT
L6750
CRITICAL
1
OUT
FERR-1000-OHM
MIC_LO_CONN_F
MIC_LO_CONN
0402
6B1 55D3
0402
AUD_CONNJ2_TIPDET_F
MIC_HI
FERR-1000-OHM
AUD_CONNJ2_RING_F
56A6 6B1
0402
L6773
FERR-1000-OHM
L6754
FERR-1000-OHM
AUD_CONNJ2_RING
5
1
L6772
L6753
AUD_CONNJ2_TIP
AUD_CONNJ2_TIPDET
AUD_PORTC_R
BI
OUT
FERR-1000-OHM
MIC_HI_CONN_F
0402
56A2
MIC_HI_CONN
6B1 55D3
0402
0402
CRITICAL
L6755
L6756
FERR-1000-OHM
7
6
FERR-1000-OHM
1
AUD_CONNJ2_TIP_F
0402
AUD_PORTC_L
DZ6770
6.8V-100PF
BI
402
56B2
CRITICAL
0402
2
L6757
10
AUD_CONNJ2_SLEEVEDET
AUD_CONNJ2_SLEEVEDET_F
0402
1
C6750
1UF
10%
2 6.3V
CERM
402
NO STUFF
20%
2 6.3V
X5R
603
GND_AUDIO_SPDIF_DGND
DZ6751
10uF
0405
2
NO STUFF
CRITICAL
CRITICAL
6.8V-100PF
402
1
4.7
AUD_J2_TIPDET_R
C6756
100PF
5%
2 50V
CERM
402
OUT
56A8
55C8 55C1 55A8
5%
1/16W
MF-LF
2 402
AUDIO: JACK
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
J6700
CRITICAL
NORMAL
TABLE_5_ITEM
514-0459
CONN, 3.5MM COMBO AUDIO OUT, RA MG3, LF
TABLE_5_ITEM
514-0458
R6740
0
5%
1/16W
MF-LF
402
402
1
6.8V-100PF
402
0405
2
DZ6755
DZ6754
6.8V-100PF
5.6V-15A
402
DZ6752
DZ6750
CRITICAL
6.8V-100PF
6B1 55D3 56A6
R6751
CRITICAL
DZ6753
5.6V-15A
MIC_SHLD_CONN
402
5%
1/16W
MF-LF
402
C6751
10K
DZ6771
6.8V-100PF
R6750
FERR-1000-OHM
APN:514-0458
55C8 55C1 55A3
0402
2
4
56A6 6B1
0402-LF
F-RT-TH
55C8
L6771
FERR-1000-OHM
MIC_LO
FERR-1000-OHM
AUDIO-IN-MG3-M71
SHLD_PIN
SHLD_PIN
L6752
J6750
VCC
GND
VOUT
L6770
FERR-120-OHM-1.5A
0402-LF
OMIT
53C2
L6751
FERR-120-OHM-1.5A
1
2
AUD_CONNJ2_SLEEVE_F
AUD_CONNJ2_SLEEVE
8B4 53A7 53B7 53D3 54A8 54B8 54C8 56A4 56A8 56B1 56B4
56B5 56B8 56C4
AUD_SPDIF_I
5%
1/16W
MF-LF
402
PP3V3_S0_AUDIO_SPDIF
=GND_AUDIO_CODEC
MIC EMI FILTER
R6749
1
CONN, 3.5MM COMBO AUDIO IN, RA, MG3, LF
J6750
CRITICAL
NORMAL

TABLE_5_ITEM
514-0479
CONN, 3.5MM COMBO AUDIO OUT, RA, BLACK, LF
J6700
CRITICAL
FANCY
TABLE_5_ITEM
AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX
514-0478
CONN, 3.5MM COMBO AUDIO IN, RA, BLACK, LF
J6750
CRITICAL
FANCY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
55
76
01
CODEC OUTPUT SIGNAL PATHS

FUNCTION
HP OUT
SAT SPKR
SUB SPKR
SPDIF OUT
VOLUME
0X0F (15)
0X26 (38)
0X0E (14)
N/A
CONVERTER
0X05 (5)
0X25 (37)
0X04 (4)
0X06 (6)
PIN COMPLEX
0X15 (21,PORTA)
0X14 (20,PORTD)
0X16 (22,PORTG)
0X1E (30,SPDIF OUT)
MUTE CONTROL
VREF_A(100%)
GPIO 0
GPIO 0
N/A
DET ASSIGNMENT
0X15 (21,PORTA)
N/A
N/A
0X1B (27,PORTE)
CODEC INPUT SIGNAL PATHS

FUNCTION
LINE IN
MIC IN
SPDIF IN
MIXER
0X23 (35)
0X24 (36)
N/A
VOLUME
0X08 (8)
0X07 (7)
N/A
MUTE CONTROL
0X08 (8)
0X07 (7)
N/A
CONVERTER
0X08 (8)
0X07 (7)
0X0A (10)
PIN COMPLEX
0X1A (26,PORTC)
0X18 (24,PORTB)
0X1F (31,SPDIF IN)
VREF
N/A
VREF_B (80%)
N/A
DET ASSIGNMENT
0X1A (26,PORTC)
N/A
N/A
HP/LO DE-POP SWITCH

APN:353S1459
53A7 7A7 6D1
PORT A HP/LO
=PP5V_S0_AUDIO
OMIT
CRITICAL
C6830
100UF
1
MAX9890BETA+
C6836
53C2
OUT AUD_SENSE_B
56A8 53C2
OUT AUD_SENSE_A
56B8 56B3 56A8
PP3V3_S0_AUDIO_F
AUD_OUTJACK_INSERT_L
R6801
Q6800
270K
5%
1/16W
MF-LF
2 402
SSM6N15FE
Q6801
2
47K
1
39.2K
39.2K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
S 1
NC
GND
SSM6N15FE
SSM6N15FE
SOT563
SOT563
IN
MAX9890_CEXT
1
10%
16V
2 X5R
402
OUT
55C3
6.3V
53C2
POLY
B2
R6835
R6839
C6835
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
27.4K
10K
0.1UF
NC
AUD_PORTA_R
20%
AUD_VREF_PORT_A
=GND_AUDIO_CODEC
56A8 56A4 55B3 54C8 54B8 54A8 53D3 53B7 53A7 8B4
56B8 56B5 56B4 56B1
C6801
S 4
S 1
0.1UF
16V
10%
X5R
402
PLACE L6800/C6800 CLOSE TO Q6800
=GND_AUDIO_CODEC
L6800
R6803
1
PP3V3_S0_AUDIO_F
100K 2
5%
1/16W
MF-LF
402
R6861
270K
5%
1/16W
MF-LF
2 402
FERR-1000-OHM
AUD_J1_SLEEVEDET_INV
55D8 53D7 53A7 7C4
=PP3V3_S0_AUDIO
PP3V3_S0_AUDIO_F
56A8 56B8 56C8
0402
Q6800
D 3
56B8 55C3
AUD_J1_SLEEVEDET_R
10%
SOT563
=GND_AUDIO_CODEC
56A8 56A4 55B3 54C8 54B8 54A8 53D3 53B7 53A7 8B4
56C4 56B8 56B4 56B1
C6800
0.1UF
SSM6N15FE
AUD_J1_SLEEVEDET_R
IN
CEXT
THM
PAD
C6831
100UF
D 6
56C4 56B8 56B5

54B8 54A8 53D3 53B7 53A7 8B4
56B4 56B1 56A8 56A4 55B3 54C8
56B6 55C3
MAX9890_OUTR
1%
1/16W
MF-LF
402
AUD_J1_DET_RC
5%
1/16W
MF-LF
402
56C8 56B3 56A8
MAX9890_OUTL
INL
OUTR
55C3
OUT
27.4K
OMIT
CRITICAL
TDFN
INRCRITICALOUTL
SHDN*
AUD_PORTE_DET_L
Q6801
D 3
IN
AUD_BI_PORT_A_L
R6834
POLY
B2
U6801
R6805
AUD_PORTA_DET_L
SOT563
R6802
AUD_J1_TIPDET_R
IN
D 6
2 6.3V
CERM
R6806
10%
AUD_BI_PORT_A_R
402
53C2
55C3
IN
PORT E DETECT(SPDIF DELEGATE)
AUD_PORTA_L
6.3V
VCC
1UF
53C2
PORT A DETECT
20%
16V
X5R
402
S 4
PORT C LI
MIC INPUT CIRCUITRY
CRITICAL
1
C6802
R6850
R6855
6.81K
2.2K
0.01UF
10%
16V
2 CERM
VREF_PORT_B_R
C6832
AUD_VREF_PORT_B
56C4 56B8 56B5

54B8 54A8 53D3 53B7 53A7 8B4
56B4 56B1 56A8 56A4 55B3 54C8
=GND_AUDIO_CODEC
1%
402
1/16W
MF-LF
5%
402
IN
AUD_PORTC_L
R6836
CRITICAL
C6853
27.4K
10UF
1%
1/16W
MF-LF
402
20%
6.3V
2 X5R
R6851
AUD_SENSE_A
55B3 6B1
IN
1
1/16W
MF-LF
R6813
56C8 56B8 56B3
C6851
5%
1/16W
MF-LF
402 2
R6811
AUD_INJACK_INSERT_L
270K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
Q6802
SSM3K15FV
NC
IN
MIC_LO
47K
5%
1/16W
MF-LF
402
C6811
IN
XW6800
50V
CERM
402
AUD_BI_PORT_C_R
OUT
53C7
10%
16V
TANT
SMA-LF
53C2
NO STUFF
=GND_AUDIO_CODEC
3.3UF
2
AUD_PORTC_R
PLACE C6852 NEAR U6200
5%
IN
8B4 53A7 53B7 53D3 54A8 54B8 54C8 55B3 56A8 56B1 56B4
56B5 56B8 56C4
AUDIO: JACK TRANSLATORS
5%
1/16W
MF-LF
402
S 2
NO STUFF
0.1UF
10%
X5R
55B3
R6853
55D3 55A1 6B1
AUD_BI_PORT_B_R
100PF
AUD_J2_DET_RC
1
53C2
CRITICAL
C6833
2
NO STUFF
MIC_SHLD_CONN
R6812
AUD_J2_TIPDET_R
IN
C6852
D 3
SOD-VESM
55A3
AUD_BI_PORT_B_L
MAKE_BASE=TRUE
CRITICAL
SM
55B3 6B1
CRITICAL
R6852
100K
10%
CERM
402
1%
1/16W
MF-LF
402
8B4 53A7 53B7 53D3 54A8 54B8 54C8 55B3 56A4 56A8 56B4
56B5 56B8 56C4
27.4K
10% 16V
X5R 402
1
680PF
50V
MIC_IN
2
5%
402
CRITICAL
10K
PP3V3_S0_AUDIO_F
8B4 53A7 53B7 53D3 54A8 54B8 54C8 55B3 56A4 56A8 56B1
56B5 56B8 56C4
0.1uF
330
MIC_HI
R6837
C6850
53C7
10%
16V
TANT
SMA-LF
=GND_AUDIO_CODEC
=GND_AUDIO_CODEC
56C8 53C2
1 AUD_BI_PORT_C_L
OUT
603
Line-in (PORT C) DETECT
3.3UF
53C2
55B3
1/16W
MF-LF
402
402
0
1
56C4 56B8
54B8 54A8 53D3 53B7 53A7 8B4
56B5 56B4 56B1 56A4 55B3 54C8
=GND_AUDIO_CODEC
R6854
16V
=GND_CHASSIS_AUDIO_MIC

8D8
5%
1/16W
MF-LF
402

NO STUFF
R6856
0
1
SIZE
5%
1/16W
MF-LF
402
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
56
76
01
DC-JACK INTERFACE
CRITICAL
D6901
HN2D01JEF
R6905
47
5%
1/8W
MF-LF
805
2
518S0526
66B2 57B2
87438-0563
M-RT-SM
CRITICAL
VOLTAGE=18.5V
MIN_LINE_WIDTH=2 MM 1
C6902
0.01uF
1
SYS_ONEWIRE_BILAT
S
G
2
OVP
SOI
3
2
1
G
ONEWIRE_PWR_EN_L_DIV
5 G
S 4
R6908
R6906
102K
102K
Q6940
NTK3142P
1%
1/16W
MF-LF
2402
1%
1/16W
MF-LF
2402
10%
2 25V
X5R
402
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
ONEWIRE_EN
Q6999
SSM3K15FV
10%
2 50V
CERM
402
10%
2 25V
X5R
402
ONEWIRE_OV
U6990
2
-
5%
1/16W
MF-LF
2 402
V+
ONEWIRE_ESD
R6910
R6907 1R6909
1/16W
MF-LF
2402
R6931
100K
51.1K
1%
U6900
TLV7211
SC70
1
TC7SZ08AFEF
5 SOT665
SOT23-5
0.22UF
20%
2 25V
X5R
603
66A6
45B6
SMC_BC_ACOK 6C1
1/16W
MF-LF
2402
44C5
57C7
66A6 6C1
R6914
330K
5%
1/16W
MF-LF
2402
A
Y
5%
1/16W
MF-LF
2 402
VOLTAGE=18.5V
ACIN_ENABLE_L_DIV
5%
1/16W
MF-LF
402
=PP18V5_G3H_INRUSH7B3
R6913
1 C6917 4
470K
U6950
V-
NC
1M
10.7K
1%
8
7
6
5
SMC_ADAPTER_EN
CRITICAL
ACIN_DIV
R6933
100K
ONEWIRE_DCIN_DIV
LM397
2 S
V+
CRITICALV-
R6900
1 C6903
100K
0.001UF
5%
1/16W
MF-LF
C6930
0.1UF
1%
1/16W
MF-LF
2 402
3 D
SOD-VESM
2 402
R6903
1
10K
R6901
1K
S1
CRITICAL
ACIN_1V20_REF 4
1
D2
D1
44D5
33C7 6C1
38C6 35C7
45B3
Q6920
SSM6N15FE1 R6932
24.3K
D3
5%
1/16W
MF-LF
2402
C6918
0.1UF
D4
S3
S2
GATE
ACIN DETECTION
SOT563
AO4409
66A5 7B1
66B8 66A8
PP18V5_DCIN_ONEWIRE
SOT563
CRITICAL
Q6950
INRUSH LIMITER
=PP3V42_G3H_ACIN
3 D
5%
2 1/16W
MF-LF
402
SOT723-3
G 5
Q6920
SSM6N15FE
R6904
47K
5%
1/16W
MF-LF
402
C6907
0.001UF
10%
2 50V
CERM
402
4 S
45D5 44B8 6C1
ONEWIRE_PWR_EN_L
1
2 SMC_BC_ACOK_ONEWIRE_R
1
7B3
Q6910
SSM6N15FE
R6911
D 3 100K
SOT563
RCLAMP2402B
SYS_ONEWIRE
6
NC
=PPDCIN_G3H
5%
1/16W
MF-LF
402
ADAPTER_SENSE
PPVBATT_G3H_R
1/8W
MF-LF
VOLTAGE=18.5V
805
PP18V5_DCIN
R6902
6C1
44C5
45B6
66A6 57C3
3
=GND_DCIN_CHGND
SMC_BC_ACOK
1
NC
47
5%
1K
10%
2 25V
X7R
402
D6900
SC-75
8C8
PP18V5_DCIN_F
1
2
3
4
5
PPDCIN_G3H_R
R6940
CRITICAL
F6900
6AMP-24V
1206-1
J6900
ACIN_ENABLE_GATE
CRITICAL
1
BATT_POS_F
SOT665
ACIN_ENABLE_L
D 6
Q6910
SSM6N15FE
SOT563
2 G
S 1
G 1
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
376S0466
376S0543
Q6950
AOS MOSFET
353S1717
353S1297
U6990
TI & NATIONAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BATTERY INTERFACE
L6901
FERR-50-OHM
SM-LF
6D1
BATT_POS
BATT_POS_F
57D5 66B2
L6902
120-OHM-0.3A-EMI
L6909
600-OHM-300MA
0402
7B1
=PP3V42_G3H_LIDSWITCH
NC
VOID
0402-LF
6D1
SMBUS_BATT_SCL_F
NC
10
6D1
12
11
6D1
14
13
16
15
PP3V42_G3H_LIDSWITCH_F 18
20
GND_SMC_LID_F
17
L6907
0402
2
=SMBUS_BATT_SCL
47C1
L6903
SMBUS_BATT_SDA_F
BATT_NEG
120-OHM-0.3A-EMI
0402-LF
1
600-OHM-300MA
1
SMC_BS_ALRT_L_F
=SMBUS_BATT_SDA
47C1
L6904
19
120-OHM-0.3A-EMI
0402-LF
CRITICAL
L6908
127216FA020
0402
45C5 44B5 42C3 6B2
SMC_LID
J6950
600-OHM-300MA
F-ST-SM
C6911
0.001UF
10%
2 50V
CERM
402
SMC_LID_F
C6905
0.001UF
10%
50V
2 CERM
402
C6909
0.001UF
10%
2 50V
CERM
402
C6915
47pF
C6906
47pF
5%
2 50V
CERM
402
5%
2 50V
CERM
402
L6905
FERR-50-OHM
SM-LF
1
C6920
0.01uF
10%
2 16V
CERM
402
C6921
57A6 8D8
SMC_BS_ALRT_L
6D1 44C5 45C5
DC-In & Battery Connectors

SYNC_MASTER=POWER
A
=GND_BATT_CHGND
0.01uF
10%
2 16V
CERM
402
=GND_BATT_CHGND

MLB TOP VIEW
8D8 57A6
LID HALL EFFECT SENSOR
SIZE
PIN 1
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
57
76
01
S0 FETS & POWER SEQUENCING & PGOOD

D
CRITICAL
Q7000
FDM6296
65B5 58C6 58B3
G
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
10%
50V
CERM
402
TABLE_ALT_ITEM
376S0448
376S0445
MOSFET
CHANNEL
RDS(ON)
LOADING
0.0022UF
Q7000
P5VS0_EN
1.05V S0 RUN/SS CONTROL
7A8 58C8
5V S0 FET
C7003
TABLE_ALT_HEAD
PART NUMBER
=PP5V_S0_FET
MICROFET3X33
2
5
1
7C1 =PP5V_S5_FET
D
S
R7030
100K
FDM6296
N-TYPE
15 mOhm @4.5V
4.348 A
58C4 58C3 58B8 58B3 58A3
5%
1/16W
MF-LF
=PP3V3_S0_FET
402
2
1
7D6
Q7001
FDC655BN
1
=PP3V3_S5_FET
=PP3V3_S0_FET
SOT6
2
5
6
S
MOSFET
CHANNEL
RDS(ON)
LOADING
0.0022UF
10%
50V
CERM
402
P3V3S0_EN 1
FDC655BN
N-TYPE
33 mOhm @4.5V
1.810 A
Q7004
FDC655BN
=PP5V_S0_FET
65B5 58D5 58B3 7C1
1%
1/16W
MF-LF
402
2
=PP3V3_S0_FET
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
2
=PP1V8_S0_FET
0.0022UF
10%
CERM
402
VDD
P1V8S0_EN 1
U7000
R7004
7.5K
PGOOD_1V8S3 20
12
S0PWRGD_5V_DIV
17
S0PWRGD_3V3_DIV
14
S0PWRGD_1V8_DIV
QFN
UVLO_A
GATE_A
UVLO_B
UVLO_C
GATE_B
GATE_C
UVLO_D
GATE_D
DLY_ON_A
S0SEQ_BEGIN 1
NC
NC
NC
NC
R7006
R7005
22.1K
13.7K
1%
1/16W
MF-LF
2 402
ENABLE_1
DLY_ON_B
DLY_ON_C
9
11
19
22
NC
DLY_OFF_A
NC
DLY_OFF_B
NC
NC
DLY_OFF_C
DLY_OFF_D
RESET*
PM_SLP_S3_L
10
GND
62B8 45A6 44C5 35C7 33C7 24D3
2
5
6
7
RUNSS_GATE_D
21
8
16
15
TP_DLY_ON_A
TP_DLY_ON_B
TP_DLY_ON_C
TP_DLY_ON_D
R7040
330
5%
1/16W
MF-LF
1
402
1V25S0_RUNSS_BUF
2
5 G
FDC655BN
N-TYPE
33 mOhm @4.5V
0.260 A
58C2 58B2
65B5 58D5 58C6 7C1
S 4
RUNSS_GATE_D_L
THML
PAD
5%
1/16W
MF-LF
402
2
1
7D6 =PP3V3_S0_FET
=PP5V_S5_FET
R7061
470K
5%
R7051
330
5%
1/16W
MF-LF
1
402
1V5S0_RUNSS_BUF
2
Q7007
58C2
NOSTUFF
10%
16V
2 CERM
402
2 16V
CERM
402
R7007
47
NOSTUFF
C7022
0.01UF
10%
2 16V
CERM
402
C7023
0.022UF
10%
Q7006
D 6
2 G
S 1
1V5S0_RUNSS
D 3
5 G
6D7 61B5
C7050
0.001UF
SSM6N15FE
10%
2 50V
CERM
402
SOT563
1/16W
MF-LF
2402
NOSTUFF 1
C7021
C7024
0.01UF 0.01UF
10%
C7040
10%
2 50V
CERM
402

58D3 58C4 58C3 58B8 58A3
24
64B6
0.0012UF
SOT563
R7050
10K
18 DLY_OFF_A
13 DLY_OFF_B
3 DLY_OFF_C
4 DLY_OFF_D
1V25S0_RUNSS
D 3
Q7006
7B8 58B8
CRITICAL
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
MOSFET
CHANNEL
RDS(ON)
LOADING
C7005
25
58C4 7B8
50V
DLY_ON_D
5%
1/16W
MF-LF
402
2
1
7D6 =PP3V3_S0_FET
ISL6130IRZA
R7003
28.7K
C7000
6.3V
10%
CERM
402
1UF
62A3
58D3 58C4 58C3 58B3 58A3 7D6
0.01UF
R7041
100K
1.8V S0 FET
C7030
10%
2 16V
CERM
402
SSM6N15FE
=PP5V_S5_FET
1
R7002
R7001
30.9K
4.87K
=PP1V8_S0_FET
SOT6
23
58D4 7A8
S 1
RUNSS_GATE_D_L
2
5
6
2 G
61B5
58D3 58C4 58B8 58B3 58A3
CRITICAL
1
=PP1V8_S3_FET
D 6
1V05S0_RUNSS
3.3V S0 FET
C7004
7B4
Q7007
7D6 58A3 58B3 58B8 58C3 58D3

58C2 58B2
5%
1/16W
MF-LF
1
402
1V05S0_RUNSS_BUF
2
SSM6N15FE
SOT563
CRITICAL
65C4 65A5 7D1
R7031
330
S 4
RUNSS_GATE_D_L
SSM6N15FE
SOT563
2 16V
CERM-X5R
402
~26MS
5%
1/16W
MF-LF
402
DEASSERTED 160MS
AFTER UVLO_D VALID
=PP3V3_S0_FET
1
R7012
100K
PGOOD_SEQUENCER
TPS3808-1.25V
ALL_SYS_PWRGD_AND 3
MAKEBASE=TRUE
U7002.3 has int 90K pull-up
VDD
CRITICAL
SENSE
U7002
RESET*
MR*
SOT23-6
GND
61A6
61A3
PGOOD_1V05S0
PGOOD_1V5S0
10%
2 16V
X5R
402
5%
1/16W
MF-LF
2402
7D6 58B3 58B8 58C3 58C4 58D3
C7001
0.1UF
CT
=PP1V25_S0_FET
7C7
S0 FETS & Power Sequencing
ALL_SYSPWRGD_DLY
1
C7002
0.001UF
ALL_SYS_PWRGD
10%
2 50V
CERM
402

6B2 27A5 44D8

SIZE
LATEST ISSUE: 2007/01/02
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
58
76
01
=PP5V_S0_CPU_IMVP
7A7
59D8 59C2 48D7 7B1
R7112
1UF
10%
6.3V
CERM
402
10
5%
1/16W
MF-LF
402
PSI*
Operation Mode
0
0
1
1
1
1
0
0
1
0
1
0
2-Phase CCM
10UF
PPVIN_S5_IMVP6_VIN
R7120
10
5%
1/16W
MF-LF
402
PM_DPRSLPVR
DPRSTP*
20%
6.3V
X5R
603
=PPVIN_S5_CPU_IMVP
59C2 48D7 7B1

59D4
24C3 15A6
70B3 IN
C7135
DPRSLPVR
C7196
0.01UF
10%
16V
CERM
402
5%
1/16W
MF-LF
402
VIN
R7126
470K
402
70A3
70A3
2
1
R7145
NO STUFF
C7110
499
ERT-J0EV474J
1%
1/16W
MF-LF
2 402
0.01uF
IMVP6_NTC_R
70A3
70A3
CPU_DPRSTP_L
70B3 IMVP_DPRSLPVR
27B2
IN IMVP6_PSI_L
70B3 22C4 15B6 9B2
NO STUFF
R7106
44C5
48C1 OUT
R7146
1/16W
MF-LF
4.53K
1% 27A7
1/16W
FROM SMC MF-LF
402
27B5 15B6
IN
OUT
147K
0.015uF
1%
1/16W
MF-LF
402
10%
16V
X7R
402
59A4
59A4 6D7
IMVP6_SOFT
R7125
CRITICAL
U7100BOOT2
59A6
41 VID4
40 VID3
QFN
39 VID2
38 VID1
37 VID0
46 DPRSTP*
45 DPRSLPVR
2 PSI*
3 IMON
48 3V3
IMVP6_VR_TT
IMVP6_NTC
31
PVCC
59A8 36
BOOT1
43 VID6
42 VID5
VR_PWRGD_CK505_L 47 CLK_EN*
44 VR_ON
IMVP_VR_ON
VR_PWRGOOD_DELAY 1 PGOOD
OUT
R7108
C7105
IMVP6_PMON
VDD
NO STUFF
CPU_PROCHOT_L 402
1
IN
1
SMC_CPU_ISENSE
0
5%
70C3 45C3 45B5 9C5
CPU_VID<6>
10B7 CPU_VID<5>
10B7 CPU_VID<4>
10B7 CPU_VID<3>
70A3
10B7 CPU_VID<2>
70A3
10B7 CPU_VID<1>
10B7 CPU_VID<0>
70A3 10B7
CRITICAL
10%
16V
CERM
402
22
20
R7127
59A8
UGATE1
59A8
PHASE1
59A8
LGATE1
PGND1
59A8
ISEN1
R7109
1K
1%
1/16W
MF-LF
2 402
0.001UF
10%
50V
CERM
402
R7113
1K
IMVP6_VDIFF_RC
1
R7111
1%
1/16W
MF-LF
402
IMVP6_PHASE2
IMVP6_LGATE2
(GND)
59A4 48C5
VO
29
12 FB2
11 FB
VSEN
10 COMP
9 VW
RTN
16
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
17
IMVP6_DFB
18
49
0.068UF
10%
10V
CERM
402
59A4
C7113
220PF
R7114
C7107
0.001UF
10%
50V
CERM
402
NO STUFF
NO STUFF
1
C7100
0.0022UF
R7100
C7190
10%
50V
CERM
402
C7103
10K
R7104
0.22uF
1%
1/16W
MF-LF
402
0.0022UF
10%
50V
CERM
402
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
C
1
1 2 3
C7116
R7118 R7117
1%
1/16W
MF-LF
2 402
10%
50V
CERM
402
4.32K
1%
1/16W
MF-LF
402
C7129
180pF
5%
2 50V
CERM
402
C7101
33UF
20%
16V
POLY
CASED2E-SM
1
C7108
33UF
20%
16V
2
POLY
CASED2E-SM
59D8
59D4
7B1
48D7
C7199
1UF
10%
25V
X5R
603
R7101
3.65K
1%
1/16W
MF-LF
2 402
RJK0305DPB
LFPAK
(IMVP6_PHASE2)
CRITICAL
Q7103
R7116
RJK0301DPB
LFPAK
L7101
CRITICAL
0.36UH-30A-0.80MOHM
Q7105
MPC1055-SM
MPC1055LR36
DCR=0.8mOhm
RJK0301DPB
LFPAK
1%
1/16W
MF-LF
2 402
1 2 3
R7130
3.92K
0.033UF
10%
16V
X5R
402
C7128
0.22UF
10%
6.3V
CERM-X5R
402
R7115
11K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
NO STUFF
IMVP6_VO_R
CRITICAL
R7131
C7102
NO STUFF
2
R7152
10K
R7143
3.65K
10%
50V
CERM
402
10KOHM-5%
5%
1/16W
MF-LF
402
C7192
0.0022UF
R7107
10%
6.3V
CERM-X5R
402
NO STUFF
1
0.0022UF
10%
50V
CERM
402
0.22uF
1%
1/16W
MF-LF
402
1 2 3
C7104
10K
C7134 1
R7105
(IMVP6_VO)
CRITICAL
13.7K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
(IMVP6_ISEN2)
0603-LF
2
C7133
(IMVP6_VSUM)
ERT-J1VR103J
0.018UF
97.6K
1/16W
MF-LF
402
1 2 3
0.1UF
6.81K
1%
1/16W
MF-LF
2 402
Q7102
10%
16V
CERM
402
R7110
NO STUFF
C7132
MPC1055LR36
DCR=0.8mOhm
=PPVIN_S5_CPU_IMVP
CRITICAL
CRITICAL
0.01UF
5%
25V
CERM
402
Q7104
MPC1055-SM
RJK0301DPB
1 2 3
C7115
1K
C7131
0.36UH-30A-0.80MOHM
CRITICAL
15
7D8
NO STUFF
R7151
10K
1%
10%
16V
2 X5R
402
10%
16V
X5R
402
CRITICAL
LFPAK
NO STUFF
470PF
0.1UF
14
TPAD
GND_IMVP6_SGND
(IMVP6_VW)
IMVP6_COMP_RC
=PPVORE_S0_CPU_REG
L7100
RJK0301DPB
IMVP6_ISEN2
59A4
10%
50V
CERM
402
Q7101
59A4
CRITICAL
CRITICAL
0.001UF
21
C7114
1%
1/16W
MF-LF
2 402
(IMVP6_PHASE1)
C7127
PWM FREQ. = 300 kHz

MAX CURRENT = 44A
LFPAK
1UF
10%
25V
X5R
603
1-Phase DCM
C7118
20%
16V
POLY
CASED2E-SM 2
(IMVP6_ISEN1)
30
PGND2
GND
59A4
59C8
IMVP6_ISEN1
25 NC
(IMVP6_FB)
24
IMVP6_UGATE2
59A6
LGATE2
1%
1/16W
MF-LF
2 402
IMVP6_LGATE1
(GND)
19
255
33
59A4
VSUM
OCSET 8
IMVP6_VDIFF
59A4
32
7 SOFT
13 VDIFF
59A4
IMVP6_PHASE1
59A6 23
ISEN2
4 RBIAS
IMVP6_FB2
IMVP6_FB
59A4 6D7 IMVP6_COMP
59A4 IMVP6_VW
NO STUFF
34
59A6 28
PHASE2
59A4
DFB
C7106
IMVP6_UGATE1
5%
1/16W
MF-LF
402
59A6 27
UGATE2
59A4
48D5
DROOP
59A4
26
35
5 VR_TT*
6 NTC
IMVP6_RBIAS
IMVP6_BOOT1
IMVP6_BOOT2
C7117
33UF
1 2 3
5%
1/16W
MF-LF
402
1
2 IMVP6_BOOT2_RC
0.1uF
10%
16V
X5R
402
NO STUFF
4.02K
1%
1/16W
MF-LF
402
1-Phase DCM
IMVP6_BOOT1_RC
20%
16V
POLY
CASED2E-SM
1-Phase CCM
IMVP6_VSEN
R7121
GND_IMVP6_SGND
NO STUFF
RJK0305DPB
C7109
33UF
LFPAK
R7124
C7130
10
59B7 59A4
Q7100
PP3V3_S0_IMVP6_3V3
IMVP6_RTN
=PP3V3_S0_IMVP1
ISL9504BCRZ
7C4
CRITICAL
5
CRITICAL
CRITICAL
VOLTAGE=5V
C7126
=PPVIN_S5_CPU_IMVP
PP5V_S0_IMVP6_VDD
10%
16V
X7R
402
(IMVP6_VO)
(IMVP6_COMP)
1
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY.

2
OMIT
C7121
10%
6.3V
CERM-X5R
402
5%
1/16W
MF-LF
2 402
0.22uF
XW7100
SM
1
R7123
0
R7122
TABLE_ALT_HEAD
5%
1/16W
MF-LF
2 402
10A6 59A4 70A3

10A6 59A4 70A3
IMVP6 CPU VCORE REGULATOR
59B6
59C8 59B7
59B6 48C5
59B6 48D5
59B6
59C7
59B7 6D7
59C6
59C6
59C6
59C6
59C6
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
MIN_LINE_WIDTH
1.5 MM
0.25 MM
1.5 MM
1.5 MM
0.25 MM
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
59C6
59C6
59C6
59C6
59C6
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
59B7
59B7
59B7
59B7 6D7
59B7
59A5 10A6
70A3
70A3 59A5 10A6
59B6

8
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
128S0093
128S0092
C7101,C7108 KEMET
T520V336M016ATE0457650
128S0093
128S0092
C7109,C7117 KEMET
T520V336M016ATE0457650
TABLE_ALT_ITEM
CPU_VCCSENSE_P
CPU_VCCSENSE_N
59C6
PART NUMBER
59B5
IMVP6_OCSET
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_RTN
IMVP6_VSEN
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.50 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
TABLE_ALT_ITEM
IMVP6 CPU VCore Regulator

SYNC_MASTER=POWER

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
59
76
01
RENDER VCORE POWER SUPPLY
60C5 60A7 60A5
GND_GCORE_SGND
R7217
150K
1%
1/16W
MF-LF
402
1
2
GCORE_VDD1
60A7
C7221
GCORE_RBIAS
=PP5V_S0_NB_GFX_IMVP
7A7
R7202
10
5%
1/16W
MF-LF
402
1
60A7 GCORE_PVCC
1UF
10%
60A5
6.3V
CERM
402
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
128S0093
128S0092
REF DES
COMMENTS:
TABLE_ALT_ITEM
1%
1/16W
MF-LF
2402
R7222
10K
1%
1/16W
MF-LF
2402
R7220
30K
60B2 44A2
5%
1/16W
MF-LF
2 402
R7225
VDD
PVCC
R7224
10K
5%
1/16W
MF-LF
402
1/16W
MF-LF
402
1
2
1 RBIAS
2 SOFT
NC 31
R7223
10K
15B3
21B6
15B3
21B6
5%
1/16W
MF-LF
402
15B3
21B6
15B3
21B6
1 C7213
C7214
0.001UF 0.001UF
10%
2 50V
CERM
402
15A3
10%
2 50V
CERM
402
23
GFX_VID<0>
24
GFX_VID<1>
25
GFX_VID<2>
26
GFX_VID<3>
27
GFX_VID<4>
8B1 GFX_VR_EN 29
30
GCORE_AF_EN
GCORE_FDE 32
60A5 GCORE_VSEN 8
60A5 GCORE_RTN 9
60A5
PGOOD
VID0
VID1
VID2
VID3
VID4
VR_ON
AF_EN
FDE
VSEN
RTN
VIN
R7214
6.98K
0.001UF
10%
1%
1/16W
MF-LF
2402
2 50V
CERM
402
10%
50V
CERM
402
60A5
19 GCORE_PHASE
60A7
LGATE
21
60A5
OCSET
60A7
DFB
R7208
6 FB
60A5
R7216 1R7215
0
0
5%
1/16W
MF-LF
2402
1/16W
MF-LF
402
60A5
15
C7208
THRM_PAD
XW7200
SM
60A7
R7210
2.94K
1%
1/16W
MF-LF
402
1
330PF
10%
R7212
60C5
60C5
60C5
60D7 60C5 60A5
60D5
60D5
60C5
60B5
60B5
60B5
GCORE_PHASE
GCORE_BOOT
GCORE_UGATE
GCORE_LGATE
GCORE_BOOT_RC
GND_GCORE_SGND
GCORE_VDD
GCORE_PVCC
GCORE_VIN
GCORE_DROOP
GCORE_VSUM
GCORE_DFB
PLACE RC CLOSE TO SMC
GPU_ISENSE1
CRITICAL
R2
U7201
R7207 C7203
470PF
1/16W
MF-LF
402
SMC_GPU1_ISENSE 44A2
60C7
R7227 C7222
0.22UF
1
4.53K
INA326EA-250
1%
MSOP
200K
1%
1/16W
MF-LF
402
20%
6.3V
2 X5R
402
GND_SMC_AVSS 44C1
45B6 48A1 48B1 48C1 48C6 61C5 62C2 66B1 66C2
10%
50V
2 CERM
402
OMIT
C7205
50V
CERM
402
20%
6.3V
2 X5R
603
C7219
10UF
CRITICAL
1
C7220
330UF
20%
2.5V
2 POLY
CASE-D2E-LF
C7206
0.1UF
MIN_LINE_WIDTH
1 MM
0.3 MM
1 MM
1 MM
0.3 MM
0.6 MM
0.3 MM
0.3 MM
0.3 MM
0.3 MM
0.3 MM
0.3 MM
PLACE C7221 NEAR U7201 PIN 7
4
V-
1%
1/16W
MF-LF
402
50V
CERM
402
2
1
2.21K
1%
60C5
7C4 61C5 66C3
1%
1/16W
MF-LF
402
GPU_ISENSE_R2
1%
1/16W
MF-LF
402
0.001UF
10%
1
=PP3V3_S0_PDCISENS
R7209
C7207 1K
0.0018UF
10%
50V
CERM
402
2
1
2 GCORE_VDIFF_RC
1/16W
MF-LF
402
1
8 R1+
3
R7204
C7204
750
47PF
5%
2 50V
CERM
402
1/16W
MF-LF
402
10
33
VSS
GCORE_FB
R7211
1.1K
1%
PGND
20
10%
50V
CERM
402
2
1
2 GCORE_FB_RC
15.8K
1%
DROOP
60A5
60C5
GPU_ISENSE_R1_P
Placement Note:
7
2
1 R1- V+
GCORE_VSUM_R
3 GCORE_OCSET
11 GCORE_DFB
R7206
2.21K
1%
1/16W
MF-LF
402
12
GCORE_DROOP
1%
1/16W
2 MF-LF
402
60A5 1
GCORE_COMP 5 COMP
10%
16V
X5R
402
GPU_ISENSE_R1_N
1 2 3
C72231 R7226
0.1UF
100
LFPAK
VO
GCORE_VDIFF
5%
50V
CERM
402
GPU_ISENSE_VCC
RJK0303DPB
GCORE_VW 4 VW
C7209
680PF
7B8
1/4W
MF-LF
1206
Q7201
GCORE_LGATE
=PPVCORE_S0_NB_GFX_IMVP
0.002
1%
CRITICAL
7 VDIFF
C7210
R7213
150PF 1 150K
PWM FREQ. = 333 kHz

MAX CURRENT = 7.7A
CRITICAL
L7200
0.82UH-16.5A
IHLP2525EZ-SM
CRITICAL
1
2
1
2
1 2 3
R7205
C7211
20%
16V
POLY
CASED2E-SM
LFPAK
1
1
C7218 1 CRITICAL
C7217
33UF
10%
25V
X5R
603
RJK0305DPB
13 GCORE_VSUM
60A7
VSUM
C7212
0.001UF
5%
1/16W
MF-LF
2402
Q7200
16V
X5R
MF-LF
402
402
2
2 GCORE_BOOT_RC
7B1
1UF
CRITICAL
60D7
0.1UF
10%
18 GCORE_UGATE 1/16W
17 GCORE_BOOT 1
60A7
BOOT
60A7
PHASE
C7201
R7201
0
5%
60A7
UGATE
KEMET T520V336M016ATE0457650
=PPVIN_S5_NB_GFX_IMVP
4
14
C7217
C7200 R7200
0.01UF 10
10%
5%
1/16W
2 25V
X7R
MF-LF
402
402
GND_GCORE_SGND 60A5 60A7
U7200
CRITICAL
QFN
28 IMON
5%
1/16W
MF-LF
402
60A7 GCORE_VIN
GCORE_PMON
100K
5%
R7203
C7202
2.2UF 1
20%
6.3V
CERM1
2 603
22
10K
1%
16V
1/16W
X7R
MF-LF
402
402
SMC_GPU1_ISENSE1
2
ISL6263B
R7221
GCORE_SOFT
STUFF
C7215 NO
R7218
0.015UF
4.53K
10%
7C4
NO STUFF NO STUFF 1
60A5
16
=PP3V3_S0_NB_GFX_IMVP
60D7 60C5 60A7
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
10%
2 16V
X5R
402
GND_GCORE_SGND
I103
60B5
I104
60B6
I105
60B6
I106
60C6
I107
60D6
I108
60C6
I109
60B6
I110
60B6
I111
60B6
I112
60B6
I113
60B6
GCORE_OCSET
GCORE_VW
GCORE_RTN
GCORE_VSEN
GCORE_RBIAS
GCORE_SOFT
GCORE_COMP
GCORE_FB
GCORE_VDIFF
GCORE_FB_RC
GCORE_VDIFF_RC
MIN_LINE_WIDTH MIN_NECK_WIDTH
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
0.3 MM
0.25 MM
I115
I116
I117
I118
Render VCore Supplies
I119
I120
SYNC_MASTER=GPU
I121
I122
I123

I124
I125
I114

SIZE
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
60
76
01
1.5V/1.05V POWER SUPPLY

=PP1V05_S0_REG_RNB_ISENSE_VCC
7D8
22UF
Placement Note:
10%
16V
X5R
402
20%
2 6.3V
CERM
805
PLACE C7390,C7391
NEAR NB
=PP3V3_S0_PDCISENS
7C4 60C2 66C3
C73031 R7390
0.1UF
100
C7390
State
S0
S3/S5/G3Hot
1%
1/16W
MF-LF
402
Placement Note:
1%
1/16W
MF-LF
402
U7301
4.53K
INA326EA-250
1%
MSOP
C7351
10UF
20%
2 6.3V
X5R
603
402
45B6 48A1 48B1 48C1 48C6 60B2
62C2 66B1 66C2
1%
1/16W
MF-LF
402
1/16W
MF-LF
402
402
1V51V05S0_V5FILT
1
Routing Note:
The discharge path (VO1) should have
a dedicated trace to the output cap;
separate from the output voltage
sensing trace,
61A3
PWM FREQ. = 300 kHz

MAX CURRENT = 8A
1
2
=PP1V05_S0_REG
B
1
2
<Rc>
NO STUFF 1
C7329 R7327
7.68K
100PF
5%
50V
CERM
402
1%
1/16W
MF-LF
2 402
Q7321
SI7108DNS
PWRPK-1212-8
<Rd>
NO STUFF 1 R7328
20.0K
C7328
1%
1/16W
0.001UF
2 10%
50V
CERM
402
CRITICAL
CRITICAL
C7352
2 330UF
20%
2.5V
POLY
CASE-D2E-LF
R7361,C7305 close to U7300 pin 15.

C7301 close to U7600 pin 16.
20%
6.3V
X5R
603
7A1
R7324
0
R7326
1/16W
MF-LF
402
NO STUFF
1
MF-LF
2 402
V5FILT
1
1V05S0_VBST 22
1V05S0_VH
21
mm
1V05S0_LL
20
mm
1V05S0_VL
19
VO1
VBST1
DR_VH1
LL1
DR_VL1
24
TRIP1
VFB1
PGOOD1
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
1V05S0_TRIP 17
1V05S0_VFB
2
1V05S0_LL_RC
S
3 2 1
NO STUFF
274K
1%
OMIT
Routing Note:
sensing trace,
7A1
10%
5%
16V
1/16W
X5R
MF-LF
402
402
2
1 1V05S0_VBST_RC
1
2
3 2 1
SM-IHLP
1
10UF
10%
10V
X5R
402
GND_1V51V05S0_SGND
C7324
0.1UF
CRITICAL
S
L7320
1.0UH-13A-5.6M-OHM
VOLTAGE=1.05V
=PP5V_S5_1V51V05S0
C7301 Placement Note:
7C1
PWRPK-1212-8
POLY
2 CASED2E-SM
X5R
603
C7305
1UF
CRITICAL
C73411 C7340 CRITICAL
Q7320
1UF
33UF
10%
20%
SI7110DN
25V
16V
R7361
3.3
5%
10%
50V
2 CERM
=PPVIN_S5_1V05S0
7D8 6B2
20%
6.3V
2 X5R
GND_SMC_AVSS 44C1
R7391 C7399
470PF
200K
1/16W
MF-LF
402
NB_ISENSE_R2
NB_ISENSE_R1_P
SMC_NB_CORE_ISENSE 44A8
1
C7325
0.1UF
10%
R7325
6.65K
1%
1/16W
MF-LF
2 402
16V
X5R
402
R7364
0
5%
1/16W
MF-LF
402
V5IN
6
9 1V5S0_VBST 1
101V5S0_VH MIN_LINE_WIDTH=1 mm
111V5S0_LL MIN_LINE_WIDTH=1 mm
121V5S0_VL MIN_LINE_WIDTH=1 mm
TRIP2
VFB2
PGOOD2
141V5S0_TRIP
5 1V5S0_VFB
7
CRITICAL
U7300
TPS51124
QFN
10%
16V
X5R
402
1
2 1V5S0_VBST_RC2
1V05S0_RUNSS
23 EN1
8 EN2
6D7 1V5S0_RUNSS
58B1
GND
C7398
220PF
5%
25V
CERM
402
TONSEL
4 NC
128S0093
128S0092
Q7361
25V
CERM
402
1%
1/16W
MF-LF
2 402
220PF
5%
COMMENTS:
SI7110DN
C7392
330UF
10%
3 2 2.0V
TANT
D2T
R7365
3.74K
=PP1V5_S0_REG
JUMPER
7C8
62C5
VOLTAGE=1.5V
CRITICAL
CRITICAL
C7389
XW7320
OPEN-SAWTOOTH
PGND THRM_PAD
PWM FREQ. = 360 kHz

MAX CURRENT = 4A
20%
16V
POLY
2 CASED2E-SM
PP1V5_S0_REG_P
<Ra> 1
C7350 R7367
20.0K
10UF
20%
6.3V
2 X5R
603
2 1%
1/16W
MF-LF
402
NO STUFF
C7369
100PF
5%
50V
CERM
402
1 2 3
<Rb>
R7368
20.5K
1%
1/16W
MF-LF
2 402
GND_1V51V05S0_SGND
Vout = 0.758V * (1 + Ra / Rb)
Routing Note:
put 6 vias under the thermal
pad (pin 25)
TABLE_ALT_HEAD
REF DES
10%
25V
X5R
603
1 2 3 SM-IHLP
Vout = 0.758V * (1 + Rc / Rd)

BOM OPTION
MICROFET3X3
C7381 1 C7380
1UF
33UF
CRITICAL
L7360
1.0UH-13A-5.6M-OHM
61B6
ALTERNATE FOR
PART NUMBER
PWRPK-1212-8
58D1
CRITICAL
Q7360
FDM6296
XW7300
SM
PART NUMBER
=PPVIN_S5_1V5S0
CRITICAL
5
D
C7364
0.1UF
VO2
VBST2
DR_VH2
LL2
DR_VL2
SYM(1 OF 2)
25
PP1V05_S0
1.05V
0.00V
R7305 C7306
0.22UF
16
1/4W
MF-LF
2 1206
CRITICAL
R2
13
0.002
1%
8 R1+
3
NB_ISENSE 1
PP1V5_S0
1.5V
0.0V
R7302
R7392
2.21K
15
CRITICAL
4
V-
18
NB_ISENSE_R1_N
7
2
1 R1- V+
PM_SLP_S3_L
HIGH
LOW
TABLE_ALT_ITEM
C7380,C7340 KEMET
T520V336M016ATE0457650
58A5
PGOOD_1V05S0
PGOOD_1V5S0
Note: pu on PGOOD page
58A5
"note: pu on pgood page"
1.5V / 1.05V Supplies

SYNC_MASTER=POWER

TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
376S0448
376S0445
Q7360
COMMENTS:
TABLE_ALT_ITEM

SIZE
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
61
76
01
1.8V/0.9V POWER SUPPLY
State
PM_SLP_S4_LPM_SLP_S3_LPP1V8_S3
S0
HIGH
HIGH
1.8V
S3
HIGH
LOW
1.8V
S5/G3Hot
LOW
LOW
0.0V
Vout = 0.75V * (1 + Ra / Rb)
NO STUFF
<Rb>
1
2
1
2
1V8S3_VDDQSET
R7522
<Ra>
C7503
20.0K
1%
100PF
R7521 5%
1/16W
MF-LF
28K
402
MEM_ISENSE_VCC
Placement Note:
0.1UF
10%
=PP1V8_S3_REG_R
CONNECT VDDQSNS TO C7542 PIN1

using separate trace.
=PP1V5_S0_REG
1 C7501
MEMVTT_VREF
C7540
0.033UF
10%
16V
X5R
402
1
R7560
C7500
1UF
62A6
5%
1/16W
MF-LF
402
4
V-
20%
6.3V
X5R
603
MEM_ISENSE1
CRITICAL
R2
R7503
4.53K
U7501
1%
INA326EA-250
1/16W
MSOP
R7563
1%
1/16W
MF-LF
402
10%
2 50V
CERM
402
200K
MEM_ISENSE_R1_P
7A4 62A2
Placement Note:
MF-LF
402
MEM_ISENSE_R2
10UF
5%
1/16W
MF-LF
402
10%
10V
X5R
402
2.94K
1%
1/16W
MF-LF
402
CRITICAL
1
R7502
=PP5V_S5_1V8S30V9S0 0.002
1%
1/4W
MF-LF
R7507 1 C7502
21206
4.7
1V8S3_V5FILT
1
8 R1+
3
=PP3V3_S3_PDCISENS
R7561
100
7
2
1 R1- V+
7C8 61B1
10UF
20%
2 6.3V
X5R
603 GND_1V8S3_VTTGND
16V
X5R
402
7B5
MEM_ISENSE_R1_N
C75041
PLACE C7543 NEAR NB
Routing Note:
50V
CERM
402
1%
1/16W
MF-LF
402
1
2
PP0V9_S0
0.9V
0.0V
0.0V
SMC_NB_1V8_ISENSE
1
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
C7564
470PF
44A8
C7505
44C1 45B6 48A1 48B1 48C1 48C6 60B2 61C5 66B1 66C2
=PP0V9_S0_REG
7D8
1%
1/16W
MF-LF
2 402
VDDQSET VTTREF VLDOIN VTT V5FILT
5%
1/16W
MF-LF
402
VBST V5IN VDDQSNS VTTSNS
Routing Note:
CONNECT VTTSNS TO C7507 PIN1

using separate trace.
58B7 45A6 44C5 35C7 33C7 24D3

65C2
PM_SLP_S3_L
1V8S3_RUNSS
10
11
S3
S5
PGOOD
CRITICAL
DRVH
LL
U7500
SYM (1 OF 2)
1V8S3_CS 16
13
21 1V8S3_DRVH
20 1V8S3_LL
TPS51116
COMP
QFN
CS
Routing Note:
DRVL
19 1V8S3_DRVL
MODE
Connect CS_GND to
Q7521 PIN1,2.3
using Kevin connection.
NC0
NC1
=PPVIN_S5_1V8S30V9S0
CRITICAL 1 C7531
CRITICAL
1 C7530
1UF
Q7520
10%
33UF
25V
7A1
R7500
0
15
22
14
24
23
R7510
8.25K
1V8S3_VBST_RC
1
1V8S3_VBST
1
C7509
0.1uF
10%
16V
X5R
402
SI7110DN
1 2 3
SM-IHLP
1
MIN_LINE_WIDTH=1 mm
=PP1V8_S3_REG
CRITICAL
SI7108DNS
PWRPK-1212-8
7B6
OMIT
OMIT
Q7521
CRITICAL
CRITICAL
D
7 NC
12 NC
PWM FREQ. = 400 kHz

MAX CURRENT = 10.75A
VOLTAGE=1.8V
MIN_LINE_WIDTH=1 mm
20%
2 X5R
16V
603
POLY
CASED2E-SM
CRITICAL
L7520
1.0UH-13A-5.6M-OHM
MIN_LINE_WIDTH=1 mm
PWRPK-1212-8
C7542
330UF
1
1
C7541
10UF
20%
20%
2.5V
6.3V
2 POLY
CASE-D2E-LF 2 X5R
603
C7543
330UF
20%
2 2.5V
POLY
CASE-C2
62C5
GND
PGND
VTTGND
18
CS_GND
17
C7508
10UF
20%
2 6.3V
X5R
603
THRM_PAD
25
C7507
10UF
20%
2 6.3V
X5R
603
1 2 3
GND_1V8S3_VTTGND
XW7501
SM
GND_1V8S3_SGND
Routing Note:
put 6 vias under the thermal pad
Placement Note:
PLACE XW7500,XW7501 NEAR C7542 PIN 2
PGOOD_1V8S3
XW7500
SM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
128S0093
128S0092
C7530
KEMET T520V336M016ATE0457650
58B6
R7599
100K
TABLE_ALT_HEAD
5%
1/16W
MF-LF
402
2
=PP3V3_S3_PDCISENS
1.8V/0.9V Supplies
SYNC_MASTER=POWER

SIZE
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
62
76
01
5V/3.3V POWER SUPPLY
State
G3H
SMC_PM_G2_EN
PP3V3_G3H
PP5V_S5
PP3V3_S5
LOW
HIGH
3.3V
3.3V
0.0V
5.0V
0.0V
3.3V
S0/S3/S5
Vout = 1V * (1 + Ra / Rb)
<Ra> CRITICAL<Rb>
R7667
R7668
20K
4.99K
Vout = 1V * (1 + Rc / Rd)
<Rd>CRITICAL<Rc>
R7628
R7627
8.66K
20K
CRITICAL
XW7660
OPEN-SAWTOOTH
1
2
=PP5V_S5_REG
3 2 1
1
L7660
VOLTAGE=5V
PP5V_S5_REG_P
OMIT
CRITICAL
1
C7690
C7691
2.2UF
150UF
10%
2 16V
X5R
603
20%
2 6.3V
POLY
CASE-B2
6D7
65C5
3.3UH
OMIT
CRITICAL
C7692
Q7661
150UF
20%
2 6.3V
POLY
SI7110DN
PWRPK-1212-8
CASE-B2
63C4 63B4 63A4
3 2 1
GND
COMP2
VO2
VFB1
VREF2
VO1
VFB2
11
EN2
RSMRST_PWRGD 44D8
12
5%
1/16W
MF-LF
402
13 3V3S5_VBST
5VS5_DRVL
25 DRVL1
mm
128S0093
128S0092
REF DES
1%
1/16W
MF-LF
402
MICROFET3X3
XW7620
1 2 3
OPEN-SAWTOOTH
L7620
IHLP
OMIT
CRITICAL
4
63A4 63B6 63C4
1%
1/16W
MF-LF
Q7621
PWRPK-1212-8
20%
2 6.3V
POLY
CASE-B2
C7652
150UF
C7651
150UF
20%
2 6.3V
POLY
CASE-B2
C7640
T520V336M016ATE0457650
KEMET T520V336M016ATE0457650
376S0445
Q7620
C7602
1UF
10%
2 25V
X5R
603
TABLE_ALT_ITEM
376S0448
20%
603
5V3V3S5_V5FILT 63C4
C7650
10UF
2 6.3V
X5R
5V3V3S5_VREG3
5%
1/16W
MF-LF
402
TABLE_ALT_ITEM
128S0092
5%
1/16W
MF-LF
TABLE_ALT_ITEM
128S0093
PP3V3_S5_REG_P
2 402
=PPVIN_S5_5VS5
COMMENTS:
C7682,C7680 KEMET
KEMET T520V336M016ATE0457650
1 C7605 1 C7603
C7604
1UF
10UF
10UF
10%
2 10V
X5R
402
20%
6.3V
X5R
603
20%
2 6.3V
X5R
603
GND_5V3V3S5_SGND
5V/3.3V Supplies
Placement Note:
R7601,C7605
C7602 close
C7604 close
C7603 CLOSE
R7605,R7603
close to
to U7600
to U7600
TO U7600
close to
U7600 pin 20.

pin 22.
pin 21.
PIN 19.
U7600.
SYNC_MASTER=POWER

63B4 63B6 63C4

SIZE

7
XW7601
SM
7D3
OMIT
CRITICAL CRITICAL
1
SI7110DN
=PP3V3_S5_REG
VOLTAGE=3.3V
4.7UH
C7671
0.01UF
JUMPER
CRITICAL
NO STUFF
R7603
1
R7671
5.90K
100K
2 402
PWM FREQ. = 430 kHz

MAX CURRENT = 5A
FDM6296
10%
2 16V
CERM
402
20%
16V
POLY
CASED2E-SM
Q7620
1 2 3
1
R7605
7.87K
CRITICAL
C7640
33UF
CRITICAL
GND_5V3V3S5_SGND
TABLE_ALT_HEAD
BOM OPTION
3V3S5_RUNSS
R7601
4.7
ALTERNATE FOR
PART NUMBER
3V3S5_VBST_RC2
R7670
100K
PART NUMBER
1
2
16V
X5R
402
GND_5V3V3S5_SGND
5%
1/16W
MF-LF
402
0.1UF
10%
65C5
C7641
1UF
10%
2 25V
X5R
603
C7620
R7620
0
143V3S5_DRVH
5VS5_LL
26 LL1
mm
45D5 63B5
MIN_LINE_WIDTH=1 mm
DRVH2
MIN_LINE_WIDTH=1 mm
LL2 153V3S5_LL
MIN_LINE_WIDTH=1 mm
DRVL2 163V3S5_DRVL MIN_NECK_WIDTH=0.25 mm
NO STUFF1
7A1
63B6
PGOOD2
NC
NC
27 DRVH1
5VS5_DRVH
mm
5VS5_RUNSS
5%
25V
CERM
402
=PPVIN_S5_3V3S5
7A1
VBST2
C7670
220PF
CRITICAL
10
EN1
NO STUFF1
IHLP
C7622
22PF
28 VBST1
5VS5_VBST
CRITICAL
JUMPER
EN3
PGND2
PWRPK-1212-8
29
2
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25
PGOOD1
EN5
LLP
17
SI7110DN
1 5VS5_VBST_RC
1
402
18 CS2
3V3S5_CS
7C3
30
3V3S5_VFB
5%
U7600
V5FILT
PWM FREQ. = 280 kHz

MAX CURRENT = 7.5A
63A4
2 50V
CERM
TPS51120
VREG3
Q7660
TONSEL
Routing Note:
sensing trace,
5%
50V
CERM
402
SYM (2 OF 3)
5%
1/16W
MF-LF
402
16V
X5R
402
SKIPSEL
31
20
CRITICAL
R7660
0
0.1UF
10%
32
19
C7660
603
RSMRST_PWRGD
VIN
63B4 45D5 44D8
22
1UF
10%
2 25V
X5R
PWPD
C7627
100PF
CRITICAL
33
21 VREG5
5VS5_VREG
C7681
NO STUFF
5V3V3S5_V5FILT
COMP1
Routing Note:
put 6 vias under the thermal pad
(pin 33)
10%
50V
CERM
402
5VS5_VFB
PGND1
C7680
33UF
20%
2 20%
16V
16V
POLY
POLY
CASED2E-SM
CASED2E-SM
0.1%
1/16W
MF
402
C7600
0.001UF
2
25V3V3S5_VREF
24
C7682
33UF
5%
1/16W
MF-LF
402
0.1%
1/16W
MF
402
GND_5V3V3S5_SGND
63B6 63B4 63A4
R7610
0
5%
50V
CERM
402
=PPVIN_S5_5VS5
CRITICAL 1 CRITICAL
C7667
100PF
2
5V3V3S5_TONSEL
NO STUFF
23 CS1
5VS5_CS
Routing Note:
sensing trace,
CRITICAL
0.1%
1/16W
MF
402
0.1%
1/16W
MF
402
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
63
76
01
3.425V G3H SUPPLY
Supply needs to guarantee 3.31V delivered to SMC VRef generator

7B1
=PPVIN_G3H_P3V42G3H
P3V42G3H5_BOOST
3
VIN
BOOST
C77911
CRITICAL
U7790
LT3470
SHDN*TSOT23-8 SW
BIAS
NC 2
CRITICAL
L7790
33uH
0.22uF
10%
2
6.3V
CERM-X5R
402
CDPH4D19F-SM
1
5 PP3V42G3H_SW
7
22pF
GND
P3V42G3H_FB
1
=PP3V42_G3H_REG
7C3
<Ra>
1
1 C7792 R7791
348K
NC
FB
PWM FREQ. = 1 MHz @16.5V

MAX CURRENT = 0.2A
5%
2 50V
CERM
402
CRITICAL
C7790
10UF
10%
1%
1/16W
MF-LF
2402
1 C7793
22UF
20%
<Rb>
2 6.3V
CERM
1
R7792
805
200K
1%
1/16W
MF-LF
2402
25V
X5R
1206-1
Vout = 1.25V * (1 + Ra / Rb)
1.25V S0 REGULATOR
=PP3V3_S5_1V25S0
1M
1V25S0_RUNSS
QFN
RT
PGOOD 12
RUN/SS
CRITICAL
ITH
SYNC/MODE
SW
P1V25S0_ITH_RC
C7723 C7724
100PF
5%
50V
CERM
402
R7728
14
C7725
1
1
2.2UH-3.25A
L7720
2
2
=PP1V25_S0_REG
P1V25S0_SW
<Ra>
R7723
47.0K
R7726
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VOLTAGE=0V
C7728
1000PF
10%
25V
X7R
402
C7729
20%
4V
CERM-X5R
0805
47UF
XW7700
SM
GND_P1V2S3_SGND
7C8
Vout = 1.2516V
3.0A max output
(Switcher limit)
MIN_LINE_WIDTH=0.6 mm IHLP1616BZ-SM
309K
470PF
10%
50V
CERM
402
CRITICAL
8
9
VFB
THERM
SGND PGND PAD
5%
1/16W
MF-LF
2 402
4
5
17
1%
1/16W
MF-LF
402 2
Burst
8.25K
10%
25V
2 X7R
402
15
P1V25S0_ITH 13
P1V25S0_MODE16
R7721
1000PF
47UF
20%
4V
CERM-X5R 2
0805
U7720
LTC3412A
P1V25S0_RT
Connect RUNSS off-page to control

If unconnected, powers up with PVIN.
NOTE: Be aware of pull-up on this signal.
C7720 1
SVIN PVIN
5%
1/16W
MF-LF
402
2
58C1
R7727
5%
1/16W
MF-LF
402 2
NO STUFF
1
10
3
11
R7722
Continuous
7C1
C7730
47UF
20%
4V
2 CERM-X5R
0805
P1V25S0_VFB
<Rb>
R7724
60.4K
1%
1/16W
MF-LF
402
3.42V/1.25V Switcher
P1V25S0_VFB_DIV
SYNC_MASTER=ENETSYNC_DATE=12/06/2005
<Rc>
R7725
23.2K
1%
1/16W
MF-LF
402

2

Vout = 0.8V * (1 + Ra / (Rb + Rc))

SIZE

8
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
64
76
01
S3 FETS & S3/S5 CONTROL

5V/3.3V S5 RUN/SS CONTROL
5VS5_RUNSS
6D7 63B5
65A4 7A6
=PP3V3_S3_FET
D 3
Q7859
R7857
C
7B1
65A5 58C5 7D1
=PP3V3_S5_FET
1/16W
5 G
MF-LF
402
=PP3V42_G3H_PWRCTL
1
2 SMC_PM_G2_EN_L
S 4
IN
3V3S5_RUNSS
D 3
5 G
1/16W
MF-LF
2 402
1V8S3_RUNSS
C
62B8
Open drain output

1
63B4
NC
D 6
SMC_PM_G2_EN
1
SC70
4
2
PM_S4_STATE_L
SOT563
IN
U7870
74LVC1G07
NC
SSM6N15FE
R7875
10K
1%
CRITICAL
65A6 44C5 33B7 24D3
Q7860
44D5
SSM6N15FE
SOT563
470K
5%
Q7859
SSM6N15FE
S 4
SOT563
R7856
100K
2 G
S 1
5%
1/16W
MF-LF
2 402
CRITICAL
Q7865
FDC638P
SM-LF
=PP5V_S3_FET
7A5
58D5 58C6 58B3 7C1
6
5
2
1
=PP5V_S5_FET4
R7805
100K
5%
1/16W
MF-LF
402
7C1
=PP5V_S5_PWRCTL
1
2 PM_SLP_S4_LS5V
P5VS3_EN_L
5V S3 FET
MOSFET
C7801
0.0022uF CHANNEL
10%
RDS(ON)
50V
CERM
402
LOADING
1
2
FDC638P
P-TYPE
48 mOhm @4.5V
0.051 A
R7806
10K
5%
1/16W
MF-LF
402
D 6
Q7860
CRITICAL
Q7866
FDC638P
SSM6N15FE
65C4 44C5 33B7 24D3
IN
PM_S4_STATE_L
2 G
1
R7807
100K
5%
1/16W
MF-LF
402
=PP3V3_S3_FET
SM-LF
SOT563
S 1
7A6 65C3
6
5
2
1
=PP3V3_S5_FET
4
65C4 58C5 7D1
R7808
10K
5%
1/16W
MF-LF
402
P3V3S3_EN_L
C7802
0.01UF
10%
16V
CERM
402
3.3V S3 FET
MOSFET
CHANNEL
RDS(ON)
LOADING
FDC638P
P-TYPE
65 mOhm @2.5V
0.098 A
S3 FET & S3/S5 Control

SIZE
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
65
76
01
LDO_FDBK
PBUS SUPPLY / BATTERY CHARGER

D
U7950
1 IN
SOI
=PP18V5_G3H_CHGR
CRITICAL
D
G
SOT-23
66B5
R7906
MMBD914XXG
2.2
SOT23
5%
1/16W
MF-LF
2 402
CHGR_ACSET_RC
100K
23
27
ACPRN
ACSET
1
2
13
DCIN
BOOT
UGATE
PHASE
LGATE
EN
DCPRN
DCSET
14 CHGR_BOOT
15 CHGR_UGATE
16 CHGR_PHASE
10%
402
GND_CHGR_SGND
NOSTUFF
R7964
2.43K
1%
1/16W
MF-LF
402
CHGR_CHLIM_R
2
R7979
10K
5%
1/16W
MF-LF
402
D 6
Q7961
SSM6N15FE
SOT563
44B5 6C1
SMC_BATT_ISET_L
66B8 66A5 57C4 7B1
=PP3V42_G3H_ACIN
1
Q7961
66B8 66B5
D 3
1%
1/16W
MF-LF
402
R7963
44.2K
1%
1/16W
MF-LF
2 402
S 4
S 1
C7917
C7916
128S0092
376S0543
Q7900,Q7920,Q7921
AOS
66C6
66C2 6B1
CHGR_VDD
10%
16V
2 CERM
402
100K
1%
1/16W
MF-LF
402
C7920
0.01uF
R7950
7AMP
PPVBAT_G3H_CHGR_OUT
6B1 66B5
C7910
1UF
100UF
10%
25V
2 X5R
603
PLACE NEAR R7908
VIN+ VIN-
10%
2 50V
CERM
402
1/10W
MF-LF
603
Placement Note:
C7981
0.0022UF
C7921
0.1UF
10%
16V
2 X5R
402
C7922 1R79301 C7918 1

0.01UF 470K
10%
2 16V
CERM
402
1%
1/16W
MF-LF
2 402
CRITICAL
5
=PP3V3_S0_PBATTISENS
U7975
V+INA193
OUT 1 BATT_ISENSE1
2 G
10%
2 10V
CERM
402
S1
GATE
C7928
SMC_BATT_ISENSE 44C5
Q7950
SSM6N15FE D
SOT563
D 6
10%
5 G
402
66B8
66A8
57C4 7B1
Q7924
S 4
2 G
S 1
R7922
1%
1/16W
MF-LF
2 402
P3V42_G3H_ACIN_R
Q7922
1
SMC_BC_ACOK
Q7921
AO4409
SOI
R7923
35.7K
BYPASS_R_DRV
6 D
Q7924
PBUS Supply/Battery Charger
SSM6N15FE
SOT563
SYNC_MASTER=SMC
G 2

6C1 44C8 45B6
BATT_RC
1
C7923
0.1UF
10%
16V
X5R
402
S 4
44C8 6C1 SMC_BATT_CHG_EN

45B6
SSM6N15FE
SOT563
T520V336M016ATE0457650
57B2 57D5
8
7
6
5
BYPASS_R_GATEMIN_NECK_WIDTH=0.2 MM
1 S
D 3
5 G
S 4
SIZE
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
60B2 61C5 62C2

44C1 45B6 48A1
48B1 48C1 48C6
66C2
D 3
SSM6N15FE
SOT563
5 G
20%
6.3V
CRITICAL
4
39.2K
1%
1/16W
MF-LF
402
1
=PP3V42_G3H_ACIN
D4
D3
0.22UF
GND_SMC_AVSS
BATT_POS_F
D2
D1
C7972
2 X5R
1%
1/16W
MF-LF
2 402
Q7922
SSM6N15FE
SOT563
2 16V
CERM
C7924
0.01uF
402
5%
3W
MF
2525
8 PPVBATT_G3H_PRE
1
7
6
3
S3
5
2
S2
1
S1
GATE
10%
2 16V
CERM
402
1%
1/16W
MF-LF
402
GND
R7920
27
NO STUFF
1
BATT_ENABLE_L
57C7 57C3 45B6 44C5 6C1
402
BATT_FET_GATE
5%
1/16W
MF-LF
2 402
S 1
0.1UF
10%
16V
X5R
402
10%
D3
330K
Q7950
SSM6N15FE
SOT563
C7980 1
1UF
D2
D1
R7971
4.53K
C7975
2 6.3V
CERM
D4
S3
S2
0.22UF
D 6
0.01UF
MOSFET
3
2
NO STUFF
R7931
1%
1/16W
MF-LF
402
7B3
2 CHGR_PHASE_RC
R7981
49.9
1%
1 2 3
PPVBAT_G3H_CHGR_OUT
1
R7925
10K
=PPBUSA_G3H
1206
C7909
SOI
TABLE_ALT_ITEM
376S0466
1
2
COMMENTS:
C7908,C7910 KEMET
7B3
Q7920
AO4409
TABLE_ALT_ITEM
128S0093
20%
2 16V
ELEC
6.3X5.5SM1
=PPBUSB_G3H
10%
50V
CERM
402
1%
1/16W
MF-LF
2 402
TABLE_ALT_HEAD
REF DES
20%
CASED2E-SM
0.001UF
R7965
BOM OPTION
C7908
2 16V
POLY
44C1 45B6 48A1 48B1 48C1 48C6 60B2 61C5 62C2 66B1
NO STUFF
100K
ALTERNATE FOR
PART NUMBER
20%
6.3V
F7900
CRITICAL CRITICAL
33UF
FDA1254-3SM
GND_CHGR_SGND
PART NUMBER
1%
1/16W
MF-LF
402
5 G
L7900
4.7UH
CRITICAL
R7909
100K
R7962
SOT563
SMC_BATT_ISET
2 G
15.0K
SSM6N15FE
0.5%
1W
MF
0612
PPVBAT_G3H_CHGR_REG
1
CRITICAL
5
R7951
SOT563
0.022UF
2 16V
CERM-X5R
S 4
0.22UF
C
1
LFPAK
GND_CHGR_SGND
TLV341
1%
1/16W
MF-LF
2 402
C7927
U7901
CRITICAL
5 G
1 2 3
100K
66B5 66A8
R7961
20.0K
S 1
SMC_SYS_ISET
V+
44B5
1%
1/16W
MF-LF
402
SOT563
2 G
R7960
15.0K
Q7960
D 3
SSM6N15FE
2 X5R
44A2
45C5
10%
25V
X5R
603
PWM FREQ. = 300 kHz

1
SOT563
1/16W
MF-LF
402
SMC_ENRGYSTR_LDO_PGOOD
C7971
CRITICAL
NC
RJK0305DPB
CHGR_VREF_VF
1UF
10%
25V
2 X5R
603
1
C7907
C7950
1UF
1UF
10%
25V
X5R
603
V-
D 6
Q7960
SSM6N15FE
CHGR_ACLIM_R 1
C7951
SOT23-5
5%
1/16W
MF-LF
402
20%
25V
2
POLY
CASE-D2-LF
7C4
ACIN_ENABLE_GATE
R7969
10K
CRITICAL
CRITICAL
R7908
0.01
XW7900
SM
SMC_SYS_ISET_L
66A8 66A5 57C4 7B1
R7953
402
RJK0305DPB
Q7902
R7968
2.37K
=PP3V42_G3H_ACIN
1
GND_SMC_AVSS
LFPAK
10%
25V
X5R
402
0.1UF
1%
1/16W
MF-LF
402
R7970
0.1UF
NO STUFF
GND
Q7901
C7903
10%
2 25V
X5R
402
66B8
66A8
25V
2
2
POLY
CASE-D2-LF
CRITICAL
CHGR_BOOT_RC
SMC_DCIN_ISENSE 44C5
4.53K
1%
C7905 1 C7906
22UF
22UF
20%
CRITICAL
10%
2 25V
X5R
402
CRITICAL
24 NC
28 NC
C7941
CRITICAL
1
22.6K
DCIN_ISENSE 1
C7970
10%
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
0.1UF
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
2
R7910
2.2
12 CHGR_LGATE
1
FB 3
THRML
PAD
0.1%
1/16W
MF
402
2
0.5%
402
1W
MF
2 0612
MIN_NECK_WIDTH=0.25PP18V5_S5_CHGR_SW_R
MM
NO STUFF
R7902
100K
17 CHGR_BGATE
25 CHGR_DCIN
INA193
2 6.3V
CERM
0.02
VREF
CHGR_ACSET
D7922
R7944
ISL6257HRZ
U7970 OUT 1
1UF
R7997
R7905
18
1
PGND
470PF
10%
50V
2 CERM
402
CHLIM
GND
1UF
SOD-123
BGATE
=PP3V3_S0_PDCISENS
5 V+
1CRITICAL
0.1UF
10%
25V
X5R
402
GND
SOT23-5
C7904 1
CRITICAL
D7900
B0530WXF
5%
1/16W
MF-LF
2 402
D7950
CRITICAL
61C5 60C2 7C4
CRITICAL
SGATE 18 CHGR_SGATE
CSIP 19
CSIN 20 CHGR_CSIN
THRML_PAD
10%
2 10V
X5R
402
1%
1/16W
MF-LF
2 402
CSON
10%
2 10V
X5R
402
QFN
VADJ
CELLS
22
CHGR_CHLIM
7
1UF
7 I.C.
NC
100K
0.1%-50PPM
BAT54CW-X-F
1/16W
MF-LF
SOT-323
402
1
2
VIN+ VIN-
5%
1/16W
MF-LF
2 402
U7900
29
88.7K
1 C7967
CHGR_VREF
CHGR_ACPRN
R7940
1%
1/16W
MF-LF
2 402
100K
VDDP
CHGR_CSOP
21 CSOP
C7902
C7912
11
0.1UF
26
NC 9
2
10%
2 25V
X5R
402
10K
FB
CHGR_ACLIM
8 ACLIM
CHGR_ICOMP
3 ICOMP
CHGR_VCOMP
4 VCOMP
C7940
16V
X5R
402
1
2
VDD
10
CHGR_FB_R 1
CHGR_FB
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10%
10V
X5R
402
R7967
3.01K
R7954
C7952
10%
2 25V
X5R
603
R7903
R7952
221K
PGOOD 5
1UF
NO STUFF
CHGR_VDDP
R7900
4.7
1UF
1%
50V
1/16W
CERM
MF-LF
402
402
1
2 CHGR_VCOMP_RC
1
2
0.033uF
10%
R7901
C7911
56.2K
0.001UF
10%
C7900
CHGR_VDD
1
C7901
R7941
S1
S
2
D2
D1
PPVDCIN_G3H_PRE
3
2
1
GATE
FDN360P_NL
S3
S2
Q7940
D4
D3
8
7
6
5
TDFN
SMC_ENRGYSTR_LDO_EN6 SHDN*
PLACE NEAR R7997
CHGR_EN
7B1
44A2
CRITICAL
OUT 8
Placement Note:
MAX8719
Q7900
AO4409
LDO_OUT
VCCCRITICAL
OF
66
76
01
=PP5V_S0_LCD
7A7
PP5V_INV
100K
1%
R9001
100K
1
INV_PWREN_F_L
Q9006
SSM3K15FV
FERR-120-OHM-1.5A
PPBUS_ALL_INV_CONN
=PPBUS_S5_INV 1
2
6B1
1/16W
MF-LF
2 402
L9003
VOLTAGE=5V
R9000
INV_PWREN_L
1 G
VOLTAGE=12.6V
0402-LF
NTK3142P
SOT723-3
L9002
INVERTER CONNECTOR D
FERR-120-OHM-1.5A
1%
1/16W
MF-LF
402
D 3
SOD-VESM
7B1
Q9005
CRITICAL
J9000
0402-LF
78171-0004
2
1 G
14D5
IN
C9014
S 2
0.0022UF
LVDS_BKLT_EN
M-RT-SM
5
L9000
120-OHM-0.3A-EMI
2
6B1
10%
50V
CERM
402
PP5V_INV_F
1
2
3
4
6B1 INV_BKLIGHT_PWM_L
VOLTAGE=5V
0402-LF
6B1
L9001
INV_GND
120-OHM-0.3A-EMI
1
67B7 67B5 7C4
=PP3V3_S0_LCD
518S0521
0402-LF
27D4 23A6
14D5
PLT_RST_L
LVDS_BKLT_CTL
SOT665
U9053Y
100PF
5%
5%
2 50V
CERM
402
5 TC7SZ08AFEF
1 C90021 C90031 C9000

C9001
100PF
100PF 100PF
CRITICAL
2 50V
CERM
402
BKLIGHT_CTL
5%
5%
2 50V
CERM
2 50V
CERM
402
402
C90591
0.1UF
INVT_CHGND
10%
16V
X5R 2
402
8D8
THIS GND CONECTS TO CHASSIS GND
C
=PP3V3_S5_LCD
CRITICAL
Q9003
R9002
5%
1/16W
MF-LF
402
Q9004
D 3
SOD-VESM
6
5
2
1
CONNECTOR
PP3V3_LCDVDD_SW
1
1
LCDVDD_PWREN_L
SSM3K15FV
R9023
10K
5%
1/16W
MF-LF
2 402
LCD + CAMERA
FDC606P
SOT-6
100K
7D1
C9011
0.1UF
0.001UF
C9012
10UF
20%
2 6.3V
X5R
603
10%
2 16V
X5R
402
LCDVDD_PWREN_L_R
C9009
VOLTAGE=3.3V
CRITICAL
J9001
S-050162B
F-RT-SM
10%
50V
CERM
402
25
C9013
0.0033UF
1
1 G
14D5
IN
S 2
67A6
67A4 67A2 8C8
=PP3V3_S0_LCD
10%
50V
CERM
402
LVDS_VDD_EN
5%
1/16W
MF-LF
2402
1%
1/16W
MF-LF
2 402
14D5
14D5
67C6 67B5 7C4
5%
1/16W
MF-LF
2402 67C6
VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MIN_NECK_WIDTH=0.20
MM
MM
0402-LF
L9008
67B7 67B5 7C4
PP3V3_S0_LCD_F
(LVDS DDC POWER)
VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.20
MM
MM
120-OHM-0.3A-EMI
1
2
=PP3V3_S0_LCD
0402-LF
LVDS_DDC_CLK
LVDS_DDC_DATA
CRITICAL
L9006
90-OHM-200MA
SM
=PP3V3_S0_LCD
CRITICAL
NOSTUFF
5%
1/16W
MF-LF
2 402
SM
5%
1/16W
MF-LF
LVDS_CTRL_CLK
14D5 12B1
LVDS_CTRL_DATA
71D3 14C5
SYM_VER-1
8C2
2402
8C2
14D5 12B1
IO
LVDS_A_CLK_N1
IO
LVDS_A_CLK_P2
L9007
90-OHM-200MA
R9015
R9016
10K
10K
71D3 14C5
IO
71D3 14C5
IO
71D3 14C5
IO
71D3 14C5
IO
71D3 14C5
IO
71D3 14C5
IO
SYM_VER-1
71D3 14C5
NOSTUFF
IO
IO
=USB2_CAMERA_P
=USB2_CAMERA_N
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<2>
LVDS_A_DATA_P<2>
LVDS_A_CLK_F_N
LVDS_A_CLK_F_P
USB2_CAMERA_CONN_P
USB2_CAMERA_CONN_N
L9005
FERR-120-OHM-1.5A
7A4
1
=PP5V_S3_CAMERA
PP5V_S3_CAMERA_F
L9010
FERR-1000-OHM
OUT
MIC_LO_LVDS
MIC_LO_LVDS_CONN
0402NOSTUFF
OUT
MIC_HI_LVDS
C90161
MIC_HI_LVDS_CONN
C9010
C90151 0.001UF
10%
50V
50V
CERM
402
67A2
0.001UF
10%
50V
CERM
402
CERM
402
67A4
=GND_CHASSIS_LVDS
LVDS REFERENCE CURRENT,2.37K OHM PULL DOWN RESISTOR NEEDED

MIC_SHIELD_LVDS1
OUT
71C3 14D5
LVDS_IBG
R9013
2.37K
1
=GND_CHASSIS_LVDS
0402 NOSTUFF
NOSTUFF
CRITICAL 2 CRITICAL
1%
1/16W
MF-LF
402
DZ9000
DZ9001
8V-100PF
8V-100PF
402-1
402-1
26
INVERTER,LVDS,TMDS
0.001UF
10%
50V
CERM
402

1
67B2 67A4 67A2 8C8

SIZE
=GND_CHASSIS_LVDS
D
APPLE INC.
DRAWING NUMBER
REV.
051-7455
SCALE
SHT
NONE
CAMERA I/F
SYNC_MASTER=GPU SYNC_DATE=06/23/2006
C90081
8C8 67A2 67A6 67B2
LCD I/F
Plexi: 516S0212
*Enclosure: 518S0364
0402NOSTUFF
L9012
FERR-1000-OHM
MIC_LO_LVDS_CONN
MIC_HI_LVDS_CONN
24
67B2 67A6 67A4 8C8
0.001UF
10%
L9011
FERR-1000-OHM
67A4
VOLTAGE=5V
0402-LF
NOSTUFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PP3V3_LCDVDD_SW_F
R9009
R9008
10K
10K
R9014
100K
23
FERR-120-OHM-1.5A
7C4 67B5 67B7

67C6
L9004
=GND_CHASSIS_LVDS
OF
67
76
01
7
L9206
L9201
FERR-120-OHM-1.5A
69C8
68D8 68C8
68B1 7C4
68B7 68B2
69C2 69B7
1
=PP3V3_S0_TMDS
PP3V3_S0_ANALOG_TMDS_F
VOLTAGE=3.3V
0402-LF
1
C9236
0.001UF
10%
50V
2 CERM
402
68B1
68B4
7B7
68D6
FERR-120-OHM-1.5A
2
=PP1V8_S0_TMDS1
10%
2 50V
CERM
402
0.1UF
10%
2 16V
X5R
402
0.1UF
C9207
0.1UF
10UF
10%
16V
2 X5R
402
20%
2 6.3V
X5R
603
10%
2 16V
X5R
402
C9208 1C9209
0.001UF
10%
2 50V
CERM
402
C9210 1C9211
0.001UF
10%
16V
2 X5R
402
10%
2 50V
CERM
402
0.1UF
10%
2 16V
X5R
402
PP3V3_S0_ANALOG_SDVO_F
0.001UF
10%
2 50V
CERM
402
68C4
68D6 7B7
=PP1V8_S0_TMDS 1
C9230
C9231
0.001UF
0.1UF
10%
2 50V
CERM
402
10%
2 16V
X5R
402
R9207
R9237
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
TMDS_TX_P<1>
R9208
49.9
1
C9214
0.1UF
C9200
0.001UF
10%
2 16V
X5R
402
10%
2 50V
CERM
402
C9201
0.001UF
10%
2 50V
CERM
402
C9202
C9203
0.1UF
1%
1/16W
MF-LF
402
68C4
C9204
2 6.3V
X5R
603
R9209
R9239
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
49.92 TMDS_TX<2> 149.92

1
TMDS_TX_P<2>
L9204
FERR-120-OHM-1.5A
C9224
0.001UF
PP3V3_S0_PVCC1_TMDS_F
10%
2 50V
CERM
402
68C4
VOLTAGE=3.3V
0402-LF
1
68B2 69B2
1%
1/16W
MF-LF
402
C9223
0.001UF
ONE 0.1UF AND 1000PF FOR EACH PIN

1
=PP3V3_S0_TMDS
TMDS_TX_N<2>
10%
2 50V
CERM
402
69B2 68B2
69C8
68D8 68C8
68B1 7C4
68B7 68B2
69C2 69B7
68B2 69B2
10UF
20%
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
TMDS_TX_N<1>
R9238
TMDS_TX<1> 149.92
VOLTAGE=1.8V
68B2 69B2
10%
2 50V
CERM
402
20%
6.3V
2 X5R
603
0402-LF
C9222
TMDS_TX_N<0>
0.001UF
10UF
69B2 68B2
TMDS_TX_P<0> 149.92 TMDS_TX<0> 149.92
VOLTAGE=3.3V
0402-LF
68B2
69B2
C9212 1 C9213
L9200
FERR-120-OHM-1.5A
0.1UF

1
=PP3V3_S0_TMDS
68B4
VOLTAGE=1.8V
C9237 1C9238 1C9239 1 C9240

0.001UF
PP1V8_S0_TMDS_F
0402-LF
L9203
FERR-120-OHM-1.5A
69C8
68D8 68C8
68B1 7C4
68B7 68B2
69C2 69B7
C9232
C9233
0.001UF
0.1UF
10%
2 50V
CERM
402
10%
2 16V
X5R
402
C9206
R9210
0.1UF
10%
2 16V
X5R
402
69A2 68B2
49.92
1
TMDS_TX_CLK_P
R9240
49.92 TMDS_TX_CLK_N
1
TMDS_TX_CLK
1%
1/16W
MF-LF
402
68B2 69A2
1%
1/16W
MF-LF
402
C9225
0.001UF
10%
2 50V
CERM
402
L9205
FERR-120-OHM-1.5A
68C4
PLACE THE CAP NEAR THE NB SIDE
IN
71D3 14B3
IN
71D3 14C3
IN
71D3 14B3
IN
71D3 14B3
IN
68D3
68C7
PEG_R2D_C_N<1>
PEG_R2D_C_P<2>
PEG_R2D_C_N<2>
PEG_R2D_C_P<3>
PEG_R2D_C_N<3>
68C6
68D6 68B1
68D3
PP1V8_S0_TMDS_F
0.1UF
10%
2 16V
X5R
402 TMDS_SDR_P37 SDR_P
=PP3V3_S0_TMDS
14C3
71D3 OUT
R9201
2.94K
PLACE R9200,U9201 CLOSE TO
MINI DVI CONN J9401
CRITICAL
R9200 5.5V
69C6
IN
TMDS_HTPLG
TOL INPUT
10K 2TMDS_HTPLG_R
2
5%
1/16W
MF-LF
402
U9201
74LVC1G17DRL
1/16W
MF-LF
402
2.94K
2
1%
1/16W
MF-LF
402
OUT
PEG_D2R_N<1>
10% 16V
X5R 402
TMDS_INT_P
TMDS_INT_N
32
33
TMDS_EXT_RES
35
TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH

27D1
IO
15A3
IO
15A3
SOT-553
4
TMDS_RST_L
SDVO_CTRLCLK
SDVO_CTRLDATA
TMDS_HTPLG_BUF
IF
5
4
6
ADDRESS=0X70
NC
HIGH, ADDRESS=0X72
29
3.3V ACTIVE OUTPUT
NC
R9200 INSURES ESD DIODE R9213

270K
CURRENT IS SMALL
5%
1%
1/16W
MF-LF
402
R9202
1
PEG_D2R_P<1>
0.1UF
R9211
R9212
9.09K
9.09K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
DVI_HOTPLUG_DET
R9203
23A6 68B8
1K
5%
SDG_N
SDB_P
SDVO RCVR
CORE
SDB_N
TXC_P
TXC_N
EXT_SWING
25
TX1_P
TX1_N
TX2_P
DIFF SIG
DATA
TX2_N
SDC_P
SDC_N
10UF
20%
2 6.3V
X5R
603
69B2 68D3
69B2 68D1
69B2 68D3
69B2 68D1
69B2 68C3
69B2 68C1
69A2 68C3
69A2 68C1
TMDS_TX_P<0>
OUT
TMDS_TX_N<0>
OUT
TMDS_TX_P<1>
OUT
TMDS_TX_N<1>
OUT
TMDS_TX_P<2>
OUT
TMDS_TX_N<2>
OUT
TMDS_TX_CLK_P
OUT
TMDS_TX_CLK_N
OUT
I2C MASTER
INTER SCLDDC 8
SDADDC 9
EXT_RES
RESET*
SDSCL
SDSDA
68B4 68D6
R9204
249
1%
1/16W
MF-LF
2402
CONFIG/
PRGRM
TEXT MODE
=PP3V3_S0_TMDS
B
7C4 68B2 68B7 68C8 68D8 69B7
69C2 69C8
1
R9205
R9206
10K
10K
TMDS_EXT_SWING
SDI_P
SDI_N
TMDS_I2C_SCL
TMDS_I2C_SDA
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
TMDS_I2C_SCL AND TMDS_I2C_SDA DONT NEED TO CONNECT

TEST
30
A1
HTPLG
SPGND
69C8 69C2 69B7 68D8 68C8 68B2 68B1 7C4
TMDS_SDC_P46
TMDS_SDC_N47
C9220
SDG_P
SGND1
0.1UF
10% 16V
X5R 402
402
17
16
20
19
23
22
14
13
C9219
0.1UF
10%
2 16V
X5R
TX0_P
TX0_N
LQFP
SGND0
U9200
SIL1362ACLU
SDR_N
39
45
TMDS_SDR_N38
TMDS_SDG_P40
TMDS_SDG_N41
TMDS_SDB_P43
TMDS_SDB_N44
7C4 68B1 68B7 68C8 68D8 69B7 69C2 69C8
C92211 C9205
CRITICAL
PGND2
0.1UF
0.1UF
10%
10%
2 16V
2 16V
X5R
X5R
402
402
27
0.1UF
0.1UF
10%
10%
2 16V
2 16V
X5R
X5R
402
402
AGND2
0.1UF
10%
16V
X5R
402
VCC2
C92431 C92441 C9245 1 C92461 C92471 C9248
AGND0
AGND1
"Place R9250 near U2300.F12"
5%
1/16W
MF-LF
2402
VCC0
C92411 C92421
0.1UF
0.1UF
10%
10%
2 16V
2 16V
2
X5R
X5R
402
402
12
18
24
100K
GND0
GND1
R9250
VCC1
10
28
34
DVI_HOTPLUG_DET
1
=PP3V3_S0_TMDS
1
71D3 14C3
68D6
48
IN
PEG_R2D_C_P<1>
OVCC
PEG_R2D_C_N<0>
SPVCC
IN
71D3 14B3
36
42
0.1UF
10%
2 16V
X5R
402
SVCC0
SVCC1
71D3 14C3
0.001UF
10%
2 50V
CERM
402
11
26
PEG_R2D_C_P<0>
PVCC2
C9235
IN
PVCC1
C9234
71D3 14B3
15
21
VOLTAGE=3.3V
0402-LF
1
MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP
AVCC0
AVCC1
1
=PP3V3_S0_TMDS
69C2 69B7
68B2 68B1 7C4
68D8 68C8 68B7
69C8
7
31
1/16W
MF-LF
2402
EXTERNAL TMDS
SYNC_MASTER=GRAPHIC

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
68
76
01
NB VIDEO ALIASES
CRT_TVO_IREF
TV_A_DAC
TV_B_DAC
TV_C_DAC
=CRT_TVO_IREF
=TV_A_DAC
=TV_B_DAC
=TV_C_DAC
14A5
14C5
14B5
14B5
71C3
14B5 69D8
=CRT_BLUE
CRT_BLUE
=CRT_GREEN
CRT_GREEN
=CRT_RED
CRT_RED
=CRT_HSYNC_R
=CRT_VSYNC_R
CRT_HSYNC_R
CRT_VSYNC_R
69B8 71C3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
69B8 71C3
MAKE_BASE=TRUE
14B5
69A8 71C3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
69A8 71C3
MAKE_BASE=TRUE
14B5
Video Connectors EXTERNAL VIDEO (VGA) INTERFACE
69A8 71C3
MAKE_BASE=TRUE
14B5
14A5
69C3 71C3
MAKE_BASE=TRUE
69C3 71C3
MAKE_BASE=TRUE
Isolation required for DVI power switch
TMDS(MINI DVI) INTERFACE

A 1.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF
AND GROUND
71C3 69D7
R9469
1.21K
CRT_TVO_IREF
7A7
D9401
CRITICAL
1SS418
F9404
L9444
600-OHM-300MA
SOD-723
0.5AMP-13.2V
PP5V_S0_TMDS_FUSE
2
2
1
=PP5V_S0_TMDS 1
VOLTAGE=5V
1%
1/16W
MF-LF
402
PP5V_S0_DVIPORT
VOLTAGE=5V
SM-LF
0402
1
=PP3V3_S0_TMDS
20%
2 10V
CERM
402
=PP3V3_S0_NB
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
740S0044
740S0028
F9404
CRITICAL
8C8 69A4
R9460
39
CRT_HSYNC_R1
71C3 69D5
R9466 R9467
2.2K
5%
1/16W
MF-LF
2402
14B5
TV_DCONSEL<0>
14B5
TV_DCONSEL<1>
1/16W
MF-LF
2 402
69C2 69B7 68D8 68C8 68B7 68B2 68B1 7C4
R9463
2.2K
5%
1/16W
MF-LF
2402
125
R9470
CRT_HSYNC_LS 1 39
VGA_HSYNC
5%
1/16W
MF-LF
402
GND
R9461
39
71C3 69D5
CRT_VSYNC_R
TMDS_HTPLG
8 U9404
SN74LVC2G125DCU
R9471
39
US
125
CRT_VSYNC_LS 1
Q9401
2 50V
CERM
C9410
402
GPU_CRT_DDC_CLK
2
SSM6N15FE
5%
2 50V
CERM
402
OMIT
CRITICAL
PLACE R9450 R9451 CLOSE TO GMCH

TV_A_DAC
CRT_BLUE
2 50V
CERM
402
14B5
14B5
1%
1/16W
MF-LF
2402
NC
NC
69C8 69C2
68B2 68B1 7C4
68D8 68C8 68B7
=PP3V3_S0_TMDS
C9439
EXT_COMPVID_B
0.1UF
10%
=TV_A_RTN
69C1
2 16V
X5R
402
=CRT_BLUE_L
CRITICAL
16
FL9400
210MHZ
VGA_G
69C1 VGA_VSYNC
MEA2010P-SM
VGA_B
VGA_HSYNC
26
18
27
19
28
20
29
30
22
31
VCC
TV_B_DAC
CRT_GREEN
R9452 1R9453
75
1%
75
1%
1/16W
MF-LF
2402
14B5
14B5
1/16W
MF-LF
2 402
=TV_B_RTN
S1A
5
6
S1B
S2B
11
10
S1C
14
13
S1D
DA
U9401
S2A
S2C
SOP
DB
VGA_R
EXT_Y_G
32
24
TMDS_TX_CONN_P<2>
S2D
DC
DD
12
IN
EN_L
1
15
TMDS_TX_CONN_N<1>
69D7
71C3
69D5
71C3
TMDS_TX_N<1>
68B2 68D1
CRITICAL
TMDS_TX_CONN_P<0>
L9406
90-OHM-100MA
1210-4SM1
TMDS_TX_CONN_N<0>
TMDS_TX_P<0>
68B2 68D3
TMDS_TX_N<0>
68B2 68D1
TMDS_TX_CONN_CLK_P
1
TMDS_TX_CONN_CLK_N
4
SYM_VER-1
CRITICAL
L9404
300-OHM-50MA
1210-4SM
514-0376
CRITICAL
1
69C4 8C8
8A6
=GND_CHASSIS_TMDS_DOWN
EXT_C_R
TMDS_TX_CLK_P
68B2 68C3
TMDS_TX_CLK_N
68B2 68C1
4
SYM_VER-1
C9421
0.1UF
10%
2 16V
X5R
402
MINI-DVI CONNECTOR
SYNC_MASTER=EUGENESYNC_DATE=05/21/05
TV_C_DAC

CRT_RED
R9454 1R9455
75
1%
1/16W
MF-LF
2 402
14B5
14B5
68B2 68D3
SYM_VER-1
TMDS_TX_P<1>
TMDS_TX_CONN_P<1>
GND
=CRT_GREEN_L
68B2 68C1
L9407
90-OHM-100MA
1210-4SM1
TMDS_TX_CONN_N<2>
33
34
35
36
69D7
71C3
69D5
71C3
2
3
TS3V330
TMDS_TX_N<2>
4
CRITICAL
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
16
25
PP5V_S0_DVIPORT 17
68B2 68C3
SYM_VER-1
F-RT-TH
69D4
TMDS_TX_P<2>
MINI-DVI-M42-BLK
1%
1/16W
MF-LF
2402
J9401
C9412
100PF
5%
69D7
71C3
71C3 69D5
1
R9450
R9451
75
75
L9405
90-OHM-100MA
1210-4SM1
GPU_CRT_DDC_DATA
1
CRITICAL
100PF
SOT563
NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT
C9411
Q9401
D
SSM6N15FE
SOT563
4
14B5
C9443
33PF
10%
2 50V
CERM
402
CRT_DDC_DATA
1/16W
MF-LF
4022
IO
2.2K
5%
IO
CRT_DDC_CLK
69B4
NOSTUFF
0.001UF
14B5
VGA_VSYNC
5%
1/16W
MF-LF
402
GND
5%
R94211 R94221
1/16W
MF-LF
4022
C9442
33PF
5%
VCC
2 A
CRT_VSYNC_LS_R
5%
1/16W
MF-LF
402
=PP3V3_S0_TMDS
2.2K
5%
69B4
NOSTUFF
402
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR
CRITICAL
5%
1/16W
MF-LF
4022
20%
2 10V
CERM
402
2 50V
CERM
DVI power DIODE on page 95 (D9500)

1
R9462
2.2K
C9460
US
VCC
5 A
CRT_HSYNC_LS_R
5%
1/16W
MF-LF
402
PP5V_S0_DVIPORT_D
2.2K
5%
68A8
8 U9404
SN74LVC2G125DCU
COMMENTS:
TABLE_ALT_ITEM
7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C8
0.1UF
TABLE_ALT_HEAD
7C4
C9404
0.1UF
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR
69B4
VOLTAGE=5V
75
1%
SB_CRT_TVOUT_MUX_L
1/16W
MF-LF
2402
24D2
TABLE_5_HEAD
CRITICAL
BOM OPTION
514-0480
PART#
QTY
DESCRIPTION
CONN,REC,MINI-DVI,32P,RA,TABS,MG3
J9401
CRITICAL
NORMAL
514-0481
CONN,REC,MINI-DVI,32P,RA,TABS,BLK
J9401
CRITICAL
FANCY
=TV_C_RTN
SIZE
TABLE_5_ITEM
=CRT_RED_L
TABLE_5_ITEM
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
69
76
01
FSB (Front-Side Bus) Constraints
CPU / FSB Net Properties

NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_DSTB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
=3:1_SPACING
FSB_DATA
=3:1_SPACING
TABLE_SPACING_RULE_ITEM
=2:1_SPACING
FSB_ADSTB
=3:1_SPACING
FSB_DATA2DATA
=2:1_SPACING
FSB_DSTB
=3:1_SPACING
=3:1_SPACING
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_CPURST_L
FSB_55S
FSB_COMMON
FSB_DATA_GROUP0
FSB_55S
FSB_DATA
FSB_DATA_GROUP0
FSB_55S
FSB_DATA
FSB_DSTB0
FSB_DSTB_55S
FSB_DSTB
FSB_DSTB_55S
FSB_DSTB
FSB_DATA_GROUP1
FSB_55S
FSB_DATA
FSB_DATA_GROUP1
FSB_55S
FSB_DATA
FSB_DSTB1
FSB_DSTB_55S
FSB_DSTB
FSB_DSTB_55S
FSB_DSTB
FSB_ADDR2ADSTB
FSB_COMMON
FSB_55S
FSB_ADDR2ADDR
FSB_55S
WEIGHT
FSB_ADDR
FSB_COMMON
FSB_COMMON
FSB_DATA2DSTB
=3:1_SPACING
SPACING_RULE_SET
LAYER
WEIGHT
FSB_COMMON
=2:1_SPACING
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
FSB_ADDR
FSB_ADDR
FSB_ADDR2ADDR
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_RS_L<2..0>
FSB_TRDY_L
FSB_CPURST_L
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
9D6 13C3
9D6 13C3
9D6 13C3
9D6 13B3
9D6 13B3
9D6 13B3
9B2 13B3
9D6 13B3
9C6 13B3
9C6 13B3
9D6 13B3
9D6 13A3
9D6 13B3
9D6 12B5 13A5
9C4 13C5 13D5

9C4 13B3
9C4 13B3
9C4 13B3
FSB_ADDR
FSB_ADSTB
FSB_ADDR2ADSTB
FSB_DATA
FSB_DATA
FSB_DATA2DATA
FSB_DATA
FSB_DSTB
FSB_DATA2DSTB
All FSB signals with impedance requirements are 55-ohm single-ended.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.
DSTB complementary pairs are spaced 1:1 and routed as differential pairs.
FSB_DATA_GROUP2
FSB_55S
FSB_DATA
FSB_DATA_GROUP2
FSB_55S
FSB_DATA
FSB_DSTB2
FSB_DSTB_55S
FSB_DSTB
FSB_DSTB_55S
FSB_DSTB
Design Guide recommends each strobe/signal group is routed on the same layer.
Design Guide recommends FSB signals be routed only on internal layers.
FSB_DATA_GROUP3
FSB_55S
FSB_DATA
FSB_DATA_GROUP3
FSB_55S
FSB_DATA
FSB_DSTB3
FSB_DSTB_55S
FSB_DSTB
FSB_DSTB_55S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_55S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_55S
FSB_ADDR
FSB_ADSTB0
FSB_55S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_55S
FSB_ADDR
FSB_ADSTB1
FSB_55S
FSB_ADSTB
CPU_IERR_L
CPU_55S
CPU_FERR_L
CPU_55S
CPU_PROCHOT_L
CPU_55S
CPU_PWRGD
CPU_55S
CPU_FROM_SB
CPU_55S
CPU_FROM_SB
CPU_55S
CPU_FROM_SB
CPU_55S
CPU_FROM_SB
CPU_55S
CPU_FROM_SB
CPU_55S
CPU_INIT_L
CPU_55S
CPU_FROM_SB
CPU_55S
CPU_FROM_SB
CPU_55S
PM_THRMTRIP_L
CPU_55S
FSB_CPUSLP_L
CPU_55S
PM_DPRSLPVR
CPU_55S
CPU_2TO1
(See above)
CPU_55S
CPU_2TO1
CPU_BSEL0
CPU_55S
CPU_2TO1
(See above)
CPU_55S
CPU_2TO1
CPU_BSEL1
CPU_55S
CPU_2TO1
(See above)
CPU_55S
CPU_2TO1
CPU_BSEL2
CPU_55S
CPU_2TO1
(See above)
CPU_55S
CPU_2TO1
CPU_DPRSTP_L
CPU_55S
CPU_2TO1
CPU_GTLREF
CPU_55S
CPU_GTLREF
CPU_COMP
CPU_55S
CPU_COMP
NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3
C CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
CPU_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>
9B4 9C4 13C5

9B4 13B3
9B4 13B3
9B4 13B3
9C2 13B5 13C5

9C2 13B3
9C2 13A3
9C2 13B3
9B2 9C2 13B5

9B2 13B3
9B2 13A3
9B2 13B3
9D8 13C3 13D3

9C8 9D8 13A3
9D8 13C3
9C8 13C3
9C8 13C3
NOTE: 7 mil gap is for VCCSense pair, which

Intel says to route with 7 mil spacing without
specifying a target differential impedance.
WEIGHT
CPU_2TO1
=2:1_SPACING
CPU_COMP
25 MIL
CPU_2TO1
CPU_GTLREF
25 MIL
DG recommends at least 25 mils, >50 mils preferred

CPU_ITP
=2:1_SPACING
?
CPU_VCCSENSE
25 MIL
Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
CPU_2TO1
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_55S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_55S
CPU_ITP
XDP_TDO
CPU_55S
CPU_ITP
XDP_TMS
CPU_55S
CPU_ITP
XDP_TCK
CPU_55S
CPU_ITP
XDP_TRST_L
CPU_55S
CPU_ITP
XDP_BPM_L
CPU_55S
CPU_ITP
XDP_BPM_L5
CPU_55S
CPU_ITP
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CPU_55S
CPU_ITP
CPU_55S
CPU_2TO1
CPU_55S
CPU_2TO1
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
(FSB_CPURST_L)
CPU_IERR_L
CPU_FERR_L
CPU_PROCHOT_L
CPU_PWRGD
CPU_INTR
CPU_NMI
CPU_A20M_L
CPU_DPSLP_L
CPU_IGNNE_L
CPU_INIT_L
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_BSEL<0>
NB_BSEL<0>
CPU_BSEL<1>
NB_BSEL<1>
CPU_BSEL<2>
NB_BSEL<2>
CPU_DPRSTP_L
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CLK_P
XDP_CLK_N
ITP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
9D6
9C8 22C2
9C5 45B5 45C3 59C8
9B2 12B1 22C4
9B8 22C4
9B8 22C4
9C8 22C4
9B2 22C4
9C8 22C4
9D6 22C4 46B2
9B8 22C4
9B8 22C4
9C6 15A6 22C2 45B3
9A2 13A5
15A6 24C3 59D8
59C7
9B4 29C6
15C6 29C8
9A4 29B6
15C6 29B8
9A4 29A6
15B6 29B8
9B2 15B6 22C4 59C7
9B4
9B3
9B3
9B3
9B3
9B7 9C6 12B3

9A7 9C6 12B5
9B7 9C6 12B2
9A7 9C6 12B2 12B3
9A7 9C6 12B3
9C6 12B2 12B3
9C5 12B2
75C3
75C3
10B7 59C7
10A6 59A4 59A5

10A6 59A4 59A5
CPU/FSB Constraints
SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
70
76
01
PCI-Express / DMI Bus Constraints

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PHYSICAL
SPACING
PEG_R2D
DMI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PCIE
PCIE_100D
PCIE
PCIE_100D
PCIE
PCIE_100D
PCIE
DMI_100D
DMI
DMI_100D
DMI
DMI_100D
DMI
DMI_100D
DMI
LVDS_A_CLK
LVDS_100D
LVDS
LVDS_A_CLK
LVDS_100D
LVDS
LVDS_A_DATA
LVDS_100D
LVDS
LVDS_A_DATA
LVDS_100D
LVDS
LVDS_A_DATA3
LVDS_100D
LVDS
LVDS_A_DATA3
LVDS_100D
LVDS
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_A_DATA_P<2..0>
LVDS_A_DATA_N<2..0>
LVDS_A_DATA_P<3>
LVDS_A_DATA_N<3>
LVDS_IBG
LVDS
LVDS_IBG
CRT_TVO_IREF
CRT
CRT_TVO_IREF
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_HSYNC_R
CRT_VSYNC_R
TV_A_DAC
TV_B_DAC
TV_C_DAC
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
PEG_D2R_N<1>
PEG_D2R_P<1>
PEG_R2D_C_P<3..0>
PEG_R2D_C_N<3..0>
PCIE_100D
14D3 68B6
14C3 68B6
14B3 68B6 68C6
14B3 14C3 68B6 68C6
WEIGHT
PCIE
20 MIL
DMI
20 MIL
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5
DMI_N2S
Video Signal Constraints
DMI_S2N
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
CRT_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CRT_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
DMI_N2S_P<3..0>
DMI_N2S_N<3..0>
DMI_S2N_P<3..0>
DMI_S2N_N<3..0>
D
15B3 23D2
15B3 23D2
15B3 23D2
15B3 15C3 23D2
14C5 67B3
14C5 67B3
14C5 67B2
14C5 67B2
SPACING_RULE_SET
LAYER
WEIGHT
LVDS
20 MIL
CRT
25 MIL
CRT_2CRT
20 MIL
CRT_SYNC
25 MIL
CRT_SYNC2SYNC
20 MIL
TVDAC
25 MIL
DG Says 40 mil spacing minimum

14D5 67A8
CRT_RED
CRT_50S
CRT
CRT_GREEN
CRT_50S
CRT
CRT_BLUE
CRT_50S
CRT
CRT_SYNC
CRT_55S
CRT_SYNC
CRT_SYNC
CRT_55S
CRT_SYNC
TV_A_DAC
CRT_50S
TVDAC
TV_B_DAC
CRT_50S
TVDAC
TV_C_DAC
CRT_50S
TVDAC
TVDAC_2TVDAC
20 MIL
?
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRT
CRT
CRT_2CRT
CRT_SYNC
CRT_SYNC
CRT_SYNC2SYNC
TVDAC
TVDAC
TVDAC_2TVDAC
69D7 69D8
69A8 69D5
69A8 69D5
69B8 69D5
69C3 69D5
69C3 69D5
69B8 69D7
69A8 69D7
69A8 69D7
LVDS signals are 100-ohm +/- 20% differential impedence.

CRT & TVDAC signal single-ended impedence varies by location:
- 37.5-ohm +/- 15% from GMCH to first termination resistor.
- 50-ohm +/- 15% from first to second termination resistor.
- 55-ohm +/- 15% from second termination resistor to connector.
CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.
NB Constraints
SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
71
76
01
DDR2 Memory Bus Constraints
Memory Net Properties

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_45S
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
SPACING
MEM_A_CLK
MEM_70D
MEM_CLK
MEM_70D
MEM_CLK
MEM_A_CNTL
MEM_45S
MEM_CTRL
MEM_A_CNTL
MEM_45S
MEM_CTRL
MEM_A_CNTL
MEM_45S
MEM_CTRL
MEM_A_CMD
MEM_55S
MEM_CMD
MEM_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MEM_CLK_P<2..0>
MEM_CLK_N<2..0>
15D3 30A4 30D4

15D3 30A4 30D4
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=4:1_SPACING
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CTRL2CTRL
=2:1_SPACING
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CTRL2MEM
=3:1_SPACING
=1.5:1_SPACING
MEM_CLK
MEM_CMD
MEM_CLK2MEM
=3:1_SPACING
MEM_CMD
MEM_55S
MEM_CMD
MEM_A_CMD
MEM_55S
MEM_CMD
MEM_A_CMD
MEM_55S
MEM_CMD
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_A_DQ_BYTE0
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_55S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_55S
MEM_DATA
MEM_A_DM0
MEM_55S
MEM_DATA
MEM_A_DM1
MEM_55S
MEM_DATA
MEM_A_DM2
MEM_55S
MEM_DATA
MEM_A_DM3
MEM_55S
MEM_DATA
MEM_A_DM4
MEM_55S
MEM_DATA
MEM_A_DM5
MEM_55S
MEM_DATA
MEM_A_DM6
MEM_55S
MEM_DATA
MEM_A_DM7
MEM_55S
MEM_DATA
MEM_A_DQS0
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_70D
MEM_CLK
MEM_70D
MEM_CLK
MEM_B_CNTL
MEM_45S
MEM_CTRL
MEM_B_CNTL
MEM_45S
MEM_CTRL
MEM_B_CNTL
MEM_45S
MEM_CTRL
MEM_B_CMD
MEM_55S
MEM_CMD
MEM_B_CMD
MEM_55S
MEM_CMD
MEM_B_CMD
MEM_55S
MEM_CMD
MEM_B_CMD
MEM_55S
MEM_CMD
MEM_B_CMD
MEM_55S
MEM_CMD
MEM_B_DQ_BYTE0
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_55S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_55S
MEM_DATA
MEM_B_DM0
MEM_55S
MEM_DATA
MEM_B_DM1
MEM_55S
MEM_DATA
MEM_B_DM2
MEM_55S
MEM_DATA
MEM_B_DM3
MEM_55S
MEM_DATA
MEM_B_DM4
MEM_55S
MEM_DATA
MEM_B_DM5
MEM_55S
MEM_DATA
MEM_B_DM6
MEM_55S
MEM_DATA
MEM_B_DM7
MEM_55S
MEM_DATA
MEM_B_DQS0
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
MEM_85D
MEM_DQS
?
MEM_CMD2MEM
MEM_55S
MEM_A_CMD
MEM_CLK
MEM_DQS
MEM_CLK2MEM
MEM_DATA2DATA
=1.5:1_SPACING
?
NET_SPACING_TYPE1
MEM_DATA2MEM
=3:1_SPACING
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_DQS2MEM
=3:1_SPACING
MEM_A_A<14..0>
MEM_A_BS<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
15D3 30C4 30C6 32D6

15D3 30B4 30B6 32D6
15C3 30B4 30B6 32D6
15C6 16B5 16C5 30B4 30B6 30C4 30C6 32C6

16D5 30B4 30B6 30C6 32C6
16B5 30B4 32B6

16D5 30B6 32B6
16B5 30B6 32B6
?
MEM_CMD2CMD
MEM_A_CMD
MEM_CKE<1..0>
MEM_CS_L<1..0>
MEM_ODT<1..0>
MEM_CLK
MEM_CMD2MEM
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
16D8 30D4 30D6

16C8 30D4 30D6
16C8 30C4 30C6
16C8 30C4 30C6 30D4 30D6
16B8 16C8 30B4 30B6
16B8 30A4 30A6 30B4 30B6
16B8 30A4 30A6
16A8 16B8 30A4 30A6
MEM_CMD
MEM_2OTHER
25 MIL
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
16D5 30D4
16D5 30D4
16C5 30C6
16C5 30C4
16C5 30B4
16C5 30B6
16C5 30A6
16C5 30A4
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_A_DQS1
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_A_DQS2
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_A_DQS3
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS6
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_A_DQS7
MEM_DATA
MEM_DQS
MEM_DATA2MEM
MEM_B_CLK
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CLK
MEM_2OTHER
MEM_2OTHER
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DATA
MEM_2OTHER
MEM_DQS
MEM_2OTHER
MEM_CLK_P<5..3>
MEM_CLK_N<5..3>
16C5 30D6
16C5 30D6
16C5 30D6
16C5 30D6
16C5 30C4
16C5 30C4
16C5 30C6
16C5 30C6
16C5 30B6
16C5 30B6
16C5 30B4
16C5 30B4
16C5 30A4
16C5 30A4
16C5 30A6
16C5 30A6
15D3 31A4 31D4

15D3 31A4 31D4
SPACING_RULE_SET
MEM_CTRL
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_CKE<4..3>
MEM_CS_L<3..2>
MEM_ODT<3..2>
15D3 31C4 31C6 32D5 32D6

15C3 15D3 31B4 31B6 32D6
15C3 31B4 31B6 32D6
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DQS
MEM_DQS
MEM_DQS2MEM
Need to support MEM_*-style wildcards!

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS7
MEM_B_A<14..0>
MEM_B_BS<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
15C6 16B1 16C1 31B4 31B6 31C4 31C6 32A5 32B5

16D1 31B4 31B6 31C6 32A6
16B1 31B4 32A6
16D1 31B6 32A6
16B1 31B6 32A6
16D4 31D4 31D6

16C4 31D4 31D6
16C4 31C4 31C6
16C4 31C4 31C6
16B4 16C4 31B4 31B6

16B4 31A4 31A6 31B4 31B6
16B4 31A4 31A6
16A4 16B4 31A4 31A6
16D1 31D4
16D1 31D4
16C1 31C4
16C1 31C6
16C1 31B4
16C1 31A6
16C1 31A4
16C1 31A6
16C1 31D6
16C1 31D6
16C1 31D6
16C1 31D6
16C1 31C6
16C1 31C6
16C1 31C4
16C1 31C4
16C1 31B6
16C1 31B6
16C1 31A4
Memory Constraints
16C1 31B4
16C1 31A6
SYNC_MASTER=WFERRY
16C1 31A6
16C1 31A4
16C1 31A4

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
72
76
01
Disk Interface Constraints

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
IDE_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
SPACING
IDE_PDD
IDE_55S
IDE
IDE_PDA
IDE_55S
IDE
IDE_PDCS
IDE_55S
IDE
IDE_PDCS
IDE_55S
IDE
IDE_CNTL
IDE_55S
IDE
IDE_PDIOR_L
IDE_55S
IDE
IDE_CNTL
IDE_55S
IDE
IDE_CNTL
IDE_55S
IDE
IDE_PDIORDY
IDE_55S
IDE
IDE_IRQ14
IDE_55S
IDE
IDE_RST_L
IDE_55S
IDE
SATA_A_R2D
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
IDE
=1.8:1_SPACING
SATA
20 MIL
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9
HD Audio Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

HDA_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SATA_A_D2R
WEIGHT
HDA
=1.8:1_SPACING
IDE_PDD<15..0>
IDE_PDA<2..0>
IDE_PDCS1_L
IDE_PDCS3_L
IDE_PDIOW_L
IDE_PDIOR_L
IDE_PDDACK_L
IDE_PDDREQ
IDE_PDIORDY
IDE_IRQ14
ODD_RST_5VTOL_L
SATA_A_R2D_C_P
SATA_A_R2D_C_N
SATA_A_R2D_P
SATA_A_R2D_N
SATA_A_D2R_P
SATA_A_D2R_N
SATA_A_D2R_C_P
SATA_A_D2R_C_N
22B4 22C4 39C3 39C5

22B4 39B3 39B5
22B4 39B5
22B4 39B3
22B4 39B5
22B4 39C3
22B4 39B3
22A4 39C3
22A4 39B5
22B4 39B5
23B6 39A8
22B6 40D4
22B6 40D4
40D7
40D7
22B6 40C4
22B6 40D4
40C7
40D7
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1
USB 2.0 Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
USB_60S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

WEIGHT
USB
20 MIL
USB_2CLK
25 MIL
DG says minimum spacing 50 mils to clocks
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2
HDA_BIT_CLK
Internal Interface Constraints
HDA_SYNC
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
DIFFPAIR NECK GAP

SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
HDA_RST_L
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
HDA_SDIN0
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_L
HDA_RST_L_R
HDA_SDIN0
8A6 22C8
22C6
8A6 22C8
22C6
8A6 22C8
22C6
8A6 22C8
SPACING_RULE_SET
LAYER
WEIGHT
=3:1_SPACING
HDA_SDOUT
SMB
USB_EXTA
SPI
=1.8:1_SPACING
SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17

USB_MINI
USB_3G
USB_CAMERA
USB_BT
USB_TPAD
USB_IR
USB_EXTB
USB_EXCARD
USB_EXTC
HDA_55S
HDA
HDA_55S
HDA
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_RBIAS
USB_60S
SMB_SB_SCL
SMB_55S
SMB
SMB_SB_SDA
SMB_55S
SMB
SMB_SB_ME_SCL
SMB_55S
SMB
SMB_SB_ME_SDA
SMB_55S
SMB
SPI_SCLK
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_SI
SPI_SO
SPI_CE_L0
SPI_CE_L1
HDA_SDOUT
HDA_SDOUT_R
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_MINI_P
USB_MINI_N
USB_3G_P
USB_3G_N
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
USB_EXCARD_P
USB_EXCARD_N
USB_EXTC_P
USB_EXTC_N
USB_RBIAS
SMB_CLK
SMB_DATA
SMB_ME_CLK
SMB_ME_DATA
SPI_SCLK_R
SPI_A_SCLK_R
SPI_SI_R
SPI_A_SI_R
SPI_SO
SPI_A_SO_R
SPI_CE_R_L<0>
SPI_CE_L<0>
SPI_CE_R_L<1>
8A6 22B8
22B6
8C1 23C2
8C1 23C2
8C1 23C2
8C1 23C2
8C1 23C2
8C1 23C2
8C1 8C2 23C2
8B1 8B2 23C2
8C1 23C2
8C1 23C2
8C1 8C2 23C2
8C1 8C2 23C2
8B1 23C2
8B1 23C2
8B1 23C2
8B1 23C2
8B1 23C2
8B1 23C2
23B3
24D5 47D8
24D5 47D8
24D5 47A8
24D5 47A8
23C5 52C7
52C5
23C5 52C3
52C4
23C5 52C3
52C4
23C5 52C7
52C6
SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
73
76
01
PCI Bus Constraints

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
SPACING
PCI_AD
PCI_55S
PCI
PCI_AD19
PCI_55S
PCI
PCI_AD20
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_C_BE_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_LOCK_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_FW_REQ_L
PCI_55S
PCI
PCI_FW_GNT_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_55S
PCI
PCI_REQ2_L
PCI_55S
PCI
PCI_GNT2_L
PCI_55S
PCI
INT_PIRQA_L
PCI_55S
PCI
INT_PIRQB_L
PCI_55S
PCI
INT_PIRQC_L
PCI_55S
PCI
INT_PIRQD_L
PCI_55S
PCI
INT_PIRQE_L
PCI_55S
PCI
INT_PIRQF_L
PCI_55S
PCI
SPACING_RULE_SET
LAYER
WEIGHT
PCI
=2:1_SPACING
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19
Platform LAN (Nineveh) Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LAN_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ENET_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
GLAN_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
ENET_CLK
=2.5:1_SPACING
ENET_GLAN
20 MILS
ENET_LAN
=1.5:1_SPACING
ENET_MDI
25 MILS
DG says 30 mils min separation.
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
Controller Link (AMT) Constraints
PCI_AD<18..0>
PCI_AD<19>
PCI_AD<20>
PCI_AD<31..21>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_FW_REQ_L
PCI_FW_GNT_L
PCI_REQ1_L
PCI_GNT1_L
PCI_REQ2_L
PCI_GNT2_L
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
INT_PIRQE_L
INT_PIRQF_L
23A8 23B8 37B5 37C5

23A8 37B6
23A8 37B5
23A8 37B5
23A6 37B5
23B6 37B5
23A4 23A6 37A5
23A4 23A6 37A5
23A4 23A6 37A5

23A4 23A6
23A4 23A6 37A5
23A4 23A6 37A5
23A4 23A6 37A5
23A4 23A6 37A5
23A4 23B6 37A5
23B5 37A5
23A4 23B6
23A4 23B6
23A4 23A8
23A4 23A8
23A4 23A8
23A4 23A8 37A5
23A4 23A6
23A4 23A6
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CLINK_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLINK_12MIL
12 MILS
5 MILS
300 MILS
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
CLINK
=1.8:1_SPACING
CLINK_VREF
12 MILS
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
PCIE_E_R2D
PCIE_E_D2R
PCIE_100D
PCIE
PCIE_100D
PCIE
PCIE_100D
PCIE
PCIE_100D
PCIE
GLAN_COMP
GLAN_COMP
PCIE_E_R2D_C_P
PCIE_E_R2D_C_N
PCIE_E_D2R_P
PCIE_E_D2R_N
ENET_LAN
LAN_55S
ENET_LAN
LAN_55S
ENET_LAN
ENET_LAN
LAN_55S
ENET_LAN
ENET_GLAN_CLK
LAN_55S
ENET_CLK
LAN_55S
ENET_CLK
ENET_100D
ENET_MDI
ENET_MDI0
ENET_LAN
ENET_100D
ENET_MDI
ENET_MDI1
ENET_100D
ENET_MDI
ENET_100D
ENET_MDI
ENET_MDI2
ENET_100D
ENET_MDI
ENET_100D
ENET_MDI
ENET_100D
ENET_MDI
ENET_100D
ENET_MDI
CLINK_NB
CLINK_55S
CLINK
CLINK_NB
CLINK_55S
CLINK
CLINK_NB_RESET_L
CLINK_55S
CLINK
CLINK_WLAN
CLINK_55S
CLINK
CLINK_WLAN
CLINK_55S
CLINK
CLINK_WLAN_RESET_L
CLINK_55S
CLINK
NB_CLINK_VREF
CLINK_12MIL
CLINK_VREF
SB_CLINK_VREF0
CLINK_12MIL
CLINK_VREF
SB_CLINK_VREF1
CLINK_12MIL
CLINK_VREF
ENET_MDI3
LAN_RSTSYNC
LAN_R2D<2..0>
LAN_D2R<2..0>
ENET_GLAN_CLK_R
ENET_GLAN_CLK
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
CLINK_NB_CLK
CLINK_NB_DATA
CLINK_NB_RESET_L
CLINK_WLAN_CLK
CLINK_WLAN_DATA
CLINK_WLAN_RESET_L
NB_CLINK_VREF
SB_CLINK_VREF0
SB_CLINK_VREF1
33B5 33B6
33B5 33B6
33B5
33B5 33C5
22C6
B
34B8 36B7
34B8 36B7
34B8 36C7
34B8 36C7
34B8 36B7
34B8 36C7
34B8 36C7
34B8 36C7
15A3 24C3
15A3 24C3
15A3 24C3
24C3
24C3
24D5
15A4
24C3
24C3
SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
74
76
01
Clock Signal Constraints
Clock Net Properties

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CLK_FSB_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PHYSICAL
SPACING
CK505_CPU
CLK_FSB_100D
CLK_FSB
CK505_CPU
CLK_FSB_100D
CLK_FSB
CK505_NB
CLK_FSB_100D
CLK_FSB
CK505_NB
CLK_FSB_100D
CLK_FSB
CK505_ITP
CLK_FSB_100D
CLK_FSB
CK505_ITP
CLK_FSB_100D
CLK_FSB
CK505_PCIF0
CLK_MED_55S
CLK_MED
CK505_PCIF1
CLK_MED_55S
CLK_MED
CK505_PCI1
CLK_MED_55S
CLK_MED
CK505_PCI2
CLK_MED_55S
CLK_MED
CK505_PCI3
CLK_MED_55S
CLK_MED
CK505_PCI4
CLK_MED_55S
CLK_MED
CK505_PCI5
CLK_MED_55S
CLK_MED
(CPU_BSEL0)
(CPU_BSEL2)
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
CK505_DOT96
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
(CK505_CPU)
(CK505_CPU)
(CK505_NB)
(CK505_NB)
(CK505_ITP)
(CK505_ITP)
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
CLK_FSB_100D
CLK_FSB
(CK505_PCIF0)
(CK505_PCIF1)
(CK505_PCI1)
(CK505_PCI2)
(CK505_PCI3)
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
(CPU_BSEL0)
(CPU_BSEL2)
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
(CPU_BSEL0)
(CPU_BSEL2)
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
(CK505_DOT96)
(CK505_DOT96)
(CK505_LVDS)
(CK505_LVDS)
(CK505_SRC1)
(CK505_SRC1)
(CK505_SRC2)
(CK505_SRC2)
(CK505_SRC3)
(CK505_SRC3)
(CK505_SRC4)
(CK505_SRC4)
(CK505_SRC5)
(CK505_SRC5)
(CK505_SRC6)
(CK505_SRC6)
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
CLK_MED_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CK505_CPU0_P
CK505_CPU0_N
CK505_CPU1_P
CK505_CPU1_N
6C7 28C4 29D6

6C7 28C4 29D6
6C7 28C4 29D6
6C7 28C4 29D6
6C7 28C4 29D6
6C7 28C4 29D6
SPACING_RULE_SET
LAYER
WEIGHT
25 MIL
CLK_FSB
CLK_PCIE
20 MIL
CLK_MED
20 MIL
CLK_SLOW
10 MIL
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6
CK505_LVDS
CK505_SRC1
CK505_SRC2
CK505_SRC3
CK505_SRC4
CK505_SRC5
CK505_SRC6
CK505_SRC7
CK505_SRC8
CK505_PCIF0_CLK
CK505_PCIF1_CLK
CK505_PCI1_CLK
CK505_PCI2_CLK
CK505_PCI3_CLK
CK505_PCI4_CLK
CK505_PCI5_FCTSEL1
CK505_USB48_FSA
CK505_DOT96_27M_P
CK505_DOT96_27M_N
CK505_LVDS_P
CK505_LVDS_N
CK505_SRC1_P
CK505_SRC1_N
CK505_SRC2_P
CK505_SRC2_N
CK505_SRC3_P
CK505_SRC3_N
CK505_SRC4_P
CK505_SRC4_N
CK505_SRC5_P
CK505_SRC5_N
CK505_SRC6_P
CK505_SRC6_N
CK505_SRC7_P
CK505_SRC7_N
CK505_SRC8_P
CK505_SRC8_N
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_NB_P
FSB_CLK_NB_N
XDP_CLK_P
XDP_CLK_N
28B8 29B6
6C7 28B6 29B6

28B6 29B6
8C4 28B6
28B6 29A6
8C4 28B6
28B6 29B2
28A4 29D8
28A4 29D8
6C7 28A4 29B6

6C7 28A4 29B6
6C7 28B4 29C6
6C7 28B4 29C6
6C7 28B4 29C6

6C7 28B4 29C6
6C7 28B4 29C6

6C7 28B4 29C6
6C7 28B4 29C6
6C7 28B4 29C6
6C7 28B4 29C6
6C7 28B4 29B6
6B7 28A4 29B6

6B7 28A4 29B6
9B6 29D3
9B6 29D3
13B3 29D3
13B3 29D3
70A3
70A3
PCI_CLK33M_LPCPLUS
6C2 29B3 46C4
PCI_CLK33M_SB
23A6 29A5 29B3
PCI_CLK33M_FW
29A5 29B3 37A5
PCI_CLK33M_TPM
PCI_CLK33M_SMC
29A3 29A5 44C8
CK505 PCI4 is project-specific
CK505 PCI5 is project-specific
SB_CLK48M_USBCTLR
SB_CLK14P3M_TIMER
CK505_FSA
CK505_FSC
NB_CLK96M_DOT_P
NB_CLK96M_DOT_N
NB_CLK100M_DPLLSS_P
NB_CLK100M_DPLLSS_N
PEG_CLK100M_P
PEG_CLK100M_N
SB_CLK100M_DMI_P
SB_CLK100M_DMI_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
NB_CLK100M_PCIE_P
NB_CLK100M_PCIE_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
24D3 29A5 29D6

24D3 29A5 29D6
29C8 29D6
29A8 29D6
8B1 29B3
8B1 29B3
8B1 29C3
8A1 29C3
B
23C2 29C3
23D2 29C3
22B6 29C3
22B6 29C3
15C3 29C3
15C3 29C3
29C3 33C5
29B3 33C5
CK505 SRC7 is project-specific

CK505 SRC8 is project-specific
Clock Constraints
SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
75
76
01
FireWire Interface Constraints
FireWire Net Properties

NET_TYPE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING
PHYSICAL
FW_D_CTL
FW_55S
FW
FW_D_CTL
FW_55S
FW
FW_LCLK
CLK_MED_55S
CLK_MED
FW_110D
SPACING_RULE_SET
LAYER
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
FW_55S
FW
FW_55S
FW
FW_LPS
FW_55S
FW
FW_LREQ
FW_55S
FW
FW_PINT
FW_55S
FW
FWPHY_CLK98P304M_XI
CLK_MED_55S
CLK_MED
CLK_MED_55S
CLK_MED
FW_0_TPA
FW_110D
FW_TP
FW_0_TPA
FW_110D
FW_TP
FW_0_TPB
FW_110D
FW_TP
WEIGHT
FW_PCLK
FW
=2:1_SPACING
FW_TP
=3:1_SPACING
FW_LKON
FW_110D
FW_TP
FW_1_TPA
FW_110D
FW_TP
FW_1_TPA
FW_110D
FW_TP
FW_1_TPB
FW_110D
FW_TP
FW_110D
FW_TP
FW_LINK<7..0>
FW_CTL<1..0>
CLKFW_LINK_LCLK
CLKFW_PHY_LCLK
CLKFW_LINK_PCLK
CLKFW_PHY_PCLK
FW_LKON
FW_LKON_R
FW_LPS
FW_LREQ
FW_PINT
CLK98P304M_FW_XI_R
CLK98P304M_FW_XI
FW_0_TPA_P
FW_0_TPA_N
FW_0_TPB_P
FW_0_TPB_N
FW_1_TPA_P
FW_1_TPA_N
FW_1_TPB_P
FW_1_TPB_N
Port 2 Not Used
SMC SMBus Net Properties

NET_TYPE
PHYSICAL
SPACING
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
47D2
47D2
6B2 47C5
6B2 47C5
47D5
47D5
47C2
47C2
47B2
47B2
FireWire & SMC Constraints

SYNC_MASTER=WFERRY

SIZE
D
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7455
OF
76
76
01

051-7455 K36 DVT

Загружено:

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051-7455 K36 DVT

Загружено:

Авторское право:

Доступные форматы

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

K36 MLB SCHEMATIC

REFERENCED FROM M70

LPC+ Debug Connector

DIMENSIONS ARE IN MILLIMETERS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

U5920 SUDDEN MOTION DETECT PG 51

BSA BSB ADC

Ln1 Ln2 Ln3 Ln4

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

J6701 INTERNAL MIC

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

K36 POWER SYSTEM ARCHITECTURE

(7.5A MAX CURRENT)

ENA (PAGE 35)

Power Block Diagram

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

3.3V VOUT2 (5A MAX CURRENT)

BOM options provided by this page:

BOM OPTION REMOVED BOM OPTION REMOVED

BOM TABLE FOR HF POSCAPS

BOM OPTION REMOVED BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOARD STACK-UP AND CONSTRUCTION

IN-LINE SODIMM CONNECTOR

IC,16MBIT 8PIN SPI SERIAL FLASH,SOIC8

LOCKED BOOTROM PN 341S2197

NOTICE OF PROPRIETARY PROPERTY

M70 EVT TO DVT CHANGES

M70 DVT TO K36 CHANGES

M70 PROTO TO EVT CHANGES

M70 EVT TO DVT CHANGES

NOTICE OF PROPRIETARY PROPERTY

Functional Test Points

Battery Digital Connector

28C4 29D6 75D3

28C4 29D6 75D3

28C4 29D6 75D3

28C4 29D6 75D3

28C4 29D6 75D3

28C4 29D6 75D3

28A4 29B6 75D3

28A4 29B6 75D3

28B4 29C6 75C3

28B4 29C6 75D3

28B6 29B6 75D3

28B4 29C6 75C3

28B4 29C6 75C3

28B4 29C6 75C3