Introduction

VHDL is a high level modeling language for digital circuits VHDL stands for Very high speed integrated circuit Hardware Description Language

Known as IEEE Standard 1076

Original standard adopted in 1987 Revised in 1993 and 2008

Uses of VHDL
Design documentation -- describing structures of digital circuits Design simulation -- modeling the behavior of digital circuits Design synthesis converting code to hardware implementation

Design conception

DESIGN ENTRY Schematic capture VHDL

Synthesis

Functional simulation

No

Design correct? Yes

Physical design

Timing simulation

No

Timing requirements met?

Chip configuration

Figure 2.29. A typical CAD system.

Sections in VHDL code

Libraries & packages header

Interface definition (input/output ports)

Functional/behavioral description of circuit

Closer look at code

Using a library Use packages (in the library) that provide various data types Define a entity/model called circuit1 Define the interface ports of the entity, their types and directions

Note: VHDL code is case insensitive

Closer look at code (contd)

architecture statement to start description of circuit. We call this architecture behv1 or any name. comment starts with -declare internal signals

Define operation of circuit

Concurrency
VHDL is concurrent by nature.
different from conventional programming languages

These assignment statements are concurrent. They can be written in any order

Exercise
Deduce the circuit implemented by the following code:

Structure of VHDL code

A VHDL model consists of:
ENTITY
defines ports (inputs and outputs)

ARCHITECTURE
defines operation

ENTITY description
Syntax
entity <entity_name> is port ( <port_names> : <mode> <type>; <port_names> : <mode> <type>; -- last port has no semicolon <port_names> : <mode> <type> ); end <entity_name>;

Example

ENTITY (port mode)

<mode>: indicate the port direction
IN : input port that can only be read OUT : output port that can only be written to BUFFER : output port that can be read as well INOUT : input and output port

Syntax
entity <entity_name> is port ( <port_names> : <mode> <type>; <port_names> : <mode> <type>; -- last port has no semicolon <port_names> : <mode> <type> ); end <entity_name>;

Example

ENTITY (port type)

<type>: indicates the signal type of the port
bit : can have the value 0 and 1 bit_vector : vector of bit values (e.g. bit_vector (0 to 7) boolean : can have the value TRUE or FALSE integer : can have a range of integer values std_logic: can have 9 values to indicate the value and strength of a signal. std_logic_vector: vector of std_logic values
Syntax Part of VHDL

Requires IEEE package

Example

entity <entity_name> is port ( <port_names> : <mode> <type>; <port_names> : <mode> <type>; -- last port has no semicolon <port_names> : <mode> <type> ); end <entity_name>;

ENTITY (port type) contd

bit values: 0 -- binary Zero 1 -- binary One std_logic values 0 -- Zero 1 -- One Z -- High Impedance - -- Dont Care U -- Uninitialized X Unknown W -- Weak Unknown L -- Weak Zero H -- Weak One Example (using IEEE types)

Example (using standard types)

Vector types
BIT_VECTOR: represents array of BIT objects STD_LOGIC_VECTOR: represents array of STD_LOGIC objects Example:

c <= 1010 will result in c(1)=1, c(2)=0, c(3)=1, c(4)=0 b <= 10011000 will result in b(7)=1, b(6)=0, and so on to b(0)=0

ARCHITECTURE description
A given architecture represents one possible implementation for its associated entity
architecture declaration: defines internal signals, components, types etc to be used in architecture body architecture body: defines implementation details of input/output relationship

Multiple architectures can exist for each entity

Syntax
architecture <arch_name> of <entity_name> is -- architecture declarations begin -- architecture body end <arch_name>;

Example

General form of an ARCHITECTURE

architecture <arch_name> of <entity_name> is -- architecture declarations [SIGNAL declarations] [COMPONENT declarations] [CONSTANT declarations] [TYPE declarations] [ATTRIBUTE specifications] begin -- architecture body [CONCURRENT ASSIGNMENT statements;] [COMPONENT instantiation statements;] [PROCESS statements;] [GENERATE statements;] end <arch_name>;
SIGNAL declarations

Example

CONCURRENT ASSIGNMENT statements

ARCHITECTURE declaration
SIGNAL declarations
These are for internal signals inside the entity
General Form
architecture <arch_name> of <entity_name> is -- architecture declarations [SIGNAL declarations] [COMPONENT declarations] [CONSTANT declarations] [TYPE declarations] [ATTRIBUTE specifications] begin -- architecture body [CONCURRENT ASSIGNMENT statements;] [COMPONENT instantiation statements;] [PROCESS statements;] [GENERATE statements;] end <arch_name>;

Syntax:
SIGNAL <signal_names> : <type>

The <type> are the same as previously described

Example

ARCHITECTURE body
Concurrent Assignments Syntax:
<target> <= <expression>
General Form
architecture <arch_name> of <entity_name> is -- architecture declarations [SIGNAL declarations] [COMPONENT declarations] [CONSTANT declarations] [TYPE declarations] [ATTRIBUTE specifications] begin -- architecture body [CONCURRENT ASSIGNMENT statements;] [COMPONENT instantiation statements;] [PROCESS statements;] [GENERATE statements;] end <arch_name>;

<target> can be an internal signal or an output port <expression> operates on internal signal and/or input ports

Example

Arithmetic operators +, -, *, / Logical operators NOT, AND, OR, NAND, NOR, XOR,XNOR

Expression and operators

Arithmetic operators and logical operators are defined for standard integer, bit, bit_vector types. Part of VHDL standard. Logical operators using std_logic and std_logic_vector types require IEEE std_logic_1164 package Arithmetic operators using std_logic and std_logic_vector types require IEEE std_logic_unsigned and IEEE std_logic_arith packages Examples:

Operators order of precedence

Operator class Operator

Highest precedence

Miscellaneous
Multiply, divide Add, subtract, concatenate

NOT
*, / +, -, &

Shift
Relational Lowest precedence logical

sll, srl, sla, sra, rol, ror

=, /=, <, >, <=, >= AND, OR, NAND, NOR, XOR, XNOR

Note that logical operators all have the same precedence. So need to use parenthesis For example, an SOP function should be:
f <= (x1 and x2) or (x3 and x4)

Operators of the same class are evaluated from left to right in an expression